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[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
d685192a
MW		 12015-11-27 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64.h (aarch64_op): Add OP_BFC.
4
87018195
MW		 52015-11-27 Matthew Wahab <matthew.wahab@arm.com>
6
7 * aarch64.h (AARCH64_FEATURE_F16): New.
8 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
9 features.
10
250aafa4
MW		 112015-11-20 Matthew Wahab <matthew.wahab@arm.com>
12
13 * aarch64.h (AARCH64_FEATURE_V8_1): New.
14 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
15
56a1b672
MW		 162015-11-19 Matthew Wahab <matthew.wahab@arm.com>
17
18 * arm.h (ARM_EXT2_V8_2A): New.
19 (ARM_ARCH_V8_2A): New.
20
acb787b0
MW		 212015-11-19 Matthew Wahab <matthew.wahab@arm.com>
22
23 * aarch64.h (AARCH64_FEATURE_V8_2): New.
24 (AARCH64_ARCH_V8_2): New.
25
a680de9a
PB		 262015-11-11 Alan Modra <amodra@gmail.com>
27 Peter Bergner <bergner@vnet.ibm.com>
28
29 * ppc.h (PPC_OPCODE_POWER9): New define.
30 (PPC_OPCODE_VSX3): Likewise.
31
854eb72b
NC		 322015-11-02 Nick Clifton <nickc@redhat.com>
33
34 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
35
e292aa7a
NC		 362015-11-02 Nick Clifton <nickc@redhat.com>
37
38 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
39
43cdf5ae
YQ		 402015-10-28 Yao Qi <yao.qi@linaro.org>
41
42 * aarch64.h (aarch64_decode_insn): Update declaration.
43
875880c6
YQ		 442015-10-07 Yao Qi <yao.qi@linaro.org>
45
46 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
47 <name>: New field.
48
d3e12b29
YQ		 492015-10-07 Yao Qi <yao.qi@linaro.org>
50
51 * aarch64.h [__cplusplus]: Wrap in extern "C".
52
886a2506
NC		 532015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
54 Cupertino Miranda <cmiranda@synopsys.com>
55
56 * arc-func.h: New file.
57 * arc.h: Likewise.
58
e141d84e
YQ		 592015-10-02 Yao Qi <yao.qi@linaro.org>
60
61 * aarch64.h (aarch64_zero_register_p): Move the declaration
62 to column one.
63
36f4aab1
YQ		 642015-10-02 Yao Qi <yao.qi@linaro.org>
65
66 * aarch64.h (aarch64_decode_insn): Declare it.
67
7ecc513a
DV		 682015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
69
70 * s390.h (S390_INSTR_FLAG_HTM): New flag.
71 (S390_INSTR_FLAG_VX): New flag.
72 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
73
b6518b38
NC		 742015-09-23 Nick Clifton <nickc@redhat.com>
75
76 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
77 shifting.
78
f04265ec
NC		 792015-09-22 Nick Clifton <nickc@redhat.com>
80
81 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
82
7bdf96ef
NC		 832015-09-09 Daniel Santos <daniel.santos@pobox.com>
84
85 * visium.h (gen_reg_table): Make static.
86 (fp_reg_table): Likewise.
87 (cc_table): Likewise.
88
f33026a9
MW		 892015-07-20 Matthew Wahab <matthew.wahab@arm.com>
90
91 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
92 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
93 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
94 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
95
ef5a96d5
AM		 962015-07-03 Alan Modra <amodra@gmail.com>
97
98 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
99
c8c8175b
SL		 1002015-07-01 Sandra Loosemore <sandra@codesourcery.com>
101 Cesar Philippidis <cesar@codesourcery.com>
102
103 * nios2.h (enum iw_format_type): Add R2 formats.
104 (enum overflow_type): Add signed_immed12_overflow and
105 enumeration_overflow for R2.
106 (struct nios2_opcode): Document new argument letters for R2.
107 (REG_3BIT, REG_LDWM, REG_POP): Define.
108 (includes): Include nios2r2.h.
109 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
110 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
111 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
112 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
113 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
114 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
115 Declare.
116 * nios2r2.h: New file.
117
11a0cf2e
PB		 1182015-06-19 Peter Bergner <bergner@vnet.ibm.com>
119
120 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
121 (ppc_optional_operand_value): New inline function.
122
88f0ea34
MW		 1232015-06-04 Matthew Wahab <matthew.wahab@arm.com>
124
125 * aarch64.h (AARCH64_V8_1): New.
126
a5932920
MW		 1272015-06-03 Matthew Wahab <matthew.wahab@arm.com>
128
129 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
130 (ARM_ARCH_V8_1A): New.
131 (ARM_ARCH_V8_1A_FP): New.
132 (ARM_ARCH_V8_1A_SIMD): New.
133 (ARM_ARCH_V8_1A_CRYPTOV1): New.
134 (ARM_FEATURE_CORE): New.
135
ddfded2f
MW		 1362015-06-02 Matthew Wahab <matthew.wahab@arm.com>
137
138 * arm.h (ARM_EXT2_PAN): New.
139 (ARM_FEATURE_CORE_HIGH): New.
140
1af1dd51
MW		 1412015-06-02 Matthew Wahab <matthew.wahab@arm.com>
142
143 * arm.h (ARM_FEATURE_ALL): New.
144
9e1f0fa7
MW		 1452015-06-02 Matthew Wahab <matthew.wahab@arm.com>
146
147 * aarch64.h (AARCH64_FEATURE_RDMA): New.
148
290806fd
MW		 1492015-06-02 Matthew Wahab <matthew.wahab@arm.com>
150
151 * aarch64.h (AARCH64_FEATURE_LOR): New.
152
f21cce2c
MW		 1532015-06-01 Matthew Wahab <matthew.wahab@arm.com>
154
155 * aarch64.h (AARCH64_FEATURE_PAN): New.
156 (aarch64_sys_reg_supported_p): Declare.
157 (aarch64_pstatefield_supported_p): Declare.
158
0952813b
DD		 1592015-04-30 DJ Delorie <dj@redhat.com>
160
161 * rl78.h (RL78_Dis_Isa): New.
162 (rl78_decode_opcode): Add ISA parameter.
163
823d2571
TG		 1642015-03-24 Terry Guo <terry.guo@arm.com>
165
166 * arm.h (arm_feature_set): Extended to provide more available bits.
167 (ARM_ANY): Updated to follow above new definition.
168 (ARM_CPU_HAS_FEATURE): Likewise.
169 (ARM_CPU_IS_ANY): Likewise.
170 (ARM_MERGE_FEATURE_SETS): Likewise.
171 (ARM_CLEAR_FEATURE): Likewise.
172 (ARM_FEATURE): Likewise.
173 (ARM_FEATURE_COPY): New macro.
174 (ARM_FEATURE_EQUAL): Likewise.
175 (ARM_FEATURE_ZERO): Likewise.
176 (ARM_FEATURE_CORE_EQUAL): Likewise.
177 (ARM_FEATURE_LOW): Likewise.
178 (ARM_FEATURE_CORE_LOW): Likewise.
179 (ARM_FEATURE_CORE_COPROC): Likewise.
180
f63c1776
PA		 1812015-02-19 Pedro Alves <palves@redhat.com>
182
183 * cgen.h [__cplusplus]: Wrap in extern "C".
184 * msp430-decode.h [__cplusplus]: Likewise.
185 * nios2.h [__cplusplus]: Likewise.
186 * rl78.h [__cplusplus]: Likewise.
187 * rx.h [__cplusplus]: Likewise.
188 * tilegx.h [__cplusplus]: Likewise.
189
3f8107ab
AM		 1902015-01-28 James Bowman <james.bowman@ftdichip.com>
191
192 * ft32.h: New file.
193
1e2e8c52
AK		 1942015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
195
196 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
197
b90efa5b
AM		 1982015-01-01 Alan Modra <amodra@gmail.com>
199
200 Update year range in copyright notice of all files.
201
bffb6004
AG		 2022014-12-27 Anthony Green <green@moxielogic.com>
203
204 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
205 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
206
1945cfa5
EB		 2072014-12-06 Eric Botcazou <ebotcazou@adacore.com>
208
209 * visium.h: New file.
210
d306ce58
SL		 2112014-11-28 Sandra Loosemore <sandra@codesourcery.com>
212
213 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
214 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
215 (NIOS2_INSN_OPTARG): Renumber.
216
b4714c7c
SL		 2172014-11-06 Sandra Loosemore <sandra@codesourcery.com>
218
219 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
220 declaration. Fix obsolete comment.
221
96ba4233
SL		 2222014-10-23 Sandra Loosemore <sandra@codesourcery.com>
223
224 * nios2.h (enum iw_format_type): New.
225 (struct nios2_opcode): Update comments. Add size and format fields.
226 (NIOS2_INSN_OPTARG): New.
227 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
228 (struct nios2_reg): Add regtype field.
229 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
230 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
231 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
232 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
233 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
234 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
235 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
236 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
237 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
238 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
239 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
240 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
241 (OP_MASK_OP, OP_SH_OP): Delete.
242 (OP_MASK_IOP, OP_SH_IOP): Delete.
243 (OP_MASK_IRD, OP_SH_IRD): Delete.
244 (OP_MASK_IRT, OP_SH_IRT): Delete.
245 (OP_MASK_IRS, OP_SH_IRS): Delete.
246 (OP_MASK_ROP, OP_SH_ROP): Delete.
247 (OP_MASK_RRD, OP_SH_RRD): Delete.
248 (OP_MASK_RRT, OP_SH_RRT): Delete.
249 (OP_MASK_RRS, OP_SH_RRS): Delete.
250 (OP_MASK_JOP, OP_SH_JOP): Delete.
251 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
252 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
253 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
254 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
255 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
256 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
257 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
258 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
259 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
260 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
261 (OP_MASK_<insn>, OP_MASK): Delete.
262 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
263 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
264 Include nios2r1.h to define new instruction opcode constants
265 and accessors.
266 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
267 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
268 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
269 (NUMOPCODES, NUMREGISTERS): Delete.
270 * nios2r1.h: New file.
271
0b6be415
JM		 2722014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
273
274 * sparc.h (HWCAP2_VIS3B): Documentation improved.
275
3d68f91c
JM		 2762014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
277
278 * sparc.h (sparc_opcode): new field `hwcaps2'.
279 (HWCAP2_FJATHPLUS): New define.
280 (HWCAP2_VIS3B): Likewise.
281 (HWCAP2_ADP): Likewise.
282 (HWCAP2_SPARC5): Likewise.
283 (HWCAP2_MWAIT): Likewise.
284 (HWCAP2_XMPMUL): Likewise.
285 (HWCAP2_XMONT): Likewise.
286 (HWCAP2_NSEC): Likewise.
287 (HWCAP2_FJATHHPC): Likewise.
288 (HWCAP2_FJDES): Likewise.
289 (HWCAP2_FJAES): Likewise.
290 Document the new operand kind `{', corresponding to the mcdper
291 ancillary state register.
292 Document the new operand kind }, which represents frsd floating
293 point registers (double precision) which must be the same than
294 frs1 in its containing instruction.
295
40c7a7cb
KLC		 2962014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
297
72f4393d 298 * nds32.h: Add new opcode declaration.
40c7a7cb 299
7361da2c
AB		 3002014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
301 Matthew Fortune <matthew.fortune@imgtec.com>
302
303 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
304 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
305 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
306 +I, +O, +R, +:, +\, +", +;
307 (mips_check_prev_operand): New struct.
308 (INSN2_FORBIDDEN_SLOT): New define.
309 (INSN_ISA32R6): New define.
310 (INSN_ISA64R6): New define.
311 (INSN_UPTO32R6): New define.
312 (INSN_UPTO64R6): New define.
313 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
314 (ISA_MIPS32R6): New define.
315 (ISA_MIPS64R6): New define.
316 (CPU_MIPS32R6): New define.
317 (CPU_MIPS64R6): New define.
318 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
319
ee804238
JW		 3202014-09-03 Jiong Wang <jiong.wang@arm.com>
321
322 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
323 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
324 (aarch64_insn_class): Add lse_atomic.
325 (F_LSE_SZ): New field added.
326 (opcode_has_special_coder): Recognize F_LSE_SZ.
327
5575639b
MR		 3282014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
329
330 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
331 over to `+J'.
332
43885403
MF		 3332014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
334
335 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
336 (INSN_LOAD_COPROC): New define.
337 (INSN_COPROC_MOVE_DELAY): Rename to...
338 (INSN_COPROC_MOVE): New define.
339
f36e8886 3402014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 341 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
342 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
343 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 344
345 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
346 (AVR_ISA_2xxxa): Define ISA without LPM.
347 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
348 Add doc for contraint used in 16 bit lds/sts.
349 Adjust ISA group for icall, ijmp, pop and push.
350 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
351
00b32ff2
NC		 3522014-05-19 Nick Clifton <nickc@redhat.com>
353
354 * msp430.h (struct msp430_operand_s): Add vshift field.
355
ae52f483
AB		 3562014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
357
358 * mips.h (INSN_ISA_MASK): Updated.
359 (INSN_ISA32R3): New define.
360 (INSN_ISA32R5): New define.
361 (INSN_ISA64R3): New define.
362 (INSN_ISA64R5): New define.
363 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
364 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
365 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
366 mips64r5.
367 (INSN_UPTO32R3): New define.
368 (INSN_UPTO32R5): New define.
369 (INSN_UPTO64R3): New define.
370 (INSN_UPTO64R5): New define.
371 (ISA_MIPS32R3): New define.
372 (ISA_MIPS32R5): New define.
373 (ISA_MIPS64R3): New define.
374 (ISA_MIPS64R5): New define.
375 (CPU_MIPS32R3): New define.
376 (CPU_MIPS32R5): New define.
377 (CPU_MIPS64R3): New define.
378 (CPU_MIPS64R5): New define.
379
3efe9ec5
RS		 3802014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
381
382 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
383
73589c9d
CS		 3842014-04-22 Christian Svensson <blue@cmd.nu>
385
386 * or32.h: Delete.
387
4b95cf5c
AM		 3882014-03-05 Alan Modra <amodra@gmail.com>
389
390 Update copyright years.
391
e269fea7
AB		 3922013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
393
394 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
395 microMIPS.
396
35c08157
KLC		 3972013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
398 Wei-Cheng Wang <cole945@gmail.com>
399
400 * nds32.h: New file for Andes NDS32.
401
594d8fa8
MF		 4022013-12-07 Mike Frysinger <vapier@gentoo.org>
403
404 * bfin.h: Remove +x file mode.
405
87b8eed7
YZ		 4062013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
407
408 * aarch64.h (aarch64_pstatefields): Change element type to
409 aarch64_sys_reg.
410
c9fb6e58
YZ		 4112013-11-18 Renlin Li <Renlin.Li@arm.com>
412
413 * arm.h (ARM_AEXT_V7VE): New define.
414 (ARM_ARCH_V7VE): New define.
415 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
416
a203d9b7
YZ		 4172013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
418
419 Revert
420
421 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
422
423 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
424 (aarch64_sys_reg_writeonly_p): Ditto.
425
75468c93
YZ		 4262013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
427
428 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
429 (aarch64_sys_reg_writeonly_p): Ditto.
430
49eec193
YZ		 4312013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
432
433 * aarch64.h (aarch64_sys_reg): New typedef.
434 (aarch64_sys_regs): Change to define with the new type.
435 (aarch64_sys_reg_deprecated_p): Declare.
436
68a64283
YZ		 4372013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
438
439 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
440 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
441
387a82f1
CF		 4422013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
443
444 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
445 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
446 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
447 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
448 For MIPS, update extension character sequences after +.
449 (ASE_MSA): New define.
450 (ASE_MSA64): New define.
451 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
452 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
453 For microMIPS, update extension character sequences after +.
454
9aff4b7a
NC		 4552013-08-23 Yuri Chornoivan <yurchor@ukr.net>
456
457 PR binutils/15834
458 * i960.h: Fix typos.
459
e423441d
RS		 4602013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
461
462 * mips.h: Remove references to "+I" and imm2_expr.
463
5e0dc5ba
RS		 4642013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
465
466 * mips.h (M_DEXT, M_DINS): Delete.
467
0f35dbc4
RS		 4682013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
469
470 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
471 (mips_optional_operand_p): New function.
472
14daeee3
RS		 4732013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
474 Richard Sandiford <rdsandiford@googlemail.com>
475
476 * mips.h: Document new VU0 operand characters.
477 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
478 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
479 (OP_REG_R5900_ACC): New mips_reg_operand_types.
480 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
481 (mips_vu0_channel_mask): Declare.
482
3ccad066
RS		 4832013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
484
485 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
486 (mips_int_operand_min, mips_int_operand_max): New functions.
487 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
488
fc76e730
RS		 4892013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
490
491 * mips.h (mips_decode_reg_operand): New function.
492 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
493 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
494 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
495 New macros.
496 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
497 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
498 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
499 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
500 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
501 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
502 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
503 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
504 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
505 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
506 macros to cover the gaps.
507 (INSN2_MOD_SP): Replace with...
508 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
509 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
510 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
511 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
512 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
513 Delete.
514
26545944
RS		 5152013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
516
517 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
518 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
519 (MIPS16_INSN_COND_BRANCH): Delete.
520
7e8b059b
L		 5212013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
522 Kirill Yukhin <kirill.yukhin@intel.com>
523 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
524
525 * i386.h (BND_PREFIX_OPCODE): New.
526
c3c07478
RS		 5272013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
528
529 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
530 OP_SAVE_RESTORE_LIST.
531 (decode_mips16_operand): Declare.
532
ab902481
RS		 5332013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
534
535 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
536 (mips_operand, mips_int_operand, mips_mapped_int_operand)
537 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
538 (mips_pcrel_operand): New structures.
539 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
540 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
541 (decode_mips_operand, decode_micromips_operand): Declare.
542
cc537e56
RS		 5432013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
544
545 * mips.h: Document MIPS16 "I" opcode.
546
f2ae14a1
RS		 5472013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
548
549 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
550 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
551 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
552 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
553 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
554 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
555 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
556 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
557 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
558 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
559 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
560 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
561 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
562 Rename to...
563 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
564 (M_USD_AB): ...these.
565
5c324c16
RS		 5662013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
567
568 * mips.h: Remove documentation of "[" and "]". Update documentation
569 of "k" and the MDMX formats.
570
23e69e47
RS		 5712013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
572
573 * mips.h: Update documentation of "+s" and "+S".
574
27c5c572
RS		 5752013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
576
577 * mips.h: Document "+i".
578
e76ff5ab
RS		 5792013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
580
581 * mips.h: Remove "mi" documentation. Update "mh" documentation.
582 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
583 Delete.
584 (INSN2_WRITE_GPR_MHI): Rename to...
585 (INSN2_WRITE_GPR_MH): ...this.
586
fa7616a4
RS		 5872013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
588
589 * mips.h: Remove documentation of "+D" and "+T".
590
18870af7
RS		 5912013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
592
593 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
594 Use "source" rather than "destination" for microMIPS "G".
595
833794fc
MR		 5962013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
597
598 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
599 values.
600
c3678916
RS		 6012013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
602
603 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
604
7f3c4072
CM		 6052013-06-17 Catherine Moore <clm@codesourcery.com>
606 Maciej W. Rozycki <macro@codesourcery.com>
607 Chao-Ying Fu <fu@mips.com>
608
609 * mips.h (OP_SH_EVAOFFSET): Define.
610 (OP_MASK_EVAOFFSET): Define.
611 (INSN_ASE_MASK): Delete.
612 (ASE_EVA): Define.
613 (M_CACHEE_AB, M_CACHEE_OB): New.
614 (M_LBE_OB, M_LBE_AB): New.
615 (M_LBUE_OB, M_LBUE_AB): New.
616 (M_LHE_OB, M_LHE_AB): New.
617 (M_LHUE_OB, M_LHUE_AB): New.
618 (M_LLE_AB, M_LLE_OB): New.
619 (M_LWE_OB, M_LWE_AB): New.
620 (M_LWLE_AB, M_LWLE_OB): New.
621 (M_LWRE_AB, M_LWRE_OB): New.
622 (M_PREFE_AB, M_PREFE_OB): New.
623 (M_SCE_AB, M_SCE_OB): New.
624 (M_SBE_OB, M_SBE_AB): New.
625 (M_SHE_OB, M_SHE_AB): New.
626 (M_SWE_OB, M_SWE_AB): New.
627 (M_SWLE_AB, M_SWLE_OB): New.
628 (M_SWRE_AB, M_SWRE_OB): New.
629 (MICROMIPSOP_SH_EVAOFFSET): Define.
630 (MICROMIPSOP_MASK_EVAOFFSET): Define.
631
0c8fe7cf
SL		 6322013-06-12 Sandra Loosemore <sandra@codesourcery.com>
633
634 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
635
c77c0862
RS		 6362013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
637
638 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
639
b015e599
AP		 6402013-05-09 Andrew Pinski <apinski@cavium.com>
641
642 * mips.h (OP_MASK_CODE10): Correct definition.
643 (OP_SH_CODE10): Likewise.
644 Add a comment that "+J" is used now for OP_*CODE10.
645 (INSN_ASE_MASK): Update.
646 (INSN_VIRT): New macro.
647 (INSN_VIRT64): New macro
648
13761a11
NC		 6492013-05-02 Nick Clifton <nickc@redhat.com>
650
651 * msp430.h: Add patterns for MSP430X instructions.
652
0afd1215
DM		 6532013-04-06 David S. Miller <davem@davemloft.net>
654
655 * sparc.h (F_PREFERRED): Define.
656 (F_PREF_ALIAS): Define.
657
41702d50
NC		 6582013-04-03 Nick Clifton <nickc@redhat.com>
659
660 * v850.h (V850_INVERSE_PCREL): Define.
661
e21e1a51
NC		 6622013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
663
664 PR binutils/15068
665 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
666
51dcdd4d
NC		 6672013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
668
669 PR binutils/15068
670 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
671 Add 16-bit opcodes.
672 * tic6xc-opcode-table.h: Add 16-bit insns.
673 * tic6x.h: Add support for 16-bit insns.
674
81f5558e
NC		 6752013-03-21 Michael Schewe <michael.schewe@gmx.net>
676
677 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
678 and mov.b/w/l Rs,@(d:32,ERd).
679
165546ad
NC		 6802013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
681
682 PR gas/15082
683 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
684 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
685 tic6x_operand_xregpair operand coding type.
686 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
687 opcode field, usu ORXREGD1324 for the src2 operand and remove the
688 TIC6X_FLAG_NO_CROSS.
689
795b8e6b
NC		 6902013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
691
692 PR gas/15095
693 * tic6x.h (enum tic6x_coding_method): Add
694 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
695 separately the msb and lsb of a register pair. This is needed to
696 encode the opcodes in the same way as TI assembler does.
697 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
698 and rsqrdp opcodes to use the new field coding types.
699
dd5181d5
KT		 7002013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
701
702 * arm.h (CRC_EXT_ARMV8): New constant.
703 (ARCH_CRC_ARMV8): New macro.
704
e60bb1dd
YZ		 7052013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
706
707 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
708
36591ba1 7092013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 710 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 711
712 Based on patches from Altera Corporation.
713
714 * nios2.h: New file.
715
e30181a5
YZ		 7162013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
717
718 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
719
0c9573f4
NC		 7202013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
721
722 PR gas/15069
723 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
724
981dc7f1
NC		 7252013-01-24 Nick Clifton <nickc@redhat.com>
726
727 * v850.h: Add e3v5 support.
728
f5555712
YZ		 7292013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
730
731 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
732
5817ffd1
PB		 7332013-01-10 Peter Bergner <bergner@vnet.ibm.com>
734
735 * ppc.h (PPC_OPCODE_POWER8): New define.
736 (PPC_OPCODE_HTM): Likewise.
737
a3c62988
NC		 7382013-01-10 Will Newton <will.newton@imgtec.com>
739
740 * metag.h: New file.
741
73335eae
NC		 7422013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
743
744 * cr16.h (make_instruction): Rename to cr16_make_instruction.
745 (match_opcode): Rename to cr16_match_opcode.
746
e407c74b
NC		 7472013-01-04 Juergen Urban <JuergenUrban@gmx.de>
748
749 * mips.h: Add support for r5900 instructions including lq and sq.
750
bab4becb
NC		 7512013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
752
753 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
754 (make_instruction,match_opcode): Added function prototypes.
755 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
756
776fc418
AM		 7572012-11-23 Alan Modra <amodra@gmail.com>
758
759 * ppc.h (ppc_parse_cpu): Update prototype.
760
f05682d4
DA		 7612012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
762
763 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
764 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
765
cfc72779
AK		 7662012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
767
768 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
769
b3e14eda
L		 7702012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
771
772 * ia64.h (ia64_opnd): Add new operand types.
773
2c63854f
DM		 7742012-08-21 David S. Miller <davem@davemloft.net>
775
776 * sparc.h (F3F4): New macro.
777
a06ea964 7782012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 779 Laurent Desnogues <laurent.desnogues@arm.com>
780 Jim MacArthur <jim.macarthur@arm.com>
781 Marcus Shawcroft <marcus.shawcroft@arm.com>
782 Nigel Stephens <nigel.stephens@arm.com>
783 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
784 Richard Earnshaw <rearnsha@arm.com>
785 Sofiane Naci <sofiane.naci@arm.com>
786 Tejas Belagod <tejas.belagod@arm.com>
787 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 788
789 * aarch64.h: New file.
790
35d0a169 7912012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 792 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 793
794 * mips.h (mips_opcode): Add the exclusions field.
795 (OPCODE_IS_MEMBER): Remove macro.
796 (cpu_is_member): New inline function.
797 (opcode_is_member): Likewise.
798
03f66e8a 7992012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 800 Catherine Moore <clm@codesourcery.com>
801 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 802
803 * mips.h: Document microMIPS DSP ASE usage.
804 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
805 microMIPS DSP ASE support.
806 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
807 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
808 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
809 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
810 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
811 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
812 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
813
9d7b4c23
MR		 8142012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
815
816 * mips.h: Fix a typo in description.
817
76e879f8
NC		 8182012-06-07 Georg-Johann Lay <avr@gjlay.de>
819
820 * avr.h: (AVR_ISA_XCH): New define.
821 (AVR_ISA_XMEGA): Use it.
822 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
823
6927f982
NC		 8242012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
825
826 * m68hc11.h: Add XGate definitions.
827 (struct m68hc11_opcode): Add xg_mask field.
828
b9c361e0
JL		 8292012-05-14 Catherine Moore <clm@codesourcery.com>
830 Maciej W. Rozycki <macro@codesourcery.com>
831 Rhonda Wittels <rhonda@codesourcery.com>
832
6927f982 833 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 834 (PPC_OP_SA): New macro.
835 (PPC_OP_SE_VLE): New macro.
836 (PPC_OP): Use a variable shift amount.
837 (powerpc_operand): Update comments.
838 (PPC_OPSHIFT_INV): New macro.
839 (PPC_OPERAND_CR): Replace with...
840 (PPC_OPERAND_CR_BIT): ...this and
841 (PPC_OPERAND_CR_REG): ...this.
842
843
f6c1a2d5
NC		 8442012-05-03 Sean Keys <skeys@ipdatasys.com>
845
846 * xgate.h: Header file for XGATE assembler.
847
ec668d69
DM		 8482012-04-27 David S. Miller <davem@davemloft.net>
849
6cda1326
DM		 850 * sparc.h: Document new arg code' )' for crypto RS3
851 immediates.
852
ec668d69
DM		 853 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
854 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
855 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
856 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
857 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
858 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
859 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
860 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
861 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
862 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
863 HWCAP_CBCOND, HWCAP_CRC32): New defines.
864
aea77599
AM		 8652012-03-10 Edmar Wienskoski <edmar@freescale.com>
866
867 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
868
1f42f8b3
AM		 8692012-02-27 Alan Modra <amodra@gmail.com>
870
871 * crx.h (cst4_map): Update declaration.
872
6f7be959
WL		 8732012-02-25 Walter Lee <walt@tilera.com>
874
875 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
876 TILEGX_OPC_LD_TLS.
877 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
878 TILEPRO_OPC_LW_TLS_SN.
879
42164a71
L		 8802012-02-08 H.J. Lu <hongjiu.lu@intel.com>
881
882 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
883 (XRELEASE_PREFIX_OPCODE): Likewise.
884
432233b3 8852011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 886 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 887
888 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
889 (INSN_OCTEON2): New macro.
890 (CPU_OCTEON2): New macro.
891 (OPCODE_IS_MEMBER): Add Octeon2.
892
dd6a37e7
AP		 8932011-11-29 Andrew Pinski <apinski@cavium.com>
894
895 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
896 (INSN_OCTEONP): New macro.
897 (CPU_OCTEONP): New macro.
898 (OPCODE_IS_MEMBER): Add Octeon+.
899 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
900
99c513f6
DD		 9012011-11-01 DJ Delorie <dj@redhat.com>
902
903 * rl78.h: New file.
904
26f85d7a
MR		 9052011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
906
907 * mips.h: Fix a typo in description.
908
9e8c70f9
DM		 9092011-09-21 David S. Miller <davem@davemloft.net>
910
911 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
912 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
913 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
914 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
915
dec0624d 9162011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 917 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 918
919 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
920 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
921 (INSN_ASE_MASK): Add the MCU bit.
922 (INSN_MCU): New macro.
923 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
924 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
925
2b0c8b40
MR		 9262011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
927
928 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
929 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
930 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
931 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
932 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
933 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
934 (INSN2_READ_GPR_MMN): Likewise.
935 (INSN2_READ_FPR_D): Change the bit used.
936 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
937 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
938 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
939 (INSN2_COND_BRANCH): Likewise.
940 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
941 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
942 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
943 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
944 (INSN2_MOD_GPR_MN): Likewise.
945
ea783ef3
DM		 9462011-08-05 David S. Miller <davem@davemloft.net>
947
948 * sparc.h: Document new format codes '4', '5', and '('.
949 (OPF_LOW4, RS3): New macros.
950
7c176fa8
MR		 9512011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
952
953 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
954 order of flags documented.
955
2309ddf2
MR		 9562011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
957
958 * mips.h: Clarify the description of microMIPS instruction
959 manipulation macros.
960 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
961
df58fc94 9622011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 963 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 964
965 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
966 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
967 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
968 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
969 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
970 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
971 (OP_MASK_RS3, OP_SH_RS3): Likewise.
972 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
973 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
974 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
975 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
976 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
977 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
978 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
979 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
980 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
981 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
982 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
983 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
984 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
985 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
986 (INSN_WRITE_GPR_S): New macro.
987 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
988 (INSN2_READ_FPR_D): Likewise.
989 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
990 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
991 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
992 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
993 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
994 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
995 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
996 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
997 (CPU_MICROMIPS): New macro.
998 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
999 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1000 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1001 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1002 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1003 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1004 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1005 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1006 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1007 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1008 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1009 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1010 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1011 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1012 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1013 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1014 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1015 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1016 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1017 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1018 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1019 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1020 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1021 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1022 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1023 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1024 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1025 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1026 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1027 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1028 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1029 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1030 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1031 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1032 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1033 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1034 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1035 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1036 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1037 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1038 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1039 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1040 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1041 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1042 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1043 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1044 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1045 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1046 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1047 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1048 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1049 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1050 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1051 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1052 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1053 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1054 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1055 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1056 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1057 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1058 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1059 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1060 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1061 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1062 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1063 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1064 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1065 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1066 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1067 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1068 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1069 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1070 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1071 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1072 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1073 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1074 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1075 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1076 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1077 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1078 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1079 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1080 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1081 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1082 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1083 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1084 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1085 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1086 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1087 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1088 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1089 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1090 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1091 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1092 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1093 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1094 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1095 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1096 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1097 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1098 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1099 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1100 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1101 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1102 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1103 (micromips_opcodes): New declaration.
1104 (bfd_micromips_num_opcodes): Likewise.
1105
bcd530a7
RS		 11062011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1107
1108 * mips.h (INSN_TRAP): Rename to...
1109 (INSN_NO_DELAY_SLOT): ... this.
1110 (INSN_SYNC): Remove macro.
1111
2dad5a91
EW		 11122011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1113
1114 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1115 a duplicate of AVR_ISA_SPM.
1116
5d73b1f1
NC		 11172011-07-01 Nick Clifton <nickc@redhat.com>
1118
1119 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1120
ef26d60e
MF		 11212011-06-18 Robin Getz <robin.getz@analog.com>
1122
1123 * bfin.h (is_macmod_signed): New func
1124
8fb8dca7
MF		 11252011-06-18 Mike Frysinger <vapier@gentoo.org>
1126
1127 * bfin.h (is_macmod_pmove): Add missing space before func args.
1128 (is_macmod_hmove): Likewise.
1129
aa137e4d
NC		 11302011-06-13 Walter Lee <walt@tilera.com>
1131
1132 * tilegx.h: New file.
1133 * tilepro.h: New file.
1134
3b2f0793
PB		 11352011-05-31 Paul Brook <paul@codesourcery.com>
1136
aa137e4d
NC		 1137 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1138
11392011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1140
1141 * s390.h: Replace S390_OPERAND_REG_EVEN with
1142 S390_OPERAND_REG_PAIR.
1143
11442011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1145
1146 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1147
ac7f631b
NC		 11482011-04-18 Julian Brown <julian@codesourcery.com>
1149
1150 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1151
84701018
NC		 11522011-04-11 Dan McDonald <dan@wellkeeper.com>
1153
1154 PR gas/12296
1155 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1156
8cc66334
EW		 11572011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1158
1159 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1160 New instruction set flags.
1161 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1162
3eebd5eb
MR		 11632011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1164
1165 * mips.h (M_PREF_AB): New enum value.
1166
26bb3ddd
MF		 11672011-02-12 Mike Frysinger <vapier@gentoo.org>
1168
89c0d58c
MR		 1169 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1170 M_IU): Define.
1171 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1172
dd76fcb8
MF		 11732011-02-11 Mike Frysinger <vapier@gentoo.org>
1174
1175 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1176
98d23bef
BS		 11772011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1178
1179 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1180 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1181
3c853d93
DA		 11822010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1183
1184 PR gas/11395
1185 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1186 "bb" entries.
1187
79676006
DA		 11882010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1189
1190 PR gas/11395
1191 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1192
1bec78e9
RS		 11932010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1194
1195 * mips.h: Update commentary after last commit.
1196
98675402
RS		 11972010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1198
1199 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1200 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1201 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1202
aa137e4d
NC		 12032010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1204
1205 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1206
435b94a4
RS		 12072010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1208
1209 * mips.h: Fix previous commit.
1210
d051516a
NC		 12112010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1212
1213 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1214 (INSN_LOONGSON_3A): Clear bit 31.
1215
251665fc
MGD		 12162010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1217
1218 PR gas/12198
1219 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1220 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1221 (ARM_ARCH_V6M_ONLY): New define.
1222
fd503541
NC		 12232010-11-11 Mingming Sun <mingm.sun@gmail.com>
1224
1225 * mips.h (INSN_LOONGSON_3A): Defined.
1226 (CPU_LOONGSON_3A): Defined.
1227 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1228
4469d2be
AM		 12292010-10-09 Matt Rice <ratmice@gmail.com>
1230
1231 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1232 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1233
90ec0d68
MGD		 12342010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1235
1236 * arm.h (ARM_EXT_VIRT): New define.
1237 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1238 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1239 Extensions.
1240
eea54501 12412010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1242
eea54501
MGD		 1243 * arm.h (ARM_AEXT_ADIV): New define.
1244 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1245
b2a5fbdc
MGD		 12462010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1247
1248 * arm.h (ARM_EXT_OS): New define.
1249 (ARM_AEXT_V6SM): Likewise.
1250 (ARM_ARCH_V6SM): Likewise.
1251
60e5ef9f
MGD		 12522010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1253
1254 * arm.h (ARM_EXT_MP): Add.
1255 (ARM_ARCH_V7A_MP): Likewise.
1256
73a63ccf
MF		 12572010-09-22 Mike Frysinger <vapier@gentoo.org>
1258
1259 * bfin.h: Declare pseudoChr structs/defines.
1260
ee99860a
MF		 12612010-09-21 Mike Frysinger <vapier@gentoo.org>
1262
1263 * bfin.h: Strip trailing whitespace.
1264
f9c7014e
DD		 12652010-07-29 DJ Delorie <dj@redhat.com>
1266
1267 * rx.h (RX_Operand_Type): Add TwoReg.
1268 (RX_Opcode_ID): Remove ediv and ediv2.
1269
93378652
DD		 12702010-07-27 DJ Delorie <dj@redhat.com>
1271
1272 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1273
1cd986c5
NC		 12742010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1275 Ina Pandit <ina.pandit@kpitcummins.com>
1276
1277 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1278 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1279 PROCESSOR_V850E2_ALL.
1280 Remove PROCESSOR_V850EA support.
1281 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1282 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1283 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1284 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1285 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1286 V850_OPERAND_PERCENT.
1287 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1288 V850_NOT_R0.
1289 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1290 and V850E_PUSH_POP
1291
9a2c7088
MR		 12922010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1293
1294 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1295 (MIPS16_INSN_BRANCH): Rename to...
1296 (MIPS16_INSN_COND_BRANCH): ... this.
1297
bdc70b4a
AM		 12982010-07-03 Alan Modra <amodra@gmail.com>
1299
1300 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1301 Renumber other PPC_OPCODE defines.
1302
f2bae120
AM		 13032010-07-03 Alan Modra <amodra@gmail.com>
1304
1305 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1306
360cfc9c
AM		 13072010-06-29 Alan Modra <amodra@gmail.com>
1308
1309 * maxq.h: Delete file.
1310
e01d869a
AM		 13112010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1312
1313 * ppc.h (PPC_OPCODE_E500): Define.
1314
f79e2745
CM		 13152010-05-26 Catherine Moore <clm@codesourcery.com>
1316
1317 * opcode/mips.h (INSN_MIPS16): Remove.
1318
2462afa1
JM		 13192010-04-21 Joseph Myers <joseph@codesourcery.com>
1320
1321 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1322
e4e42b45
NC		 13232010-04-15 Nick Clifton <nickc@redhat.com>
1324
1325 * alpha.h: Update copyright notice to use GPLv3.
1326 * arc.h: Likewise.
1327 * arm.h: Likewise.
1328 * avr.h: Likewise.
1329 * bfin.h: Likewise.
1330 * cgen.h: Likewise.
1331 * convex.h: Likewise.
1332 * cr16.h: Likewise.
1333 * cris.h: Likewise.
1334 * crx.h: Likewise.
1335 * d10v.h: Likewise.
1336 * d30v.h: Likewise.
1337 * dlx.h: Likewise.
1338 * h8300.h: Likewise.
1339 * hppa.h: Likewise.
1340 * i370.h: Likewise.
1341 * i386.h: Likewise.
1342 * i860.h: Likewise.
1343 * i960.h: Likewise.
1344 * ia64.h: Likewise.
1345 * m68hc11.h: Likewise.
1346 * m68k.h: Likewise.
1347 * m88k.h: Likewise.
1348 * maxq.h: Likewise.
1349 * mips.h: Likewise.
1350 * mmix.h: Likewise.
1351 * mn10200.h: Likewise.
1352 * mn10300.h: Likewise.
1353 * msp430.h: Likewise.
1354 * np1.h: Likewise.
1355 * ns32k.h: Likewise.
1356 * or32.h: Likewise.
1357 * pdp11.h: Likewise.
1358 * pj.h: Likewise.
1359 * pn.h: Likewise.
1360 * ppc.h: Likewise.
1361 * pyr.h: Likewise.
1362 * rx.h: Likewise.
1363 * s390.h: Likewise.
1364 * score-datadep.h: Likewise.
1365 * score-inst.h: Likewise.
1366 * sparc.h: Likewise.
1367 * spu-insns.h: Likewise.
1368 * spu.h: Likewise.
1369 * tic30.h: Likewise.
1370 * tic4x.h: Likewise.
1371 * tic54x.h: Likewise.
1372 * tic80.h: Likewise.
1373 * v850.h: Likewise.
1374 * vax.h: Likewise.
1375
40b36596
JM		 13762010-03-25 Joseph Myers <joseph@codesourcery.com>
1377
1378 * tic6x-control-registers.h, tic6x-insn-formats.h,
1379 tic6x-opcode-table.h, tic6x.h: New.
1380
c67a084a
NC		 13812010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1382
1383 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1384
466ef64f
AM		 13852010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1386
1387 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1388
1319d143
L		 13892010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1390
1391 * ia64.h (ia64_find_opcode): Remove argument name.
1392 (ia64_find_next_opcode): Likewise.
1393 (ia64_dis_opcode): Likewise.
1394 (ia64_free_opcode): Likewise.
1395 (ia64_find_dependency): Likewise.
1396
1fbb9298
DE		 13972009-11-22 Doug Evans <dje@sebabeach.org>
1398
1399 * cgen.h: Include bfd_stdint.h.
1400 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1401
ada65aa3
PB		 14022009-11-18 Paul Brook <paul@codesourcery.com>
1403
1404 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1405
9e3c6df6
PB		 14062009-11-17 Paul Brook <paul@codesourcery.com>
1407 Daniel Jacobowitz <dan@codesourcery.com>
1408
1409 * arm.h (ARM_EXT_V6_DSP): Define.
1410 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1411 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1412
0d734b5d
DD		 14132009-11-04 DJ Delorie <dj@redhat.com>
1414
1415 * rx.h (rx_decode_opcode) (mvtipl): Add.
1416 (mvtcp, mvfcp, opecp): Remove.
1417
62f3b8c8
PB		 14182009-11-02 Paul Brook <paul@codesourcery.com>
1419
1420 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1421 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1422 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1423 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1424 FPU_ARCH_NEON_VFP_V4): Define.
1425
ac1e9eca
DE		 14262009-10-23 Doug Evans <dje@sebabeach.org>
1427
1428 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1429 * cgen.h: Update. Improve multi-inclusion macro name.
1430
9fe54b1c
PB		 14312009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1432
1433 * ppc.h (PPC_OPCODE_476): Define.
1434
634b50f2
PB		 14352009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1436
1437 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1438
c7927a3c
NC		 14392009-09-29 DJ Delorie <dj@redhat.com>
1440
1441 * rx.h: New file.
1442
b961e85b
AM		 14432009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1444
1445 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1446
e0d602ec
BE		 14472009-09-21 Ben Elliston <bje@au.ibm.com>
1448
1449 * ppc.h (PPC_OPCODE_PPCA2): New.
1450
96d56e9f
NC		 14512009-09-05 Martin Thuresson <martin@mtme.org>
1452
1453 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1454
d3ce72d0
NC		 14552009-08-29 Martin Thuresson <martin@mtme.org>
1456
1457 * tic30.h (template): Rename type template to
1458 insn_template. Updated code to use new name.
1459 * tic54x.h (template): Rename type template to
1460 insn_template.
1461
824b28db
NH		 14622009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1463
1464 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1465
f865a31d
AG		 14662009-06-11 Anthony Green <green@moxielogic.com>
1467
1468 * moxie.h (MOXIE_F3_PCREL): Define.
1469 (moxie_form3_opc_info): Grow.
1470
0e7c7f11
AG		 14712009-06-06 Anthony Green <green@moxielogic.com>
1472
1473 * moxie.h (MOXIE_F1_M): Define.
1474
20135e4c
NC		 14752009-04-15 Anthony Green <green@moxielogic.com>
1476
1477 * moxie.h: Created.
1478
bcb012d3
DD		 14792009-04-06 DJ Delorie <dj@redhat.com>
1480
1481 * h8300.h: Add relaxation attributes to MOVA opcodes.
1482
69fe9ce5
AM		 14832009-03-10 Alan Modra <amodra@bigpond.net.au>
1484
1485 * ppc.h (ppc_parse_cpu): Declare.
1486
c3b7224a
NC		 14872009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1488
1489 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1490 and _IMM11 for mbitclr and mbitset.
1491 * score-datadep.h: Update dependency information.
1492
066be9f7
PB		 14932009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1494
1495 * ppc.h (PPC_OPCODE_POWER7): New.
1496
fedc618e
DE		 14972009-02-06 Doug Evans <dje@google.com>
1498
1499 * i386.h: Add comment regarding sse* insns and prefixes.
1500
52b6b6b9
JM		 15012009-02-03 Sandip Matte <sandip@rmicorp.com>
1502
1503 * mips.h (INSN_XLR): Define.
1504 (INSN_CHIP_MASK): Update.
1505 (CPU_XLR): Define.
1506 (OPCODE_IS_MEMBER): Update.
1507 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1508
35669430
DE		 15092009-01-28 Doug Evans <dje@google.com>
1510
1511 * opcode/i386.h: Add multiple inclusion protection.
1512 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1513 (EDI_REG_NUM): New macros.
1514 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1515 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1516 (REX_PREFIX_P): New macro.
35669430 1517
1cb0a767
PB		 15182009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1519
1520 * ppc.h (struct powerpc_opcode): New field "deprecated".
1521 (PPC_OPCODE_NOPOWER4): Delete.
1522
3aa3176b
TS		 15232008-11-28 Joshua Kinard <kumba@gentoo.org>
1524
1525 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1526 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1527
8e79c3df
CM		 15282008-11-18 Catherine Moore <clm@codesourcery.com>
1529
1530 * arm.h (FPU_NEON_FP16): New.
1531 (FPU_ARCH_NEON_FP16): New.
1532
de9a3e51
CF		 15332008-11-06 Chao-ying Fu <fu@mips.com>
1534
1535 * mips.h: Doucument '1' for 5-bit sync type.
1536
1ca35711
L		 15372008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1538
1539 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1540 IA64_RS_CR.
1541
9b4e5766
PB		 15422008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1543
1544 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1545
081ba1b3
AM		 15462008-07-30 Michael J. Eager <eager@eagercon.com>
1547
1548 * ppc.h (PPC_OPCODE_405): Define.
1549 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1550
fa452fa6
PB		 15512008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1552
1553 * ppc.h (ppc_cpu_t): New typedef.
1554 (struct powerpc_opcode <flags>): Use it.
1555 (struct powerpc_operand <insert, extract>): Likewise.
1556 (struct powerpc_macro <flags>): Likewise.
1557
bb35fb24
NC		 15582008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1559
1560 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1561 Update comment before MIPS16 field descriptors to mention MIPS16.
1562 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1563 BBIT.
1564 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1565 New bit masks and shift counts for cins and exts.
1566
dd3cbb7e
NC		 1567 * mips.h: Document new field descriptors +Q.
1568 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1569
d0799671
AN		 15702008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1571
9aff4b7a 1572 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1573 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1574
19a6653c
AM		 15752008-04-14 Edmar Wienskoski <edmar@freescale.com>
1576
1577 * ppc.h: (PPC_OPCODE_E500MC): New.
1578
c0f3af97
L		 15792008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1580
1581 * i386.h (MAX_OPERANDS): Set to 5.
1582 (MAX_MNEM_SIZE): Changed to 20.
1583
e210c36b
NC		 15842008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1585
1586 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1587
b1cc4aeb
PB		 15882008-03-09 Paul Brook <paul@codesourcery.com>
1589
1590 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1591
7e806470
PB		 15922008-03-04 Paul Brook <paul@codesourcery.com>
1593
1594 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1595 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1596 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1597
7b2185f9 15982008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1599 Nick Clifton <nickc@redhat.com>
1600
1601 PR 3134
1602 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1603 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1604 set.
af7329f0 1605
796d5313
NC		 16062008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1607
1608 * cr16.h (cr16_num_optab): Declared.
1609
d669d37f
NC		 16102008-02-14 Hakan Ardo <hakan@debian.org>
1611
1612 PR gas/2626
1613 * avr.h (AVR_ISA_2xxe): Define.
1614
e6429699
AN		 16152008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1616
1617 * mips.h: Update copyright.
1618 (INSN_CHIP_MASK): New macro.
1619 (INSN_OCTEON): New macro.
1620 (CPU_OCTEON): New macro.
1621 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1622
e210c36b
NC		 16232008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1624
1625 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1626
16272008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1628
1629 * avr.h (AVR_ISA_USB162): Add new opcode set.
1630 (AVR_ISA_AVR3): Likewise.
1631
350cc38d
MS		 16322007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1633
1634 * mips.h (INSN_LOONGSON_2E): New.
1635 (INSN_LOONGSON_2F): New.
1636 (CPU_LOONGSON_2E): New.
1637 (CPU_LOONGSON_2F): New.
1638 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1639
56950294
MS		 16402007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1641
1642 * mips.h (INSN_ISA*): Redefine certain values as an
1643 enumeration. Update comments.
1644 (mips_isa_table): New.
1645 (ISA_MIPS*): Redefine to match enumeration.
1646 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1647 values.
1648
c3d65c1c
BE		 16492007-08-08 Ben Elliston <bje@au.ibm.com>
1650
1651 * ppc.h (PPC_OPCODE_PPCPS): New.
1652
0fdaa005
L		 16532007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1654
1655 * m68k.h: Document j K & E.
1656
16572007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1658
1659 * cr16.h: New file for CR16 target.
1660
3896c469
AM		 16612007-05-02 Alan Modra <amodra@bigpond.net.au>
1662
1663 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1664
9a2e615a
NS		 16652007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1666
1667 * m68k.h (mcfisa_c): New.
1668 (mcfusp, mcf_mask): Adjust.
1669
b84bf58a
AM		 16702007-04-20 Alan Modra <amodra@bigpond.net.au>
1671
1672 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1673 (num_powerpc_operands): Declare.
1674 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1675 (PPC_OPERAND_PLUS1): Define.
1676
831480e9 16772007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1678
1679 * i386.h (REX_MODE64): Renamed to ...
1680 (REX_W): This.
1681 (REX_EXTX): Renamed to ...
1682 (REX_R): This.
1683 (REX_EXTY): Renamed to ...
1684 (REX_X): This.
1685 (REX_EXTZ): Renamed to ...
1686 (REX_B): This.
1687
0b1cf022
L		 16882007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1689
1690 * i386.h: Add entries from config/tc-i386.h and move tables
1691 to opcodes/i386-opc.h.
1692
d796c0ad
L		 16932007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1694
1695 * i386.h (FloatDR): Removed.
1696 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1697
30ac7323
AM		 16982007-03-01 Alan Modra <amodra@bigpond.net.au>
1699
1700 * spu-insns.h: Add soma double-float insns.
1701
8b082fb1 17022007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1703 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1704
1705 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1706 (INSN_DSPR2): Add flag for DSP R2 instructions.
1707 (M_BALIGN): New macro.
1708
4eed87de
AM		 17092007-02-14 Alan Modra <amodra@bigpond.net.au>
1710
1711 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1712 and Seg3ShortFrom with Shortform.
1713
fda592e8
L		 17142007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1715
1716 PR gas/4027
1717 * i386.h (i386_optab): Put the real "test" before the pseudo
1718 one.
1719
3bdcfdf4
KH		 17202007-01-08 Kazu Hirata <kazu@codesourcery.com>
1721
1722 * m68k.h (m68010up): OR fido_a.
1723
9840d27e
KH		 17242006-12-25 Kazu Hirata <kazu@codesourcery.com>
1725
1726 * m68k.h (fido_a): New.
1727
c629cdac
KH		 17282006-12-24 Kazu Hirata <kazu@codesourcery.com>
1729
1730 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1731 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1732 values.
1733
b7d9ef37
L		 17342006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1735
1736 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1737
b138abaa
NC		 17382006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1739
1740 * score-inst.h (enum score_insn_type): Add Insn_internal.
1741
e9f53129
AM		 17422006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1743 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1744 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1745 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1746 Alan Modra <amodra@bigpond.net.au>
1747
1748 * spu-insns.h: New file.
1749 * spu.h: New file.
1750
ede602d7
AM		 17512006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1752
1753 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1754
7918206c
MM		 17552006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1756
e4e42b45 1757 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1758 in amdfam10 architecture.
1759
ef05d495
L		 17602006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1761
1762 * i386.h: Replace CpuMNI with CpuSSSE3.
1763
2d447fca 17642006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1765 Joseph Myers <joseph@codesourcery.com>
1766 Ian Lance Taylor <ian@wasabisystems.com>
1767 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1768
1769 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1770
1c0d3aa6
NC		 17712006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1772
1773 * score-datadep.h: New file.
1774 * score-inst.h: New file.
1775
c2f0420e
L		 17762006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1777
1778 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1779 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1780 movdq2q and movq2dq.
1781
050dfa73
MM		 17822006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1783 Michael Meissner <michael.meissner@amd.com>
1784
1785 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1786
15965411
L		 17872006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1788
1789 * i386.h (i386_optab): Add "nop" with memory reference.
1790
46e883c5
L		 17912006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1792
1793 * i386.h (i386_optab): Update comment for 64bit NOP.
1794
9622b051
AM		 17952006-06-06 Ben Elliston <bje@au.ibm.com>
1796 Anton Blanchard <anton@samba.org>
1797
1798 * ppc.h (PPC_OPCODE_POWER6): Define.
1799 Adjust whitespace.
1800
a9e24354
TS		 18012006-06-05 Thiemo Seufer <ths@mips.com>
1802
e4e42b45 1803 * mips.h: Improve description of MT flags.
a9e24354 1804
a596001e
RS		 18052006-05-25 Richard Sandiford <richard@codesourcery.com>
1806
1807 * m68k.h (mcf_mask): Define.
1808
d43b4baf 18092006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1810 David Ung <davidu@mips.com>
d43b4baf
TS		 1811
1812 * mips.h (enum): Add macro M_CACHE_AB.
1813
39a7806d 18142006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1815 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1816 David Ung <davidu@mips.com>
1817
1818 * mips.h: Add INSN_SMARTMIPS define.
1819
9bcd4f99 18202006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1821 David Ung <davidu@mips.com>
9bcd4f99
TS		 1822
1823 * mips.h: Defines udi bits and masks. Add description of
1824 characters which may appear in the args field of udi
1825 instructions.
1826
ef0ee844
TS		 18272006-04-26 Thiemo Seufer <ths@networkno.de>
1828
1829 * mips.h: Improve comments describing the bitfield instruction
1830 fields.
1831
f7675147
L		 18322006-04-26 Julian Brown <julian@codesourcery.com>
1833
1834 * arm.h (FPU_VFP_EXT_V3): Define constant.
1835 (FPU_NEON_EXT_V1): Likewise.
1836 (FPU_VFP_HARD): Update.
1837 (FPU_VFP_V3): Define macro.
1838 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1839
ef0ee844 18402006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1841
1842 * avr.h (AVR_ISA_PWMx): New.
1843
2da12c60
NS		 18442006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1845
1846 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1847 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1848 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1849 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1850 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1851
0715c387
PB		 18522006-03-10 Paul Brook <paul@codesourcery.com>
1853
1854 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1855
34bdd094
DA		 18562006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1857
1858 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1859 first. Correct mask of bb "B" opcode.
1860
331d2d0d
L		 18612006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1862
1863 * i386.h (i386_optab): Support Intel Merom New Instructions.
1864
62b3e311
PB		 18652006-02-24 Paul Brook <paul@codesourcery.com>
1866
1867 * arm.h: Add V7 feature bits.
1868
59cf82fe
L		 18692006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1870
1871 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1872
e74cfd16
PB		 18732006-01-31 Paul Brook <paul@codesourcery.com>
1874 Richard Earnshaw <rearnsha@arm.com>
1875
1876 * arm.h: Use ARM_CPU_FEATURE.
1877 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1878 (arm_feature_set): Change to a structure.
1879 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1880 ARM_FEATURE): New macros.
1881
5b3f8a92
HPN		 18822005-12-07 Hans-Peter Nilsson <hp@axis.com>
1883
1884 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1885 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1886 (ADD_PC_INCR_OPCODE): Don't define.
1887
cb712a9e
L		 18882005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1889
1890 PR gas/1874
1891 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1892
0499d65b
TS		 18932005-11-14 David Ung <davidu@mips.com>
1894
1895 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1896 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1897 save/restore encoding of the args field.
1898
ea5ca089
DB		 18992005-10-28 Dave Brolley <brolley@redhat.com>
1900
1901 Contribute the following changes:
1902 2005-02-16 Dave Brolley <brolley@redhat.com>
1903
1904 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1905 cgen_isa_mask_* to cgen_bitset_*.
1906 * cgen.h: Likewise.
1907
16175d96
DB		 1908 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1909
1910 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1911 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1912 (CGEN_CPU_TABLE): Make isas a ponter.
1913
1914 2003-09-29 Dave Brolley <brolley@redhat.com>
1915
1916 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1917 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1918 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1919
1920 2002-12-13 Dave Brolley <brolley@redhat.com>
1921
1922 * cgen.h (symcat.h): #include it.
1923 (cgen-bitset.h): #include it.
1924 (CGEN_ATTR_VALUE_TYPE): Now a union.
1925 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1926 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1927 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1928 * cgen-bitset.h: New file.
1929
3c9b82ba
NC		 19302005-09-30 Catherine Moore <clm@cm00re.com>
1931
1932 * bfin.h: New file.
1933
6a2375c6
JB		 19342005-10-24 Jan Beulich <jbeulich@novell.com>
1935
1936 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1937 indirect operands.
1938
c06a12f8
DA		 19392005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1940
1941 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1942 Add FLAG_STRICT to pa10 ftest opcode.
1943
4d443107
DA		 19442005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1945
1946 * hppa.h (pa_opcodes): Remove lha entries.
1947
f0a3b40f
DA		 19482005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1949
1950 * hppa.h (FLAG_STRICT): Revise comment.
1951 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1952 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1953 entries for "fdc".
1954
e210c36b
NC		 19552005-09-30 Catherine Moore <clm@cm00re.com>
1956
1957 * bfin.h: New file.
1958
1b7e1362
DA		 19592005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1960
1961 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1962
089b39de
CF		 19632005-09-06 Chao-ying Fu <fu@mips.com>
1964
1965 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1966 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1967 define.
1968 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1969 (INSN_ASE_MASK): Update to include INSN_MT.
1970 (INSN_MT): New define for MT ASE.
1971
93c34b9b
CF		 19722005-08-25 Chao-ying Fu <fu@mips.com>
1973
1974 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1975 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1976 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1977 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1978 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1979 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1980 instructions.
1981 (INSN_DSP): New define for DSP ASE.
1982
848cf006
AM		 19832005-08-18 Alan Modra <amodra@bigpond.net.au>
1984
1985 * a29k.h: Delete.
1986
36ae0db3
DJ		 19872005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1988
1989 * ppc.h (PPC_OPCODE_E300): Define.
1990
8c929562
MS		 19912005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1992
1993 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1994
f7b8cccc
DA		 19952005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1996
1997 PR gas/336
1998 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1999 and pitlb.
2000
8b5328ac
JB		 20012005-07-27 Jan Beulich <jbeulich@novell.com>
2002
2003 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2004 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2005 Add movq-s as 64-bit variants of movd-s.
2006
f417d200
DA		 20072005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2008
18b3bdfc
DA		 2009 * hppa.h: Fix punctuation in comment.
2010
f417d200
DA		 2011 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2012 implicit space-register addressing. Set space-register bits on opcodes
2013 using implicit space-register addressing. Add various missing pa20
2014 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2015 space-register addressing. Use "fE" instead of "fe" in various
2016 fstw opcodes.
2017
9a145ce6
JB		 20182005-07-18 Jan Beulich <jbeulich@novell.com>
2019
2020 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2021
90700ea2
L		 20222007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2023
2024 * i386.h (i386_optab): Support Intel VMX Instructions.
2025
48f130a8
DA		 20262005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2027
2028 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2029
30123838
JB		 20302005-07-05 Jan Beulich <jbeulich@novell.com>
2031
2032 * i386.h (i386_optab): Add new insns.
2033
47b0e7ad
NC		 20342005-07-01 Nick Clifton <nickc@redhat.com>
2035
2036 * sparc.h: Add typedefs to structure declarations.
2037
b300c311
L		 20382005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2039
2040 PR 1013
2041 * i386.h (i386_optab): Update comments for 64bit addressing on
2042 mov. Allow 64bit addressing for mov and movq.
2043
2db495be
DA		 20442005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2045
2046 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2047 respectively, in various floating-point load and store patterns.
2048
caa05036
DA		 20492005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2050
2051 * hppa.h (FLAG_STRICT): Correct comment.
2052 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2053 PA 2.0 mneumonics when equivalent. Entries with cache control
2054 completers now require PA 1.1. Adjust whitespace.
2055
f4411256
AM		 20562005-05-19 Anton Blanchard <anton@samba.org>
2057
2058 * ppc.h (PPC_OPCODE_POWER5): Define.
2059
e172dbf8
NC		 20602005-05-10 Nick Clifton <nickc@redhat.com>
2061
2062 * Update the address and phone number of the FSF organization in
2063 the GPL notices in the following files:
2064 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2065 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2066 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2067 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2068 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2069 tic54x.h, tic80.h, v850.h, vax.h
2070
e44823cf
JB		 20712005-05-09 Jan Beulich <jbeulich@novell.com>
2072
2073 * i386.h (i386_optab): Add ht and hnt.
2074
791fe849
MK		 20752005-04-18 Mark Kettenis <kettenis@gnu.org>
2076
2077 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2078 Add xcrypt-ctr. Provide aliases without hyphens.
2079
faa7ef87
L		 20802005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2081
a63027e5
L		 2082 Moved from ../ChangeLog
2083
faa7ef87
L		 2084 2005-04-12 Paul Brook <paul@codesourcery.com>
2085 * m88k.h: Rename psr macros to avoid conflicts.
2086
2087 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2088 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2089 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2090 and ARM_ARCH_V6ZKT2.
2091
2092 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2093 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2094 Remove redundant instruction types.
2095 (struct argument): X_op - new field.
2096 (struct cst4_entry): Remove.
2097 (no_op_insn): Declare.
2098
2099 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2100 * crx.h (enum argtype): Rename types, remove unused types.
2101
2102 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2103 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2104 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2105 (enum operand_type): Rearrange operands, edit comments.
2106 replace us<N> with ui<N> for unsigned immediate.
2107 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2108 displacements (respectively).
2109 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2110 (instruction type): Add NO_TYPE_INS.
2111 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2112 (operand_entry): New field - 'flags'.
2113 (operand flags): New.
2114
2115 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2116 * crx.h (operand_type): Remove redundant types i3, i4,
2117 i5, i8, i12.
2118 Add new unsigned immediate types us3, us4, us5, us16.
2119
bc4bd9ab
MK		 21202005-04-12 Mark Kettenis <kettenis@gnu.org>
2121
2122 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2123 adjust them accordingly.
2124
373ff435
JB		 21252005-04-01 Jan Beulich <jbeulich@novell.com>
2126
2127 * i386.h (i386_optab): Add rdtscp.
2128
4cc91dba
L		 21292005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2130
2131 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2132 between memory and segment register. Allow movq for moving between
2133 general-purpose register and segment register.
4cc91dba 2134
9ae09ff9
JB		 21352005-02-09 Jan Beulich <jbeulich@novell.com>
2136
2137 PR gas/707
2138 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2139 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2140 fnstsw.
2141
638e7a64
NS		 21422006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2143
2144 * m68k.h (m68008, m68ec030, m68882): Remove.
2145 (m68k_mask): New.
2146 (cpu_m68k, cpu_cf): New.
2147 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2148 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2149
90219bd0
AO		 21502005-01-25 Alexandre Oliva <aoliva@redhat.com>
2151
2152 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2153 * cgen.h (enum cgen_parse_operand_type): Add
2154 CGEN_PARSE_OPERAND_SYMBOLIC.
2155
239cb185
FF		 21562005-01-21 Fred Fish <fnf@specifixinc.com>
2157
2158 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2159 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2160 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2161
dc9a9f39
FF		 21622005-01-19 Fred Fish <fnf@specifixinc.com>
2163
2164 * mips.h (struct mips_opcode): Add new pinfo2 member.
2165 (INSN_ALIAS): New define for opcode table entries that are
2166 specific instances of another entry, such as 'move' for an 'or'
2167 with a zero operand.
2168 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2169 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2170
98e7aba8
ILT		 21712004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2172
2173 * mips.h (CPU_RM9000): Define.
2174 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2175
37edbb65
JB		 21762004-11-25 Jan Beulich <jbeulich@novell.com>
2177
2178 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2179 to/from test registers are illegal in 64-bit mode. Add missing
2180 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2181 (previously one had to explicitly encode a rex64 prefix). Re-enable
2182 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2183 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2184
21852004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2186
2187 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2188 available only with SSE2. Change the MMX additions introduced by SSE
2189 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2190 instructions by their now designated identifier (since combining i686
2191 and 3DNow! does not really imply 3DNow!A).
2192
f5c7edf4
AM		 21932004-11-19 Alan Modra <amodra@bigpond.net.au>
2194
2195 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2196 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2197
7499d566
NC		 21982004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2199 Vineet Sharma <vineets@noida.hcltech.com>
2200
2201 * maxq.h: New file: Disassembly information for the maxq port.
2202
bcb9eebe
L		 22032004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2204
2205 * i386.h (i386_optab): Put back "movzb".
2206
94bb3d38
HPN		 22072004-11-04 Hans-Peter Nilsson <hp@axis.com>
2208
2209 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2210 comments. Remove member cris_ver_sim. Add members
2211 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2212 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2213 (struct cris_support_reg, struct cris_cond15): New types.
2214 (cris_conds15): Declare.
2215 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2216 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2217 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2218 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2219 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2220 SIZE_FIELD_UNSIGNED.
2221
37edbb65 22222004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2223
2224 * i386.h (sldx_Suf): Remove.
2225 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2226 (q_FP): Define, implying no REX64.
2227 (x_FP, sl_FP): Imply FloatMF.
2228 (i386_optab): Split reg and mem forms of moving from segment registers
2229 so that the memory forms can ignore the 16-/32-bit operand size
2230 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2231 all non-floating-point instructions. Unite 32- and 64-bit forms of
2232 movsx, movzx, and movd. Adjust floating point operations for the above
2233 changes to the *FP macros. Add DefaultSize to floating point control
2234 insns operating on larger memory ranges. Remove left over comments
2235 hinting at certain insns being Intel-syntax ones where the ones
2236 actually meant are already gone.
2237
48c9f030
NC		 22382004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2239
2240 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2241 instruction type.
2242
0dd132b6
NC		 22432004-09-30 Paul Brook <paul@codesourcery.com>
2244
2245 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2246 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2247
23794b24
MM		 22482004-09-11 Theodore A. Roth <troth@openavr.org>
2249
2250 * avr.h: Add support for
2251 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2252
2a309db0
AM		 22532004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2254
2255 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2256
b18c562e
NC		 22572004-08-24 Dmitry Diky <diwil@spec.ru>
2258
2259 * msp430.h (msp430_opc): Add new instructions.
2260 (msp430_rcodes): Declare new instructions.
2261 (msp430_hcodes): Likewise..
2262
45d313cd
NC		 22632004-08-13 Nick Clifton <nickc@redhat.com>
2264
2265 PR/301
2266 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2267 processors.
2268
30d1c836
ML		 22692004-08-30 Michal Ludvig <mludvig@suse.cz>
2270
2271 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2272
9a45f1c2
L		 22732004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2274
2275 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2276
543613e9
NC		 22772004-07-21 Jan Beulich <jbeulich@novell.com>
2278
2279 * i386.h: Adjust instruction descriptions to better match the
2280 specification.
2281
b781e558
RE		 22822004-07-16 Richard Earnshaw <rearnsha@arm.com>
2283
2284 * arm.h: Remove all old content. Replace with architecture defines
2285 from gas/config/tc-arm.c.
2286
8577e690
AS		 22872004-07-09 Andreas Schwab <schwab@suse.de>
2288
2289 * m68k.h: Fix comment.
2290
1fe1f39c
NC		 22912004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2292
2293 * crx.h: New file.
2294
1d9f512f
AM		 22952004-06-24 Alan Modra <amodra@bigpond.net.au>
2296
2297 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2298
be8c092b
NC		 22992004-05-24 Peter Barada <peter@the-baradas.com>
2300
2301 * m68k.h: Add 'size' to m68k_opcode.
2302
6b6e92f4
NC		 23032004-05-05 Peter Barada <peter@the-baradas.com>
2304
2305 * m68k.h: Switch from ColdFire chip name to core variant.
2306
23072004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2308
2309 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2310 descriptions for new EMAC cases.
2311 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2312 handle Motorola MAC syntax.
2313 Allow disassembly of ColdFire V4e object files.
2314
fdd12ef3
AM		 23152004-03-16 Alan Modra <amodra@bigpond.net.au>
2316
2317 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2318
3922a64c
L		 23192004-03-12 Jakub Jelinek <jakub@redhat.com>
2320
2321 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2322
1f45d988
ML		 23232004-03-12 Michal Ludvig <mludvig@suse.cz>
2324
2325 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2326
0f10071e
ML		 23272004-03-12 Michal Ludvig <mludvig@suse.cz>
2328
2329 * i386.h (i386_optab): Added xstore/xcrypt insns.
2330
3255318a
NC		 23312004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2332
2333 * h8300.h (32bit ldc/stc): Add relaxing support.
2334
ca9a79a1 23352004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2336
ca9a79a1
NC		 2337 * h8300.h (BITOP): Pass MEMRELAX flag.
2338
875a0b14
NC		 23392004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2340
2341 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2342 except for the H8S.
252b5132 2343
c9e214e5 2344For older changes see ChangeLog-9103
252b5132 2345\f
b90efa5b 2346Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2347
2348Copying and distribution of this file, with or without modification,
2349are permitted in any medium without royalty provided the copyright
2350notice and this notice are preserved.
2351
252b5132 2352Local Variables:
c9e214e5
AM		 2353mode: change-log
2354left-margin: 8
2355fill-column: 74
252b5132
RH		 2356version-control: never
2357End:
GDB Binutils - Deliverables
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