projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Add support for files that contain multiple symbol index tables. Fixes PR 15835
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
f04265ec
NC		 12015-09-22 Nick Clifton <nickc@redhat.com>
2
3 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
4
7bdf96ef
NC		 52015-09-09 Daniel Santos <daniel.santos@pobox.com>
6
7 * visium.h (gen_reg_table): Make static.
8 (fp_reg_table): Likewise.
9 (cc_table): Likewise.
10
f33026a9
MW		 112015-07-20 Matthew Wahab <matthew.wahab@arm.com>
12
13 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
14 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
15 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
16 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
17
ef5a96d5
AM		 182015-07-03 Alan Modra <amodra@gmail.com>
19
20 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
21
c8c8175b
SL		 222015-07-01 Sandra Loosemore <sandra@codesourcery.com>
23 Cesar Philippidis <cesar@codesourcery.com>
24
25 * nios2.h (enum iw_format_type): Add R2 formats.
26 (enum overflow_type): Add signed_immed12_overflow and
27 enumeration_overflow for R2.
28 (struct nios2_opcode): Document new argument letters for R2.
29 (REG_3BIT, REG_LDWM, REG_POP): Define.
30 (includes): Include nios2r2.h.
31 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
32 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
33 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
34 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
35 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
36 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
37 Declare.
38 * nios2r2.h: New file.
39
11a0cf2e
PB		 402015-06-19 Peter Bergner <bergner@vnet.ibm.com>
41
42 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
43 (ppc_optional_operand_value): New inline function.
44
88f0ea34
MW		 452015-06-04 Matthew Wahab <matthew.wahab@arm.com>
46
47 * aarch64.h (AARCH64_V8_1): New.
48
a5932920
MW		 492015-06-03 Matthew Wahab <matthew.wahab@arm.com>
50
51 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
52 (ARM_ARCH_V8_1A): New.
53 (ARM_ARCH_V8_1A_FP): New.
54 (ARM_ARCH_V8_1A_SIMD): New.
55 (ARM_ARCH_V8_1A_CRYPTOV1): New.
56 (ARM_FEATURE_CORE): New.
57
ddfded2f
MW		 582015-06-02 Matthew Wahab <matthew.wahab@arm.com>
59
60 * arm.h (ARM_EXT2_PAN): New.
61 (ARM_FEATURE_CORE_HIGH): New.
62
1af1dd51
MW		 632015-06-02 Matthew Wahab <matthew.wahab@arm.com>
64
65 * arm.h (ARM_FEATURE_ALL): New.
66
9e1f0fa7
MW		 672015-06-02 Matthew Wahab <matthew.wahab@arm.com>
68
69 * aarch64.h (AARCH64_FEATURE_RDMA): New.
70
290806fd
MW		 712015-06-02 Matthew Wahab <matthew.wahab@arm.com>
72
73 * aarch64.h (AARCH64_FEATURE_LOR): New.
74
f21cce2c
MW		 752015-06-01 Matthew Wahab <matthew.wahab@arm.com>
76
77 * aarch64.h (AARCH64_FEATURE_PAN): New.
78 (aarch64_sys_reg_supported_p): Declare.
79 (aarch64_pstatefield_supported_p): Declare.
80
0952813b
DD		 812015-04-30 DJ Delorie <dj@redhat.com>
82
83 * rl78.h (RL78_Dis_Isa): New.
84 (rl78_decode_opcode): Add ISA parameter.
85
823d2571
TG		 862015-03-24 Terry Guo <terry.guo@arm.com>
87
88 * arm.h (arm_feature_set): Extended to provide more available bits.
89 (ARM_ANY): Updated to follow above new definition.
90 (ARM_CPU_HAS_FEATURE): Likewise.
91 (ARM_CPU_IS_ANY): Likewise.
92 (ARM_MERGE_FEATURE_SETS): Likewise.
93 (ARM_CLEAR_FEATURE): Likewise.
94 (ARM_FEATURE): Likewise.
95 (ARM_FEATURE_COPY): New macro.
96 (ARM_FEATURE_EQUAL): Likewise.
97 (ARM_FEATURE_ZERO): Likewise.
98 (ARM_FEATURE_CORE_EQUAL): Likewise.
99 (ARM_FEATURE_LOW): Likewise.
100 (ARM_FEATURE_CORE_LOW): Likewise.
101 (ARM_FEATURE_CORE_COPROC): Likewise.
102
f63c1776
PA		 1032015-02-19 Pedro Alves <palves@redhat.com>
104
105 * cgen.h [__cplusplus]: Wrap in extern "C".
106 * msp430-decode.h [__cplusplus]: Likewise.
107 * nios2.h [__cplusplus]: Likewise.
108 * rl78.h [__cplusplus]: Likewise.
109 * rx.h [__cplusplus]: Likewise.
110 * tilegx.h [__cplusplus]: Likewise.
111
3f8107ab
AM		 1122015-01-28 James Bowman <james.bowman@ftdichip.com>
113
114 * ft32.h: New file.
115
1e2e8c52
AK		 1162015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
117
118 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
119
b90efa5b
AM		 1202015-01-01 Alan Modra <amodra@gmail.com>
121
122 Update year range in copyright notice of all files.
123
bffb6004
AG		 1242014-12-27 Anthony Green <green@moxielogic.com>
125
126 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
127 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
128
1945cfa5
EB		 1292014-12-06 Eric Botcazou <ebotcazou@adacore.com>
130
131 * visium.h: New file.
132
d306ce58
SL		 1332014-11-28 Sandra Loosemore <sandra@codesourcery.com>
134
135 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
136 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
137 (NIOS2_INSN_OPTARG): Renumber.
138
b4714c7c
SL		 1392014-11-06 Sandra Loosemore <sandra@codesourcery.com>
140
141 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
142 declaration. Fix obsolete comment.
143
96ba4233
SL		 1442014-10-23 Sandra Loosemore <sandra@codesourcery.com>
145
146 * nios2.h (enum iw_format_type): New.
147 (struct nios2_opcode): Update comments. Add size and format fields.
148 (NIOS2_INSN_OPTARG): New.
149 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
150 (struct nios2_reg): Add regtype field.
151 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
152 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
153 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
154 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
155 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
156 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
157 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
158 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
159 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
160 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
161 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
162 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
163 (OP_MASK_OP, OP_SH_OP): Delete.
164 (OP_MASK_IOP, OP_SH_IOP): Delete.
165 (OP_MASK_IRD, OP_SH_IRD): Delete.
166 (OP_MASK_IRT, OP_SH_IRT): Delete.
167 (OP_MASK_IRS, OP_SH_IRS): Delete.
168 (OP_MASK_ROP, OP_SH_ROP): Delete.
169 (OP_MASK_RRD, OP_SH_RRD): Delete.
170 (OP_MASK_RRT, OP_SH_RRT): Delete.
171 (OP_MASK_RRS, OP_SH_RRS): Delete.
172 (OP_MASK_JOP, OP_SH_JOP): Delete.
173 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
174 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
175 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
176 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
177 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
178 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
179 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
180 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
181 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
182 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
183 (OP_MASK_<insn>, OP_MASK): Delete.
184 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
185 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
186 Include nios2r1.h to define new instruction opcode constants
187 and accessors.
188 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
189 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
190 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
191 (NUMOPCODES, NUMREGISTERS): Delete.
192 * nios2r1.h: New file.
193
0b6be415
JM		 1942014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
195
196 * sparc.h (HWCAP2_VIS3B): Documentation improved.
197
3d68f91c
JM		 1982014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
199
200 * sparc.h (sparc_opcode): new field `hwcaps2'.
201 (HWCAP2_FJATHPLUS): New define.
202 (HWCAP2_VIS3B): Likewise.
203 (HWCAP2_ADP): Likewise.
204 (HWCAP2_SPARC5): Likewise.
205 (HWCAP2_MWAIT): Likewise.
206 (HWCAP2_XMPMUL): Likewise.
207 (HWCAP2_XMONT): Likewise.
208 (HWCAP2_NSEC): Likewise.
209 (HWCAP2_FJATHHPC): Likewise.
210 (HWCAP2_FJDES): Likewise.
211 (HWCAP2_FJAES): Likewise.
212 Document the new operand kind `{', corresponding to the mcdper
213 ancillary state register.
214 Document the new operand kind }, which represents frsd floating
215 point registers (double precision) which must be the same than
216 frs1 in its containing instruction.
217
40c7a7cb
KLC		 2182014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
219
72f4393d 220 * nds32.h: Add new opcode declaration.
40c7a7cb 221
7361da2c
AB		 2222014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
223 Matthew Fortune <matthew.fortune@imgtec.com>
224
225 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
226 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
227 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
228 +I, +O, +R, +:, +\, +", +;
229 (mips_check_prev_operand): New struct.
230 (INSN2_FORBIDDEN_SLOT): New define.
231 (INSN_ISA32R6): New define.
232 (INSN_ISA64R6): New define.
233 (INSN_UPTO32R6): New define.
234 (INSN_UPTO64R6): New define.
235 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
236 (ISA_MIPS32R6): New define.
237 (ISA_MIPS64R6): New define.
238 (CPU_MIPS32R6): New define.
239 (CPU_MIPS64R6): New define.
240 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
241
ee804238
JW		 2422014-09-03 Jiong Wang <jiong.wang@arm.com>
243
244 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
245 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
246 (aarch64_insn_class): Add lse_atomic.
247 (F_LSE_SZ): New field added.
248 (opcode_has_special_coder): Recognize F_LSE_SZ.
249
5575639b
MR		 2502014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
251
252 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
253 over to `+J'.
254
43885403
MF		 2552014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
256
257 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
258 (INSN_LOAD_COPROC): New define.
259 (INSN_COPROC_MOVE_DELAY): Rename to...
260 (INSN_COPROC_MOVE): New define.
261
f36e8886 2622014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 263 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
264 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
265 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 266
267 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
268 (AVR_ISA_2xxxa): Define ISA without LPM.
269 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
270 Add doc for contraint used in 16 bit lds/sts.
271 Adjust ISA group for icall, ijmp, pop and push.
272 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
273
00b32ff2
NC		 2742014-05-19 Nick Clifton <nickc@redhat.com>
275
276 * msp430.h (struct msp430_operand_s): Add vshift field.
277
ae52f483
AB		 2782014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
279
280 * mips.h (INSN_ISA_MASK): Updated.
281 (INSN_ISA32R3): New define.
282 (INSN_ISA32R5): New define.
283 (INSN_ISA64R3): New define.
284 (INSN_ISA64R5): New define.
285 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
286 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
287 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
288 mips64r5.
289 (INSN_UPTO32R3): New define.
290 (INSN_UPTO32R5): New define.
291 (INSN_UPTO64R3): New define.
292 (INSN_UPTO64R5): New define.
293 (ISA_MIPS32R3): New define.
294 (ISA_MIPS32R5): New define.
295 (ISA_MIPS64R3): New define.
296 (ISA_MIPS64R5): New define.
297 (CPU_MIPS32R3): New define.
298 (CPU_MIPS32R5): New define.
299 (CPU_MIPS64R3): New define.
300 (CPU_MIPS64R5): New define.
301
3efe9ec5
RS		 3022014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
303
304 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
305
73589c9d
CS		 3062014-04-22 Christian Svensson <blue@cmd.nu>
307
308 * or32.h: Delete.
309
4b95cf5c
AM		 3102014-03-05 Alan Modra <amodra@gmail.com>
311
312 Update copyright years.
313
e269fea7
AB		 3142013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
315
316 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
317 microMIPS.
318
35c08157
KLC		 3192013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
320 Wei-Cheng Wang <cole945@gmail.com>
321
322 * nds32.h: New file for Andes NDS32.
323
594d8fa8
MF		 3242013-12-07 Mike Frysinger <vapier@gentoo.org>
325
326 * bfin.h: Remove +x file mode.
327
87b8eed7
YZ		 3282013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
329
330 * aarch64.h (aarch64_pstatefields): Change element type to
331 aarch64_sys_reg.
332
c9fb6e58
YZ		 3332013-11-18 Renlin Li <Renlin.Li@arm.com>
334
335 * arm.h (ARM_AEXT_V7VE): New define.
336 (ARM_ARCH_V7VE): New define.
337 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
338
a203d9b7
YZ		 3392013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
340
341 Revert
342
343 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
344
345 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
346 (aarch64_sys_reg_writeonly_p): Ditto.
347
75468c93
YZ		 3482013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
349
350 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
351 (aarch64_sys_reg_writeonly_p): Ditto.
352
49eec193
YZ		 3532013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
354
355 * aarch64.h (aarch64_sys_reg): New typedef.
356 (aarch64_sys_regs): Change to define with the new type.
357 (aarch64_sys_reg_deprecated_p): Declare.
358
68a64283
YZ		 3592013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
360
361 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
362 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
363
387a82f1
CF		 3642013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
365
366 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
367 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
368 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
369 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
370 For MIPS, update extension character sequences after +.
371 (ASE_MSA): New define.
372 (ASE_MSA64): New define.
373 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
374 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
375 For microMIPS, update extension character sequences after +.
376
9aff4b7a
NC		 3772013-08-23 Yuri Chornoivan <yurchor@ukr.net>
378
379 PR binutils/15834
380 * i960.h: Fix typos.
381
e423441d
RS		 3822013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
383
384 * mips.h: Remove references to "+I" and imm2_expr.
385
5e0dc5ba
RS		 3862013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
387
388 * mips.h (M_DEXT, M_DINS): Delete.
389
0f35dbc4
RS		 3902013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
391
392 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
393 (mips_optional_operand_p): New function.
394
14daeee3
RS		 3952013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
396 Richard Sandiford <rdsandiford@googlemail.com>
397
398 * mips.h: Document new VU0 operand characters.
399 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
400 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
401 (OP_REG_R5900_ACC): New mips_reg_operand_types.
402 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
403 (mips_vu0_channel_mask): Declare.
404
3ccad066
RS		 4052013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
406
407 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
408 (mips_int_operand_min, mips_int_operand_max): New functions.
409 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
410
fc76e730
RS		 4112013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
412
413 * mips.h (mips_decode_reg_operand): New function.
414 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
415 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
416 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
417 New macros.
418 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
419 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
420 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
421 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
422 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
423 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
424 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
425 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
426 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
427 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
428 macros to cover the gaps.
429 (INSN2_MOD_SP): Replace with...
430 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
431 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
432 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
433 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
434 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
435 Delete.
436
26545944
RS		 4372013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
438
439 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
440 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
441 (MIPS16_INSN_COND_BRANCH): Delete.
442
7e8b059b
L		 4432013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
444 Kirill Yukhin <kirill.yukhin@intel.com>
445 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
446
447 * i386.h (BND_PREFIX_OPCODE): New.
448
c3c07478
RS		 4492013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
450
451 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
452 OP_SAVE_RESTORE_LIST.
453 (decode_mips16_operand): Declare.
454
ab902481
RS		 4552013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
456
457 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
458 (mips_operand, mips_int_operand, mips_mapped_int_operand)
459 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
460 (mips_pcrel_operand): New structures.
461 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
462 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
463 (decode_mips_operand, decode_micromips_operand): Declare.
464
cc537e56
RS		 4652013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
466
467 * mips.h: Document MIPS16 "I" opcode.
468
f2ae14a1
RS		 4692013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
470
471 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
472 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
473 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
474 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
475 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
476 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
477 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
478 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
479 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
480 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
481 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
482 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
483 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
484 Rename to...
485 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
486 (M_USD_AB): ...these.
487
5c324c16
RS		 4882013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
489
490 * mips.h: Remove documentation of "[" and "]". Update documentation
491 of "k" and the MDMX formats.
492
23e69e47
RS		 4932013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
494
495 * mips.h: Update documentation of "+s" and "+S".
496
27c5c572
RS		 4972013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
498
499 * mips.h: Document "+i".
500
e76ff5ab
RS		 5012013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
502
503 * mips.h: Remove "mi" documentation. Update "mh" documentation.
504 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
505 Delete.
506 (INSN2_WRITE_GPR_MHI): Rename to...
507 (INSN2_WRITE_GPR_MH): ...this.
508
fa7616a4
RS		 5092013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
510
511 * mips.h: Remove documentation of "+D" and "+T".
512
18870af7
RS		 5132013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
514
515 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
516 Use "source" rather than "destination" for microMIPS "G".
517
833794fc
MR		 5182013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
519
520 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
521 values.
522
c3678916
RS		 5232013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
524
525 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
526
7f3c4072
CM		 5272013-06-17 Catherine Moore <clm@codesourcery.com>
528 Maciej W. Rozycki <macro@codesourcery.com>
529 Chao-Ying Fu <fu@mips.com>
530
531 * mips.h (OP_SH_EVAOFFSET): Define.
532 (OP_MASK_EVAOFFSET): Define.
533 (INSN_ASE_MASK): Delete.
534 (ASE_EVA): Define.
535 (M_CACHEE_AB, M_CACHEE_OB): New.
536 (M_LBE_OB, M_LBE_AB): New.
537 (M_LBUE_OB, M_LBUE_AB): New.
538 (M_LHE_OB, M_LHE_AB): New.
539 (M_LHUE_OB, M_LHUE_AB): New.
540 (M_LLE_AB, M_LLE_OB): New.
541 (M_LWE_OB, M_LWE_AB): New.
542 (M_LWLE_AB, M_LWLE_OB): New.
543 (M_LWRE_AB, M_LWRE_OB): New.
544 (M_PREFE_AB, M_PREFE_OB): New.
545 (M_SCE_AB, M_SCE_OB): New.
546 (M_SBE_OB, M_SBE_AB): New.
547 (M_SHE_OB, M_SHE_AB): New.
548 (M_SWE_OB, M_SWE_AB): New.
549 (M_SWLE_AB, M_SWLE_OB): New.
550 (M_SWRE_AB, M_SWRE_OB): New.
551 (MICROMIPSOP_SH_EVAOFFSET): Define.
552 (MICROMIPSOP_MASK_EVAOFFSET): Define.
553
0c8fe7cf
SL		 5542013-06-12 Sandra Loosemore <sandra@codesourcery.com>
555
556 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
557
c77c0862
RS		 5582013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
559
560 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
561
b015e599
AP		 5622013-05-09 Andrew Pinski <apinski@cavium.com>
563
564 * mips.h (OP_MASK_CODE10): Correct definition.
565 (OP_SH_CODE10): Likewise.
566 Add a comment that "+J" is used now for OP_*CODE10.
567 (INSN_ASE_MASK): Update.
568 (INSN_VIRT): New macro.
569 (INSN_VIRT64): New macro
570
13761a11
NC		 5712013-05-02 Nick Clifton <nickc@redhat.com>
572
573 * msp430.h: Add patterns for MSP430X instructions.
574
0afd1215
DM		 5752013-04-06 David S. Miller <davem@davemloft.net>
576
577 * sparc.h (F_PREFERRED): Define.
578 (F_PREF_ALIAS): Define.
579
41702d50
NC		 5802013-04-03 Nick Clifton <nickc@redhat.com>
581
582 * v850.h (V850_INVERSE_PCREL): Define.
583
e21e1a51
NC		 5842013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
585
586 PR binutils/15068
587 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
588
51dcdd4d
NC		 5892013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
590
591 PR binutils/15068
592 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
593 Add 16-bit opcodes.
594 * tic6xc-opcode-table.h: Add 16-bit insns.
595 * tic6x.h: Add support for 16-bit insns.
596
81f5558e
NC		 5972013-03-21 Michael Schewe <michael.schewe@gmx.net>
598
599 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
600 and mov.b/w/l Rs,@(d:32,ERd).
601
165546ad
NC		 6022013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
603
604 PR gas/15082
605 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
606 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
607 tic6x_operand_xregpair operand coding type.
608 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
609 opcode field, usu ORXREGD1324 for the src2 operand and remove the
610 TIC6X_FLAG_NO_CROSS.
611
795b8e6b
NC		 6122013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
613
614 PR gas/15095
615 * tic6x.h (enum tic6x_coding_method): Add
616 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
617 separately the msb and lsb of a register pair. This is needed to
618 encode the opcodes in the same way as TI assembler does.
619 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
620 and rsqrdp opcodes to use the new field coding types.
621
dd5181d5
KT		 6222013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
623
624 * arm.h (CRC_EXT_ARMV8): New constant.
625 (ARCH_CRC_ARMV8): New macro.
626
e60bb1dd
YZ		 6272013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
628
629 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
630
36591ba1 6312013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 632 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 633
634 Based on patches from Altera Corporation.
635
636 * nios2.h: New file.
637
e30181a5
YZ		 6382013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
639
640 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
641
0c9573f4
NC		 6422013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
643
644 PR gas/15069
645 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
646
981dc7f1
NC		 6472013-01-24 Nick Clifton <nickc@redhat.com>
648
649 * v850.h: Add e3v5 support.
650
f5555712
YZ		 6512013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
652
653 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
654
5817ffd1
PB		 6552013-01-10 Peter Bergner <bergner@vnet.ibm.com>
656
657 * ppc.h (PPC_OPCODE_POWER8): New define.
658 (PPC_OPCODE_HTM): Likewise.
659
a3c62988
NC		 6602013-01-10 Will Newton <will.newton@imgtec.com>
661
662 * metag.h: New file.
663
73335eae
NC		 6642013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
665
666 * cr16.h (make_instruction): Rename to cr16_make_instruction.
667 (match_opcode): Rename to cr16_match_opcode.
668
e407c74b
NC		 6692013-01-04 Juergen Urban <JuergenUrban@gmx.de>
670
671 * mips.h: Add support for r5900 instructions including lq and sq.
672
bab4becb
NC		 6732013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
674
675 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
676 (make_instruction,match_opcode): Added function prototypes.
677 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
678
776fc418
AM		 6792012-11-23 Alan Modra <amodra@gmail.com>
680
681 * ppc.h (ppc_parse_cpu): Update prototype.
682
f05682d4
DA		 6832012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
684
685 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
686 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
687
cfc72779
AK		 6882012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
689
690 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
691
b3e14eda
L		 6922012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
693
694 * ia64.h (ia64_opnd): Add new operand types.
695
2c63854f
DM		 6962012-08-21 David S. Miller <davem@davemloft.net>
697
698 * sparc.h (F3F4): New macro.
699
a06ea964 7002012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 701 Laurent Desnogues <laurent.desnogues@arm.com>
702 Jim MacArthur <jim.macarthur@arm.com>
703 Marcus Shawcroft <marcus.shawcroft@arm.com>
704 Nigel Stephens <nigel.stephens@arm.com>
705 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
706 Richard Earnshaw <rearnsha@arm.com>
707 Sofiane Naci <sofiane.naci@arm.com>
708 Tejas Belagod <tejas.belagod@arm.com>
709 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 710
711 * aarch64.h: New file.
712
35d0a169 7132012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 714 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 715
716 * mips.h (mips_opcode): Add the exclusions field.
717 (OPCODE_IS_MEMBER): Remove macro.
718 (cpu_is_member): New inline function.
719 (opcode_is_member): Likewise.
720
03f66e8a 7212012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 722 Catherine Moore <clm@codesourcery.com>
723 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 724
725 * mips.h: Document microMIPS DSP ASE usage.
726 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
727 microMIPS DSP ASE support.
728 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
729 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
730 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
731 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
732 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
733 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
734 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
735
9d7b4c23
MR		 7362012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
737
738 * mips.h: Fix a typo in description.
739
76e879f8
NC		 7402012-06-07 Georg-Johann Lay <avr@gjlay.de>
741
742 * avr.h: (AVR_ISA_XCH): New define.
743 (AVR_ISA_XMEGA): Use it.
744 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
745
6927f982
NC		 7462012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
747
748 * m68hc11.h: Add XGate definitions.
749 (struct m68hc11_opcode): Add xg_mask field.
750
b9c361e0
JL		 7512012-05-14 Catherine Moore <clm@codesourcery.com>
752 Maciej W. Rozycki <macro@codesourcery.com>
753 Rhonda Wittels <rhonda@codesourcery.com>
754
6927f982 755 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 756 (PPC_OP_SA): New macro.
757 (PPC_OP_SE_VLE): New macro.
758 (PPC_OP): Use a variable shift amount.
759 (powerpc_operand): Update comments.
760 (PPC_OPSHIFT_INV): New macro.
761 (PPC_OPERAND_CR): Replace with...
762 (PPC_OPERAND_CR_BIT): ...this and
763 (PPC_OPERAND_CR_REG): ...this.
764
765
f6c1a2d5
NC		 7662012-05-03 Sean Keys <skeys@ipdatasys.com>
767
768 * xgate.h: Header file for XGATE assembler.
769
ec668d69
DM		 7702012-04-27 David S. Miller <davem@davemloft.net>
771
6cda1326
DM		 772 * sparc.h: Document new arg code' )' for crypto RS3
773 immediates.
774
ec668d69
DM		 775 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
776 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
777 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
778 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
779 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
780 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
781 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
782 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
783 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
784 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
785 HWCAP_CBCOND, HWCAP_CRC32): New defines.
786
aea77599
AM		 7872012-03-10 Edmar Wienskoski <edmar@freescale.com>
788
789 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
790
1f42f8b3
AM		 7912012-02-27 Alan Modra <amodra@gmail.com>
792
793 * crx.h (cst4_map): Update declaration.
794
6f7be959
WL		 7952012-02-25 Walter Lee <walt@tilera.com>
796
797 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
798 TILEGX_OPC_LD_TLS.
799 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
800 TILEPRO_OPC_LW_TLS_SN.
801
42164a71
L		 8022012-02-08 H.J. Lu <hongjiu.lu@intel.com>
803
804 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
805 (XRELEASE_PREFIX_OPCODE): Likewise.
806
432233b3 8072011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 808 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 809
810 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
811 (INSN_OCTEON2): New macro.
812 (CPU_OCTEON2): New macro.
813 (OPCODE_IS_MEMBER): Add Octeon2.
814
dd6a37e7
AP		 8152011-11-29 Andrew Pinski <apinski@cavium.com>
816
817 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
818 (INSN_OCTEONP): New macro.
819 (CPU_OCTEONP): New macro.
820 (OPCODE_IS_MEMBER): Add Octeon+.
821 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
822
99c513f6
DD		 8232011-11-01 DJ Delorie <dj@redhat.com>
824
825 * rl78.h: New file.
826
26f85d7a
MR		 8272011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
828
829 * mips.h: Fix a typo in description.
830
9e8c70f9
DM		 8312011-09-21 David S. Miller <davem@davemloft.net>
832
833 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
834 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
835 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
836 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
837
dec0624d 8382011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 839 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 840
841 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
842 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
843 (INSN_ASE_MASK): Add the MCU bit.
844 (INSN_MCU): New macro.
845 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
846 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
847
2b0c8b40
MR		 8482011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
849
850 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
851 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
852 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
853 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
854 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
855 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
856 (INSN2_READ_GPR_MMN): Likewise.
857 (INSN2_READ_FPR_D): Change the bit used.
858 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
859 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
860 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
861 (INSN2_COND_BRANCH): Likewise.
862 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
863 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
864 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
865 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
866 (INSN2_MOD_GPR_MN): Likewise.
867
ea783ef3
DM		 8682011-08-05 David S. Miller <davem@davemloft.net>
869
870 * sparc.h: Document new format codes '4', '5', and '('.
871 (OPF_LOW4, RS3): New macros.
872
7c176fa8
MR		 8732011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
874
875 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
876 order of flags documented.
877
2309ddf2
MR		 8782011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
879
880 * mips.h: Clarify the description of microMIPS instruction
881 manipulation macros.
882 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
883
df58fc94 8842011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 885 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 886
887 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
888 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
889 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
890 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
891 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
892 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
893 (OP_MASK_RS3, OP_SH_RS3): Likewise.
894 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
895 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
896 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
897 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
898 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
899 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
900 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
901 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
902 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
903 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
904 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
905 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
906 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
907 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
908 (INSN_WRITE_GPR_S): New macro.
909 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
910 (INSN2_READ_FPR_D): Likewise.
911 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
912 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
913 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
914 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
915 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
916 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
917 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
918 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
919 (CPU_MICROMIPS): New macro.
920 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
921 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
922 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
923 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
924 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
925 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
926 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
927 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
928 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
929 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
930 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
931 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
932 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
933 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
934 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
935 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
936 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
937 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
938 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
939 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
940 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
941 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
942 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
943 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
944 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
945 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
946 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
947 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
948 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
949 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
950 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
951 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
952 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
953 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
954 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
955 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
956 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
957 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
958 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
959 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
960 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
961 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
962 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
963 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
964 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
965 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
966 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
967 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
968 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
969 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
970 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
971 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
972 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
973 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
974 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
975 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
976 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
977 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
978 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
979 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
980 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
981 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
982 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
983 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
984 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
985 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
986 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
987 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
988 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
989 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
990 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
991 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
992 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
993 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
994 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
995 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
996 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
997 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
998 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
999 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1000 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1001 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1002 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1003 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1004 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1005 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1006 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1007 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1008 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1009 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1010 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1011 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1012 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1013 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1014 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1015 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1016 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1017 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1018 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1019 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1020 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1021 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1022 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1023 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1024 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1025 (micromips_opcodes): New declaration.
1026 (bfd_micromips_num_opcodes): Likewise.
1027
bcd530a7
RS		 10282011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1029
1030 * mips.h (INSN_TRAP): Rename to...
1031 (INSN_NO_DELAY_SLOT): ... this.
1032 (INSN_SYNC): Remove macro.
1033
2dad5a91
EW		 10342011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1035
1036 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1037 a duplicate of AVR_ISA_SPM.
1038
5d73b1f1
NC		 10392011-07-01 Nick Clifton <nickc@redhat.com>
1040
1041 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1042
ef26d60e
MF		 10432011-06-18 Robin Getz <robin.getz@analog.com>
1044
1045 * bfin.h (is_macmod_signed): New func
1046
8fb8dca7
MF		 10472011-06-18 Mike Frysinger <vapier@gentoo.org>
1048
1049 * bfin.h (is_macmod_pmove): Add missing space before func args.
1050 (is_macmod_hmove): Likewise.
1051
aa137e4d
NC		 10522011-06-13 Walter Lee <walt@tilera.com>
1053
1054 * tilegx.h: New file.
1055 * tilepro.h: New file.
1056
3b2f0793
PB		 10572011-05-31 Paul Brook <paul@codesourcery.com>
1058
aa137e4d
NC		 1059 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1060
10612011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1062
1063 * s390.h: Replace S390_OPERAND_REG_EVEN with
1064 S390_OPERAND_REG_PAIR.
1065
10662011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1067
1068 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1069
ac7f631b
NC		 10702011-04-18 Julian Brown <julian@codesourcery.com>
1071
1072 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1073
84701018
NC		 10742011-04-11 Dan McDonald <dan@wellkeeper.com>
1075
1076 PR gas/12296
1077 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1078
8cc66334
EW		 10792011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1080
1081 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1082 New instruction set flags.
1083 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1084
3eebd5eb
MR		 10852011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1086
1087 * mips.h (M_PREF_AB): New enum value.
1088
26bb3ddd
MF		 10892011-02-12 Mike Frysinger <vapier@gentoo.org>
1090
89c0d58c
MR		 1091 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1092 M_IU): Define.
1093 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1094
dd76fcb8
MF		 10952011-02-11 Mike Frysinger <vapier@gentoo.org>
1096
1097 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1098
98d23bef
BS		 10992011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1100
1101 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1102 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1103
3c853d93
DA		 11042010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1105
1106 PR gas/11395
1107 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1108 "bb" entries.
1109
79676006
DA		 11102010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1111
1112 PR gas/11395
1113 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1114
1bec78e9
RS		 11152010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1116
1117 * mips.h: Update commentary after last commit.
1118
98675402
RS		 11192010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1120
1121 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1122 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1123 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1124
aa137e4d
NC		 11252010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1126
1127 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1128
435b94a4
RS		 11292010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1130
1131 * mips.h: Fix previous commit.
1132
d051516a
NC		 11332010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1134
1135 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1136 (INSN_LOONGSON_3A): Clear bit 31.
1137
251665fc
MGD		 11382010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1139
1140 PR gas/12198
1141 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1142 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1143 (ARM_ARCH_V6M_ONLY): New define.
1144
fd503541
NC		 11452010-11-11 Mingming Sun <mingm.sun@gmail.com>
1146
1147 * mips.h (INSN_LOONGSON_3A): Defined.
1148 (CPU_LOONGSON_3A): Defined.
1149 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1150
4469d2be
AM		 11512010-10-09 Matt Rice <ratmice@gmail.com>
1152
1153 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1154 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1155
90ec0d68
MGD		 11562010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1157
1158 * arm.h (ARM_EXT_VIRT): New define.
1159 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1160 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1161 Extensions.
1162
eea54501 11632010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1164
eea54501
MGD		 1165 * arm.h (ARM_AEXT_ADIV): New define.
1166 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1167
b2a5fbdc
MGD		 11682010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1169
1170 * arm.h (ARM_EXT_OS): New define.
1171 (ARM_AEXT_V6SM): Likewise.
1172 (ARM_ARCH_V6SM): Likewise.
1173
60e5ef9f
MGD		 11742010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1175
1176 * arm.h (ARM_EXT_MP): Add.
1177 (ARM_ARCH_V7A_MP): Likewise.
1178
73a63ccf
MF		 11792010-09-22 Mike Frysinger <vapier@gentoo.org>
1180
1181 * bfin.h: Declare pseudoChr structs/defines.
1182
ee99860a
MF		 11832010-09-21 Mike Frysinger <vapier@gentoo.org>
1184
1185 * bfin.h: Strip trailing whitespace.
1186
f9c7014e
DD		 11872010-07-29 DJ Delorie <dj@redhat.com>
1188
1189 * rx.h (RX_Operand_Type): Add TwoReg.
1190 (RX_Opcode_ID): Remove ediv and ediv2.
1191
93378652
DD		 11922010-07-27 DJ Delorie <dj@redhat.com>
1193
1194 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1195
1cd986c5
NC		 11962010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1197 Ina Pandit <ina.pandit@kpitcummins.com>
1198
1199 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1200 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1201 PROCESSOR_V850E2_ALL.
1202 Remove PROCESSOR_V850EA support.
1203 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1204 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1205 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1206 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1207 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1208 V850_OPERAND_PERCENT.
1209 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1210 V850_NOT_R0.
1211 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1212 and V850E_PUSH_POP
1213
9a2c7088
MR		 12142010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1215
1216 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1217 (MIPS16_INSN_BRANCH): Rename to...
1218 (MIPS16_INSN_COND_BRANCH): ... this.
1219
bdc70b4a
AM		 12202010-07-03 Alan Modra <amodra@gmail.com>
1221
1222 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1223 Renumber other PPC_OPCODE defines.
1224
f2bae120
AM		 12252010-07-03 Alan Modra <amodra@gmail.com>
1226
1227 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1228
360cfc9c
AM		 12292010-06-29 Alan Modra <amodra@gmail.com>
1230
1231 * maxq.h: Delete file.
1232
e01d869a
AM		 12332010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1234
1235 * ppc.h (PPC_OPCODE_E500): Define.
1236
f79e2745
CM		 12372010-05-26 Catherine Moore <clm@codesourcery.com>
1238
1239 * opcode/mips.h (INSN_MIPS16): Remove.
1240
2462afa1
JM		 12412010-04-21 Joseph Myers <joseph@codesourcery.com>
1242
1243 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1244
e4e42b45
NC		 12452010-04-15 Nick Clifton <nickc@redhat.com>
1246
1247 * alpha.h: Update copyright notice to use GPLv3.
1248 * arc.h: Likewise.
1249 * arm.h: Likewise.
1250 * avr.h: Likewise.
1251 * bfin.h: Likewise.
1252 * cgen.h: Likewise.
1253 * convex.h: Likewise.
1254 * cr16.h: Likewise.
1255 * cris.h: Likewise.
1256 * crx.h: Likewise.
1257 * d10v.h: Likewise.
1258 * d30v.h: Likewise.
1259 * dlx.h: Likewise.
1260 * h8300.h: Likewise.
1261 * hppa.h: Likewise.
1262 * i370.h: Likewise.
1263 * i386.h: Likewise.
1264 * i860.h: Likewise.
1265 * i960.h: Likewise.
1266 * ia64.h: Likewise.
1267 * m68hc11.h: Likewise.
1268 * m68k.h: Likewise.
1269 * m88k.h: Likewise.
1270 * maxq.h: Likewise.
1271 * mips.h: Likewise.
1272 * mmix.h: Likewise.
1273 * mn10200.h: Likewise.
1274 * mn10300.h: Likewise.
1275 * msp430.h: Likewise.
1276 * np1.h: Likewise.
1277 * ns32k.h: Likewise.
1278 * or32.h: Likewise.
1279 * pdp11.h: Likewise.
1280 * pj.h: Likewise.
1281 * pn.h: Likewise.
1282 * ppc.h: Likewise.
1283 * pyr.h: Likewise.
1284 * rx.h: Likewise.
1285 * s390.h: Likewise.
1286 * score-datadep.h: Likewise.
1287 * score-inst.h: Likewise.
1288 * sparc.h: Likewise.
1289 * spu-insns.h: Likewise.
1290 * spu.h: Likewise.
1291 * tic30.h: Likewise.
1292 * tic4x.h: Likewise.
1293 * tic54x.h: Likewise.
1294 * tic80.h: Likewise.
1295 * v850.h: Likewise.
1296 * vax.h: Likewise.
1297
40b36596
JM		 12982010-03-25 Joseph Myers <joseph@codesourcery.com>
1299
1300 * tic6x-control-registers.h, tic6x-insn-formats.h,
1301 tic6x-opcode-table.h, tic6x.h: New.
1302
c67a084a
NC		 13032010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1304
1305 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1306
466ef64f
AM		 13072010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1308
1309 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1310
1319d143
L		 13112010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1312
1313 * ia64.h (ia64_find_opcode): Remove argument name.
1314 (ia64_find_next_opcode): Likewise.
1315 (ia64_dis_opcode): Likewise.
1316 (ia64_free_opcode): Likewise.
1317 (ia64_find_dependency): Likewise.
1318
1fbb9298
DE		 13192009-11-22 Doug Evans <dje@sebabeach.org>
1320
1321 * cgen.h: Include bfd_stdint.h.
1322 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1323
ada65aa3
PB		 13242009-11-18 Paul Brook <paul@codesourcery.com>
1325
1326 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1327
9e3c6df6
PB		 13282009-11-17 Paul Brook <paul@codesourcery.com>
1329 Daniel Jacobowitz <dan@codesourcery.com>
1330
1331 * arm.h (ARM_EXT_V6_DSP): Define.
1332 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1333 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1334
0d734b5d
DD		 13352009-11-04 DJ Delorie <dj@redhat.com>
1336
1337 * rx.h (rx_decode_opcode) (mvtipl): Add.
1338 (mvtcp, mvfcp, opecp): Remove.
1339
62f3b8c8
PB		 13402009-11-02 Paul Brook <paul@codesourcery.com>
1341
1342 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1343 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1344 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1345 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1346 FPU_ARCH_NEON_VFP_V4): Define.
1347
ac1e9eca
DE		 13482009-10-23 Doug Evans <dje@sebabeach.org>
1349
1350 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1351 * cgen.h: Update. Improve multi-inclusion macro name.
1352
9fe54b1c
PB		 13532009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1354
1355 * ppc.h (PPC_OPCODE_476): Define.
1356
634b50f2
PB		 13572009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1358
1359 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1360
c7927a3c
NC		 13612009-09-29 DJ Delorie <dj@redhat.com>
1362
1363 * rx.h: New file.
1364
b961e85b
AM		 13652009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1366
1367 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1368
e0d602ec
BE		 13692009-09-21 Ben Elliston <bje@au.ibm.com>
1370
1371 * ppc.h (PPC_OPCODE_PPCA2): New.
1372
96d56e9f
NC		 13732009-09-05 Martin Thuresson <martin@mtme.org>
1374
1375 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1376
d3ce72d0
NC		 13772009-08-29 Martin Thuresson <martin@mtme.org>
1378
1379 * tic30.h (template): Rename type template to
1380 insn_template. Updated code to use new name.
1381 * tic54x.h (template): Rename type template to
1382 insn_template.
1383
824b28db
NH		 13842009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1385
1386 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1387
f865a31d
AG		 13882009-06-11 Anthony Green <green@moxielogic.com>
1389
1390 * moxie.h (MOXIE_F3_PCREL): Define.
1391 (moxie_form3_opc_info): Grow.
1392
0e7c7f11
AG		 13932009-06-06 Anthony Green <green@moxielogic.com>
1394
1395 * moxie.h (MOXIE_F1_M): Define.
1396
20135e4c
NC		 13972009-04-15 Anthony Green <green@moxielogic.com>
1398
1399 * moxie.h: Created.
1400
bcb012d3
DD		 14012009-04-06 DJ Delorie <dj@redhat.com>
1402
1403 * h8300.h: Add relaxation attributes to MOVA opcodes.
1404
69fe9ce5
AM		 14052009-03-10 Alan Modra <amodra@bigpond.net.au>
1406
1407 * ppc.h (ppc_parse_cpu): Declare.
1408
c3b7224a
NC		 14092009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1410
1411 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1412 and _IMM11 for mbitclr and mbitset.
1413 * score-datadep.h: Update dependency information.
1414
066be9f7
PB		 14152009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1416
1417 * ppc.h (PPC_OPCODE_POWER7): New.
1418
fedc618e
DE		 14192009-02-06 Doug Evans <dje@google.com>
1420
1421 * i386.h: Add comment regarding sse* insns and prefixes.
1422
52b6b6b9
JM		 14232009-02-03 Sandip Matte <sandip@rmicorp.com>
1424
1425 * mips.h (INSN_XLR): Define.
1426 (INSN_CHIP_MASK): Update.
1427 (CPU_XLR): Define.
1428 (OPCODE_IS_MEMBER): Update.
1429 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1430
35669430
DE		 14312009-01-28 Doug Evans <dje@google.com>
1432
1433 * opcode/i386.h: Add multiple inclusion protection.
1434 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1435 (EDI_REG_NUM): New macros.
1436 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1437 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1438 (REX_PREFIX_P): New macro.
35669430 1439
1cb0a767
PB		 14402009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1441
1442 * ppc.h (struct powerpc_opcode): New field "deprecated".
1443 (PPC_OPCODE_NOPOWER4): Delete.
1444
3aa3176b
TS		 14452008-11-28 Joshua Kinard <kumba@gentoo.org>
1446
1447 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1448 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1449
8e79c3df
CM		 14502008-11-18 Catherine Moore <clm@codesourcery.com>
1451
1452 * arm.h (FPU_NEON_FP16): New.
1453 (FPU_ARCH_NEON_FP16): New.
1454
de9a3e51
CF		 14552008-11-06 Chao-ying Fu <fu@mips.com>
1456
1457 * mips.h: Doucument '1' for 5-bit sync type.
1458
1ca35711
L		 14592008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1460
1461 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1462 IA64_RS_CR.
1463
9b4e5766
PB		 14642008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1465
1466 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1467
081ba1b3
AM		 14682008-07-30 Michael J. Eager <eager@eagercon.com>
1469
1470 * ppc.h (PPC_OPCODE_405): Define.
1471 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1472
fa452fa6
PB		 14732008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1474
1475 * ppc.h (ppc_cpu_t): New typedef.
1476 (struct powerpc_opcode <flags>): Use it.
1477 (struct powerpc_operand <insert, extract>): Likewise.
1478 (struct powerpc_macro <flags>): Likewise.
1479
bb35fb24
NC		 14802008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1481
1482 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1483 Update comment before MIPS16 field descriptors to mention MIPS16.
1484 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1485 BBIT.
1486 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1487 New bit masks and shift counts for cins and exts.
1488
dd3cbb7e
NC		 1489 * mips.h: Document new field descriptors +Q.
1490 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1491
d0799671
AN		 14922008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1493
9aff4b7a 1494 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1495 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1496
19a6653c
AM		 14972008-04-14 Edmar Wienskoski <edmar@freescale.com>
1498
1499 * ppc.h: (PPC_OPCODE_E500MC): New.
1500
c0f3af97
L		 15012008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1502
1503 * i386.h (MAX_OPERANDS): Set to 5.
1504 (MAX_MNEM_SIZE): Changed to 20.
1505
e210c36b
NC		 15062008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1507
1508 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1509
b1cc4aeb
PB		 15102008-03-09 Paul Brook <paul@codesourcery.com>
1511
1512 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1513
7e806470
PB		 15142008-03-04 Paul Brook <paul@codesourcery.com>
1515
1516 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1517 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1518 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1519
7b2185f9 15202008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1521 Nick Clifton <nickc@redhat.com>
1522
1523 PR 3134
1524 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1525 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1526 set.
af7329f0 1527
796d5313
NC		 15282008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1529
1530 * cr16.h (cr16_num_optab): Declared.
1531
d669d37f
NC		 15322008-02-14 Hakan Ardo <hakan@debian.org>
1533
1534 PR gas/2626
1535 * avr.h (AVR_ISA_2xxe): Define.
1536
e6429699
AN		 15372008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1538
1539 * mips.h: Update copyright.
1540 (INSN_CHIP_MASK): New macro.
1541 (INSN_OCTEON): New macro.
1542 (CPU_OCTEON): New macro.
1543 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1544
e210c36b
NC		 15452008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1546
1547 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1548
15492008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1550
1551 * avr.h (AVR_ISA_USB162): Add new opcode set.
1552 (AVR_ISA_AVR3): Likewise.
1553
350cc38d
MS		 15542007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1555
1556 * mips.h (INSN_LOONGSON_2E): New.
1557 (INSN_LOONGSON_2F): New.
1558 (CPU_LOONGSON_2E): New.
1559 (CPU_LOONGSON_2F): New.
1560 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1561
56950294
MS		 15622007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1563
1564 * mips.h (INSN_ISA*): Redefine certain values as an
1565 enumeration. Update comments.
1566 (mips_isa_table): New.
1567 (ISA_MIPS*): Redefine to match enumeration.
1568 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1569 values.
1570
c3d65c1c
BE		 15712007-08-08 Ben Elliston <bje@au.ibm.com>
1572
1573 * ppc.h (PPC_OPCODE_PPCPS): New.
1574
0fdaa005
L		 15752007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1576
1577 * m68k.h: Document j K & E.
1578
15792007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1580
1581 * cr16.h: New file for CR16 target.
1582
3896c469
AM		 15832007-05-02 Alan Modra <amodra@bigpond.net.au>
1584
1585 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1586
9a2e615a
NS		 15872007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1588
1589 * m68k.h (mcfisa_c): New.
1590 (mcfusp, mcf_mask): Adjust.
1591
b84bf58a
AM		 15922007-04-20 Alan Modra <amodra@bigpond.net.au>
1593
1594 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1595 (num_powerpc_operands): Declare.
1596 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1597 (PPC_OPERAND_PLUS1): Define.
1598
831480e9 15992007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1600
1601 * i386.h (REX_MODE64): Renamed to ...
1602 (REX_W): This.
1603 (REX_EXTX): Renamed to ...
1604 (REX_R): This.
1605 (REX_EXTY): Renamed to ...
1606 (REX_X): This.
1607 (REX_EXTZ): Renamed to ...
1608 (REX_B): This.
1609
0b1cf022
L		 16102007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1611
1612 * i386.h: Add entries from config/tc-i386.h and move tables
1613 to opcodes/i386-opc.h.
1614
d796c0ad
L		 16152007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1616
1617 * i386.h (FloatDR): Removed.
1618 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1619
30ac7323
AM		 16202007-03-01 Alan Modra <amodra@bigpond.net.au>
1621
1622 * spu-insns.h: Add soma double-float insns.
1623
8b082fb1 16242007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1625 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1626
1627 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1628 (INSN_DSPR2): Add flag for DSP R2 instructions.
1629 (M_BALIGN): New macro.
1630
4eed87de
AM		 16312007-02-14 Alan Modra <amodra@bigpond.net.au>
1632
1633 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1634 and Seg3ShortFrom with Shortform.
1635
fda592e8
L		 16362007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1637
1638 PR gas/4027
1639 * i386.h (i386_optab): Put the real "test" before the pseudo
1640 one.
1641
3bdcfdf4
KH		 16422007-01-08 Kazu Hirata <kazu@codesourcery.com>
1643
1644 * m68k.h (m68010up): OR fido_a.
1645
9840d27e
KH		 16462006-12-25 Kazu Hirata <kazu@codesourcery.com>
1647
1648 * m68k.h (fido_a): New.
1649
c629cdac
KH		 16502006-12-24 Kazu Hirata <kazu@codesourcery.com>
1651
1652 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1653 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1654 values.
1655
b7d9ef37
L		 16562006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1657
1658 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1659
b138abaa
NC		 16602006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1661
1662 * score-inst.h (enum score_insn_type): Add Insn_internal.
1663
e9f53129
AM		 16642006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1665 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1666 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1667 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1668 Alan Modra <amodra@bigpond.net.au>
1669
1670 * spu-insns.h: New file.
1671 * spu.h: New file.
1672
ede602d7
AM		 16732006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1674
1675 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1676
7918206c
MM		 16772006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1678
e4e42b45 1679 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1680 in amdfam10 architecture.
1681
ef05d495
L		 16822006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1683
1684 * i386.h: Replace CpuMNI with CpuSSSE3.
1685
2d447fca 16862006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1687 Joseph Myers <joseph@codesourcery.com>
1688 Ian Lance Taylor <ian@wasabisystems.com>
1689 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1690
1691 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1692
1c0d3aa6
NC		 16932006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1694
1695 * score-datadep.h: New file.
1696 * score-inst.h: New file.
1697
c2f0420e
L		 16982006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1699
1700 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1701 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1702 movdq2q and movq2dq.
1703
050dfa73
MM		 17042006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1705 Michael Meissner <michael.meissner@amd.com>
1706
1707 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1708
15965411
L		 17092006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1710
1711 * i386.h (i386_optab): Add "nop" with memory reference.
1712
46e883c5
L		 17132006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1714
1715 * i386.h (i386_optab): Update comment for 64bit NOP.
1716
9622b051
AM		 17172006-06-06 Ben Elliston <bje@au.ibm.com>
1718 Anton Blanchard <anton@samba.org>
1719
1720 * ppc.h (PPC_OPCODE_POWER6): Define.
1721 Adjust whitespace.
1722
a9e24354
TS		 17232006-06-05 Thiemo Seufer <ths@mips.com>
1724
e4e42b45 1725 * mips.h: Improve description of MT flags.
a9e24354 1726
a596001e
RS		 17272006-05-25 Richard Sandiford <richard@codesourcery.com>
1728
1729 * m68k.h (mcf_mask): Define.
1730
d43b4baf 17312006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1732 David Ung <davidu@mips.com>
d43b4baf
TS		 1733
1734 * mips.h (enum): Add macro M_CACHE_AB.
1735
39a7806d 17362006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1737 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1738 David Ung <davidu@mips.com>
1739
1740 * mips.h: Add INSN_SMARTMIPS define.
1741
9bcd4f99 17422006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1743 David Ung <davidu@mips.com>
9bcd4f99
TS		 1744
1745 * mips.h: Defines udi bits and masks. Add description of
1746 characters which may appear in the args field of udi
1747 instructions.
1748
ef0ee844
TS		 17492006-04-26 Thiemo Seufer <ths@networkno.de>
1750
1751 * mips.h: Improve comments describing the bitfield instruction
1752 fields.
1753
f7675147
L		 17542006-04-26 Julian Brown <julian@codesourcery.com>
1755
1756 * arm.h (FPU_VFP_EXT_V3): Define constant.
1757 (FPU_NEON_EXT_V1): Likewise.
1758 (FPU_VFP_HARD): Update.
1759 (FPU_VFP_V3): Define macro.
1760 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1761
ef0ee844 17622006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1763
1764 * avr.h (AVR_ISA_PWMx): New.
1765
2da12c60
NS		 17662006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1767
1768 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1769 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1770 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1771 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1772 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1773
0715c387
PB		 17742006-03-10 Paul Brook <paul@codesourcery.com>
1775
1776 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1777
34bdd094
DA		 17782006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1779
1780 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1781 first. Correct mask of bb "B" opcode.
1782
331d2d0d
L		 17832006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1784
1785 * i386.h (i386_optab): Support Intel Merom New Instructions.
1786
62b3e311
PB		 17872006-02-24 Paul Brook <paul@codesourcery.com>
1788
1789 * arm.h: Add V7 feature bits.
1790
59cf82fe
L		 17912006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1792
1793 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1794
e74cfd16
PB		 17952006-01-31 Paul Brook <paul@codesourcery.com>
1796 Richard Earnshaw <rearnsha@arm.com>
1797
1798 * arm.h: Use ARM_CPU_FEATURE.
1799 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1800 (arm_feature_set): Change to a structure.
1801 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1802 ARM_FEATURE): New macros.
1803
5b3f8a92
HPN		 18042005-12-07 Hans-Peter Nilsson <hp@axis.com>
1805
1806 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1807 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1808 (ADD_PC_INCR_OPCODE): Don't define.
1809
cb712a9e
L		 18102005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1811
1812 PR gas/1874
1813 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1814
0499d65b
TS		 18152005-11-14 David Ung <davidu@mips.com>
1816
1817 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1818 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1819 save/restore encoding of the args field.
1820
ea5ca089
DB		 18212005-10-28 Dave Brolley <brolley@redhat.com>
1822
1823 Contribute the following changes:
1824 2005-02-16 Dave Brolley <brolley@redhat.com>
1825
1826 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1827 cgen_isa_mask_* to cgen_bitset_*.
1828 * cgen.h: Likewise.
1829
16175d96
DB		 1830 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1831
1832 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1833 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1834 (CGEN_CPU_TABLE): Make isas a ponter.
1835
1836 2003-09-29 Dave Brolley <brolley@redhat.com>
1837
1838 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1839 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1840 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1841
1842 2002-12-13 Dave Brolley <brolley@redhat.com>
1843
1844 * cgen.h (symcat.h): #include it.
1845 (cgen-bitset.h): #include it.
1846 (CGEN_ATTR_VALUE_TYPE): Now a union.
1847 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1848 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1849 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1850 * cgen-bitset.h: New file.
1851
3c9b82ba
NC		 18522005-09-30 Catherine Moore <clm@cm00re.com>
1853
1854 * bfin.h: New file.
1855
6a2375c6
JB		 18562005-10-24 Jan Beulich <jbeulich@novell.com>
1857
1858 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1859 indirect operands.
1860
c06a12f8
DA		 18612005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1862
1863 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1864 Add FLAG_STRICT to pa10 ftest opcode.
1865
4d443107
DA		 18662005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1867
1868 * hppa.h (pa_opcodes): Remove lha entries.
1869
f0a3b40f
DA		 18702005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1871
1872 * hppa.h (FLAG_STRICT): Revise comment.
1873 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1874 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1875 entries for "fdc".
1876
e210c36b
NC		 18772005-09-30 Catherine Moore <clm@cm00re.com>
1878
1879 * bfin.h: New file.
1880
1b7e1362
DA		 18812005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1882
1883 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1884
089b39de
CF		 18852005-09-06 Chao-ying Fu <fu@mips.com>
1886
1887 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1888 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1889 define.
1890 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1891 (INSN_ASE_MASK): Update to include INSN_MT.
1892 (INSN_MT): New define for MT ASE.
1893
93c34b9b
CF		 18942005-08-25 Chao-ying Fu <fu@mips.com>
1895
1896 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1897 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1898 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1899 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1900 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1901 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1902 instructions.
1903 (INSN_DSP): New define for DSP ASE.
1904
848cf006
AM		 19052005-08-18 Alan Modra <amodra@bigpond.net.au>
1906
1907 * a29k.h: Delete.
1908
36ae0db3
DJ		 19092005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1910
1911 * ppc.h (PPC_OPCODE_E300): Define.
1912
8c929562
MS		 19132005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1914
1915 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1916
f7b8cccc
DA		 19172005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1918
1919 PR gas/336
1920 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1921 and pitlb.
1922
8b5328ac
JB		 19232005-07-27 Jan Beulich <jbeulich@novell.com>
1924
1925 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1926 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1927 Add movq-s as 64-bit variants of movd-s.
1928
f417d200
DA		 19292005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1930
18b3bdfc
DA		 1931 * hppa.h: Fix punctuation in comment.
1932
f417d200
DA		 1933 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1934 implicit space-register addressing. Set space-register bits on opcodes
1935 using implicit space-register addressing. Add various missing pa20
1936 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1937 space-register addressing. Use "fE" instead of "fe" in various
1938 fstw opcodes.
1939
9a145ce6
JB		 19402005-07-18 Jan Beulich <jbeulich@novell.com>
1941
1942 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1943
90700ea2
L		 19442007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1945
1946 * i386.h (i386_optab): Support Intel VMX Instructions.
1947
48f130a8
DA		 19482005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1949
1950 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1951
30123838
JB		 19522005-07-05 Jan Beulich <jbeulich@novell.com>
1953
1954 * i386.h (i386_optab): Add new insns.
1955
47b0e7ad
NC		 19562005-07-01 Nick Clifton <nickc@redhat.com>
1957
1958 * sparc.h: Add typedefs to structure declarations.
1959
b300c311
L		 19602005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1961
1962 PR 1013
1963 * i386.h (i386_optab): Update comments for 64bit addressing on
1964 mov. Allow 64bit addressing for mov and movq.
1965
2db495be
DA		 19662005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1967
1968 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1969 respectively, in various floating-point load and store patterns.
1970
caa05036
DA		 19712005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1972
1973 * hppa.h (FLAG_STRICT): Correct comment.
1974 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1975 PA 2.0 mneumonics when equivalent. Entries with cache control
1976 completers now require PA 1.1. Adjust whitespace.
1977
f4411256
AM		 19782005-05-19 Anton Blanchard <anton@samba.org>
1979
1980 * ppc.h (PPC_OPCODE_POWER5): Define.
1981
e172dbf8
NC		 19822005-05-10 Nick Clifton <nickc@redhat.com>
1983
1984 * Update the address and phone number of the FSF organization in
1985 the GPL notices in the following files:
1986 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1987 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1988 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1989 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1990 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1991 tic54x.h, tic80.h, v850.h, vax.h
1992
e44823cf
JB		 19932005-05-09 Jan Beulich <jbeulich@novell.com>
1994
1995 * i386.h (i386_optab): Add ht and hnt.
1996
791fe849
MK		 19972005-04-18 Mark Kettenis <kettenis@gnu.org>
1998
1999 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2000 Add xcrypt-ctr. Provide aliases without hyphens.
2001
faa7ef87
L		 20022005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2003
a63027e5
L		 2004 Moved from ../ChangeLog
2005
faa7ef87
L		 2006 2005-04-12 Paul Brook <paul@codesourcery.com>
2007 * m88k.h: Rename psr macros to avoid conflicts.
2008
2009 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2010 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2011 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2012 and ARM_ARCH_V6ZKT2.
2013
2014 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2015 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2016 Remove redundant instruction types.
2017 (struct argument): X_op - new field.
2018 (struct cst4_entry): Remove.
2019 (no_op_insn): Declare.
2020
2021 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2022 * crx.h (enum argtype): Rename types, remove unused types.
2023
2024 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2025 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2026 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2027 (enum operand_type): Rearrange operands, edit comments.
2028 replace us<N> with ui<N> for unsigned immediate.
2029 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2030 displacements (respectively).
2031 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2032 (instruction type): Add NO_TYPE_INS.
2033 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2034 (operand_entry): New field - 'flags'.
2035 (operand flags): New.
2036
2037 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2038 * crx.h (operand_type): Remove redundant types i3, i4,
2039 i5, i8, i12.
2040 Add new unsigned immediate types us3, us4, us5, us16.
2041
bc4bd9ab
MK		 20422005-04-12 Mark Kettenis <kettenis@gnu.org>
2043
2044 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2045 adjust them accordingly.
2046
373ff435
JB		 20472005-04-01 Jan Beulich <jbeulich@novell.com>
2048
2049 * i386.h (i386_optab): Add rdtscp.
2050
4cc91dba
L		 20512005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2052
2053 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2054 between memory and segment register. Allow movq for moving between
2055 general-purpose register and segment register.
4cc91dba 2056
9ae09ff9
JB		 20572005-02-09 Jan Beulich <jbeulich@novell.com>
2058
2059 PR gas/707
2060 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2061 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2062 fnstsw.
2063
638e7a64
NS		 20642006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2065
2066 * m68k.h (m68008, m68ec030, m68882): Remove.
2067 (m68k_mask): New.
2068 (cpu_m68k, cpu_cf): New.
2069 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2070 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2071
90219bd0
AO		 20722005-01-25 Alexandre Oliva <aoliva@redhat.com>
2073
2074 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2075 * cgen.h (enum cgen_parse_operand_type): Add
2076 CGEN_PARSE_OPERAND_SYMBOLIC.
2077
239cb185
FF		 20782005-01-21 Fred Fish <fnf@specifixinc.com>
2079
2080 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2081 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2082 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2083
dc9a9f39
FF		 20842005-01-19 Fred Fish <fnf@specifixinc.com>
2085
2086 * mips.h (struct mips_opcode): Add new pinfo2 member.
2087 (INSN_ALIAS): New define for opcode table entries that are
2088 specific instances of another entry, such as 'move' for an 'or'
2089 with a zero operand.
2090 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2091 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2092
98e7aba8
ILT		 20932004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2094
2095 * mips.h (CPU_RM9000): Define.
2096 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2097
37edbb65
JB		 20982004-11-25 Jan Beulich <jbeulich@novell.com>
2099
2100 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2101 to/from test registers are illegal in 64-bit mode. Add missing
2102 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2103 (previously one had to explicitly encode a rex64 prefix). Re-enable
2104 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2105 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2106
21072004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2108
2109 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2110 available only with SSE2. Change the MMX additions introduced by SSE
2111 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2112 instructions by their now designated identifier (since combining i686
2113 and 3DNow! does not really imply 3DNow!A).
2114
f5c7edf4
AM		 21152004-11-19 Alan Modra <amodra@bigpond.net.au>
2116
2117 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2118 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2119
7499d566
NC		 21202004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2121 Vineet Sharma <vineets@noida.hcltech.com>
2122
2123 * maxq.h: New file: Disassembly information for the maxq port.
2124
bcb9eebe
L		 21252004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2126
2127 * i386.h (i386_optab): Put back "movzb".
2128
94bb3d38
HPN		 21292004-11-04 Hans-Peter Nilsson <hp@axis.com>
2130
2131 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2132 comments. Remove member cris_ver_sim. Add members
2133 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2134 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2135 (struct cris_support_reg, struct cris_cond15): New types.
2136 (cris_conds15): Declare.
2137 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2138 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2139 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2140 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2141 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2142 SIZE_FIELD_UNSIGNED.
2143
37edbb65 21442004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2145
2146 * i386.h (sldx_Suf): Remove.
2147 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2148 (q_FP): Define, implying no REX64.
2149 (x_FP, sl_FP): Imply FloatMF.
2150 (i386_optab): Split reg and mem forms of moving from segment registers
2151 so that the memory forms can ignore the 16-/32-bit operand size
2152 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2153 all non-floating-point instructions. Unite 32- and 64-bit forms of
2154 movsx, movzx, and movd. Adjust floating point operations for the above
2155 changes to the *FP macros. Add DefaultSize to floating point control
2156 insns operating on larger memory ranges. Remove left over comments
2157 hinting at certain insns being Intel-syntax ones where the ones
2158 actually meant are already gone.
2159
48c9f030
NC		 21602004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2161
2162 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2163 instruction type.
2164
0dd132b6
NC		 21652004-09-30 Paul Brook <paul@codesourcery.com>
2166
2167 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2168 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2169
23794b24
MM		 21702004-09-11 Theodore A. Roth <troth@openavr.org>
2171
2172 * avr.h: Add support for
2173 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2174
2a309db0
AM		 21752004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2176
2177 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2178
b18c562e
NC		 21792004-08-24 Dmitry Diky <diwil@spec.ru>
2180
2181 * msp430.h (msp430_opc): Add new instructions.
2182 (msp430_rcodes): Declare new instructions.
2183 (msp430_hcodes): Likewise..
2184
45d313cd
NC		 21852004-08-13 Nick Clifton <nickc@redhat.com>
2186
2187 PR/301
2188 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2189 processors.
2190
30d1c836
ML		 21912004-08-30 Michal Ludvig <mludvig@suse.cz>
2192
2193 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2194
9a45f1c2
L		 21952004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2196
2197 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2198
543613e9
NC		 21992004-07-21 Jan Beulich <jbeulich@novell.com>
2200
2201 * i386.h: Adjust instruction descriptions to better match the
2202 specification.
2203
b781e558
RE		 22042004-07-16 Richard Earnshaw <rearnsha@arm.com>
2205
2206 * arm.h: Remove all old content. Replace with architecture defines
2207 from gas/config/tc-arm.c.
2208
8577e690
AS		 22092004-07-09 Andreas Schwab <schwab@suse.de>
2210
2211 * m68k.h: Fix comment.
2212
1fe1f39c
NC		 22132004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2214
2215 * crx.h: New file.
2216
1d9f512f
AM		 22172004-06-24 Alan Modra <amodra@bigpond.net.au>
2218
2219 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2220
be8c092b
NC		 22212004-05-24 Peter Barada <peter@the-baradas.com>
2222
2223 * m68k.h: Add 'size' to m68k_opcode.
2224
6b6e92f4
NC		 22252004-05-05 Peter Barada <peter@the-baradas.com>
2226
2227 * m68k.h: Switch from ColdFire chip name to core variant.
2228
22292004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2230
2231 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2232 descriptions for new EMAC cases.
2233 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2234 handle Motorola MAC syntax.
2235 Allow disassembly of ColdFire V4e object files.
2236
fdd12ef3
AM		 22372004-03-16 Alan Modra <amodra@bigpond.net.au>
2238
2239 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2240
3922a64c
L		 22412004-03-12 Jakub Jelinek <jakub@redhat.com>
2242
2243 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2244
1f45d988
ML		 22452004-03-12 Michal Ludvig <mludvig@suse.cz>
2246
2247 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2248
0f10071e
ML		 22492004-03-12 Michal Ludvig <mludvig@suse.cz>
2250
2251 * i386.h (i386_optab): Added xstore/xcrypt insns.
2252
3255318a
NC		 22532004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2254
2255 * h8300.h (32bit ldc/stc): Add relaxing support.
2256
ca9a79a1 22572004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2258
ca9a79a1
NC		 2259 * h8300.h (BITOP): Pass MEMRELAX flag.
2260
875a0b14
NC		 22612004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2262
2263 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2264 except for the H8S.
252b5132 2265
c9e214e5 2266For older changes see ChangeLog-9103
252b5132 2267\f
b90efa5b 2268Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2269
2270Copying and distribution of this file, with or without modification,
2271are permitted in any medium without royalty provided the copyright
2272notice and this notice are preserved.
2273
252b5132 2274Local Variables:
c9e214e5
AM		 2275mode: change-log
2276left-margin: 8
2277fill-column: 74
252b5132
RH		 2278version-control: never
2279End:
GDB Binutils - Deliverables
This page took 0.780166 seconds and 4 git commands to generate.