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Add support for SPARC T4 crypto instructions.
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
ec668d69
DM		 12012-04-27 David S. Miller <davem@davemloft.net>
2
6cda1326
DM		 3 * sparc.h: Document new arg code' )' for crypto RS3
4 immediates.
5
ec668d69
DM		 6 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
7 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
8 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
9 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
10 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
11 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
12 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
13 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
14 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
15 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
16 HWCAP_CBCOND, HWCAP_CRC32): New defines.
17
aea77599
AM		 182012-03-10 Edmar Wienskoski <edmar@freescale.com>
19
20 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
21
1f42f8b3
AM		 222012-02-27 Alan Modra <amodra@gmail.com>
23
24 * crx.h (cst4_map): Update declaration.
25
6f7be959
WL		 262012-02-25 Walter Lee <walt@tilera.com>
27
28 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
29 TILEGX_OPC_LD_TLS.
30 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
31 TILEPRO_OPC_LW_TLS_SN.
32
42164a71
L		 332012-02-08 H.J. Lu <hongjiu.lu@intel.com>
34
35 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
36 (XRELEASE_PREFIX_OPCODE): Likewise.
37
432233b3
AP		 382011-12-08 Andrew Pinski <apinski@cavium.com>
39 Adam Nemet <anemet@caviumnetworks.com>
40
41 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
42 (INSN_OCTEON2): New macro.
43 (CPU_OCTEON2): New macro.
44 (OPCODE_IS_MEMBER): Add Octeon2.
45
dd6a37e7
AP		 462011-11-29 Andrew Pinski <apinski@cavium.com>
47
48 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
49 (INSN_OCTEONP): New macro.
50 (CPU_OCTEONP): New macro.
51 (OPCODE_IS_MEMBER): Add Octeon+.
52 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
53
99c513f6
DD		 542011-11-01 DJ Delorie <dj@redhat.com>
55
56 * rl78.h: New file.
57
26f85d7a
MR		 582011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
59
60 * mips.h: Fix a typo in description.
61
9e8c70f9
DM		 622011-09-21 David S. Miller <davem@davemloft.net>
63
64 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
65 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
66 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
67 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
68
dec0624d
MR		 692011-08-09 Chao-ying Fu <fu@mips.com>
70 Maciej W. Rozycki <macro@codesourcery.com>
71
72 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
73 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
74 (INSN_ASE_MASK): Add the MCU bit.
75 (INSN_MCU): New macro.
76 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
77 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
78
2b0c8b40
MR		 792011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
80
81 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
82 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
83 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
84 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
85 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
86 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
87 (INSN2_READ_GPR_MMN): Likewise.
88 (INSN2_READ_FPR_D): Change the bit used.
89 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
90 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
91 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
92 (INSN2_COND_BRANCH): Likewise.
93 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
94 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
95 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
96 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
97 (INSN2_MOD_GPR_MN): Likewise.
98
ea783ef3
DM		 992011-08-05 David S. Miller <davem@davemloft.net>
100
101 * sparc.h: Document new format codes '4', '5', and '('.
102 (OPF_LOW4, RS3): New macros.
103
7c176fa8
MR		 1042011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
105
106 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
107 order of flags documented.
108
2309ddf2
MR		 1092011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
110
111 * mips.h: Clarify the description of microMIPS instruction
112 manipulation macros.
113 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
114
df58fc94
RS		 1152011-07-24 Chao-ying Fu <fu@mips.com>
116 Maciej W. Rozycki <macro@codesourcery.com>
117
118 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
119 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
120 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
121 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
122 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
123 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
124 (OP_MASK_RS3, OP_SH_RS3): Likewise.
125 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
126 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
127 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
128 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
129 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
130 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
131 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
132 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
133 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
134 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
135 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
136 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
137 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
138 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
139 (INSN_WRITE_GPR_S): New macro.
140 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
141 (INSN2_READ_FPR_D): Likewise.
142 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
143 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
144 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
145 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
146 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
147 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
148 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
149 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
150 (CPU_MICROMIPS): New macro.
151 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
152 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
153 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
154 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
155 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
156 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
157 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
158 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
159 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
160 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
161 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
162 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
163 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
164 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
165 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
166 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
167 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
168 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
169 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
170 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
171 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
172 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
173 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
174 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
175 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
176 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
177 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
178 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
179 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
180 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
181 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
182 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
183 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
184 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
185 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
186 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
187 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
188 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
189 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
190 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
191 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
192 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
193 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
194 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
195 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
196 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
197 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
198 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
199 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
200 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
201 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
202 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
203 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
204 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
205 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
206 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
207 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
208 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
209 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
210 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
211 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
212 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
213 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
214 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
215 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
216 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
217 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
218 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
219 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
220 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
221 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
222 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
223 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
224 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
225 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
226 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
227 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
228 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
229 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
230 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
231 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
232 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
233 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
234 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
235 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
236 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
237 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
238 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
239 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
240 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
241 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
242 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
243 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
244 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
245 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
246 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
247 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
248 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
249 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
250 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
251 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
252 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
253 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
254 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
255 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
256 (micromips_opcodes): New declaration.
257 (bfd_micromips_num_opcodes): Likewise.
258
bcd530a7
RS		 2592011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
260
261 * mips.h (INSN_TRAP): Rename to...
262 (INSN_NO_DELAY_SLOT): ... this.
263 (INSN_SYNC): Remove macro.
264
2dad5a91
EW		 2652011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
266
267 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
268 a duplicate of AVR_ISA_SPM.
269
5d73b1f1
NC		 2702011-07-01 Nick Clifton <nickc@redhat.com>
271
272 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
273
ef26d60e
MF		 2742011-06-18 Robin Getz <robin.getz@analog.com>
275
276 * bfin.h (is_macmod_signed): New func
277
8fb8dca7
MF		 2782011-06-18 Mike Frysinger <vapier@gentoo.org>
279
280 * bfin.h (is_macmod_pmove): Add missing space before func args.
281 (is_macmod_hmove): Likewise.
282
aa137e4d
NC		 2832011-06-13 Walter Lee <walt@tilera.com>
284
285 * tilegx.h: New file.
286 * tilepro.h: New file.
287
3b2f0793
PB		 2882011-05-31 Paul Brook <paul@codesourcery.com>
289
aa137e4d
NC		 290 * arm.h (ARM_ARCH_V7R_IDIV): Define.
291
2922011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
293
294 * s390.h: Replace S390_OPERAND_REG_EVEN with
295 S390_OPERAND_REG_PAIR.
296
2972011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
298
299 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 300
ac7f631b
NC		 3012011-04-18 Julian Brown <julian@codesourcery.com>
302
303 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
304
84701018
NC		 3052011-04-11 Dan McDonald <dan@wellkeeper.com>
306
307 PR gas/12296
308 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
309
8cc66334
EW		 3102011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
311
312 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
313 New instruction set flags.
314 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
315
3eebd5eb
MR		 3162011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
317
318 * mips.h (M_PREF_AB): New enum value.
319
26bb3ddd
MF		 3202011-02-12 Mike Frysinger <vapier@gentoo.org>
321
89c0d58c
MR		 322 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
323 M_IU): Define.
324 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 325
dd76fcb8
MF		 3262011-02-11 Mike Frysinger <vapier@gentoo.org>
327
328 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
329
98d23bef
BS		 3302011-02-04 Bernd Schmidt <bernds@codesourcery.com>
331
332 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
333 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
334
3c853d93
DA		 3352010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
336
337 PR gas/11395
338 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
339 "bb" entries.
340
79676006
DA		 3412010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
342
343 PR gas/11395
344 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
345
1bec78e9
RS		 3462010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
347
348 * mips.h: Update commentary after last commit.
349
98675402
RS		 3502010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
351
352 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
353 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
354 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
355
aa137e4d
NC		 3562010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
357
358 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
359
435b94a4
RS		 3602010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
361
362 * mips.h: Fix previous commit.
363
d051516a
NC		 3642010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
365
366 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
367 (INSN_LOONGSON_3A): Clear bit 31.
368
251665fc
MGD		 3692010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
370
371 PR gas/12198
372 * arm.h (ARM_AEXT_V6M_ONLY): New define.
373 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
374 (ARM_ARCH_V6M_ONLY): New define.
375
fd503541
NC		 3762010-11-11 Mingming Sun <mingm.sun@gmail.com>
377
378 * mips.h (INSN_LOONGSON_3A): Defined.
379 (CPU_LOONGSON_3A): Defined.
380 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
381
4469d2be
AM		 3822010-10-09 Matt Rice <ratmice@gmail.com>
383
384 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
385 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
386
90ec0d68
MGD		 3872010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
388
389 * arm.h (ARM_EXT_VIRT): New define.
390 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
391 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
392 Extensions.
393
eea54501 3942010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 395
eea54501
MGD		 396 * arm.h (ARM_AEXT_ADIV): New define.
397 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
398
b2a5fbdc
MGD		 3992010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
400
401 * arm.h (ARM_EXT_OS): New define.
402 (ARM_AEXT_V6SM): Likewise.
403 (ARM_ARCH_V6SM): Likewise.
404
60e5ef9f
MGD		 4052010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
406
407 * arm.h (ARM_EXT_MP): Add.
408 (ARM_ARCH_V7A_MP): Likewise.
409
73a63ccf
MF		 4102010-09-22 Mike Frysinger <vapier@gentoo.org>
411
412 * bfin.h: Declare pseudoChr structs/defines.
413
ee99860a
MF		 4142010-09-21 Mike Frysinger <vapier@gentoo.org>
415
416 * bfin.h: Strip trailing whitespace.
417
f9c7014e
DD		 4182010-07-29 DJ Delorie <dj@redhat.com>
419
420 * rx.h (RX_Operand_Type): Add TwoReg.
421 (RX_Opcode_ID): Remove ediv and ediv2.
422
93378652
DD		 4232010-07-27 DJ Delorie <dj@redhat.com>
424
425 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
426
1cd986c5
NC		 4272010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
428 Ina Pandit <ina.pandit@kpitcummins.com>
429
430 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
431 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
432 PROCESSOR_V850E2_ALL.
433 Remove PROCESSOR_V850EA support.
434 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
435 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
436 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
437 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
438 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
439 V850_OPERAND_PERCENT.
440 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
441 V850_NOT_R0.
442 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
443 and V850E_PUSH_POP
444
9a2c7088
MR		 4452010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
446
447 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
448 (MIPS16_INSN_BRANCH): Rename to...
449 (MIPS16_INSN_COND_BRANCH): ... this.
450
bdc70b4a
AM		 4512010-07-03 Alan Modra <amodra@gmail.com>
452
453 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
454 Renumber other PPC_OPCODE defines.
455
f2bae120
AM		 4562010-07-03 Alan Modra <amodra@gmail.com>
457
458 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
459
360cfc9c
AM		 4602010-06-29 Alan Modra <amodra@gmail.com>
461
462 * maxq.h: Delete file.
463
e01d869a
AM		 4642010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
465
466 * ppc.h (PPC_OPCODE_E500): Define.
467
f79e2745
CM		 4682010-05-26 Catherine Moore <clm@codesourcery.com>
469
470 * opcode/mips.h (INSN_MIPS16): Remove.
471
2462afa1
JM		 4722010-04-21 Joseph Myers <joseph@codesourcery.com>
473
474 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
475
e4e42b45
NC		 4762010-04-15 Nick Clifton <nickc@redhat.com>
477
478 * alpha.h: Update copyright notice to use GPLv3.
479 * arc.h: Likewise.
480 * arm.h: Likewise.
481 * avr.h: Likewise.
482 * bfin.h: Likewise.
483 * cgen.h: Likewise.
484 * convex.h: Likewise.
485 * cr16.h: Likewise.
486 * cris.h: Likewise.
487 * crx.h: Likewise.
488 * d10v.h: Likewise.
489 * d30v.h: Likewise.
490 * dlx.h: Likewise.
491 * h8300.h: Likewise.
492 * hppa.h: Likewise.
493 * i370.h: Likewise.
494 * i386.h: Likewise.
495 * i860.h: Likewise.
496 * i960.h: Likewise.
497 * ia64.h: Likewise.
498 * m68hc11.h: Likewise.
499 * m68k.h: Likewise.
500 * m88k.h: Likewise.
501 * maxq.h: Likewise.
502 * mips.h: Likewise.
503 * mmix.h: Likewise.
504 * mn10200.h: Likewise.
505 * mn10300.h: Likewise.
506 * msp430.h: Likewise.
507 * np1.h: Likewise.
508 * ns32k.h: Likewise.
509 * or32.h: Likewise.
510 * pdp11.h: Likewise.
511 * pj.h: Likewise.
512 * pn.h: Likewise.
513 * ppc.h: Likewise.
514 * pyr.h: Likewise.
515 * rx.h: Likewise.
516 * s390.h: Likewise.
517 * score-datadep.h: Likewise.
518 * score-inst.h: Likewise.
519 * sparc.h: Likewise.
520 * spu-insns.h: Likewise.
521 * spu.h: Likewise.
522 * tic30.h: Likewise.
523 * tic4x.h: Likewise.
524 * tic54x.h: Likewise.
525 * tic80.h: Likewise.
526 * v850.h: Likewise.
527 * vax.h: Likewise.
528
40b36596
JM		 5292010-03-25 Joseph Myers <joseph@codesourcery.com>
530
531 * tic6x-control-registers.h, tic6x-insn-formats.h,
532 tic6x-opcode-table.h, tic6x.h: New.
533
c67a084a
NC		 5342010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
535
536 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
537
466ef64f
AM		 5382010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
539
540 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
541
1319d143
L		 5422010-01-14 H.J. Lu <hongjiu.lu@intel.com>
543
544 * ia64.h (ia64_find_opcode): Remove argument name.
545 (ia64_find_next_opcode): Likewise.
546 (ia64_dis_opcode): Likewise.
547 (ia64_free_opcode): Likewise.
548 (ia64_find_dependency): Likewise.
549
1fbb9298
DE		 5502009-11-22 Doug Evans <dje@sebabeach.org>
551
552 * cgen.h: Include bfd_stdint.h.
553 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
554
ada65aa3
PB		 5552009-11-18 Paul Brook <paul@codesourcery.com>
556
557 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
558
9e3c6df6
PB		 5592009-11-17 Paul Brook <paul@codesourcery.com>
560 Daniel Jacobowitz <dan@codesourcery.com>
561
562 * arm.h (ARM_EXT_V6_DSP): Define.
563 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
564 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
565
0d734b5d
DD		 5662009-11-04 DJ Delorie <dj@redhat.com>
567
568 * rx.h (rx_decode_opcode) (mvtipl): Add.
569 (mvtcp, mvfcp, opecp): Remove.
570
62f3b8c8
PB		 5712009-11-02 Paul Brook <paul@codesourcery.com>
572
573 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
574 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
575 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
576 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
577 FPU_ARCH_NEON_VFP_V4): Define.
578
ac1e9eca
DE		 5792009-10-23 Doug Evans <dje@sebabeach.org>
580
581 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
582 * cgen.h: Update. Improve multi-inclusion macro name.
583
9fe54b1c
PB		 5842009-10-02 Peter Bergner <bergner@vnet.ibm.com>
585
586 * ppc.h (PPC_OPCODE_476): Define.
587
634b50f2
PB		 5882009-10-01 Peter Bergner <bergner@vnet.ibm.com>
589
590 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
591
c7927a3c
NC		 5922009-09-29 DJ Delorie <dj@redhat.com>
593
594 * rx.h: New file.
595
b961e85b
AM		 5962009-09-22 Peter Bergner <bergner@vnet.ibm.com>
597
598 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
599
e0d602ec
BE		 6002009-09-21 Ben Elliston <bje@au.ibm.com>
601
602 * ppc.h (PPC_OPCODE_PPCA2): New.
603
96d56e9f
NC		 6042009-09-05 Martin Thuresson <martin@mtme.org>
605
606 * ia64.h (struct ia64_operand): Renamed member class to op_class.
607
d3ce72d0
NC		 6082009-08-29 Martin Thuresson <martin@mtme.org>
609
610 * tic30.h (template): Rename type template to
611 insn_template. Updated code to use new name.
612 * tic54x.h (template): Rename type template to
613 insn_template.
614
824b28db
NH		 6152009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
616
617 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
618
f865a31d
AG		 6192009-06-11 Anthony Green <green@moxielogic.com>
620
621 * moxie.h (MOXIE_F3_PCREL): Define.
622 (moxie_form3_opc_info): Grow.
623
0e7c7f11
AG		 6242009-06-06 Anthony Green <green@moxielogic.com>
625
626 * moxie.h (MOXIE_F1_M): Define.
627
20135e4c
NC		 6282009-04-15 Anthony Green <green@moxielogic.com>
629
630 * moxie.h: Created.
631
bcb012d3
DD		 6322009-04-06 DJ Delorie <dj@redhat.com>
633
634 * h8300.h: Add relaxation attributes to MOVA opcodes.
635
69fe9ce5
AM		 6362009-03-10 Alan Modra <amodra@bigpond.net.au>
637
638 * ppc.h (ppc_parse_cpu): Declare.
639
c3b7224a
NC		 6402009-03-02 Qinwei <qinwei@sunnorth.com.cn>
641
642 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
643 and _IMM11 for mbitclr and mbitset.
644 * score-datadep.h: Update dependency information.
645
066be9f7
PB		 6462009-02-26 Peter Bergner <bergner@vnet.ibm.com>
647
648 * ppc.h (PPC_OPCODE_POWER7): New.
649
fedc618e
DE		 6502009-02-06 Doug Evans <dje@google.com>
651
652 * i386.h: Add comment regarding sse* insns and prefixes.
653
52b6b6b9
JM		 6542009-02-03 Sandip Matte <sandip@rmicorp.com>
655
656 * mips.h (INSN_XLR): Define.
657 (INSN_CHIP_MASK): Update.
658 (CPU_XLR): Define.
659 (OPCODE_IS_MEMBER): Update.
660 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
661
35669430
DE		 6622009-01-28 Doug Evans <dje@google.com>
663
664 * opcode/i386.h: Add multiple inclusion protection.
665 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
666 (EDI_REG_NUM): New macros.
667 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
668 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 669 (REX_PREFIX_P): New macro.
35669430 670
1cb0a767
PB		 6712009-01-09 Peter Bergner <bergner@vnet.ibm.com>
672
673 * ppc.h (struct powerpc_opcode): New field "deprecated".
674 (PPC_OPCODE_NOPOWER4): Delete.
675
3aa3176b
TS		 6762008-11-28 Joshua Kinard <kumba@gentoo.org>
677
678 * mips.h: Define CPU_R14000, CPU_R16000.
679 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
680
8e79c3df
CM		 6812008-11-18 Catherine Moore <clm@codesourcery.com>
682
683 * arm.h (FPU_NEON_FP16): New.
684 (FPU_ARCH_NEON_FP16): New.
685
de9a3e51
CF		 6862008-11-06 Chao-ying Fu <fu@mips.com>
687
688 * mips.h: Doucument '1' for 5-bit sync type.
689
1ca35711
L		 6902008-08-28 H.J. Lu <hongjiu.lu@intel.com>
691
692 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
693 IA64_RS_CR.
694
9b4e5766
PB		 6952008-08-01 Peter Bergner <bergner@vnet.ibm.com>
696
697 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
698
081ba1b3
AM		 6992008-07-30 Michael J. Eager <eager@eagercon.com>
700
701 * ppc.h (PPC_OPCODE_405): Define.
702 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
703
fa452fa6
PB		 7042008-06-13 Peter Bergner <bergner@vnet.ibm.com>
705
706 * ppc.h (ppc_cpu_t): New typedef.
707 (struct powerpc_opcode <flags>): Use it.
708 (struct powerpc_operand <insert, extract>): Likewise.
709 (struct powerpc_macro <flags>): Likewise.
710
bb35fb24
NC		 7112008-06-12 Adam Nemet <anemet@caviumnetworks.com>
712
713 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
714 Update comment before MIPS16 field descriptors to mention MIPS16.
715 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
716 BBIT.
717 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
718 New bit masks and shift counts for cins and exts.
719
dd3cbb7e
NC		 720 * mips.h: Document new field descriptors +Q.
721 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
722
d0799671
AN		 7232008-04-28 Adam Nemet <anemet@caviumnetworks.com>
724
725 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
726 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
727
19a6653c
AM		 7282008-04-14 Edmar Wienskoski <edmar@freescale.com>
729
730 * ppc.h: (PPC_OPCODE_E500MC): New.
731
c0f3af97
L		 7322008-04-03 H.J. Lu <hongjiu.lu@intel.com>
733
734 * i386.h (MAX_OPERANDS): Set to 5.
735 (MAX_MNEM_SIZE): Changed to 20.
736
e210c36b
NC		 7372008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
738
739 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
740
b1cc4aeb
PB		 7412008-03-09 Paul Brook <paul@codesourcery.com>
742
743 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
744
7e806470
PB		 7452008-03-04 Paul Brook <paul@codesourcery.com>
746
747 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
748 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
749 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
750
7b2185f9 7512008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 752 Nick Clifton <nickc@redhat.com>
753
754 PR 3134
755 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
756 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 757 set.
af7329f0 758
796d5313
NC		 7592008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
760
761 * cr16.h (cr16_num_optab): Declared.
762
d669d37f
NC		 7632008-02-14 Hakan Ardo <hakan@debian.org>
764
765 PR gas/2626
766 * avr.h (AVR_ISA_2xxe): Define.
767
e6429699
AN		 7682008-02-04 Adam Nemet <anemet@caviumnetworks.com>
769
770 * mips.h: Update copyright.
771 (INSN_CHIP_MASK): New macro.
772 (INSN_OCTEON): New macro.
773 (CPU_OCTEON): New macro.
774 (OPCODE_IS_MEMBER): Handle Octeon instructions.
775
e210c36b
NC		 7762008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
777
778 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
779
7802008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
781
782 * avr.h (AVR_ISA_USB162): Add new opcode set.
783 (AVR_ISA_AVR3): Likewise.
784
350cc38d
MS		 7852007-11-29 Mark Shinwell <shinwell@codesourcery.com>
786
787 * mips.h (INSN_LOONGSON_2E): New.
788 (INSN_LOONGSON_2F): New.
789 (CPU_LOONGSON_2E): New.
790 (CPU_LOONGSON_2F): New.
791 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
792
56950294
MS		 7932007-11-29 Mark Shinwell <shinwell@codesourcery.com>
794
795 * mips.h (INSN_ISA*): Redefine certain values as an
796 enumeration. Update comments.
797 (mips_isa_table): New.
798 (ISA_MIPS*): Redefine to match enumeration.
799 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
800 values.
801
c3d65c1c
BE		 8022007-08-08 Ben Elliston <bje@au.ibm.com>
803
804 * ppc.h (PPC_OPCODE_PPCPS): New.
805
0fdaa005
L		 8062007-07-03 Nathan Sidwell <nathan@codesourcery.com>
807
808 * m68k.h: Document j K & E.
809
8102007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 811
812 * cr16.h: New file for CR16 target.
813
3896c469
AM		 8142007-05-02 Alan Modra <amodra@bigpond.net.au>
815
816 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
817
9a2e615a
NS		 8182007-04-23 Nathan Sidwell <nathan@codesourcery.com>
819
820 * m68k.h (mcfisa_c): New.
821 (mcfusp, mcf_mask): Adjust.
822
b84bf58a
AM		 8232007-04-20 Alan Modra <amodra@bigpond.net.au>
824
825 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
826 (num_powerpc_operands): Declare.
827 (PPC_OPERAND_SIGNED et al): Redefine as hex.
828 (PPC_OPERAND_PLUS1): Define.
829
831480e9 8302007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 831
832 * i386.h (REX_MODE64): Renamed to ...
833 (REX_W): This.
834 (REX_EXTX): Renamed to ...
835 (REX_R): This.
836 (REX_EXTY): Renamed to ...
837 (REX_X): This.
838 (REX_EXTZ): Renamed to ...
839 (REX_B): This.
840
0b1cf022
L		 8412007-03-15 H.J. Lu <hongjiu.lu@intel.com>
842
843 * i386.h: Add entries from config/tc-i386.h and move tables
844 to opcodes/i386-opc.h.
845
d796c0ad
L		 8462007-03-13 H.J. Lu <hongjiu.lu@intel.com>
847
848 * i386.h (FloatDR): Removed.
849 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
850
30ac7323
AM		 8512007-03-01 Alan Modra <amodra@bigpond.net.au>
852
853 * spu-insns.h: Add soma double-float insns.
854
8b082fb1 8552007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 856 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 857
858 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
859 (INSN_DSPR2): Add flag for DSP R2 instructions.
860 (M_BALIGN): New macro.
861
4eed87de
AM		 8622007-02-14 Alan Modra <amodra@bigpond.net.au>
863
864 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
865 and Seg3ShortFrom with Shortform.
866
fda592e8
L		 8672007-02-11 H.J. Lu <hongjiu.lu@intel.com>
868
869 PR gas/4027
870 * i386.h (i386_optab): Put the real "test" before the pseudo
871 one.
872
3bdcfdf4
KH		 8732007-01-08 Kazu Hirata <kazu@codesourcery.com>
874
875 * m68k.h (m68010up): OR fido_a.
876
9840d27e
KH		 8772006-12-25 Kazu Hirata <kazu@codesourcery.com>
878
879 * m68k.h (fido_a): New.
880
c629cdac
KH		 8812006-12-24 Kazu Hirata <kazu@codesourcery.com>
882
883 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
884 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
885 values.
886
b7d9ef37
L		 8872006-11-08 H.J. Lu <hongjiu.lu@intel.com>
888
889 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
890
b138abaa
NC		 8912006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
892
893 * score-inst.h (enum score_insn_type): Add Insn_internal.
894
e9f53129
AM		 8952006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
896 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
897 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
898 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
899 Alan Modra <amodra@bigpond.net.au>
900
901 * spu-insns.h: New file.
902 * spu.h: New file.
903
ede602d7
AM		 9042006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
905
906 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 907
7918206c
MM		 9082006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
909
e4e42b45 910 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 911 in amdfam10 architecture.
912
ef05d495
L		 9132006-09-28 H.J. Lu <hongjiu.lu@intel.com>
914
915 * i386.h: Replace CpuMNI with CpuSSSE3.
916
2d447fca
JM		 9172006-09-26 Mark Shinwell <shinwell@codesourcery.com>
918 Joseph Myers <joseph@codesourcery.com>
919 Ian Lance Taylor <ian@wasabisystems.com>
920 Ben Elliston <bje@wasabisystems.com>
921
922 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
923
1c0d3aa6
NC		 9242006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
925
926 * score-datadep.h: New file.
927 * score-inst.h: New file.
928
c2f0420e
L		 9292006-07-14 H.J. Lu <hongjiu.lu@intel.com>
930
931 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
932 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
933 movdq2q and movq2dq.
934
050dfa73
MM		 9352006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
936 Michael Meissner <michael.meissner@amd.com>
937
938 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
939
15965411
L		 9402006-06-12 H.J. Lu <hongjiu.lu@intel.com>
941
942 * i386.h (i386_optab): Add "nop" with memory reference.
943
46e883c5
L		 9442006-06-12 H.J. Lu <hongjiu.lu@intel.com>
945
946 * i386.h (i386_optab): Update comment for 64bit NOP.
947
9622b051
AM		 9482006-06-06 Ben Elliston <bje@au.ibm.com>
949 Anton Blanchard <anton@samba.org>
950
951 * ppc.h (PPC_OPCODE_POWER6): Define.
952 Adjust whitespace.
953
a9e24354
TS		 9542006-06-05 Thiemo Seufer <ths@mips.com>
955
e4e42b45 956 * mips.h: Improve description of MT flags.
a9e24354 957
a596001e
RS		 9582006-05-25 Richard Sandiford <richard@codesourcery.com>
959
960 * m68k.h (mcf_mask): Define.
961
d43b4baf
TS		 9622006-05-05 Thiemo Seufer <ths@mips.com>
963 David Ung <davidu@mips.com>
964
965 * mips.h (enum): Add macro M_CACHE_AB.
966
39a7806d
TS		 9672006-05-04 Thiemo Seufer <ths@mips.com>
968 Nigel Stephens <nigel@mips.com>
969 David Ung <davidu@mips.com>
970
971 * mips.h: Add INSN_SMARTMIPS define.
972
9bcd4f99
TS		 9732006-04-30 Thiemo Seufer <ths@mips.com>
974 David Ung <davidu@mips.com>
975
976 * mips.h: Defines udi bits and masks. Add description of
977 characters which may appear in the args field of udi
978 instructions.
979
ef0ee844
TS		 9802006-04-26 Thiemo Seufer <ths@networkno.de>
981
982 * mips.h: Improve comments describing the bitfield instruction
983 fields.
984
f7675147
L		 9852006-04-26 Julian Brown <julian@codesourcery.com>
986
987 * arm.h (FPU_VFP_EXT_V3): Define constant.
988 (FPU_NEON_EXT_V1): Likewise.
989 (FPU_VFP_HARD): Update.
990 (FPU_VFP_V3): Define macro.
991 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
992
ef0ee844 9932006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 994
995 * avr.h (AVR_ISA_PWMx): New.
996
2da12c60
NS		 9972006-03-28 Nathan Sidwell <nathan@codesourcery.com>
998
999 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1000 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1001 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1002 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1003 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1004
0715c387
PB		 10052006-03-10 Paul Brook <paul@codesourcery.com>
1006
1007 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1008
34bdd094
DA		 10092006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1010
1011 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1012 first. Correct mask of bb "B" opcode.
1013
331d2d0d
L		 10142006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1015
1016 * i386.h (i386_optab): Support Intel Merom New Instructions.
1017
62b3e311
PB		 10182006-02-24 Paul Brook <paul@codesourcery.com>
1019
1020 * arm.h: Add V7 feature bits.
1021
59cf82fe
L		 10222006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1023
1024 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1025
e74cfd16
PB		 10262006-01-31 Paul Brook <paul@codesourcery.com>
1027 Richard Earnshaw <rearnsha@arm.com>
1028
1029 * arm.h: Use ARM_CPU_FEATURE.
1030 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1031 (arm_feature_set): Change to a structure.
1032 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1033 ARM_FEATURE): New macros.
1034
5b3f8a92
HPN		 10352005-12-07 Hans-Peter Nilsson <hp@axis.com>
1036
1037 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1038 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1039 (ADD_PC_INCR_OPCODE): Don't define.
1040
cb712a9e
L		 10412005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1042
1043 PR gas/1874
1044 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1045
0499d65b
TS		 10462005-11-14 David Ung <davidu@mips.com>
1047
1048 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1049 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1050 save/restore encoding of the args field.
1051
ea5ca089
DB		 10522005-10-28 Dave Brolley <brolley@redhat.com>
1053
1054 Contribute the following changes:
1055 2005-02-16 Dave Brolley <brolley@redhat.com>
1056
1057 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1058 cgen_isa_mask_* to cgen_bitset_*.
1059 * cgen.h: Likewise.
1060
16175d96
DB		 1061 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1062
1063 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1064 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1065 (CGEN_CPU_TABLE): Make isas a ponter.
1066
1067 2003-09-29 Dave Brolley <brolley@redhat.com>
1068
1069 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1070 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1071 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1072
1073 2002-12-13 Dave Brolley <brolley@redhat.com>
1074
1075 * cgen.h (symcat.h): #include it.
1076 (cgen-bitset.h): #include it.
1077 (CGEN_ATTR_VALUE_TYPE): Now a union.
1078 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1079 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1080 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1081 * cgen-bitset.h: New file.
1082
3c9b82ba
NC		 10832005-09-30 Catherine Moore <clm@cm00re.com>
1084
1085 * bfin.h: New file.
1086
6a2375c6
JB		 10872005-10-24 Jan Beulich <jbeulich@novell.com>
1088
1089 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1090 indirect operands.
1091
c06a12f8
DA		 10922005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1093
1094 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1095 Add FLAG_STRICT to pa10 ftest opcode.
1096
4d443107
DA		 10972005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1098
1099 * hppa.h (pa_opcodes): Remove lha entries.
1100
f0a3b40f
DA		 11012005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1102
1103 * hppa.h (FLAG_STRICT): Revise comment.
1104 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1105 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1106 entries for "fdc".
1107
e210c36b
NC		 11082005-09-30 Catherine Moore <clm@cm00re.com>
1109
1110 * bfin.h: New file.
1111
1b7e1362
DA		 11122005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1113
1114 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1115
089b39de
CF		 11162005-09-06 Chao-ying Fu <fu@mips.com>
1117
1118 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1119 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1120 define.
1121 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1122 (INSN_ASE_MASK): Update to include INSN_MT.
1123 (INSN_MT): New define for MT ASE.
1124
93c34b9b
CF		 11252005-08-25 Chao-ying Fu <fu@mips.com>
1126
1127 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1128 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1129 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1130 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1131 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1132 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1133 instructions.
1134 (INSN_DSP): New define for DSP ASE.
1135
848cf006
AM		 11362005-08-18 Alan Modra <amodra@bigpond.net.au>
1137
1138 * a29k.h: Delete.
1139
36ae0db3
DJ		 11402005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1141
1142 * ppc.h (PPC_OPCODE_E300): Define.
1143
8c929562
MS		 11442005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1145
1146 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1147
f7b8cccc
DA		 11482005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1149
1150 PR gas/336
1151 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1152 and pitlb.
1153
8b5328ac
JB		 11542005-07-27 Jan Beulich <jbeulich@novell.com>
1155
1156 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1157 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1158 Add movq-s as 64-bit variants of movd-s.
1159
f417d200
DA		 11602005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1161
18b3bdfc
DA		 1162 * hppa.h: Fix punctuation in comment.
1163
f417d200
DA		 1164 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1165 implicit space-register addressing. Set space-register bits on opcodes
1166 using implicit space-register addressing. Add various missing pa20
1167 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1168 space-register addressing. Use "fE" instead of "fe" in various
1169 fstw opcodes.
1170
9a145ce6
JB		 11712005-07-18 Jan Beulich <jbeulich@novell.com>
1172
1173 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1174
90700ea2
L		 11752007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1176
1177 * i386.h (i386_optab): Support Intel VMX Instructions.
1178
48f130a8
DA		 11792005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1180
1181 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1182
30123838
JB		 11832005-07-05 Jan Beulich <jbeulich@novell.com>
1184
1185 * i386.h (i386_optab): Add new insns.
1186
47b0e7ad
NC		 11872005-07-01 Nick Clifton <nickc@redhat.com>
1188
1189 * sparc.h: Add typedefs to structure declarations.
1190
b300c311
L		 11912005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1192
1193 PR 1013
1194 * i386.h (i386_optab): Update comments for 64bit addressing on
1195 mov. Allow 64bit addressing for mov and movq.
1196
2db495be
DA		 11972005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1198
1199 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1200 respectively, in various floating-point load and store patterns.
1201
caa05036
DA		 12022005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1203
1204 * hppa.h (FLAG_STRICT): Correct comment.
1205 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1206 PA 2.0 mneumonics when equivalent. Entries with cache control
1207 completers now require PA 1.1. Adjust whitespace.
1208
f4411256
AM		 12092005-05-19 Anton Blanchard <anton@samba.org>
1210
1211 * ppc.h (PPC_OPCODE_POWER5): Define.
1212
e172dbf8
NC		 12132005-05-10 Nick Clifton <nickc@redhat.com>
1214
1215 * Update the address and phone number of the FSF organization in
1216 the GPL notices in the following files:
1217 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1218 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1219 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1220 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1221 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1222 tic54x.h, tic80.h, v850.h, vax.h
1223
e44823cf
JB		 12242005-05-09 Jan Beulich <jbeulich@novell.com>
1225
1226 * i386.h (i386_optab): Add ht and hnt.
1227
791fe849
MK		 12282005-04-18 Mark Kettenis <kettenis@gnu.org>
1229
1230 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1231 Add xcrypt-ctr. Provide aliases without hyphens.
1232
faa7ef87
L		 12332005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1234
a63027e5
L		 1235 Moved from ../ChangeLog
1236
faa7ef87
L		 1237 2005-04-12 Paul Brook <paul@codesourcery.com>
1238 * m88k.h: Rename psr macros to avoid conflicts.
1239
1240 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1241 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1242 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1243 and ARM_ARCH_V6ZKT2.
1244
1245 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1246 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1247 Remove redundant instruction types.
1248 (struct argument): X_op - new field.
1249 (struct cst4_entry): Remove.
1250 (no_op_insn): Declare.
1251
1252 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1253 * crx.h (enum argtype): Rename types, remove unused types.
1254
1255 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1256 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1257 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1258 (enum operand_type): Rearrange operands, edit comments.
1259 replace us<N> with ui<N> for unsigned immediate.
1260 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1261 displacements (respectively).
1262 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1263 (instruction type): Add NO_TYPE_INS.
1264 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1265 (operand_entry): New field - 'flags'.
1266 (operand flags): New.
1267
1268 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1269 * crx.h (operand_type): Remove redundant types i3, i4,
1270 i5, i8, i12.
1271 Add new unsigned immediate types us3, us4, us5, us16.
1272
bc4bd9ab
MK		 12732005-04-12 Mark Kettenis <kettenis@gnu.org>
1274
1275 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1276 adjust them accordingly.
1277
373ff435
JB		 12782005-04-01 Jan Beulich <jbeulich@novell.com>
1279
1280 * i386.h (i386_optab): Add rdtscp.
1281
4cc91dba
L		 12822005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1283
1284 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1285 between memory and segment register. Allow movq for moving between
1286 general-purpose register and segment register.
4cc91dba 1287
9ae09ff9
JB		 12882005-02-09 Jan Beulich <jbeulich@novell.com>
1289
1290 PR gas/707
1291 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1292 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1293 fnstsw.
1294
638e7a64
NS		 12952006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1296
1297 * m68k.h (m68008, m68ec030, m68882): Remove.
1298 (m68k_mask): New.
1299 (cpu_m68k, cpu_cf): New.
1300 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1301 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1302
90219bd0
AO		 13032005-01-25 Alexandre Oliva <aoliva@redhat.com>
1304
1305 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1306 * cgen.h (enum cgen_parse_operand_type): Add
1307 CGEN_PARSE_OPERAND_SYMBOLIC.
1308
239cb185
FF		 13092005-01-21 Fred Fish <fnf@specifixinc.com>
1310
1311 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1312 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1313 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1314
dc9a9f39
FF		 13152005-01-19 Fred Fish <fnf@specifixinc.com>
1316
1317 * mips.h (struct mips_opcode): Add new pinfo2 member.
1318 (INSN_ALIAS): New define for opcode table entries that are
1319 specific instances of another entry, such as 'move' for an 'or'
1320 with a zero operand.
1321 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1322 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1323
98e7aba8
ILT		 13242004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1325
1326 * mips.h (CPU_RM9000): Define.
1327 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1328
37edbb65
JB		 13292004-11-25 Jan Beulich <jbeulich@novell.com>
1330
1331 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1332 to/from test registers are illegal in 64-bit mode. Add missing
1333 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1334 (previously one had to explicitly encode a rex64 prefix). Re-enable
1335 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1336 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1337
13382004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 1339
1340 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1341 available only with SSE2. Change the MMX additions introduced by SSE
1342 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1343 instructions by their now designated identifier (since combining i686
1344 and 3DNow! does not really imply 3DNow!A).
1345
f5c7edf4
AM		 13462004-11-19 Alan Modra <amodra@bigpond.net.au>
1347
1348 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1349 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1350
7499d566
NC		 13512004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1352 Vineet Sharma <vineets@noida.hcltech.com>
1353
1354 * maxq.h: New file: Disassembly information for the maxq port.
1355
bcb9eebe
L		 13562004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1357
1358 * i386.h (i386_optab): Put back "movzb".
1359
94bb3d38
HPN		 13602004-11-04 Hans-Peter Nilsson <hp@axis.com>
1361
1362 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1363 comments. Remove member cris_ver_sim. Add members
1364 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1365 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1366 (struct cris_support_reg, struct cris_cond15): New types.
1367 (cris_conds15): Declare.
1368 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1369 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1370 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1371 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1372 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1373 SIZE_FIELD_UNSIGNED.
1374
37edbb65 13752004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 1376
1377 * i386.h (sldx_Suf): Remove.
1378 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1379 (q_FP): Define, implying no REX64.
1380 (x_FP, sl_FP): Imply FloatMF.
1381 (i386_optab): Split reg and mem forms of moving from segment registers
1382 so that the memory forms can ignore the 16-/32-bit operand size
1383 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1384 all non-floating-point instructions. Unite 32- and 64-bit forms of
1385 movsx, movzx, and movd. Adjust floating point operations for the above
1386 changes to the *FP macros. Add DefaultSize to floating point control
1387 insns operating on larger memory ranges. Remove left over comments
1388 hinting at certain insns being Intel-syntax ones where the ones
1389 actually meant are already gone.
1390
48c9f030
NC		 13912004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1392
1393 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1394 instruction type.
1395
0dd132b6
NC		 13962004-09-30 Paul Brook <paul@codesourcery.com>
1397
1398 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1399 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1400
23794b24
MM		 14012004-09-11 Theodore A. Roth <troth@openavr.org>
1402
1403 * avr.h: Add support for
1404 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1405
2a309db0
AM		 14062004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1407
1408 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1409
b18c562e
NC		 14102004-08-24 Dmitry Diky <diwil@spec.ru>
1411
1412 * msp430.h (msp430_opc): Add new instructions.
1413 (msp430_rcodes): Declare new instructions.
1414 (msp430_hcodes): Likewise..
1415
45d313cd
NC		 14162004-08-13 Nick Clifton <nickc@redhat.com>
1417
1418 PR/301
1419 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1420 processors.
1421
30d1c836
ML		 14222004-08-30 Michal Ludvig <mludvig@suse.cz>
1423
1424 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1425
9a45f1c2
L		 14262004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1427
1428 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1429
543613e9
NC		 14302004-07-21 Jan Beulich <jbeulich@novell.com>
1431
1432 * i386.h: Adjust instruction descriptions to better match the
1433 specification.
1434
b781e558
RE		 14352004-07-16 Richard Earnshaw <rearnsha@arm.com>
1436
1437 * arm.h: Remove all old content. Replace with architecture defines
1438 from gas/config/tc-arm.c.
1439
8577e690
AS		 14402004-07-09 Andreas Schwab <schwab@suse.de>
1441
1442 * m68k.h: Fix comment.
1443
1fe1f39c
NC		 14442004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1445
1446 * crx.h: New file.
1447
1d9f512f
AM		 14482004-06-24 Alan Modra <amodra@bigpond.net.au>
1449
1450 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1451
be8c092b
NC		 14522004-05-24 Peter Barada <peter@the-baradas.com>
1453
1454 * m68k.h: Add 'size' to m68k_opcode.
1455
6b6e92f4
NC		 14562004-05-05 Peter Barada <peter@the-baradas.com>
1457
1458 * m68k.h: Switch from ColdFire chip name to core variant.
1459
14602004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 1461
1462 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1463 descriptions for new EMAC cases.
1464 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1465 handle Motorola MAC syntax.
1466 Allow disassembly of ColdFire V4e object files.
1467
fdd12ef3
AM		 14682004-03-16 Alan Modra <amodra@bigpond.net.au>
1469
1470 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1471
3922a64c
L		 14722004-03-12 Jakub Jelinek <jakub@redhat.com>
1473
1474 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1475
1f45d988
ML		 14762004-03-12 Michal Ludvig <mludvig@suse.cz>
1477
1478 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1479
0f10071e
ML		 14802004-03-12 Michal Ludvig <mludvig@suse.cz>
1481
1482 * i386.h (i386_optab): Added xstore/xcrypt insns.
1483
3255318a
NC		 14842004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1485
1486 * h8300.h (32bit ldc/stc): Add relaxing support.
1487
ca9a79a1 14882004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 1489
ca9a79a1
NC		 1490 * h8300.h (BITOP): Pass MEMRELAX flag.
1491
875a0b14
NC		 14922004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1493
1494 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1495 except for the H8S.
252b5132 1496
c9e214e5 1497For older changes see ChangeLog-9103
252b5132
RH		 1498\f
1499Local Variables:
c9e214e5
AM		 1500mode: change-log
1501left-margin: 8
1502fill-column: 74
252b5132
RH		 1503version-control: never
1504End:
GDB Binutils - Deliverables
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