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[aarch64] Remove argument pc from disas_aarch64_insn
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
7ecc513a
DV		 12015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
2
3 * s390.h (S390_INSTR_FLAG_HTM): New flag.
4 (S390_INSTR_FLAG_VX): New flag.
5 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
6
b6518b38
NC		 72015-09-23 Nick Clifton <nickc@redhat.com>
8
9 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
10 shifting.
11
f04265ec
NC		 122015-09-22 Nick Clifton <nickc@redhat.com>
13
14 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
15
7bdf96ef
NC		 162015-09-09 Daniel Santos <daniel.santos@pobox.com>
17
18 * visium.h (gen_reg_table): Make static.
19 (fp_reg_table): Likewise.
20 (cc_table): Likewise.
21
f33026a9
MW		 222015-07-20 Matthew Wahab <matthew.wahab@arm.com>
23
24 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
25 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
26 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
27 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
28
ef5a96d5
AM		 292015-07-03 Alan Modra <amodra@gmail.com>
30
31 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
32
c8c8175b
SL		 332015-07-01 Sandra Loosemore <sandra@codesourcery.com>
34 Cesar Philippidis <cesar@codesourcery.com>
35
36 * nios2.h (enum iw_format_type): Add R2 formats.
37 (enum overflow_type): Add signed_immed12_overflow and
38 enumeration_overflow for R2.
39 (struct nios2_opcode): Document new argument letters for R2.
40 (REG_3BIT, REG_LDWM, REG_POP): Define.
41 (includes): Include nios2r2.h.
42 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
43 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
44 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
45 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
46 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
47 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
48 Declare.
49 * nios2r2.h: New file.
50
11a0cf2e
PB		 512015-06-19 Peter Bergner <bergner@vnet.ibm.com>
52
53 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
54 (ppc_optional_operand_value): New inline function.
55
88f0ea34
MW		 562015-06-04 Matthew Wahab <matthew.wahab@arm.com>
57
58 * aarch64.h (AARCH64_V8_1): New.
59
a5932920
MW		 602015-06-03 Matthew Wahab <matthew.wahab@arm.com>
61
62 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
63 (ARM_ARCH_V8_1A): New.
64 (ARM_ARCH_V8_1A_FP): New.
65 (ARM_ARCH_V8_1A_SIMD): New.
66 (ARM_ARCH_V8_1A_CRYPTOV1): New.
67 (ARM_FEATURE_CORE): New.
68
ddfded2f
MW		 692015-06-02 Matthew Wahab <matthew.wahab@arm.com>
70
71 * arm.h (ARM_EXT2_PAN): New.
72 (ARM_FEATURE_CORE_HIGH): New.
73
1af1dd51
MW		 742015-06-02 Matthew Wahab <matthew.wahab@arm.com>
75
76 * arm.h (ARM_FEATURE_ALL): New.
77
9e1f0fa7
MW		 782015-06-02 Matthew Wahab <matthew.wahab@arm.com>
79
80 * aarch64.h (AARCH64_FEATURE_RDMA): New.
81
290806fd
MW		 822015-06-02 Matthew Wahab <matthew.wahab@arm.com>
83
84 * aarch64.h (AARCH64_FEATURE_LOR): New.
85
f21cce2c
MW		 862015-06-01 Matthew Wahab <matthew.wahab@arm.com>
87
88 * aarch64.h (AARCH64_FEATURE_PAN): New.
89 (aarch64_sys_reg_supported_p): Declare.
90 (aarch64_pstatefield_supported_p): Declare.
91
0952813b
DD		 922015-04-30 DJ Delorie <dj@redhat.com>
93
94 * rl78.h (RL78_Dis_Isa): New.
95 (rl78_decode_opcode): Add ISA parameter.
96
823d2571
TG		 972015-03-24 Terry Guo <terry.guo@arm.com>
98
99 * arm.h (arm_feature_set): Extended to provide more available bits.
100 (ARM_ANY): Updated to follow above new definition.
101 (ARM_CPU_HAS_FEATURE): Likewise.
102 (ARM_CPU_IS_ANY): Likewise.
103 (ARM_MERGE_FEATURE_SETS): Likewise.
104 (ARM_CLEAR_FEATURE): Likewise.
105 (ARM_FEATURE): Likewise.
106 (ARM_FEATURE_COPY): New macro.
107 (ARM_FEATURE_EQUAL): Likewise.
108 (ARM_FEATURE_ZERO): Likewise.
109 (ARM_FEATURE_CORE_EQUAL): Likewise.
110 (ARM_FEATURE_LOW): Likewise.
111 (ARM_FEATURE_CORE_LOW): Likewise.
112 (ARM_FEATURE_CORE_COPROC): Likewise.
113
f63c1776
PA		 1142015-02-19 Pedro Alves <palves@redhat.com>
115
116 * cgen.h [__cplusplus]: Wrap in extern "C".
117 * msp430-decode.h [__cplusplus]: Likewise.
118 * nios2.h [__cplusplus]: Likewise.
119 * rl78.h [__cplusplus]: Likewise.
120 * rx.h [__cplusplus]: Likewise.
121 * tilegx.h [__cplusplus]: Likewise.
122
3f8107ab
AM		 1232015-01-28 James Bowman <james.bowman@ftdichip.com>
124
125 * ft32.h: New file.
126
1e2e8c52
AK		 1272015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
128
129 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
130
b90efa5b
AM		 1312015-01-01 Alan Modra <amodra@gmail.com>
132
133 Update year range in copyright notice of all files.
134
bffb6004
AG		 1352014-12-27 Anthony Green <green@moxielogic.com>
136
137 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
138 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
139
1945cfa5
EB		 1402014-12-06 Eric Botcazou <ebotcazou@adacore.com>
141
142 * visium.h: New file.
143
d306ce58
SL		 1442014-11-28 Sandra Loosemore <sandra@codesourcery.com>
145
146 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
147 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
148 (NIOS2_INSN_OPTARG): Renumber.
149
b4714c7c
SL		 1502014-11-06 Sandra Loosemore <sandra@codesourcery.com>
151
152 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
153 declaration. Fix obsolete comment.
154
96ba4233
SL		 1552014-10-23 Sandra Loosemore <sandra@codesourcery.com>
156
157 * nios2.h (enum iw_format_type): New.
158 (struct nios2_opcode): Update comments. Add size and format fields.
159 (NIOS2_INSN_OPTARG): New.
160 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
161 (struct nios2_reg): Add regtype field.
162 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
163 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
164 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
165 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
166 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
167 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
168 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
169 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
170 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
171 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
172 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
173 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
174 (OP_MASK_OP, OP_SH_OP): Delete.
175 (OP_MASK_IOP, OP_SH_IOP): Delete.
176 (OP_MASK_IRD, OP_SH_IRD): Delete.
177 (OP_MASK_IRT, OP_SH_IRT): Delete.
178 (OP_MASK_IRS, OP_SH_IRS): Delete.
179 (OP_MASK_ROP, OP_SH_ROP): Delete.
180 (OP_MASK_RRD, OP_SH_RRD): Delete.
181 (OP_MASK_RRT, OP_SH_RRT): Delete.
182 (OP_MASK_RRS, OP_SH_RRS): Delete.
183 (OP_MASK_JOP, OP_SH_JOP): Delete.
184 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
185 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
186 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
187 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
188 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
189 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
190 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
191 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
192 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
193 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
194 (OP_MASK_<insn>, OP_MASK): Delete.
195 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
196 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
197 Include nios2r1.h to define new instruction opcode constants
198 and accessors.
199 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
200 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
201 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
202 (NUMOPCODES, NUMREGISTERS): Delete.
203 * nios2r1.h: New file.
204
0b6be415
JM		 2052014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
206
207 * sparc.h (HWCAP2_VIS3B): Documentation improved.
208
3d68f91c
JM		 2092014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
210
211 * sparc.h (sparc_opcode): new field `hwcaps2'.
212 (HWCAP2_FJATHPLUS): New define.
213 (HWCAP2_VIS3B): Likewise.
214 (HWCAP2_ADP): Likewise.
215 (HWCAP2_SPARC5): Likewise.
216 (HWCAP2_MWAIT): Likewise.
217 (HWCAP2_XMPMUL): Likewise.
218 (HWCAP2_XMONT): Likewise.
219 (HWCAP2_NSEC): Likewise.
220 (HWCAP2_FJATHHPC): Likewise.
221 (HWCAP2_FJDES): Likewise.
222 (HWCAP2_FJAES): Likewise.
223 Document the new operand kind `{', corresponding to the mcdper
224 ancillary state register.
225 Document the new operand kind }, which represents frsd floating
226 point registers (double precision) which must be the same than
227 frs1 in its containing instruction.
228
40c7a7cb
KLC		 2292014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
230
72f4393d 231 * nds32.h: Add new opcode declaration.
40c7a7cb 232
7361da2c
AB		 2332014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
234 Matthew Fortune <matthew.fortune@imgtec.com>
235
236 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
237 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
238 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
239 +I, +O, +R, +:, +\, +", +;
240 (mips_check_prev_operand): New struct.
241 (INSN2_FORBIDDEN_SLOT): New define.
242 (INSN_ISA32R6): New define.
243 (INSN_ISA64R6): New define.
244 (INSN_UPTO32R6): New define.
245 (INSN_UPTO64R6): New define.
246 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
247 (ISA_MIPS32R6): New define.
248 (ISA_MIPS64R6): New define.
249 (CPU_MIPS32R6): New define.
250 (CPU_MIPS64R6): New define.
251 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
252
ee804238
JW		 2532014-09-03 Jiong Wang <jiong.wang@arm.com>
254
255 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
256 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
257 (aarch64_insn_class): Add lse_atomic.
258 (F_LSE_SZ): New field added.
259 (opcode_has_special_coder): Recognize F_LSE_SZ.
260
5575639b
MR		 2612014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
262
263 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
264 over to `+J'.
265
43885403
MF		 2662014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
267
268 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
269 (INSN_LOAD_COPROC): New define.
270 (INSN_COPROC_MOVE_DELAY): Rename to...
271 (INSN_COPROC_MOVE): New define.
272
f36e8886 2732014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 274 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
275 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
276 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 277
278 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
279 (AVR_ISA_2xxxa): Define ISA without LPM.
280 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
281 Add doc for contraint used in 16 bit lds/sts.
282 Adjust ISA group for icall, ijmp, pop and push.
283 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
284
00b32ff2
NC		 2852014-05-19 Nick Clifton <nickc@redhat.com>
286
287 * msp430.h (struct msp430_operand_s): Add vshift field.
288
ae52f483
AB		 2892014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
290
291 * mips.h (INSN_ISA_MASK): Updated.
292 (INSN_ISA32R3): New define.
293 (INSN_ISA32R5): New define.
294 (INSN_ISA64R3): New define.
295 (INSN_ISA64R5): New define.
296 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
297 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
298 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
299 mips64r5.
300 (INSN_UPTO32R3): New define.
301 (INSN_UPTO32R5): New define.
302 (INSN_UPTO64R3): New define.
303 (INSN_UPTO64R5): New define.
304 (ISA_MIPS32R3): New define.
305 (ISA_MIPS32R5): New define.
306 (ISA_MIPS64R3): New define.
307 (ISA_MIPS64R5): New define.
308 (CPU_MIPS32R3): New define.
309 (CPU_MIPS32R5): New define.
310 (CPU_MIPS64R3): New define.
311 (CPU_MIPS64R5): New define.
312
3efe9ec5
RS		 3132014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
314
315 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
316
73589c9d
CS		 3172014-04-22 Christian Svensson <blue@cmd.nu>
318
319 * or32.h: Delete.
320
4b95cf5c
AM		 3212014-03-05 Alan Modra <amodra@gmail.com>
322
323 Update copyright years.
324
e269fea7
AB		 3252013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
326
327 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
328 microMIPS.
329
35c08157
KLC		 3302013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
331 Wei-Cheng Wang <cole945@gmail.com>
332
333 * nds32.h: New file for Andes NDS32.
334
594d8fa8
MF		 3352013-12-07 Mike Frysinger <vapier@gentoo.org>
336
337 * bfin.h: Remove +x file mode.
338
87b8eed7
YZ		 3392013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
340
341 * aarch64.h (aarch64_pstatefields): Change element type to
342 aarch64_sys_reg.
343
c9fb6e58
YZ		 3442013-11-18 Renlin Li <Renlin.Li@arm.com>
345
346 * arm.h (ARM_AEXT_V7VE): New define.
347 (ARM_ARCH_V7VE): New define.
348 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
349
a203d9b7
YZ		 3502013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
351
352 Revert
353
354 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
355
356 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
357 (aarch64_sys_reg_writeonly_p): Ditto.
358
75468c93
YZ		 3592013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
360
361 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
362 (aarch64_sys_reg_writeonly_p): Ditto.
363
49eec193
YZ		 3642013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
365
366 * aarch64.h (aarch64_sys_reg): New typedef.
367 (aarch64_sys_regs): Change to define with the new type.
368 (aarch64_sys_reg_deprecated_p): Declare.
369
68a64283
YZ		 3702013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
371
372 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
373 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
374
387a82f1
CF		 3752013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
376
377 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
378 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
379 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
380 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
381 For MIPS, update extension character sequences after +.
382 (ASE_MSA): New define.
383 (ASE_MSA64): New define.
384 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
385 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
386 For microMIPS, update extension character sequences after +.
387
9aff4b7a
NC		 3882013-08-23 Yuri Chornoivan <yurchor@ukr.net>
389
390 PR binutils/15834
391 * i960.h: Fix typos.
392
e423441d
RS		 3932013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
394
395 * mips.h: Remove references to "+I" and imm2_expr.
396
5e0dc5ba
RS		 3972013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
398
399 * mips.h (M_DEXT, M_DINS): Delete.
400
0f35dbc4
RS		 4012013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
402
403 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
404 (mips_optional_operand_p): New function.
405
14daeee3
RS		 4062013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
407 Richard Sandiford <rdsandiford@googlemail.com>
408
409 * mips.h: Document new VU0 operand characters.
410 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
411 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
412 (OP_REG_R5900_ACC): New mips_reg_operand_types.
413 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
414 (mips_vu0_channel_mask): Declare.
415
3ccad066
RS		 4162013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
417
418 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
419 (mips_int_operand_min, mips_int_operand_max): New functions.
420 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
421
fc76e730
RS		 4222013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
423
424 * mips.h (mips_decode_reg_operand): New function.
425 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
426 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
427 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
428 New macros.
429 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
430 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
431 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
432 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
433 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
434 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
435 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
436 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
437 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
438 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
439 macros to cover the gaps.
440 (INSN2_MOD_SP): Replace with...
441 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
442 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
443 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
444 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
445 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
446 Delete.
447
26545944
RS		 4482013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
449
450 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
451 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
452 (MIPS16_INSN_COND_BRANCH): Delete.
453
7e8b059b
L		 4542013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
455 Kirill Yukhin <kirill.yukhin@intel.com>
456 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
457
458 * i386.h (BND_PREFIX_OPCODE): New.
459
c3c07478
RS		 4602013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
461
462 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
463 OP_SAVE_RESTORE_LIST.
464 (decode_mips16_operand): Declare.
465
ab902481
RS		 4662013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
467
468 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
469 (mips_operand, mips_int_operand, mips_mapped_int_operand)
470 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
471 (mips_pcrel_operand): New structures.
472 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
473 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
474 (decode_mips_operand, decode_micromips_operand): Declare.
475
cc537e56
RS		 4762013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
477
478 * mips.h: Document MIPS16 "I" opcode.
479
f2ae14a1
RS		 4802013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
481
482 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
483 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
484 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
485 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
486 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
487 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
488 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
489 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
490 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
491 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
492 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
493 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
494 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
495 Rename to...
496 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
497 (M_USD_AB): ...these.
498
5c324c16
RS		 4992013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
500
501 * mips.h: Remove documentation of "[" and "]". Update documentation
502 of "k" and the MDMX formats.
503
23e69e47
RS		 5042013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
505
506 * mips.h: Update documentation of "+s" and "+S".
507
27c5c572
RS		 5082013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
509
510 * mips.h: Document "+i".
511
e76ff5ab
RS		 5122013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
513
514 * mips.h: Remove "mi" documentation. Update "mh" documentation.
515 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
516 Delete.
517 (INSN2_WRITE_GPR_MHI): Rename to...
518 (INSN2_WRITE_GPR_MH): ...this.
519
fa7616a4
RS		 5202013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
521
522 * mips.h: Remove documentation of "+D" and "+T".
523
18870af7
RS		 5242013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
525
526 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
527 Use "source" rather than "destination" for microMIPS "G".
528
833794fc
MR		 5292013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
530
531 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
532 values.
533
c3678916
RS		 5342013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
535
536 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
537
7f3c4072
CM		 5382013-06-17 Catherine Moore <clm@codesourcery.com>
539 Maciej W. Rozycki <macro@codesourcery.com>
540 Chao-Ying Fu <fu@mips.com>
541
542 * mips.h (OP_SH_EVAOFFSET): Define.
543 (OP_MASK_EVAOFFSET): Define.
544 (INSN_ASE_MASK): Delete.
545 (ASE_EVA): Define.
546 (M_CACHEE_AB, M_CACHEE_OB): New.
547 (M_LBE_OB, M_LBE_AB): New.
548 (M_LBUE_OB, M_LBUE_AB): New.
549 (M_LHE_OB, M_LHE_AB): New.
550 (M_LHUE_OB, M_LHUE_AB): New.
551 (M_LLE_AB, M_LLE_OB): New.
552 (M_LWE_OB, M_LWE_AB): New.
553 (M_LWLE_AB, M_LWLE_OB): New.
554 (M_LWRE_AB, M_LWRE_OB): New.
555 (M_PREFE_AB, M_PREFE_OB): New.
556 (M_SCE_AB, M_SCE_OB): New.
557 (M_SBE_OB, M_SBE_AB): New.
558 (M_SHE_OB, M_SHE_AB): New.
559 (M_SWE_OB, M_SWE_AB): New.
560 (M_SWLE_AB, M_SWLE_OB): New.
561 (M_SWRE_AB, M_SWRE_OB): New.
562 (MICROMIPSOP_SH_EVAOFFSET): Define.
563 (MICROMIPSOP_MASK_EVAOFFSET): Define.
564
0c8fe7cf
SL		 5652013-06-12 Sandra Loosemore <sandra@codesourcery.com>
566
567 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
568
c77c0862
RS		 5692013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
570
571 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
572
b015e599
AP		 5732013-05-09 Andrew Pinski <apinski@cavium.com>
574
575 * mips.h (OP_MASK_CODE10): Correct definition.
576 (OP_SH_CODE10): Likewise.
577 Add a comment that "+J" is used now for OP_*CODE10.
578 (INSN_ASE_MASK): Update.
579 (INSN_VIRT): New macro.
580 (INSN_VIRT64): New macro
581
13761a11
NC		 5822013-05-02 Nick Clifton <nickc@redhat.com>
583
584 * msp430.h: Add patterns for MSP430X instructions.
585
0afd1215
DM		 5862013-04-06 David S. Miller <davem@davemloft.net>
587
588 * sparc.h (F_PREFERRED): Define.
589 (F_PREF_ALIAS): Define.
590
41702d50
NC		 5912013-04-03 Nick Clifton <nickc@redhat.com>
592
593 * v850.h (V850_INVERSE_PCREL): Define.
594
e21e1a51
NC		 5952013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
596
597 PR binutils/15068
598 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
599
51dcdd4d
NC		 6002013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
601
602 PR binutils/15068
603 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
604 Add 16-bit opcodes.
605 * tic6xc-opcode-table.h: Add 16-bit insns.
606 * tic6x.h: Add support for 16-bit insns.
607
81f5558e
NC		 6082013-03-21 Michael Schewe <michael.schewe@gmx.net>
609
610 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
611 and mov.b/w/l Rs,@(d:32,ERd).
612
165546ad
NC		 6132013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
614
615 PR gas/15082
616 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
617 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
618 tic6x_operand_xregpair operand coding type.
619 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
620 opcode field, usu ORXREGD1324 for the src2 operand and remove the
621 TIC6X_FLAG_NO_CROSS.
622
795b8e6b
NC		 6232013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
624
625 PR gas/15095
626 * tic6x.h (enum tic6x_coding_method): Add
627 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
628 separately the msb and lsb of a register pair. This is needed to
629 encode the opcodes in the same way as TI assembler does.
630 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
631 and rsqrdp opcodes to use the new field coding types.
632
dd5181d5
KT		 6332013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
634
635 * arm.h (CRC_EXT_ARMV8): New constant.
636 (ARCH_CRC_ARMV8): New macro.
637
e60bb1dd
YZ		 6382013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
639
640 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
641
36591ba1 6422013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 643 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 644
645 Based on patches from Altera Corporation.
646
647 * nios2.h: New file.
648
e30181a5
YZ		 6492013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
650
651 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
652
0c9573f4
NC		 6532013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
654
655 PR gas/15069
656 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
657
981dc7f1
NC		 6582013-01-24 Nick Clifton <nickc@redhat.com>
659
660 * v850.h: Add e3v5 support.
661
f5555712
YZ		 6622013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
663
664 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
665
5817ffd1
PB		 6662013-01-10 Peter Bergner <bergner@vnet.ibm.com>
667
668 * ppc.h (PPC_OPCODE_POWER8): New define.
669 (PPC_OPCODE_HTM): Likewise.
670
a3c62988
NC		 6712013-01-10 Will Newton <will.newton@imgtec.com>
672
673 * metag.h: New file.
674
73335eae
NC		 6752013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
676
677 * cr16.h (make_instruction): Rename to cr16_make_instruction.
678 (match_opcode): Rename to cr16_match_opcode.
679
e407c74b
NC		 6802013-01-04 Juergen Urban <JuergenUrban@gmx.de>
681
682 * mips.h: Add support for r5900 instructions including lq and sq.
683
bab4becb
NC		 6842013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
685
686 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
687 (make_instruction,match_opcode): Added function prototypes.
688 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
689
776fc418
AM		 6902012-11-23 Alan Modra <amodra@gmail.com>
691
692 * ppc.h (ppc_parse_cpu): Update prototype.
693
f05682d4
DA		 6942012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
695
696 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
697 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
698
cfc72779
AK		 6992012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
700
701 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
702
b3e14eda
L		 7032012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
704
705 * ia64.h (ia64_opnd): Add new operand types.
706
2c63854f
DM		 7072012-08-21 David S. Miller <davem@davemloft.net>
708
709 * sparc.h (F3F4): New macro.
710
a06ea964 7112012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 712 Laurent Desnogues <laurent.desnogues@arm.com>
713 Jim MacArthur <jim.macarthur@arm.com>
714 Marcus Shawcroft <marcus.shawcroft@arm.com>
715 Nigel Stephens <nigel.stephens@arm.com>
716 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
717 Richard Earnshaw <rearnsha@arm.com>
718 Sofiane Naci <sofiane.naci@arm.com>
719 Tejas Belagod <tejas.belagod@arm.com>
720 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 721
722 * aarch64.h: New file.
723
35d0a169 7242012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 725 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 726
727 * mips.h (mips_opcode): Add the exclusions field.
728 (OPCODE_IS_MEMBER): Remove macro.
729 (cpu_is_member): New inline function.
730 (opcode_is_member): Likewise.
731
03f66e8a 7322012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 733 Catherine Moore <clm@codesourcery.com>
734 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 735
736 * mips.h: Document microMIPS DSP ASE usage.
737 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
738 microMIPS DSP ASE support.
739 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
740 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
741 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
742 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
743 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
744 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
745 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
746
9d7b4c23
MR		 7472012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
748
749 * mips.h: Fix a typo in description.
750
76e879f8
NC		 7512012-06-07 Georg-Johann Lay <avr@gjlay.de>
752
753 * avr.h: (AVR_ISA_XCH): New define.
754 (AVR_ISA_XMEGA): Use it.
755 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
756
6927f982
NC		 7572012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
758
759 * m68hc11.h: Add XGate definitions.
760 (struct m68hc11_opcode): Add xg_mask field.
761
b9c361e0
JL		 7622012-05-14 Catherine Moore <clm@codesourcery.com>
763 Maciej W. Rozycki <macro@codesourcery.com>
764 Rhonda Wittels <rhonda@codesourcery.com>
765
6927f982 766 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 767 (PPC_OP_SA): New macro.
768 (PPC_OP_SE_VLE): New macro.
769 (PPC_OP): Use a variable shift amount.
770 (powerpc_operand): Update comments.
771 (PPC_OPSHIFT_INV): New macro.
772 (PPC_OPERAND_CR): Replace with...
773 (PPC_OPERAND_CR_BIT): ...this and
774 (PPC_OPERAND_CR_REG): ...this.
775
776
f6c1a2d5
NC		 7772012-05-03 Sean Keys <skeys@ipdatasys.com>
778
779 * xgate.h: Header file for XGATE assembler.
780
ec668d69
DM		 7812012-04-27 David S. Miller <davem@davemloft.net>
782
6cda1326
DM		 783 * sparc.h: Document new arg code' )' for crypto RS3
784 immediates.
785
ec668d69
DM		 786 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
787 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
788 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
789 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
790 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
791 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
792 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
793 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
794 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
795 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
796 HWCAP_CBCOND, HWCAP_CRC32): New defines.
797
aea77599
AM		 7982012-03-10 Edmar Wienskoski <edmar@freescale.com>
799
800 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
801
1f42f8b3
AM		 8022012-02-27 Alan Modra <amodra@gmail.com>
803
804 * crx.h (cst4_map): Update declaration.
805
6f7be959
WL		 8062012-02-25 Walter Lee <walt@tilera.com>
807
808 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
809 TILEGX_OPC_LD_TLS.
810 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
811 TILEPRO_OPC_LW_TLS_SN.
812
42164a71
L		 8132012-02-08 H.J. Lu <hongjiu.lu@intel.com>
814
815 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
816 (XRELEASE_PREFIX_OPCODE): Likewise.
817
432233b3 8182011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 819 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 820
821 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
822 (INSN_OCTEON2): New macro.
823 (CPU_OCTEON2): New macro.
824 (OPCODE_IS_MEMBER): Add Octeon2.
825
dd6a37e7
AP		 8262011-11-29 Andrew Pinski <apinski@cavium.com>
827
828 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
829 (INSN_OCTEONP): New macro.
830 (CPU_OCTEONP): New macro.
831 (OPCODE_IS_MEMBER): Add Octeon+.
832 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
833
99c513f6
DD		 8342011-11-01 DJ Delorie <dj@redhat.com>
835
836 * rl78.h: New file.
837
26f85d7a
MR		 8382011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
839
840 * mips.h: Fix a typo in description.
841
9e8c70f9
DM		 8422011-09-21 David S. Miller <davem@davemloft.net>
843
844 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
845 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
846 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
847 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
848
dec0624d 8492011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 850 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 851
852 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
853 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
854 (INSN_ASE_MASK): Add the MCU bit.
855 (INSN_MCU): New macro.
856 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
857 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
858
2b0c8b40
MR		 8592011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
860
861 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
862 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
863 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
864 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
865 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
866 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
867 (INSN2_READ_GPR_MMN): Likewise.
868 (INSN2_READ_FPR_D): Change the bit used.
869 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
870 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
871 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
872 (INSN2_COND_BRANCH): Likewise.
873 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
874 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
875 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
876 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
877 (INSN2_MOD_GPR_MN): Likewise.
878
ea783ef3
DM		 8792011-08-05 David S. Miller <davem@davemloft.net>
880
881 * sparc.h: Document new format codes '4', '5', and '('.
882 (OPF_LOW4, RS3): New macros.
883
7c176fa8
MR		 8842011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
885
886 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
887 order of flags documented.
888
2309ddf2
MR		 8892011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
890
891 * mips.h: Clarify the description of microMIPS instruction
892 manipulation macros.
893 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
894
df58fc94 8952011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 896 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 897
898 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
899 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
900 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
901 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
902 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
903 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
904 (OP_MASK_RS3, OP_SH_RS3): Likewise.
905 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
906 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
907 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
908 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
909 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
910 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
911 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
912 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
913 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
914 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
915 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
916 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
917 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
918 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
919 (INSN_WRITE_GPR_S): New macro.
920 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
921 (INSN2_READ_FPR_D): Likewise.
922 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
923 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
924 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
925 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
926 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
927 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
928 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
929 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
930 (CPU_MICROMIPS): New macro.
931 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
932 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
933 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
934 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
935 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
936 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
937 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
938 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
939 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
940 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
941 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
942 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
943 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
944 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
945 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
946 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
947 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
948 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
949 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
950 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
951 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
952 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
953 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
954 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
955 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
956 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
957 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
958 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
959 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
960 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
961 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
962 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
963 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
964 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
965 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
966 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
967 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
968 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
969 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
970 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
971 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
972 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
973 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
974 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
975 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
976 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
977 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
978 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
979 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
980 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
981 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
982 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
983 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
984 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
985 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
986 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
987 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
988 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
989 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
990 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
991 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
992 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
993 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
994 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
995 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
996 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
997 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
998 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
999 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1000 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1001 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1002 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1003 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1004 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1005 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1006 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1007 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1008 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1009 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1010 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1011 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1012 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1013 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1014 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1015 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1016 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1017 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1018 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1019 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1020 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1021 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1022 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1023 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1024 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1025 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1026 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1027 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1028 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1029 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1030 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1031 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1032 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1033 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1034 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1035 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1036 (micromips_opcodes): New declaration.
1037 (bfd_micromips_num_opcodes): Likewise.
1038
bcd530a7
RS		 10392011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1040
1041 * mips.h (INSN_TRAP): Rename to...
1042 (INSN_NO_DELAY_SLOT): ... this.
1043 (INSN_SYNC): Remove macro.
1044
2dad5a91
EW		 10452011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1046
1047 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1048 a duplicate of AVR_ISA_SPM.
1049
5d73b1f1
NC		 10502011-07-01 Nick Clifton <nickc@redhat.com>
1051
1052 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1053
ef26d60e
MF		 10542011-06-18 Robin Getz <robin.getz@analog.com>
1055
1056 * bfin.h (is_macmod_signed): New func
1057
8fb8dca7
MF		 10582011-06-18 Mike Frysinger <vapier@gentoo.org>
1059
1060 * bfin.h (is_macmod_pmove): Add missing space before func args.
1061 (is_macmod_hmove): Likewise.
1062
aa137e4d
NC		 10632011-06-13 Walter Lee <walt@tilera.com>
1064
1065 * tilegx.h: New file.
1066 * tilepro.h: New file.
1067
3b2f0793
PB		 10682011-05-31 Paul Brook <paul@codesourcery.com>
1069
aa137e4d
NC		 1070 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1071
10722011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1073
1074 * s390.h: Replace S390_OPERAND_REG_EVEN with
1075 S390_OPERAND_REG_PAIR.
1076
10772011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1078
1079 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1080
ac7f631b
NC		 10812011-04-18 Julian Brown <julian@codesourcery.com>
1082
1083 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1084
84701018
NC		 10852011-04-11 Dan McDonald <dan@wellkeeper.com>
1086
1087 PR gas/12296
1088 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1089
8cc66334
EW		 10902011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1091
1092 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1093 New instruction set flags.
1094 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1095
3eebd5eb
MR		 10962011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1097
1098 * mips.h (M_PREF_AB): New enum value.
1099
26bb3ddd
MF		 11002011-02-12 Mike Frysinger <vapier@gentoo.org>
1101
89c0d58c
MR		 1102 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1103 M_IU): Define.
1104 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1105
dd76fcb8
MF		 11062011-02-11 Mike Frysinger <vapier@gentoo.org>
1107
1108 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1109
98d23bef
BS		 11102011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1111
1112 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1113 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1114
3c853d93
DA		 11152010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1116
1117 PR gas/11395
1118 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1119 "bb" entries.
1120
79676006
DA		 11212010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1122
1123 PR gas/11395
1124 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1125
1bec78e9
RS		 11262010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1127
1128 * mips.h: Update commentary after last commit.
1129
98675402
RS		 11302010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1131
1132 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1133 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1134 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1135
aa137e4d
NC		 11362010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1137
1138 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1139
435b94a4
RS		 11402010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1141
1142 * mips.h: Fix previous commit.
1143
d051516a
NC		 11442010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1145
1146 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1147 (INSN_LOONGSON_3A): Clear bit 31.
1148
251665fc
MGD		 11492010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1150
1151 PR gas/12198
1152 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1153 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1154 (ARM_ARCH_V6M_ONLY): New define.
1155
fd503541
NC		 11562010-11-11 Mingming Sun <mingm.sun@gmail.com>
1157
1158 * mips.h (INSN_LOONGSON_3A): Defined.
1159 (CPU_LOONGSON_3A): Defined.
1160 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1161
4469d2be
AM		 11622010-10-09 Matt Rice <ratmice@gmail.com>
1163
1164 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1165 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1166
90ec0d68
MGD		 11672010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1168
1169 * arm.h (ARM_EXT_VIRT): New define.
1170 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1171 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1172 Extensions.
1173
eea54501 11742010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1175
eea54501
MGD		 1176 * arm.h (ARM_AEXT_ADIV): New define.
1177 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1178
b2a5fbdc
MGD		 11792010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1180
1181 * arm.h (ARM_EXT_OS): New define.
1182 (ARM_AEXT_V6SM): Likewise.
1183 (ARM_ARCH_V6SM): Likewise.
1184
60e5ef9f
MGD		 11852010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1186
1187 * arm.h (ARM_EXT_MP): Add.
1188 (ARM_ARCH_V7A_MP): Likewise.
1189
73a63ccf
MF		 11902010-09-22 Mike Frysinger <vapier@gentoo.org>
1191
1192 * bfin.h: Declare pseudoChr structs/defines.
1193
ee99860a
MF		 11942010-09-21 Mike Frysinger <vapier@gentoo.org>
1195
1196 * bfin.h: Strip trailing whitespace.
1197
f9c7014e
DD		 11982010-07-29 DJ Delorie <dj@redhat.com>
1199
1200 * rx.h (RX_Operand_Type): Add TwoReg.
1201 (RX_Opcode_ID): Remove ediv and ediv2.
1202
93378652
DD		 12032010-07-27 DJ Delorie <dj@redhat.com>
1204
1205 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1206
1cd986c5
NC		 12072010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1208 Ina Pandit <ina.pandit@kpitcummins.com>
1209
1210 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1211 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1212 PROCESSOR_V850E2_ALL.
1213 Remove PROCESSOR_V850EA support.
1214 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1215 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1216 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1217 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1218 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1219 V850_OPERAND_PERCENT.
1220 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1221 V850_NOT_R0.
1222 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1223 and V850E_PUSH_POP
1224
9a2c7088
MR		 12252010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1226
1227 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1228 (MIPS16_INSN_BRANCH): Rename to...
1229 (MIPS16_INSN_COND_BRANCH): ... this.
1230
bdc70b4a
AM		 12312010-07-03 Alan Modra <amodra@gmail.com>
1232
1233 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1234 Renumber other PPC_OPCODE defines.
1235
f2bae120
AM		 12362010-07-03 Alan Modra <amodra@gmail.com>
1237
1238 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1239
360cfc9c
AM		 12402010-06-29 Alan Modra <amodra@gmail.com>
1241
1242 * maxq.h: Delete file.
1243
e01d869a
AM		 12442010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1245
1246 * ppc.h (PPC_OPCODE_E500): Define.
1247
f79e2745
CM		 12482010-05-26 Catherine Moore <clm@codesourcery.com>
1249
1250 * opcode/mips.h (INSN_MIPS16): Remove.
1251
2462afa1
JM		 12522010-04-21 Joseph Myers <joseph@codesourcery.com>
1253
1254 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1255
e4e42b45
NC		 12562010-04-15 Nick Clifton <nickc@redhat.com>
1257
1258 * alpha.h: Update copyright notice to use GPLv3.
1259 * arc.h: Likewise.
1260 * arm.h: Likewise.
1261 * avr.h: Likewise.
1262 * bfin.h: Likewise.
1263 * cgen.h: Likewise.
1264 * convex.h: Likewise.
1265 * cr16.h: Likewise.
1266 * cris.h: Likewise.
1267 * crx.h: Likewise.
1268 * d10v.h: Likewise.
1269 * d30v.h: Likewise.
1270 * dlx.h: Likewise.
1271 * h8300.h: Likewise.
1272 * hppa.h: Likewise.
1273 * i370.h: Likewise.
1274 * i386.h: Likewise.
1275 * i860.h: Likewise.
1276 * i960.h: Likewise.
1277 * ia64.h: Likewise.
1278 * m68hc11.h: Likewise.
1279 * m68k.h: Likewise.
1280 * m88k.h: Likewise.
1281 * maxq.h: Likewise.
1282 * mips.h: Likewise.
1283 * mmix.h: Likewise.
1284 * mn10200.h: Likewise.
1285 * mn10300.h: Likewise.
1286 * msp430.h: Likewise.
1287 * np1.h: Likewise.
1288 * ns32k.h: Likewise.
1289 * or32.h: Likewise.
1290 * pdp11.h: Likewise.
1291 * pj.h: Likewise.
1292 * pn.h: Likewise.
1293 * ppc.h: Likewise.
1294 * pyr.h: Likewise.
1295 * rx.h: Likewise.
1296 * s390.h: Likewise.
1297 * score-datadep.h: Likewise.
1298 * score-inst.h: Likewise.
1299 * sparc.h: Likewise.
1300 * spu-insns.h: Likewise.
1301 * spu.h: Likewise.
1302 * tic30.h: Likewise.
1303 * tic4x.h: Likewise.
1304 * tic54x.h: Likewise.
1305 * tic80.h: Likewise.
1306 * v850.h: Likewise.
1307 * vax.h: Likewise.
1308
40b36596
JM		 13092010-03-25 Joseph Myers <joseph@codesourcery.com>
1310
1311 * tic6x-control-registers.h, tic6x-insn-formats.h,
1312 tic6x-opcode-table.h, tic6x.h: New.
1313
c67a084a
NC		 13142010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1315
1316 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1317
466ef64f
AM		 13182010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1319
1320 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1321
1319d143
L		 13222010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1323
1324 * ia64.h (ia64_find_opcode): Remove argument name.
1325 (ia64_find_next_opcode): Likewise.
1326 (ia64_dis_opcode): Likewise.
1327 (ia64_free_opcode): Likewise.
1328 (ia64_find_dependency): Likewise.
1329
1fbb9298
DE		 13302009-11-22 Doug Evans <dje@sebabeach.org>
1331
1332 * cgen.h: Include bfd_stdint.h.
1333 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1334
ada65aa3
PB		 13352009-11-18 Paul Brook <paul@codesourcery.com>
1336
1337 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1338
9e3c6df6
PB		 13392009-11-17 Paul Brook <paul@codesourcery.com>
1340 Daniel Jacobowitz <dan@codesourcery.com>
1341
1342 * arm.h (ARM_EXT_V6_DSP): Define.
1343 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1344 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1345
0d734b5d
DD		 13462009-11-04 DJ Delorie <dj@redhat.com>
1347
1348 * rx.h (rx_decode_opcode) (mvtipl): Add.
1349 (mvtcp, mvfcp, opecp): Remove.
1350
62f3b8c8
PB		 13512009-11-02 Paul Brook <paul@codesourcery.com>
1352
1353 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1354 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1355 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1356 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1357 FPU_ARCH_NEON_VFP_V4): Define.
1358
ac1e9eca
DE		 13592009-10-23 Doug Evans <dje@sebabeach.org>
1360
1361 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1362 * cgen.h: Update. Improve multi-inclusion macro name.
1363
9fe54b1c
PB		 13642009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1365
1366 * ppc.h (PPC_OPCODE_476): Define.
1367
634b50f2
PB		 13682009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1369
1370 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1371
c7927a3c
NC		 13722009-09-29 DJ Delorie <dj@redhat.com>
1373
1374 * rx.h: New file.
1375
b961e85b
AM		 13762009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1377
1378 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1379
e0d602ec
BE		 13802009-09-21 Ben Elliston <bje@au.ibm.com>
1381
1382 * ppc.h (PPC_OPCODE_PPCA2): New.
1383
96d56e9f
NC		 13842009-09-05 Martin Thuresson <martin@mtme.org>
1385
1386 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1387
d3ce72d0
NC		 13882009-08-29 Martin Thuresson <martin@mtme.org>
1389
1390 * tic30.h (template): Rename type template to
1391 insn_template. Updated code to use new name.
1392 * tic54x.h (template): Rename type template to
1393 insn_template.
1394
824b28db
NH		 13952009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1396
1397 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1398
f865a31d
AG		 13992009-06-11 Anthony Green <green@moxielogic.com>
1400
1401 * moxie.h (MOXIE_F3_PCREL): Define.
1402 (moxie_form3_opc_info): Grow.
1403
0e7c7f11
AG		 14042009-06-06 Anthony Green <green@moxielogic.com>
1405
1406 * moxie.h (MOXIE_F1_M): Define.
1407
20135e4c
NC		 14082009-04-15 Anthony Green <green@moxielogic.com>
1409
1410 * moxie.h: Created.
1411
bcb012d3
DD		 14122009-04-06 DJ Delorie <dj@redhat.com>
1413
1414 * h8300.h: Add relaxation attributes to MOVA opcodes.
1415
69fe9ce5
AM		 14162009-03-10 Alan Modra <amodra@bigpond.net.au>
1417
1418 * ppc.h (ppc_parse_cpu): Declare.
1419
c3b7224a
NC		 14202009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1421
1422 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1423 and _IMM11 for mbitclr and mbitset.
1424 * score-datadep.h: Update dependency information.
1425
066be9f7
PB		 14262009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1427
1428 * ppc.h (PPC_OPCODE_POWER7): New.
1429
fedc618e
DE		 14302009-02-06 Doug Evans <dje@google.com>
1431
1432 * i386.h: Add comment regarding sse* insns and prefixes.
1433
52b6b6b9
JM		 14342009-02-03 Sandip Matte <sandip@rmicorp.com>
1435
1436 * mips.h (INSN_XLR): Define.
1437 (INSN_CHIP_MASK): Update.
1438 (CPU_XLR): Define.
1439 (OPCODE_IS_MEMBER): Update.
1440 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1441
35669430
DE		 14422009-01-28 Doug Evans <dje@google.com>
1443
1444 * opcode/i386.h: Add multiple inclusion protection.
1445 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1446 (EDI_REG_NUM): New macros.
1447 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1448 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1449 (REX_PREFIX_P): New macro.
35669430 1450
1cb0a767
PB		 14512009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1452
1453 * ppc.h (struct powerpc_opcode): New field "deprecated".
1454 (PPC_OPCODE_NOPOWER4): Delete.
1455
3aa3176b
TS		 14562008-11-28 Joshua Kinard <kumba@gentoo.org>
1457
1458 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1459 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1460
8e79c3df
CM		 14612008-11-18 Catherine Moore <clm@codesourcery.com>
1462
1463 * arm.h (FPU_NEON_FP16): New.
1464 (FPU_ARCH_NEON_FP16): New.
1465
de9a3e51
CF		 14662008-11-06 Chao-ying Fu <fu@mips.com>
1467
1468 * mips.h: Doucument '1' for 5-bit sync type.
1469
1ca35711
L		 14702008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1471
1472 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1473 IA64_RS_CR.
1474
9b4e5766
PB		 14752008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1476
1477 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1478
081ba1b3
AM		 14792008-07-30 Michael J. Eager <eager@eagercon.com>
1480
1481 * ppc.h (PPC_OPCODE_405): Define.
1482 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1483
fa452fa6
PB		 14842008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1485
1486 * ppc.h (ppc_cpu_t): New typedef.
1487 (struct powerpc_opcode <flags>): Use it.
1488 (struct powerpc_operand <insert, extract>): Likewise.
1489 (struct powerpc_macro <flags>): Likewise.
1490
bb35fb24
NC		 14912008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1492
1493 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1494 Update comment before MIPS16 field descriptors to mention MIPS16.
1495 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1496 BBIT.
1497 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1498 New bit masks and shift counts for cins and exts.
1499
dd3cbb7e
NC		 1500 * mips.h: Document new field descriptors +Q.
1501 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1502
d0799671
AN		 15032008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1504
9aff4b7a 1505 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1506 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1507
19a6653c
AM		 15082008-04-14 Edmar Wienskoski <edmar@freescale.com>
1509
1510 * ppc.h: (PPC_OPCODE_E500MC): New.
1511
c0f3af97
L		 15122008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1513
1514 * i386.h (MAX_OPERANDS): Set to 5.
1515 (MAX_MNEM_SIZE): Changed to 20.
1516
e210c36b
NC		 15172008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1518
1519 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1520
b1cc4aeb
PB		 15212008-03-09 Paul Brook <paul@codesourcery.com>
1522
1523 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1524
7e806470
PB		 15252008-03-04 Paul Brook <paul@codesourcery.com>
1526
1527 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1528 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1529 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1530
7b2185f9 15312008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1532 Nick Clifton <nickc@redhat.com>
1533
1534 PR 3134
1535 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1536 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1537 set.
af7329f0 1538
796d5313
NC		 15392008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1540
1541 * cr16.h (cr16_num_optab): Declared.
1542
d669d37f
NC		 15432008-02-14 Hakan Ardo <hakan@debian.org>
1544
1545 PR gas/2626
1546 * avr.h (AVR_ISA_2xxe): Define.
1547
e6429699
AN		 15482008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1549
1550 * mips.h: Update copyright.
1551 (INSN_CHIP_MASK): New macro.
1552 (INSN_OCTEON): New macro.
1553 (CPU_OCTEON): New macro.
1554 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1555
e210c36b
NC		 15562008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1557
1558 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1559
15602008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1561
1562 * avr.h (AVR_ISA_USB162): Add new opcode set.
1563 (AVR_ISA_AVR3): Likewise.
1564
350cc38d
MS		 15652007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1566
1567 * mips.h (INSN_LOONGSON_2E): New.
1568 (INSN_LOONGSON_2F): New.
1569 (CPU_LOONGSON_2E): New.
1570 (CPU_LOONGSON_2F): New.
1571 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1572
56950294
MS		 15732007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1574
1575 * mips.h (INSN_ISA*): Redefine certain values as an
1576 enumeration. Update comments.
1577 (mips_isa_table): New.
1578 (ISA_MIPS*): Redefine to match enumeration.
1579 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1580 values.
1581
c3d65c1c
BE		 15822007-08-08 Ben Elliston <bje@au.ibm.com>
1583
1584 * ppc.h (PPC_OPCODE_PPCPS): New.
1585
0fdaa005
L		 15862007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1587
1588 * m68k.h: Document j K & E.
1589
15902007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1591
1592 * cr16.h: New file for CR16 target.
1593
3896c469
AM		 15942007-05-02 Alan Modra <amodra@bigpond.net.au>
1595
1596 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1597
9a2e615a
NS		 15982007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1599
1600 * m68k.h (mcfisa_c): New.
1601 (mcfusp, mcf_mask): Adjust.
1602
b84bf58a
AM		 16032007-04-20 Alan Modra <amodra@bigpond.net.au>
1604
1605 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1606 (num_powerpc_operands): Declare.
1607 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1608 (PPC_OPERAND_PLUS1): Define.
1609
831480e9 16102007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1611
1612 * i386.h (REX_MODE64): Renamed to ...
1613 (REX_W): This.
1614 (REX_EXTX): Renamed to ...
1615 (REX_R): This.
1616 (REX_EXTY): Renamed to ...
1617 (REX_X): This.
1618 (REX_EXTZ): Renamed to ...
1619 (REX_B): This.
1620
0b1cf022
L		 16212007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1622
1623 * i386.h: Add entries from config/tc-i386.h and move tables
1624 to opcodes/i386-opc.h.
1625
d796c0ad
L		 16262007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1627
1628 * i386.h (FloatDR): Removed.
1629 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1630
30ac7323
AM		 16312007-03-01 Alan Modra <amodra@bigpond.net.au>
1632
1633 * spu-insns.h: Add soma double-float insns.
1634
8b082fb1 16352007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1636 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1637
1638 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1639 (INSN_DSPR2): Add flag for DSP R2 instructions.
1640 (M_BALIGN): New macro.
1641
4eed87de
AM		 16422007-02-14 Alan Modra <amodra@bigpond.net.au>
1643
1644 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1645 and Seg3ShortFrom with Shortform.
1646
fda592e8
L		 16472007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1648
1649 PR gas/4027
1650 * i386.h (i386_optab): Put the real "test" before the pseudo
1651 one.
1652
3bdcfdf4
KH		 16532007-01-08 Kazu Hirata <kazu@codesourcery.com>
1654
1655 * m68k.h (m68010up): OR fido_a.
1656
9840d27e
KH		 16572006-12-25 Kazu Hirata <kazu@codesourcery.com>
1658
1659 * m68k.h (fido_a): New.
1660
c629cdac
KH		 16612006-12-24 Kazu Hirata <kazu@codesourcery.com>
1662
1663 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1664 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1665 values.
1666
b7d9ef37
L		 16672006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1668
1669 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1670
b138abaa
NC		 16712006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1672
1673 * score-inst.h (enum score_insn_type): Add Insn_internal.
1674
e9f53129
AM		 16752006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1676 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1677 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1678 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1679 Alan Modra <amodra@bigpond.net.au>
1680
1681 * spu-insns.h: New file.
1682 * spu.h: New file.
1683
ede602d7
AM		 16842006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1685
1686 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1687
7918206c
MM		 16882006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1689
e4e42b45 1690 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1691 in amdfam10 architecture.
1692
ef05d495
L		 16932006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1694
1695 * i386.h: Replace CpuMNI with CpuSSSE3.
1696
2d447fca 16972006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1698 Joseph Myers <joseph@codesourcery.com>
1699 Ian Lance Taylor <ian@wasabisystems.com>
1700 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1701
1702 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1703
1c0d3aa6
NC		 17042006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1705
1706 * score-datadep.h: New file.
1707 * score-inst.h: New file.
1708
c2f0420e
L		 17092006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1710
1711 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1712 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1713 movdq2q and movq2dq.
1714
050dfa73
MM		 17152006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1716 Michael Meissner <michael.meissner@amd.com>
1717
1718 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1719
15965411
L		 17202006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1721
1722 * i386.h (i386_optab): Add "nop" with memory reference.
1723
46e883c5
L		 17242006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1725
1726 * i386.h (i386_optab): Update comment for 64bit NOP.
1727
9622b051
AM		 17282006-06-06 Ben Elliston <bje@au.ibm.com>
1729 Anton Blanchard <anton@samba.org>
1730
1731 * ppc.h (PPC_OPCODE_POWER6): Define.
1732 Adjust whitespace.
1733
a9e24354
TS		 17342006-06-05 Thiemo Seufer <ths@mips.com>
1735
e4e42b45 1736 * mips.h: Improve description of MT flags.
a9e24354 1737
a596001e
RS		 17382006-05-25 Richard Sandiford <richard@codesourcery.com>
1739
1740 * m68k.h (mcf_mask): Define.
1741
d43b4baf 17422006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1743 David Ung <davidu@mips.com>
d43b4baf
TS		 1744
1745 * mips.h (enum): Add macro M_CACHE_AB.
1746
39a7806d 17472006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1748 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1749 David Ung <davidu@mips.com>
1750
1751 * mips.h: Add INSN_SMARTMIPS define.
1752
9bcd4f99 17532006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1754 David Ung <davidu@mips.com>
9bcd4f99
TS		 1755
1756 * mips.h: Defines udi bits and masks. Add description of
1757 characters which may appear in the args field of udi
1758 instructions.
1759
ef0ee844
TS		 17602006-04-26 Thiemo Seufer <ths@networkno.de>
1761
1762 * mips.h: Improve comments describing the bitfield instruction
1763 fields.
1764
f7675147
L		 17652006-04-26 Julian Brown <julian@codesourcery.com>
1766
1767 * arm.h (FPU_VFP_EXT_V3): Define constant.
1768 (FPU_NEON_EXT_V1): Likewise.
1769 (FPU_VFP_HARD): Update.
1770 (FPU_VFP_V3): Define macro.
1771 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1772
ef0ee844 17732006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1774
1775 * avr.h (AVR_ISA_PWMx): New.
1776
2da12c60
NS		 17772006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1778
1779 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1780 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1781 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1782 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1783 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1784
0715c387
PB		 17852006-03-10 Paul Brook <paul@codesourcery.com>
1786
1787 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1788
34bdd094
DA		 17892006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1790
1791 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1792 first. Correct mask of bb "B" opcode.
1793
331d2d0d
L		 17942006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1795
1796 * i386.h (i386_optab): Support Intel Merom New Instructions.
1797
62b3e311
PB		 17982006-02-24 Paul Brook <paul@codesourcery.com>
1799
1800 * arm.h: Add V7 feature bits.
1801
59cf82fe
L		 18022006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1803
1804 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1805
e74cfd16
PB		 18062006-01-31 Paul Brook <paul@codesourcery.com>
1807 Richard Earnshaw <rearnsha@arm.com>
1808
1809 * arm.h: Use ARM_CPU_FEATURE.
1810 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1811 (arm_feature_set): Change to a structure.
1812 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1813 ARM_FEATURE): New macros.
1814
5b3f8a92
HPN		 18152005-12-07 Hans-Peter Nilsson <hp@axis.com>
1816
1817 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1818 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1819 (ADD_PC_INCR_OPCODE): Don't define.
1820
cb712a9e
L		 18212005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1822
1823 PR gas/1874
1824 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1825
0499d65b
TS		 18262005-11-14 David Ung <davidu@mips.com>
1827
1828 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1829 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1830 save/restore encoding of the args field.
1831
ea5ca089
DB		 18322005-10-28 Dave Brolley <brolley@redhat.com>
1833
1834 Contribute the following changes:
1835 2005-02-16 Dave Brolley <brolley@redhat.com>
1836
1837 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1838 cgen_isa_mask_* to cgen_bitset_*.
1839 * cgen.h: Likewise.
1840
16175d96
DB		 1841 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1842
1843 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1844 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1845 (CGEN_CPU_TABLE): Make isas a ponter.
1846
1847 2003-09-29 Dave Brolley <brolley@redhat.com>
1848
1849 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1850 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1851 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1852
1853 2002-12-13 Dave Brolley <brolley@redhat.com>
1854
1855 * cgen.h (symcat.h): #include it.
1856 (cgen-bitset.h): #include it.
1857 (CGEN_ATTR_VALUE_TYPE): Now a union.
1858 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1859 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1860 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1861 * cgen-bitset.h: New file.
1862
3c9b82ba
NC		 18632005-09-30 Catherine Moore <clm@cm00re.com>
1864
1865 * bfin.h: New file.
1866
6a2375c6
JB		 18672005-10-24 Jan Beulich <jbeulich@novell.com>
1868
1869 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1870 indirect operands.
1871
c06a12f8
DA		 18722005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1873
1874 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1875 Add FLAG_STRICT to pa10 ftest opcode.
1876
4d443107
DA		 18772005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1878
1879 * hppa.h (pa_opcodes): Remove lha entries.
1880
f0a3b40f
DA		 18812005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1882
1883 * hppa.h (FLAG_STRICT): Revise comment.
1884 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1885 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1886 entries for "fdc".
1887
e210c36b
NC		 18882005-09-30 Catherine Moore <clm@cm00re.com>
1889
1890 * bfin.h: New file.
1891
1b7e1362
DA		 18922005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1893
1894 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1895
089b39de
CF		 18962005-09-06 Chao-ying Fu <fu@mips.com>
1897
1898 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1899 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1900 define.
1901 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1902 (INSN_ASE_MASK): Update to include INSN_MT.
1903 (INSN_MT): New define for MT ASE.
1904
93c34b9b
CF		 19052005-08-25 Chao-ying Fu <fu@mips.com>
1906
1907 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1908 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1909 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1910 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1911 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1912 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1913 instructions.
1914 (INSN_DSP): New define for DSP ASE.
1915
848cf006
AM		 19162005-08-18 Alan Modra <amodra@bigpond.net.au>
1917
1918 * a29k.h: Delete.
1919
36ae0db3
DJ		 19202005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1921
1922 * ppc.h (PPC_OPCODE_E300): Define.
1923
8c929562
MS		 19242005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1925
1926 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1927
f7b8cccc
DA		 19282005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1929
1930 PR gas/336
1931 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1932 and pitlb.
1933
8b5328ac
JB		 19342005-07-27 Jan Beulich <jbeulich@novell.com>
1935
1936 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1937 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1938 Add movq-s as 64-bit variants of movd-s.
1939
f417d200
DA		 19402005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1941
18b3bdfc
DA		 1942 * hppa.h: Fix punctuation in comment.
1943
f417d200
DA		 1944 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1945 implicit space-register addressing. Set space-register bits on opcodes
1946 using implicit space-register addressing. Add various missing pa20
1947 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1948 space-register addressing. Use "fE" instead of "fe" in various
1949 fstw opcodes.
1950
9a145ce6
JB		 19512005-07-18 Jan Beulich <jbeulich@novell.com>
1952
1953 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1954
90700ea2
L		 19552007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1956
1957 * i386.h (i386_optab): Support Intel VMX Instructions.
1958
48f130a8
DA		 19592005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1960
1961 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1962
30123838
JB		 19632005-07-05 Jan Beulich <jbeulich@novell.com>
1964
1965 * i386.h (i386_optab): Add new insns.
1966
47b0e7ad
NC		 19672005-07-01 Nick Clifton <nickc@redhat.com>
1968
1969 * sparc.h: Add typedefs to structure declarations.
1970
b300c311
L		 19712005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1972
1973 PR 1013
1974 * i386.h (i386_optab): Update comments for 64bit addressing on
1975 mov. Allow 64bit addressing for mov and movq.
1976
2db495be
DA		 19772005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1978
1979 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1980 respectively, in various floating-point load and store patterns.
1981
caa05036
DA		 19822005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1983
1984 * hppa.h (FLAG_STRICT): Correct comment.
1985 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1986 PA 2.0 mneumonics when equivalent. Entries with cache control
1987 completers now require PA 1.1. Adjust whitespace.
1988
f4411256
AM		 19892005-05-19 Anton Blanchard <anton@samba.org>
1990
1991 * ppc.h (PPC_OPCODE_POWER5): Define.
1992
e172dbf8
NC		 19932005-05-10 Nick Clifton <nickc@redhat.com>
1994
1995 * Update the address and phone number of the FSF organization in
1996 the GPL notices in the following files:
1997 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1998 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1999 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2000 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2001 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2002 tic54x.h, tic80.h, v850.h, vax.h
2003
e44823cf
JB		 20042005-05-09 Jan Beulich <jbeulich@novell.com>
2005
2006 * i386.h (i386_optab): Add ht and hnt.
2007
791fe849
MK		 20082005-04-18 Mark Kettenis <kettenis@gnu.org>
2009
2010 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2011 Add xcrypt-ctr. Provide aliases without hyphens.
2012
faa7ef87
L		 20132005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2014
a63027e5
L		 2015 Moved from ../ChangeLog
2016
faa7ef87
L		 2017 2005-04-12 Paul Brook <paul@codesourcery.com>
2018 * m88k.h: Rename psr macros to avoid conflicts.
2019
2020 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2021 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2022 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2023 and ARM_ARCH_V6ZKT2.
2024
2025 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2026 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2027 Remove redundant instruction types.
2028 (struct argument): X_op - new field.
2029 (struct cst4_entry): Remove.
2030 (no_op_insn): Declare.
2031
2032 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2033 * crx.h (enum argtype): Rename types, remove unused types.
2034
2035 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2036 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2037 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2038 (enum operand_type): Rearrange operands, edit comments.
2039 replace us<N> with ui<N> for unsigned immediate.
2040 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2041 displacements (respectively).
2042 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2043 (instruction type): Add NO_TYPE_INS.
2044 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2045 (operand_entry): New field - 'flags'.
2046 (operand flags): New.
2047
2048 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2049 * crx.h (operand_type): Remove redundant types i3, i4,
2050 i5, i8, i12.
2051 Add new unsigned immediate types us3, us4, us5, us16.
2052
bc4bd9ab
MK		 20532005-04-12 Mark Kettenis <kettenis@gnu.org>
2054
2055 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2056 adjust them accordingly.
2057
373ff435
JB		 20582005-04-01 Jan Beulich <jbeulich@novell.com>
2059
2060 * i386.h (i386_optab): Add rdtscp.
2061
4cc91dba
L		 20622005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2063
2064 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2065 between memory and segment register. Allow movq for moving between
2066 general-purpose register and segment register.
4cc91dba 2067
9ae09ff9
JB		 20682005-02-09 Jan Beulich <jbeulich@novell.com>
2069
2070 PR gas/707
2071 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2072 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2073 fnstsw.
2074
638e7a64
NS		 20752006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2076
2077 * m68k.h (m68008, m68ec030, m68882): Remove.
2078 (m68k_mask): New.
2079 (cpu_m68k, cpu_cf): New.
2080 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2081 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2082
90219bd0
AO		 20832005-01-25 Alexandre Oliva <aoliva@redhat.com>
2084
2085 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2086 * cgen.h (enum cgen_parse_operand_type): Add
2087 CGEN_PARSE_OPERAND_SYMBOLIC.
2088
239cb185
FF		 20892005-01-21 Fred Fish <fnf@specifixinc.com>
2090
2091 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2092 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2093 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2094
dc9a9f39
FF		 20952005-01-19 Fred Fish <fnf@specifixinc.com>
2096
2097 * mips.h (struct mips_opcode): Add new pinfo2 member.
2098 (INSN_ALIAS): New define for opcode table entries that are
2099 specific instances of another entry, such as 'move' for an 'or'
2100 with a zero operand.
2101 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2102 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2103
98e7aba8
ILT		 21042004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2105
2106 * mips.h (CPU_RM9000): Define.
2107 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2108
37edbb65
JB		 21092004-11-25 Jan Beulich <jbeulich@novell.com>
2110
2111 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2112 to/from test registers are illegal in 64-bit mode. Add missing
2113 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2114 (previously one had to explicitly encode a rex64 prefix). Re-enable
2115 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2116 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2117
21182004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2119
2120 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2121 available only with SSE2. Change the MMX additions introduced by SSE
2122 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2123 instructions by their now designated identifier (since combining i686
2124 and 3DNow! does not really imply 3DNow!A).
2125
f5c7edf4
AM		 21262004-11-19 Alan Modra <amodra@bigpond.net.au>
2127
2128 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2129 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2130
7499d566
NC		 21312004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2132 Vineet Sharma <vineets@noida.hcltech.com>
2133
2134 * maxq.h: New file: Disassembly information for the maxq port.
2135
bcb9eebe
L		 21362004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2137
2138 * i386.h (i386_optab): Put back "movzb".
2139
94bb3d38
HPN		 21402004-11-04 Hans-Peter Nilsson <hp@axis.com>
2141
2142 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2143 comments. Remove member cris_ver_sim. Add members
2144 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2145 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2146 (struct cris_support_reg, struct cris_cond15): New types.
2147 (cris_conds15): Declare.
2148 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2149 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2150 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2151 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2152 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2153 SIZE_FIELD_UNSIGNED.
2154
37edbb65 21552004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2156
2157 * i386.h (sldx_Suf): Remove.
2158 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2159 (q_FP): Define, implying no REX64.
2160 (x_FP, sl_FP): Imply FloatMF.
2161 (i386_optab): Split reg and mem forms of moving from segment registers
2162 so that the memory forms can ignore the 16-/32-bit operand size
2163 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2164 all non-floating-point instructions. Unite 32- and 64-bit forms of
2165 movsx, movzx, and movd. Adjust floating point operations for the above
2166 changes to the *FP macros. Add DefaultSize to floating point control
2167 insns operating on larger memory ranges. Remove left over comments
2168 hinting at certain insns being Intel-syntax ones where the ones
2169 actually meant are already gone.
2170
48c9f030
NC		 21712004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2172
2173 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2174 instruction type.
2175
0dd132b6
NC		 21762004-09-30 Paul Brook <paul@codesourcery.com>
2177
2178 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2179 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2180
23794b24
MM		 21812004-09-11 Theodore A. Roth <troth@openavr.org>
2182
2183 * avr.h: Add support for
2184 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2185
2a309db0
AM		 21862004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2187
2188 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2189
b18c562e
NC		 21902004-08-24 Dmitry Diky <diwil@spec.ru>
2191
2192 * msp430.h (msp430_opc): Add new instructions.
2193 (msp430_rcodes): Declare new instructions.
2194 (msp430_hcodes): Likewise..
2195
45d313cd
NC		 21962004-08-13 Nick Clifton <nickc@redhat.com>
2197
2198 PR/301
2199 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2200 processors.
2201
30d1c836
ML		 22022004-08-30 Michal Ludvig <mludvig@suse.cz>
2203
2204 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2205
9a45f1c2
L		 22062004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2207
2208 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2209
543613e9
NC		 22102004-07-21 Jan Beulich <jbeulich@novell.com>
2211
2212 * i386.h: Adjust instruction descriptions to better match the
2213 specification.
2214
b781e558
RE		 22152004-07-16 Richard Earnshaw <rearnsha@arm.com>
2216
2217 * arm.h: Remove all old content. Replace with architecture defines
2218 from gas/config/tc-arm.c.
2219
8577e690
AS		 22202004-07-09 Andreas Schwab <schwab@suse.de>
2221
2222 * m68k.h: Fix comment.
2223
1fe1f39c
NC		 22242004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2225
2226 * crx.h: New file.
2227
1d9f512f
AM		 22282004-06-24 Alan Modra <amodra@bigpond.net.au>
2229
2230 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2231
be8c092b
NC		 22322004-05-24 Peter Barada <peter@the-baradas.com>
2233
2234 * m68k.h: Add 'size' to m68k_opcode.
2235
6b6e92f4
NC		 22362004-05-05 Peter Barada <peter@the-baradas.com>
2237
2238 * m68k.h: Switch from ColdFire chip name to core variant.
2239
22402004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2241
2242 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2243 descriptions for new EMAC cases.
2244 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2245 handle Motorola MAC syntax.
2246 Allow disassembly of ColdFire V4e object files.
2247
fdd12ef3
AM		 22482004-03-16 Alan Modra <amodra@bigpond.net.au>
2249
2250 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2251
3922a64c
L		 22522004-03-12 Jakub Jelinek <jakub@redhat.com>
2253
2254 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2255
1f45d988
ML		 22562004-03-12 Michal Ludvig <mludvig@suse.cz>
2257
2258 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2259
0f10071e
ML		 22602004-03-12 Michal Ludvig <mludvig@suse.cz>
2261
2262 * i386.h (i386_optab): Added xstore/xcrypt insns.
2263
3255318a
NC		 22642004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2265
2266 * h8300.h (32bit ldc/stc): Add relaxing support.
2267
ca9a79a1 22682004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2269
ca9a79a1
NC		 2270 * h8300.h (BITOP): Pass MEMRELAX flag.
2271
875a0b14
NC		 22722004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2273
2274 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2275 except for the H8S.
252b5132 2276
c9e214e5 2277For older changes see ChangeLog-9103
252b5132 2278\f
b90efa5b 2279Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2280
2281Copying and distribution of this file, with or without modification,
2282are permitted in any medium without royalty provided the copyright
2283notice and this notice are preserved.
2284
252b5132 2285Local Variables:
c9e214e5
AM		 2286mode: change-log
2287left-margin: 8
2288fill-column: 74
252b5132
RH		 2289version-control: never
2290End:
GDB Binutils - Deliverables
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