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Stop using nowarnings in gdb/testsuite/gdb.multi/
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
c8a6db6f
MW		 12015-12-10 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64.h (AARCH64_FEATURE_RAS): New.
4 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
5
af117b3c
MW		 62015-12-10 Matthew Wahab <matthew.wahab@arm.com>
7
8 * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
9 AARCH64_FEATURE_V8_1.
10 (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
11 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
12 AARCH64_FEATURE_V8_1.
13
24b368f8
CZ		 142015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
15
16 * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
17
d685192a
MW		 182015-11-27 Matthew Wahab <matthew.wahab@arm.com>
19
20 * aarch64.h (aarch64_op): Add OP_BFC.
21
87018195
MW		 222015-11-27 Matthew Wahab <matthew.wahab@arm.com>
23
24 * aarch64.h (AARCH64_FEATURE_F16): New.
25 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
26 features.
27
250aafa4
MW		 282015-11-20 Matthew Wahab <matthew.wahab@arm.com>
29
30 * aarch64.h (AARCH64_FEATURE_V8_1): New.
31 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
32
56a1b672
MW		 332015-11-19 Matthew Wahab <matthew.wahab@arm.com>
34
35 * arm.h (ARM_EXT2_V8_2A): New.
36 (ARM_ARCH_V8_2A): New.
37
acb787b0
MW		 382015-11-19 Matthew Wahab <matthew.wahab@arm.com>
39
40 * aarch64.h (AARCH64_FEATURE_V8_2): New.
41 (AARCH64_ARCH_V8_2): New.
42
a680de9a
PB		 432015-11-11 Alan Modra <amodra@gmail.com>
44 Peter Bergner <bergner@vnet.ibm.com>
45
46 * ppc.h (PPC_OPCODE_POWER9): New define.
47 (PPC_OPCODE_VSX3): Likewise.
48
854eb72b
NC		 492015-11-02 Nick Clifton <nickc@redhat.com>
50
51 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
52
e292aa7a
NC		 532015-11-02 Nick Clifton <nickc@redhat.com>
54
55 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
56
43cdf5ae
YQ		 572015-10-28 Yao Qi <yao.qi@linaro.org>
58
59 * aarch64.h (aarch64_decode_insn): Update declaration.
60
875880c6
YQ		 612015-10-07 Yao Qi <yao.qi@linaro.org>
62
63 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
64 <name>: New field.
65
d3e12b29
YQ		 662015-10-07 Yao Qi <yao.qi@linaro.org>
67
68 * aarch64.h [__cplusplus]: Wrap in extern "C".
69
886a2506
NC		 702015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
71 Cupertino Miranda <cmiranda@synopsys.com>
72
73 * arc-func.h: New file.
74 * arc.h: Likewise.
75
e141d84e
YQ		 762015-10-02 Yao Qi <yao.qi@linaro.org>
77
78 * aarch64.h (aarch64_zero_register_p): Move the declaration
79 to column one.
80
36f4aab1
YQ		 812015-10-02 Yao Qi <yao.qi@linaro.org>
82
83 * aarch64.h (aarch64_decode_insn): Declare it.
84
7ecc513a
DV		 852015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
86
87 * s390.h (S390_INSTR_FLAG_HTM): New flag.
88 (S390_INSTR_FLAG_VX): New flag.
89 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
90
b6518b38
NC		 912015-09-23 Nick Clifton <nickc@redhat.com>
92
93 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
94 shifting.
95
f04265ec
NC		 962015-09-22 Nick Clifton <nickc@redhat.com>
97
98 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
99
7bdf96ef
NC		 1002015-09-09 Daniel Santos <daniel.santos@pobox.com>
101
102 * visium.h (gen_reg_table): Make static.
103 (fp_reg_table): Likewise.
104 (cc_table): Likewise.
105
f33026a9
MW		 1062015-07-20 Matthew Wahab <matthew.wahab@arm.com>
107
108 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
109 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
110 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
111 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
112
ef5a96d5
AM		 1132015-07-03 Alan Modra <amodra@gmail.com>
114
115 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
116
c8c8175b
SL		 1172015-07-01 Sandra Loosemore <sandra@codesourcery.com>
118 Cesar Philippidis <cesar@codesourcery.com>
119
120 * nios2.h (enum iw_format_type): Add R2 formats.
121 (enum overflow_type): Add signed_immed12_overflow and
122 enumeration_overflow for R2.
123 (struct nios2_opcode): Document new argument letters for R2.
124 (REG_3BIT, REG_LDWM, REG_POP): Define.
125 (includes): Include nios2r2.h.
126 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
127 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
128 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
129 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
130 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
131 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
132 Declare.
133 * nios2r2.h: New file.
134
11a0cf2e
PB		 1352015-06-19 Peter Bergner <bergner@vnet.ibm.com>
136
137 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
138 (ppc_optional_operand_value): New inline function.
139
88f0ea34
MW		 1402015-06-04 Matthew Wahab <matthew.wahab@arm.com>
141
142 * aarch64.h (AARCH64_V8_1): New.
143
a5932920
MW		 1442015-06-03 Matthew Wahab <matthew.wahab@arm.com>
145
146 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
147 (ARM_ARCH_V8_1A): New.
148 (ARM_ARCH_V8_1A_FP): New.
149 (ARM_ARCH_V8_1A_SIMD): New.
150 (ARM_ARCH_V8_1A_CRYPTOV1): New.
151 (ARM_FEATURE_CORE): New.
152
ddfded2f
MW		 1532015-06-02 Matthew Wahab <matthew.wahab@arm.com>
154
155 * arm.h (ARM_EXT2_PAN): New.
156 (ARM_FEATURE_CORE_HIGH): New.
157
1af1dd51
MW		 1582015-06-02 Matthew Wahab <matthew.wahab@arm.com>
159
160 * arm.h (ARM_FEATURE_ALL): New.
161
9e1f0fa7
MW		 1622015-06-02 Matthew Wahab <matthew.wahab@arm.com>
163
164 * aarch64.h (AARCH64_FEATURE_RDMA): New.
165
290806fd
MW		 1662015-06-02 Matthew Wahab <matthew.wahab@arm.com>
167
168 * aarch64.h (AARCH64_FEATURE_LOR): New.
169
f21cce2c
MW		 1702015-06-01 Matthew Wahab <matthew.wahab@arm.com>
171
172 * aarch64.h (AARCH64_FEATURE_PAN): New.
173 (aarch64_sys_reg_supported_p): Declare.
174 (aarch64_pstatefield_supported_p): Declare.
175
0952813b
DD		 1762015-04-30 DJ Delorie <dj@redhat.com>
177
178 * rl78.h (RL78_Dis_Isa): New.
179 (rl78_decode_opcode): Add ISA parameter.
180
823d2571
TG		 1812015-03-24 Terry Guo <terry.guo@arm.com>
182
183 * arm.h (arm_feature_set): Extended to provide more available bits.
184 (ARM_ANY): Updated to follow above new definition.
185 (ARM_CPU_HAS_FEATURE): Likewise.
186 (ARM_CPU_IS_ANY): Likewise.
187 (ARM_MERGE_FEATURE_SETS): Likewise.
188 (ARM_CLEAR_FEATURE): Likewise.
189 (ARM_FEATURE): Likewise.
190 (ARM_FEATURE_COPY): New macro.
191 (ARM_FEATURE_EQUAL): Likewise.
192 (ARM_FEATURE_ZERO): Likewise.
193 (ARM_FEATURE_CORE_EQUAL): Likewise.
194 (ARM_FEATURE_LOW): Likewise.
195 (ARM_FEATURE_CORE_LOW): Likewise.
196 (ARM_FEATURE_CORE_COPROC): Likewise.
197
f63c1776
PA		 1982015-02-19 Pedro Alves <palves@redhat.com>
199
200 * cgen.h [__cplusplus]: Wrap in extern "C".
201 * msp430-decode.h [__cplusplus]: Likewise.
202 * nios2.h [__cplusplus]: Likewise.
203 * rl78.h [__cplusplus]: Likewise.
204 * rx.h [__cplusplus]: Likewise.
205 * tilegx.h [__cplusplus]: Likewise.
206
3f8107ab
AM		 2072015-01-28 James Bowman <james.bowman@ftdichip.com>
208
209 * ft32.h: New file.
210
1e2e8c52
AK		 2112015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
212
213 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
214
b90efa5b
AM		 2152015-01-01 Alan Modra <amodra@gmail.com>
216
217 Update year range in copyright notice of all files.
218
bffb6004
AG		 2192014-12-27 Anthony Green <green@moxielogic.com>
220
221 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
222 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
223
1945cfa5
EB		 2242014-12-06 Eric Botcazou <ebotcazou@adacore.com>
225
226 * visium.h: New file.
227
d306ce58
SL		 2282014-11-28 Sandra Loosemore <sandra@codesourcery.com>
229
230 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
231 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
232 (NIOS2_INSN_OPTARG): Renumber.
233
b4714c7c
SL		 2342014-11-06 Sandra Loosemore <sandra@codesourcery.com>
235
236 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
237 declaration. Fix obsolete comment.
238
96ba4233
SL		 2392014-10-23 Sandra Loosemore <sandra@codesourcery.com>
240
241 * nios2.h (enum iw_format_type): New.
242 (struct nios2_opcode): Update comments. Add size and format fields.
243 (NIOS2_INSN_OPTARG): New.
244 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
245 (struct nios2_reg): Add regtype field.
246 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
247 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
248 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
249 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
250 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
251 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
252 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
253 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
254 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
255 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
256 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
257 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
258 (OP_MASK_OP, OP_SH_OP): Delete.
259 (OP_MASK_IOP, OP_SH_IOP): Delete.
260 (OP_MASK_IRD, OP_SH_IRD): Delete.
261 (OP_MASK_IRT, OP_SH_IRT): Delete.
262 (OP_MASK_IRS, OP_SH_IRS): Delete.
263 (OP_MASK_ROP, OP_SH_ROP): Delete.
264 (OP_MASK_RRD, OP_SH_RRD): Delete.
265 (OP_MASK_RRT, OP_SH_RRT): Delete.
266 (OP_MASK_RRS, OP_SH_RRS): Delete.
267 (OP_MASK_JOP, OP_SH_JOP): Delete.
268 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
269 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
270 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
271 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
272 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
273 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
274 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
275 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
276 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
277 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
278 (OP_MASK_<insn>, OP_MASK): Delete.
279 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
280 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
281 Include nios2r1.h to define new instruction opcode constants
282 and accessors.
283 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
284 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
285 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
286 (NUMOPCODES, NUMREGISTERS): Delete.
287 * nios2r1.h: New file.
288
0b6be415
JM		 2892014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
290
291 * sparc.h (HWCAP2_VIS3B): Documentation improved.
292
3d68f91c
JM		 2932014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
294
295 * sparc.h (sparc_opcode): new field `hwcaps2'.
296 (HWCAP2_FJATHPLUS): New define.
297 (HWCAP2_VIS3B): Likewise.
298 (HWCAP2_ADP): Likewise.
299 (HWCAP2_SPARC5): Likewise.
300 (HWCAP2_MWAIT): Likewise.
301 (HWCAP2_XMPMUL): Likewise.
302 (HWCAP2_XMONT): Likewise.
303 (HWCAP2_NSEC): Likewise.
304 (HWCAP2_FJATHHPC): Likewise.
305 (HWCAP2_FJDES): Likewise.
306 (HWCAP2_FJAES): Likewise.
307 Document the new operand kind `{', corresponding to the mcdper
308 ancillary state register.
309 Document the new operand kind }, which represents frsd floating
310 point registers (double precision) which must be the same than
311 frs1 in its containing instruction.
312
40c7a7cb
KLC		 3132014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
314
72f4393d 315 * nds32.h: Add new opcode declaration.
40c7a7cb 316
7361da2c
AB		 3172014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
318 Matthew Fortune <matthew.fortune@imgtec.com>
319
320 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
321 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
322 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
323 +I, +O, +R, +:, +\, +", +;
324 (mips_check_prev_operand): New struct.
325 (INSN2_FORBIDDEN_SLOT): New define.
326 (INSN_ISA32R6): New define.
327 (INSN_ISA64R6): New define.
328 (INSN_UPTO32R6): New define.
329 (INSN_UPTO64R6): New define.
330 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
331 (ISA_MIPS32R6): New define.
332 (ISA_MIPS64R6): New define.
333 (CPU_MIPS32R6): New define.
334 (CPU_MIPS64R6): New define.
335 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
336
ee804238
JW		 3372014-09-03 Jiong Wang <jiong.wang@arm.com>
338
339 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
340 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
341 (aarch64_insn_class): Add lse_atomic.
342 (F_LSE_SZ): New field added.
343 (opcode_has_special_coder): Recognize F_LSE_SZ.
344
5575639b
MR		 3452014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
346
347 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
348 over to `+J'.
349
43885403
MF		 3502014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
351
352 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
353 (INSN_LOAD_COPROC): New define.
354 (INSN_COPROC_MOVE_DELAY): Rename to...
355 (INSN_COPROC_MOVE): New define.
356
f36e8886 3572014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 358 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
359 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
360 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 361
362 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
363 (AVR_ISA_2xxxa): Define ISA without LPM.
364 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
365 Add doc for contraint used in 16 bit lds/sts.
366 Adjust ISA group for icall, ijmp, pop and push.
367 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
368
00b32ff2
NC		 3692014-05-19 Nick Clifton <nickc@redhat.com>
370
371 * msp430.h (struct msp430_operand_s): Add vshift field.
372
ae52f483
AB		 3732014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
374
375 * mips.h (INSN_ISA_MASK): Updated.
376 (INSN_ISA32R3): New define.
377 (INSN_ISA32R5): New define.
378 (INSN_ISA64R3): New define.
379 (INSN_ISA64R5): New define.
380 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
381 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
382 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
383 mips64r5.
384 (INSN_UPTO32R3): New define.
385 (INSN_UPTO32R5): New define.
386 (INSN_UPTO64R3): New define.
387 (INSN_UPTO64R5): New define.
388 (ISA_MIPS32R3): New define.
389 (ISA_MIPS32R5): New define.
390 (ISA_MIPS64R3): New define.
391 (ISA_MIPS64R5): New define.
392 (CPU_MIPS32R3): New define.
393 (CPU_MIPS32R5): New define.
394 (CPU_MIPS64R3): New define.
395 (CPU_MIPS64R5): New define.
396
3efe9ec5
RS		 3972014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
398
399 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
400
73589c9d
CS		 4012014-04-22 Christian Svensson <blue@cmd.nu>
402
403 * or32.h: Delete.
404
4b95cf5c
AM		 4052014-03-05 Alan Modra <amodra@gmail.com>
406
407 Update copyright years.
408
e269fea7
AB		 4092013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
410
411 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
412 microMIPS.
413
35c08157
KLC		 4142013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
415 Wei-Cheng Wang <cole945@gmail.com>
416
417 * nds32.h: New file for Andes NDS32.
418
594d8fa8
MF		 4192013-12-07 Mike Frysinger <vapier@gentoo.org>
420
421 * bfin.h: Remove +x file mode.
422
87b8eed7
YZ		 4232013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
424
425 * aarch64.h (aarch64_pstatefields): Change element type to
426 aarch64_sys_reg.
427
c9fb6e58
YZ		 4282013-11-18 Renlin Li <Renlin.Li@arm.com>
429
430 * arm.h (ARM_AEXT_V7VE): New define.
431 (ARM_ARCH_V7VE): New define.
432 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
433
a203d9b7
YZ		 4342013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
435
436 Revert
437
438 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
439
440 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
441 (aarch64_sys_reg_writeonly_p): Ditto.
442
75468c93
YZ		 4432013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
444
445 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
446 (aarch64_sys_reg_writeonly_p): Ditto.
447
49eec193
YZ		 4482013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
449
450 * aarch64.h (aarch64_sys_reg): New typedef.
451 (aarch64_sys_regs): Change to define with the new type.
452 (aarch64_sys_reg_deprecated_p): Declare.
453
68a64283
YZ		 4542013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
455
456 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
457 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
458
387a82f1
CF		 4592013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
460
461 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
462 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
463 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
464 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
465 For MIPS, update extension character sequences after +.
466 (ASE_MSA): New define.
467 (ASE_MSA64): New define.
468 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
469 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
470 For microMIPS, update extension character sequences after +.
471
9aff4b7a
NC		 4722013-08-23 Yuri Chornoivan <yurchor@ukr.net>
473
474 PR binutils/15834
475 * i960.h: Fix typos.
476
e423441d
RS		 4772013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
478
479 * mips.h: Remove references to "+I" and imm2_expr.
480
5e0dc5ba
RS		 4812013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
482
483 * mips.h (M_DEXT, M_DINS): Delete.
484
0f35dbc4
RS		 4852013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
486
487 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
488 (mips_optional_operand_p): New function.
489
14daeee3
RS		 4902013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
491 Richard Sandiford <rdsandiford@googlemail.com>
492
493 * mips.h: Document new VU0 operand characters.
494 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
495 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
496 (OP_REG_R5900_ACC): New mips_reg_operand_types.
497 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
498 (mips_vu0_channel_mask): Declare.
499
3ccad066
RS		 5002013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
501
502 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
503 (mips_int_operand_min, mips_int_operand_max): New functions.
504 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
505
fc76e730
RS		 5062013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
507
508 * mips.h (mips_decode_reg_operand): New function.
509 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
510 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
511 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
512 New macros.
513 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
514 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
515 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
516 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
517 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
518 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
519 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
520 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
521 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
522 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
523 macros to cover the gaps.
524 (INSN2_MOD_SP): Replace with...
525 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
526 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
527 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
528 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
529 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
530 Delete.
531
26545944
RS		 5322013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
533
534 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
535 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
536 (MIPS16_INSN_COND_BRANCH): Delete.
537
7e8b059b
L		 5382013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
539 Kirill Yukhin <kirill.yukhin@intel.com>
540 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
541
542 * i386.h (BND_PREFIX_OPCODE): New.
543
c3c07478
RS		 5442013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
545
546 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
547 OP_SAVE_RESTORE_LIST.
548 (decode_mips16_operand): Declare.
549
ab902481
RS		 5502013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
551
552 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
553 (mips_operand, mips_int_operand, mips_mapped_int_operand)
554 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
555 (mips_pcrel_operand): New structures.
556 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
557 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
558 (decode_mips_operand, decode_micromips_operand): Declare.
559
cc537e56
RS		 5602013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
561
562 * mips.h: Document MIPS16 "I" opcode.
563
f2ae14a1
RS		 5642013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
565
566 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
567 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
568 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
569 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
570 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
571 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
572 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
573 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
574 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
575 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
576 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
577 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
578 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
579 Rename to...
580 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
581 (M_USD_AB): ...these.
582
5c324c16
RS		 5832013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
584
585 * mips.h: Remove documentation of "[" and "]". Update documentation
586 of "k" and the MDMX formats.
587
23e69e47
RS		 5882013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
589
590 * mips.h: Update documentation of "+s" and "+S".
591
27c5c572
RS		 5922013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
593
594 * mips.h: Document "+i".
595
e76ff5ab
RS		 5962013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
597
598 * mips.h: Remove "mi" documentation. Update "mh" documentation.
599 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
600 Delete.
601 (INSN2_WRITE_GPR_MHI): Rename to...
602 (INSN2_WRITE_GPR_MH): ...this.
603
fa7616a4
RS		 6042013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
605
606 * mips.h: Remove documentation of "+D" and "+T".
607
18870af7
RS		 6082013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
609
610 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
611 Use "source" rather than "destination" for microMIPS "G".
612
833794fc
MR		 6132013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
614
615 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
616 values.
617
c3678916
RS		 6182013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
619
620 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
621
7f3c4072
CM		 6222013-06-17 Catherine Moore <clm@codesourcery.com>
623 Maciej W. Rozycki <macro@codesourcery.com>
624 Chao-Ying Fu <fu@mips.com>
625
626 * mips.h (OP_SH_EVAOFFSET): Define.
627 (OP_MASK_EVAOFFSET): Define.
628 (INSN_ASE_MASK): Delete.
629 (ASE_EVA): Define.
630 (M_CACHEE_AB, M_CACHEE_OB): New.
631 (M_LBE_OB, M_LBE_AB): New.
632 (M_LBUE_OB, M_LBUE_AB): New.
633 (M_LHE_OB, M_LHE_AB): New.
634 (M_LHUE_OB, M_LHUE_AB): New.
635 (M_LLE_AB, M_LLE_OB): New.
636 (M_LWE_OB, M_LWE_AB): New.
637 (M_LWLE_AB, M_LWLE_OB): New.
638 (M_LWRE_AB, M_LWRE_OB): New.
639 (M_PREFE_AB, M_PREFE_OB): New.
640 (M_SCE_AB, M_SCE_OB): New.
641 (M_SBE_OB, M_SBE_AB): New.
642 (M_SHE_OB, M_SHE_AB): New.
643 (M_SWE_OB, M_SWE_AB): New.
644 (M_SWLE_AB, M_SWLE_OB): New.
645 (M_SWRE_AB, M_SWRE_OB): New.
646 (MICROMIPSOP_SH_EVAOFFSET): Define.
647 (MICROMIPSOP_MASK_EVAOFFSET): Define.
648
0c8fe7cf
SL		 6492013-06-12 Sandra Loosemore <sandra@codesourcery.com>
650
651 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
652
c77c0862
RS		 6532013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
654
655 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
656
b015e599
AP		 6572013-05-09 Andrew Pinski <apinski@cavium.com>
658
659 * mips.h (OP_MASK_CODE10): Correct definition.
660 (OP_SH_CODE10): Likewise.
661 Add a comment that "+J" is used now for OP_*CODE10.
662 (INSN_ASE_MASK): Update.
663 (INSN_VIRT): New macro.
664 (INSN_VIRT64): New macro
665
13761a11
NC		 6662013-05-02 Nick Clifton <nickc@redhat.com>
667
668 * msp430.h: Add patterns for MSP430X instructions.
669
0afd1215
DM		 6702013-04-06 David S. Miller <davem@davemloft.net>
671
672 * sparc.h (F_PREFERRED): Define.
673 (F_PREF_ALIAS): Define.
674
41702d50
NC		 6752013-04-03 Nick Clifton <nickc@redhat.com>
676
677 * v850.h (V850_INVERSE_PCREL): Define.
678
e21e1a51
NC		 6792013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
680
681 PR binutils/15068
682 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
683
51dcdd4d
NC		 6842013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
685
686 PR binutils/15068
687 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
688 Add 16-bit opcodes.
689 * tic6xc-opcode-table.h: Add 16-bit insns.
690 * tic6x.h: Add support for 16-bit insns.
691
81f5558e
NC		 6922013-03-21 Michael Schewe <michael.schewe@gmx.net>
693
694 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
695 and mov.b/w/l Rs,@(d:32,ERd).
696
165546ad
NC		 6972013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
698
699 PR gas/15082
700 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
701 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
702 tic6x_operand_xregpair operand coding type.
703 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
704 opcode field, usu ORXREGD1324 for the src2 operand and remove the
705 TIC6X_FLAG_NO_CROSS.
706
795b8e6b
NC		 7072013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
708
709 PR gas/15095
710 * tic6x.h (enum tic6x_coding_method): Add
711 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
712 separately the msb and lsb of a register pair. This is needed to
713 encode the opcodes in the same way as TI assembler does.
714 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
715 and rsqrdp opcodes to use the new field coding types.
716
dd5181d5
KT		 7172013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
718
719 * arm.h (CRC_EXT_ARMV8): New constant.
720 (ARCH_CRC_ARMV8): New macro.
721
e60bb1dd
YZ		 7222013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
723
724 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
725
36591ba1 7262013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 727 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 728
729 Based on patches from Altera Corporation.
730
731 * nios2.h: New file.
732
e30181a5
YZ		 7332013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
734
735 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
736
0c9573f4
NC		 7372013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
738
739 PR gas/15069
740 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
741
981dc7f1
NC		 7422013-01-24 Nick Clifton <nickc@redhat.com>
743
744 * v850.h: Add e3v5 support.
745
f5555712
YZ		 7462013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
747
748 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
749
5817ffd1
PB		 7502013-01-10 Peter Bergner <bergner@vnet.ibm.com>
751
752 * ppc.h (PPC_OPCODE_POWER8): New define.
753 (PPC_OPCODE_HTM): Likewise.
754
a3c62988
NC		 7552013-01-10 Will Newton <will.newton@imgtec.com>
756
757 * metag.h: New file.
758
73335eae
NC		 7592013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
760
761 * cr16.h (make_instruction): Rename to cr16_make_instruction.
762 (match_opcode): Rename to cr16_match_opcode.
763
e407c74b
NC		 7642013-01-04 Juergen Urban <JuergenUrban@gmx.de>
765
766 * mips.h: Add support for r5900 instructions including lq and sq.
767
bab4becb
NC		 7682013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
769
770 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
771 (make_instruction,match_opcode): Added function prototypes.
772 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
773
776fc418
AM		 7742012-11-23 Alan Modra <amodra@gmail.com>
775
776 * ppc.h (ppc_parse_cpu): Update prototype.
777
f05682d4
DA		 7782012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
779
780 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
781 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
782
cfc72779
AK		 7832012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
784
785 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
786
b3e14eda
L		 7872012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
788
789 * ia64.h (ia64_opnd): Add new operand types.
790
2c63854f
DM		 7912012-08-21 David S. Miller <davem@davemloft.net>
792
793 * sparc.h (F3F4): New macro.
794
a06ea964 7952012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 796 Laurent Desnogues <laurent.desnogues@arm.com>
797 Jim MacArthur <jim.macarthur@arm.com>
798 Marcus Shawcroft <marcus.shawcroft@arm.com>
799 Nigel Stephens <nigel.stephens@arm.com>
800 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
801 Richard Earnshaw <rearnsha@arm.com>
802 Sofiane Naci <sofiane.naci@arm.com>
803 Tejas Belagod <tejas.belagod@arm.com>
804 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 805
806 * aarch64.h: New file.
807
35d0a169 8082012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 809 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 810
811 * mips.h (mips_opcode): Add the exclusions field.
812 (OPCODE_IS_MEMBER): Remove macro.
813 (cpu_is_member): New inline function.
814 (opcode_is_member): Likewise.
815
03f66e8a 8162012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 817 Catherine Moore <clm@codesourcery.com>
818 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 819
820 * mips.h: Document microMIPS DSP ASE usage.
821 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
822 microMIPS DSP ASE support.
823 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
824 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
825 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
826 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
827 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
828 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
829 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
830
9d7b4c23
MR		 8312012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
832
833 * mips.h: Fix a typo in description.
834
76e879f8
NC		 8352012-06-07 Georg-Johann Lay <avr@gjlay.de>
836
837 * avr.h: (AVR_ISA_XCH): New define.
838 (AVR_ISA_XMEGA): Use it.
839 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
840
6927f982
NC		 8412012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
842
843 * m68hc11.h: Add XGate definitions.
844 (struct m68hc11_opcode): Add xg_mask field.
845
b9c361e0
JL		 8462012-05-14 Catherine Moore <clm@codesourcery.com>
847 Maciej W. Rozycki <macro@codesourcery.com>
848 Rhonda Wittels <rhonda@codesourcery.com>
849
6927f982 850 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 851 (PPC_OP_SA): New macro.
852 (PPC_OP_SE_VLE): New macro.
853 (PPC_OP): Use a variable shift amount.
854 (powerpc_operand): Update comments.
855 (PPC_OPSHIFT_INV): New macro.
856 (PPC_OPERAND_CR): Replace with...
857 (PPC_OPERAND_CR_BIT): ...this and
858 (PPC_OPERAND_CR_REG): ...this.
859
860
f6c1a2d5
NC		 8612012-05-03 Sean Keys <skeys@ipdatasys.com>
862
863 * xgate.h: Header file for XGATE assembler.
864
ec668d69
DM		 8652012-04-27 David S. Miller <davem@davemloft.net>
866
6cda1326
DM		 867 * sparc.h: Document new arg code' )' for crypto RS3
868 immediates.
869
ec668d69
DM		 870 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
871 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
872 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
873 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
874 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
875 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
876 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
877 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
878 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
879 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
880 HWCAP_CBCOND, HWCAP_CRC32): New defines.
881
aea77599
AM		 8822012-03-10 Edmar Wienskoski <edmar@freescale.com>
883
884 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
885
1f42f8b3
AM		 8862012-02-27 Alan Modra <amodra@gmail.com>
887
888 * crx.h (cst4_map): Update declaration.
889
6f7be959
WL		 8902012-02-25 Walter Lee <walt@tilera.com>
891
892 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
893 TILEGX_OPC_LD_TLS.
894 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
895 TILEPRO_OPC_LW_TLS_SN.
896
42164a71
L		 8972012-02-08 H.J. Lu <hongjiu.lu@intel.com>
898
899 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
900 (XRELEASE_PREFIX_OPCODE): Likewise.
901
432233b3 9022011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 903 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 904
905 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
906 (INSN_OCTEON2): New macro.
907 (CPU_OCTEON2): New macro.
908 (OPCODE_IS_MEMBER): Add Octeon2.
909
dd6a37e7
AP		 9102011-11-29 Andrew Pinski <apinski@cavium.com>
911
912 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
913 (INSN_OCTEONP): New macro.
914 (CPU_OCTEONP): New macro.
915 (OPCODE_IS_MEMBER): Add Octeon+.
916 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
917
99c513f6
DD		 9182011-11-01 DJ Delorie <dj@redhat.com>
919
920 * rl78.h: New file.
921
26f85d7a
MR		 9222011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
923
924 * mips.h: Fix a typo in description.
925
9e8c70f9
DM		 9262011-09-21 David S. Miller <davem@davemloft.net>
927
928 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
929 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
930 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
931 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
932
dec0624d 9332011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 934 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 935
936 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
937 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
938 (INSN_ASE_MASK): Add the MCU bit.
939 (INSN_MCU): New macro.
940 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
941 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
942
2b0c8b40
MR		 9432011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
944
945 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
946 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
947 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
948 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
949 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
950 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
951 (INSN2_READ_GPR_MMN): Likewise.
952 (INSN2_READ_FPR_D): Change the bit used.
953 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
954 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
955 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
956 (INSN2_COND_BRANCH): Likewise.
957 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
958 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
959 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
960 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
961 (INSN2_MOD_GPR_MN): Likewise.
962
ea783ef3
DM		 9632011-08-05 David S. Miller <davem@davemloft.net>
964
965 * sparc.h: Document new format codes '4', '5', and '('.
966 (OPF_LOW4, RS3): New macros.
967
7c176fa8
MR		 9682011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
969
970 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
971 order of flags documented.
972
2309ddf2
MR		 9732011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
974
975 * mips.h: Clarify the description of microMIPS instruction
976 manipulation macros.
977 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
978
df58fc94 9792011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 980 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 981
982 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
983 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
984 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
985 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
986 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
987 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
988 (OP_MASK_RS3, OP_SH_RS3): Likewise.
989 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
990 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
991 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
992 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
993 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
994 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
995 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
996 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
997 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
998 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
999 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
1000 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
1001 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
1002 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
1003 (INSN_WRITE_GPR_S): New macro.
1004 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
1005 (INSN2_READ_FPR_D): Likewise.
1006 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
1007 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
1008 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
1009 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
1010 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
1011 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
1012 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
1013 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
1014 (CPU_MICROMIPS): New macro.
1015 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
1016 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1017 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1018 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1019 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1020 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1021 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1022 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1023 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1024 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1025 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1026 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1027 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1028 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1029 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1030 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1031 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1032 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1033 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1034 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1035 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1036 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1037 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1038 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1039 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1040 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1041 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1042 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1043 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1044 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1045 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1046 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1047 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1048 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1049 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1050 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1051 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1052 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1053 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1054 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1055 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1056 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1057 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1058 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1059 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1060 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1061 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1062 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1063 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1064 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1065 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1066 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1067 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1068 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1069 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1070 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1071 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1072 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1073 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1074 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1075 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1076 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1077 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1078 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1079 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1080 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1081 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1082 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1083 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1084 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1085 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1086 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1087 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1088 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1089 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1090 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1091 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1092 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1093 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1094 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1095 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1096 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1097 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1098 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1099 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1100 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1101 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1102 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1103 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1104 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1105 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1106 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1107 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1108 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1109 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1110 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1111 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1112 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1113 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1114 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1115 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1116 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1117 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1118 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1119 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1120 (micromips_opcodes): New declaration.
1121 (bfd_micromips_num_opcodes): Likewise.
1122
bcd530a7
RS		 11232011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1124
1125 * mips.h (INSN_TRAP): Rename to...
1126 (INSN_NO_DELAY_SLOT): ... this.
1127 (INSN_SYNC): Remove macro.
1128
2dad5a91
EW		 11292011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1130
1131 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1132 a duplicate of AVR_ISA_SPM.
1133
5d73b1f1
NC		 11342011-07-01 Nick Clifton <nickc@redhat.com>
1135
1136 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1137
ef26d60e
MF		 11382011-06-18 Robin Getz <robin.getz@analog.com>
1139
1140 * bfin.h (is_macmod_signed): New func
1141
8fb8dca7
MF		 11422011-06-18 Mike Frysinger <vapier@gentoo.org>
1143
1144 * bfin.h (is_macmod_pmove): Add missing space before func args.
1145 (is_macmod_hmove): Likewise.
1146
aa137e4d
NC		 11472011-06-13 Walter Lee <walt@tilera.com>
1148
1149 * tilegx.h: New file.
1150 * tilepro.h: New file.
1151
3b2f0793
PB		 11522011-05-31 Paul Brook <paul@codesourcery.com>
1153
aa137e4d
NC		 1154 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1155
11562011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1157
1158 * s390.h: Replace S390_OPERAND_REG_EVEN with
1159 S390_OPERAND_REG_PAIR.
1160
11612011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1162
1163 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1164
ac7f631b
NC		 11652011-04-18 Julian Brown <julian@codesourcery.com>
1166
1167 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1168
84701018
NC		 11692011-04-11 Dan McDonald <dan@wellkeeper.com>
1170
1171 PR gas/12296
1172 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1173
8cc66334
EW		 11742011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1175
1176 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1177 New instruction set flags.
1178 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1179
3eebd5eb
MR		 11802011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1181
1182 * mips.h (M_PREF_AB): New enum value.
1183
26bb3ddd
MF		 11842011-02-12 Mike Frysinger <vapier@gentoo.org>
1185
89c0d58c
MR		 1186 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1187 M_IU): Define.
1188 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1189
dd76fcb8
MF		 11902011-02-11 Mike Frysinger <vapier@gentoo.org>
1191
1192 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1193
98d23bef
BS		 11942011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1195
1196 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1197 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1198
3c853d93
DA		 11992010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1200
1201 PR gas/11395
1202 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1203 "bb" entries.
1204
79676006
DA		 12052010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1206
1207 PR gas/11395
1208 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1209
1bec78e9
RS		 12102010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1211
1212 * mips.h: Update commentary after last commit.
1213
98675402
RS		 12142010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1215
1216 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1217 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1218 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1219
aa137e4d
NC		 12202010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1221
1222 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1223
435b94a4
RS		 12242010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1225
1226 * mips.h: Fix previous commit.
1227
d051516a
NC		 12282010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1229
1230 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1231 (INSN_LOONGSON_3A): Clear bit 31.
1232
251665fc
MGD		 12332010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1234
1235 PR gas/12198
1236 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1237 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1238 (ARM_ARCH_V6M_ONLY): New define.
1239
fd503541
NC		 12402010-11-11 Mingming Sun <mingm.sun@gmail.com>
1241
1242 * mips.h (INSN_LOONGSON_3A): Defined.
1243 (CPU_LOONGSON_3A): Defined.
1244 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1245
4469d2be
AM		 12462010-10-09 Matt Rice <ratmice@gmail.com>
1247
1248 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1249 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1250
90ec0d68
MGD		 12512010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1252
1253 * arm.h (ARM_EXT_VIRT): New define.
1254 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1255 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1256 Extensions.
1257
eea54501 12582010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1259
eea54501
MGD		 1260 * arm.h (ARM_AEXT_ADIV): New define.
1261 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1262
b2a5fbdc
MGD		 12632010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1264
1265 * arm.h (ARM_EXT_OS): New define.
1266 (ARM_AEXT_V6SM): Likewise.
1267 (ARM_ARCH_V6SM): Likewise.
1268
60e5ef9f
MGD		 12692010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1270
1271 * arm.h (ARM_EXT_MP): Add.
1272 (ARM_ARCH_V7A_MP): Likewise.
1273
73a63ccf
MF		 12742010-09-22 Mike Frysinger <vapier@gentoo.org>
1275
1276 * bfin.h: Declare pseudoChr structs/defines.
1277
ee99860a
MF		 12782010-09-21 Mike Frysinger <vapier@gentoo.org>
1279
1280 * bfin.h: Strip trailing whitespace.
1281
f9c7014e
DD		 12822010-07-29 DJ Delorie <dj@redhat.com>
1283
1284 * rx.h (RX_Operand_Type): Add TwoReg.
1285 (RX_Opcode_ID): Remove ediv and ediv2.
1286
93378652
DD		 12872010-07-27 DJ Delorie <dj@redhat.com>
1288
1289 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1290
1cd986c5
NC		 12912010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1292 Ina Pandit <ina.pandit@kpitcummins.com>
1293
1294 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1295 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1296 PROCESSOR_V850E2_ALL.
1297 Remove PROCESSOR_V850EA support.
1298 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1299 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1300 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1301 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1302 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1303 V850_OPERAND_PERCENT.
1304 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1305 V850_NOT_R0.
1306 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1307 and V850E_PUSH_POP
1308
9a2c7088
MR		 13092010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1310
1311 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1312 (MIPS16_INSN_BRANCH): Rename to...
1313 (MIPS16_INSN_COND_BRANCH): ... this.
1314
bdc70b4a
AM		 13152010-07-03 Alan Modra <amodra@gmail.com>
1316
1317 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1318 Renumber other PPC_OPCODE defines.
1319
f2bae120
AM		 13202010-07-03 Alan Modra <amodra@gmail.com>
1321
1322 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1323
360cfc9c
AM		 13242010-06-29 Alan Modra <amodra@gmail.com>
1325
1326 * maxq.h: Delete file.
1327
e01d869a
AM		 13282010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1329
1330 * ppc.h (PPC_OPCODE_E500): Define.
1331
f79e2745
CM		 13322010-05-26 Catherine Moore <clm@codesourcery.com>
1333
1334 * opcode/mips.h (INSN_MIPS16): Remove.
1335
2462afa1
JM		 13362010-04-21 Joseph Myers <joseph@codesourcery.com>
1337
1338 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1339
e4e42b45
NC		 13402010-04-15 Nick Clifton <nickc@redhat.com>
1341
1342 * alpha.h: Update copyright notice to use GPLv3.
1343 * arc.h: Likewise.
1344 * arm.h: Likewise.
1345 * avr.h: Likewise.
1346 * bfin.h: Likewise.
1347 * cgen.h: Likewise.
1348 * convex.h: Likewise.
1349 * cr16.h: Likewise.
1350 * cris.h: Likewise.
1351 * crx.h: Likewise.
1352 * d10v.h: Likewise.
1353 * d30v.h: Likewise.
1354 * dlx.h: Likewise.
1355 * h8300.h: Likewise.
1356 * hppa.h: Likewise.
1357 * i370.h: Likewise.
1358 * i386.h: Likewise.
1359 * i860.h: Likewise.
1360 * i960.h: Likewise.
1361 * ia64.h: Likewise.
1362 * m68hc11.h: Likewise.
1363 * m68k.h: Likewise.
1364 * m88k.h: Likewise.
1365 * maxq.h: Likewise.
1366 * mips.h: Likewise.
1367 * mmix.h: Likewise.
1368 * mn10200.h: Likewise.
1369 * mn10300.h: Likewise.
1370 * msp430.h: Likewise.
1371 * np1.h: Likewise.
1372 * ns32k.h: Likewise.
1373 * or32.h: Likewise.
1374 * pdp11.h: Likewise.
1375 * pj.h: Likewise.
1376 * pn.h: Likewise.
1377 * ppc.h: Likewise.
1378 * pyr.h: Likewise.
1379 * rx.h: Likewise.
1380 * s390.h: Likewise.
1381 * score-datadep.h: Likewise.
1382 * score-inst.h: Likewise.
1383 * sparc.h: Likewise.
1384 * spu-insns.h: Likewise.
1385 * spu.h: Likewise.
1386 * tic30.h: Likewise.
1387 * tic4x.h: Likewise.
1388 * tic54x.h: Likewise.
1389 * tic80.h: Likewise.
1390 * v850.h: Likewise.
1391 * vax.h: Likewise.
1392
40b36596
JM		 13932010-03-25 Joseph Myers <joseph@codesourcery.com>
1394
1395 * tic6x-control-registers.h, tic6x-insn-formats.h,
1396 tic6x-opcode-table.h, tic6x.h: New.
1397
c67a084a
NC		 13982010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1399
1400 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1401
466ef64f
AM		 14022010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1403
1404 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1405
1319d143
L		 14062010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1407
1408 * ia64.h (ia64_find_opcode): Remove argument name.
1409 (ia64_find_next_opcode): Likewise.
1410 (ia64_dis_opcode): Likewise.
1411 (ia64_free_opcode): Likewise.
1412 (ia64_find_dependency): Likewise.
1413
1fbb9298
DE		 14142009-11-22 Doug Evans <dje@sebabeach.org>
1415
1416 * cgen.h: Include bfd_stdint.h.
1417 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1418
ada65aa3
PB		 14192009-11-18 Paul Brook <paul@codesourcery.com>
1420
1421 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1422
9e3c6df6
PB		 14232009-11-17 Paul Brook <paul@codesourcery.com>
1424 Daniel Jacobowitz <dan@codesourcery.com>
1425
1426 * arm.h (ARM_EXT_V6_DSP): Define.
1427 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1428 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1429
0d734b5d
DD		 14302009-11-04 DJ Delorie <dj@redhat.com>
1431
1432 * rx.h (rx_decode_opcode) (mvtipl): Add.
1433 (mvtcp, mvfcp, opecp): Remove.
1434
62f3b8c8
PB		 14352009-11-02 Paul Brook <paul@codesourcery.com>
1436
1437 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1438 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1439 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1440 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1441 FPU_ARCH_NEON_VFP_V4): Define.
1442
ac1e9eca
DE		 14432009-10-23 Doug Evans <dje@sebabeach.org>
1444
1445 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1446 * cgen.h: Update. Improve multi-inclusion macro name.
1447
9fe54b1c
PB		 14482009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1449
1450 * ppc.h (PPC_OPCODE_476): Define.
1451
634b50f2
PB		 14522009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1453
1454 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1455
c7927a3c
NC		 14562009-09-29 DJ Delorie <dj@redhat.com>
1457
1458 * rx.h: New file.
1459
b961e85b
AM		 14602009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1461
1462 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1463
e0d602ec
BE		 14642009-09-21 Ben Elliston <bje@au.ibm.com>
1465
1466 * ppc.h (PPC_OPCODE_PPCA2): New.
1467
96d56e9f
NC		 14682009-09-05 Martin Thuresson <martin@mtme.org>
1469
1470 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1471
d3ce72d0
NC		 14722009-08-29 Martin Thuresson <martin@mtme.org>
1473
1474 * tic30.h (template): Rename type template to
1475 insn_template. Updated code to use new name.
1476 * tic54x.h (template): Rename type template to
1477 insn_template.
1478
824b28db
NH		 14792009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1480
1481 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1482
f865a31d
AG		 14832009-06-11 Anthony Green <green@moxielogic.com>
1484
1485 * moxie.h (MOXIE_F3_PCREL): Define.
1486 (moxie_form3_opc_info): Grow.
1487
0e7c7f11
AG		 14882009-06-06 Anthony Green <green@moxielogic.com>
1489
1490 * moxie.h (MOXIE_F1_M): Define.
1491
20135e4c
NC		 14922009-04-15 Anthony Green <green@moxielogic.com>
1493
1494 * moxie.h: Created.
1495
bcb012d3
DD		 14962009-04-06 DJ Delorie <dj@redhat.com>
1497
1498 * h8300.h: Add relaxation attributes to MOVA opcodes.
1499
69fe9ce5
AM		 15002009-03-10 Alan Modra <amodra@bigpond.net.au>
1501
1502 * ppc.h (ppc_parse_cpu): Declare.
1503
c3b7224a
NC		 15042009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1505
1506 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1507 and _IMM11 for mbitclr and mbitset.
1508 * score-datadep.h: Update dependency information.
1509
066be9f7
PB		 15102009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1511
1512 * ppc.h (PPC_OPCODE_POWER7): New.
1513
fedc618e
DE		 15142009-02-06 Doug Evans <dje@google.com>
1515
1516 * i386.h: Add comment regarding sse* insns and prefixes.
1517
52b6b6b9
JM		 15182009-02-03 Sandip Matte <sandip@rmicorp.com>
1519
1520 * mips.h (INSN_XLR): Define.
1521 (INSN_CHIP_MASK): Update.
1522 (CPU_XLR): Define.
1523 (OPCODE_IS_MEMBER): Update.
1524 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1525
35669430
DE		 15262009-01-28 Doug Evans <dje@google.com>
1527
1528 * opcode/i386.h: Add multiple inclusion protection.
1529 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1530 (EDI_REG_NUM): New macros.
1531 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1532 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1533 (REX_PREFIX_P): New macro.
35669430 1534
1cb0a767
PB		 15352009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1536
1537 * ppc.h (struct powerpc_opcode): New field "deprecated".
1538 (PPC_OPCODE_NOPOWER4): Delete.
1539
3aa3176b
TS		 15402008-11-28 Joshua Kinard <kumba@gentoo.org>
1541
1542 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1543 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1544
8e79c3df
CM		 15452008-11-18 Catherine Moore <clm@codesourcery.com>
1546
1547 * arm.h (FPU_NEON_FP16): New.
1548 (FPU_ARCH_NEON_FP16): New.
1549
de9a3e51
CF		 15502008-11-06 Chao-ying Fu <fu@mips.com>
1551
1552 * mips.h: Doucument '1' for 5-bit sync type.
1553
1ca35711
L		 15542008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1555
1556 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1557 IA64_RS_CR.
1558
9b4e5766
PB		 15592008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1560
1561 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1562
081ba1b3
AM		 15632008-07-30 Michael J. Eager <eager@eagercon.com>
1564
1565 * ppc.h (PPC_OPCODE_405): Define.
1566 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1567
fa452fa6
PB		 15682008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1569
1570 * ppc.h (ppc_cpu_t): New typedef.
1571 (struct powerpc_opcode <flags>): Use it.
1572 (struct powerpc_operand <insert, extract>): Likewise.
1573 (struct powerpc_macro <flags>): Likewise.
1574
bb35fb24
NC		 15752008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1576
1577 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1578 Update comment before MIPS16 field descriptors to mention MIPS16.
1579 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1580 BBIT.
1581 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1582 New bit masks and shift counts for cins and exts.
1583
dd3cbb7e
NC		 1584 * mips.h: Document new field descriptors +Q.
1585 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1586
d0799671
AN		 15872008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1588
9aff4b7a 1589 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1590 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1591
19a6653c
AM		 15922008-04-14 Edmar Wienskoski <edmar@freescale.com>
1593
1594 * ppc.h: (PPC_OPCODE_E500MC): New.
1595
c0f3af97
L		 15962008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1597
1598 * i386.h (MAX_OPERANDS): Set to 5.
1599 (MAX_MNEM_SIZE): Changed to 20.
1600
e210c36b
NC		 16012008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1602
1603 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1604
b1cc4aeb
PB		 16052008-03-09 Paul Brook <paul@codesourcery.com>
1606
1607 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1608
7e806470
PB		 16092008-03-04 Paul Brook <paul@codesourcery.com>
1610
1611 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1612 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1613 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1614
7b2185f9 16152008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1616 Nick Clifton <nickc@redhat.com>
1617
1618 PR 3134
1619 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1620 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1621 set.
af7329f0 1622
796d5313
NC		 16232008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1624
1625 * cr16.h (cr16_num_optab): Declared.
1626
d669d37f
NC		 16272008-02-14 Hakan Ardo <hakan@debian.org>
1628
1629 PR gas/2626
1630 * avr.h (AVR_ISA_2xxe): Define.
1631
e6429699
AN		 16322008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1633
1634 * mips.h: Update copyright.
1635 (INSN_CHIP_MASK): New macro.
1636 (INSN_OCTEON): New macro.
1637 (CPU_OCTEON): New macro.
1638 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1639
e210c36b
NC		 16402008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1641
1642 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1643
16442008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1645
1646 * avr.h (AVR_ISA_USB162): Add new opcode set.
1647 (AVR_ISA_AVR3): Likewise.
1648
350cc38d
MS		 16492007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1650
1651 * mips.h (INSN_LOONGSON_2E): New.
1652 (INSN_LOONGSON_2F): New.
1653 (CPU_LOONGSON_2E): New.
1654 (CPU_LOONGSON_2F): New.
1655 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1656
56950294
MS		 16572007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1658
1659 * mips.h (INSN_ISA*): Redefine certain values as an
1660 enumeration. Update comments.
1661 (mips_isa_table): New.
1662 (ISA_MIPS*): Redefine to match enumeration.
1663 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1664 values.
1665
c3d65c1c
BE		 16662007-08-08 Ben Elliston <bje@au.ibm.com>
1667
1668 * ppc.h (PPC_OPCODE_PPCPS): New.
1669
0fdaa005
L		 16702007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1671
1672 * m68k.h: Document j K & E.
1673
16742007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1675
1676 * cr16.h: New file for CR16 target.
1677
3896c469
AM		 16782007-05-02 Alan Modra <amodra@bigpond.net.au>
1679
1680 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1681
9a2e615a
NS		 16822007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1683
1684 * m68k.h (mcfisa_c): New.
1685 (mcfusp, mcf_mask): Adjust.
1686
b84bf58a
AM		 16872007-04-20 Alan Modra <amodra@bigpond.net.au>
1688
1689 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1690 (num_powerpc_operands): Declare.
1691 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1692 (PPC_OPERAND_PLUS1): Define.
1693
831480e9 16942007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1695
1696 * i386.h (REX_MODE64): Renamed to ...
1697 (REX_W): This.
1698 (REX_EXTX): Renamed to ...
1699 (REX_R): This.
1700 (REX_EXTY): Renamed to ...
1701 (REX_X): This.
1702 (REX_EXTZ): Renamed to ...
1703 (REX_B): This.
1704
0b1cf022
L		 17052007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1706
1707 * i386.h: Add entries from config/tc-i386.h and move tables
1708 to opcodes/i386-opc.h.
1709
d796c0ad
L		 17102007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1711
1712 * i386.h (FloatDR): Removed.
1713 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1714
30ac7323
AM		 17152007-03-01 Alan Modra <amodra@bigpond.net.au>
1716
1717 * spu-insns.h: Add soma double-float insns.
1718
8b082fb1 17192007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1720 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1721
1722 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1723 (INSN_DSPR2): Add flag for DSP R2 instructions.
1724 (M_BALIGN): New macro.
1725
4eed87de
AM		 17262007-02-14 Alan Modra <amodra@bigpond.net.au>
1727
1728 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1729 and Seg3ShortFrom with Shortform.
1730
fda592e8
L		 17312007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1732
1733 PR gas/4027
1734 * i386.h (i386_optab): Put the real "test" before the pseudo
1735 one.
1736
3bdcfdf4
KH		 17372007-01-08 Kazu Hirata <kazu@codesourcery.com>
1738
1739 * m68k.h (m68010up): OR fido_a.
1740
9840d27e
KH		 17412006-12-25 Kazu Hirata <kazu@codesourcery.com>
1742
1743 * m68k.h (fido_a): New.
1744
c629cdac
KH		 17452006-12-24 Kazu Hirata <kazu@codesourcery.com>
1746
1747 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1748 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1749 values.
1750
b7d9ef37
L		 17512006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1752
1753 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1754
b138abaa
NC		 17552006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1756
1757 * score-inst.h (enum score_insn_type): Add Insn_internal.
1758
e9f53129
AM		 17592006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1760 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1761 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1762 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1763 Alan Modra <amodra@bigpond.net.au>
1764
1765 * spu-insns.h: New file.
1766 * spu.h: New file.
1767
ede602d7
AM		 17682006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1769
1770 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1771
7918206c
MM		 17722006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1773
e4e42b45 1774 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1775 in amdfam10 architecture.
1776
ef05d495
L		 17772006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1778
1779 * i386.h: Replace CpuMNI with CpuSSSE3.
1780
2d447fca 17812006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1782 Joseph Myers <joseph@codesourcery.com>
1783 Ian Lance Taylor <ian@wasabisystems.com>
1784 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1785
1786 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1787
1c0d3aa6
NC		 17882006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1789
1790 * score-datadep.h: New file.
1791 * score-inst.h: New file.
1792
c2f0420e
L		 17932006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1794
1795 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1796 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1797 movdq2q and movq2dq.
1798
050dfa73
MM		 17992006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1800 Michael Meissner <michael.meissner@amd.com>
1801
1802 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1803
15965411
L		 18042006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1805
1806 * i386.h (i386_optab): Add "nop" with memory reference.
1807
46e883c5
L		 18082006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1809
1810 * i386.h (i386_optab): Update comment for 64bit NOP.
1811
9622b051
AM		 18122006-06-06 Ben Elliston <bje@au.ibm.com>
1813 Anton Blanchard <anton@samba.org>
1814
1815 * ppc.h (PPC_OPCODE_POWER6): Define.
1816 Adjust whitespace.
1817
a9e24354
TS		 18182006-06-05 Thiemo Seufer <ths@mips.com>
1819
e4e42b45 1820 * mips.h: Improve description of MT flags.
a9e24354 1821
a596001e
RS		 18222006-05-25 Richard Sandiford <richard@codesourcery.com>
1823
1824 * m68k.h (mcf_mask): Define.
1825
d43b4baf 18262006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1827 David Ung <davidu@mips.com>
d43b4baf
TS		 1828
1829 * mips.h (enum): Add macro M_CACHE_AB.
1830
39a7806d 18312006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1832 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1833 David Ung <davidu@mips.com>
1834
1835 * mips.h: Add INSN_SMARTMIPS define.
1836
9bcd4f99 18372006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1838 David Ung <davidu@mips.com>
9bcd4f99
TS		 1839
1840 * mips.h: Defines udi bits and masks. Add description of
1841 characters which may appear in the args field of udi
1842 instructions.
1843
ef0ee844
TS		 18442006-04-26 Thiemo Seufer <ths@networkno.de>
1845
1846 * mips.h: Improve comments describing the bitfield instruction
1847 fields.
1848
f7675147
L		 18492006-04-26 Julian Brown <julian@codesourcery.com>
1850
1851 * arm.h (FPU_VFP_EXT_V3): Define constant.
1852 (FPU_NEON_EXT_V1): Likewise.
1853 (FPU_VFP_HARD): Update.
1854 (FPU_VFP_V3): Define macro.
1855 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1856
ef0ee844 18572006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1858
1859 * avr.h (AVR_ISA_PWMx): New.
1860
2da12c60
NS		 18612006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1862
1863 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1864 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1865 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1866 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1867 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1868
0715c387
PB		 18692006-03-10 Paul Brook <paul@codesourcery.com>
1870
1871 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1872
34bdd094
DA		 18732006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1874
1875 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1876 first. Correct mask of bb "B" opcode.
1877
331d2d0d
L		 18782006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1879
1880 * i386.h (i386_optab): Support Intel Merom New Instructions.
1881
62b3e311
PB		 18822006-02-24 Paul Brook <paul@codesourcery.com>
1883
1884 * arm.h: Add V7 feature bits.
1885
59cf82fe
L		 18862006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1887
1888 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1889
e74cfd16
PB		 18902006-01-31 Paul Brook <paul@codesourcery.com>
1891 Richard Earnshaw <rearnsha@arm.com>
1892
1893 * arm.h: Use ARM_CPU_FEATURE.
1894 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1895 (arm_feature_set): Change to a structure.
1896 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1897 ARM_FEATURE): New macros.
1898
5b3f8a92
HPN		 18992005-12-07 Hans-Peter Nilsson <hp@axis.com>
1900
1901 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1902 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1903 (ADD_PC_INCR_OPCODE): Don't define.
1904
cb712a9e
L		 19052005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1906
1907 PR gas/1874
1908 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1909
0499d65b
TS		 19102005-11-14 David Ung <davidu@mips.com>
1911
1912 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1913 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1914 save/restore encoding of the args field.
1915
ea5ca089
DB		 19162005-10-28 Dave Brolley <brolley@redhat.com>
1917
1918 Contribute the following changes:
1919 2005-02-16 Dave Brolley <brolley@redhat.com>
1920
1921 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1922 cgen_isa_mask_* to cgen_bitset_*.
1923 * cgen.h: Likewise.
1924
16175d96
DB		 1925 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1926
1927 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1928 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1929 (CGEN_CPU_TABLE): Make isas a ponter.
1930
1931 2003-09-29 Dave Brolley <brolley@redhat.com>
1932
1933 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1934 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1935 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1936
1937 2002-12-13 Dave Brolley <brolley@redhat.com>
1938
1939 * cgen.h (symcat.h): #include it.
1940 (cgen-bitset.h): #include it.
1941 (CGEN_ATTR_VALUE_TYPE): Now a union.
1942 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1943 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1944 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1945 * cgen-bitset.h: New file.
1946
3c9b82ba
NC		 19472005-09-30 Catherine Moore <clm@cm00re.com>
1948
1949 * bfin.h: New file.
1950
6a2375c6
JB		 19512005-10-24 Jan Beulich <jbeulich@novell.com>
1952
1953 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1954 indirect operands.
1955
c06a12f8
DA		 19562005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1957
1958 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1959 Add FLAG_STRICT to pa10 ftest opcode.
1960
4d443107
DA		 19612005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1962
1963 * hppa.h (pa_opcodes): Remove lha entries.
1964
f0a3b40f
DA		 19652005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1966
1967 * hppa.h (FLAG_STRICT): Revise comment.
1968 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1969 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1970 entries for "fdc".
1971
e210c36b
NC		 19722005-09-30 Catherine Moore <clm@cm00re.com>
1973
1974 * bfin.h: New file.
1975
1b7e1362
DA		 19762005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1977
1978 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1979
089b39de
CF		 19802005-09-06 Chao-ying Fu <fu@mips.com>
1981
1982 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1983 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1984 define.
1985 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1986 (INSN_ASE_MASK): Update to include INSN_MT.
1987 (INSN_MT): New define for MT ASE.
1988
93c34b9b
CF		 19892005-08-25 Chao-ying Fu <fu@mips.com>
1990
1991 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1992 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1993 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1994 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1995 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1996 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1997 instructions.
1998 (INSN_DSP): New define for DSP ASE.
1999
848cf006
AM		 20002005-08-18 Alan Modra <amodra@bigpond.net.au>
2001
2002 * a29k.h: Delete.
2003
36ae0db3
DJ		 20042005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
2005
2006 * ppc.h (PPC_OPCODE_E300): Define.
2007
8c929562
MS		 20082005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
2009
2010 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
2011
f7b8cccc
DA		 20122005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2013
2014 PR gas/336
2015 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
2016 and pitlb.
2017
8b5328ac
JB		 20182005-07-27 Jan Beulich <jbeulich@novell.com>
2019
2020 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2021 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2022 Add movq-s as 64-bit variants of movd-s.
2023
f417d200
DA		 20242005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2025
18b3bdfc
DA		 2026 * hppa.h: Fix punctuation in comment.
2027
f417d200
DA		 2028 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2029 implicit space-register addressing. Set space-register bits on opcodes
2030 using implicit space-register addressing. Add various missing pa20
2031 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2032 space-register addressing. Use "fE" instead of "fe" in various
2033 fstw opcodes.
2034
9a145ce6
JB		 20352005-07-18 Jan Beulich <jbeulich@novell.com>
2036
2037 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2038
90700ea2
L		 20392007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2040
2041 * i386.h (i386_optab): Support Intel VMX Instructions.
2042
48f130a8
DA		 20432005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2044
2045 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2046
30123838
JB		 20472005-07-05 Jan Beulich <jbeulich@novell.com>
2048
2049 * i386.h (i386_optab): Add new insns.
2050
47b0e7ad
NC		 20512005-07-01 Nick Clifton <nickc@redhat.com>
2052
2053 * sparc.h: Add typedefs to structure declarations.
2054
b300c311
L		 20552005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2056
2057 PR 1013
2058 * i386.h (i386_optab): Update comments for 64bit addressing on
2059 mov. Allow 64bit addressing for mov and movq.
2060
2db495be
DA		 20612005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2062
2063 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2064 respectively, in various floating-point load and store patterns.
2065
caa05036
DA		 20662005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2067
2068 * hppa.h (FLAG_STRICT): Correct comment.
2069 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2070 PA 2.0 mneumonics when equivalent. Entries with cache control
2071 completers now require PA 1.1. Adjust whitespace.
2072
f4411256
AM		 20732005-05-19 Anton Blanchard <anton@samba.org>
2074
2075 * ppc.h (PPC_OPCODE_POWER5): Define.
2076
e172dbf8
NC		 20772005-05-10 Nick Clifton <nickc@redhat.com>
2078
2079 * Update the address and phone number of the FSF organization in
2080 the GPL notices in the following files:
2081 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2082 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2083 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2084 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2085 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2086 tic54x.h, tic80.h, v850.h, vax.h
2087
e44823cf
JB		 20882005-05-09 Jan Beulich <jbeulich@novell.com>
2089
2090 * i386.h (i386_optab): Add ht and hnt.
2091
791fe849
MK		 20922005-04-18 Mark Kettenis <kettenis@gnu.org>
2093
2094 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2095 Add xcrypt-ctr. Provide aliases without hyphens.
2096
faa7ef87
L		 20972005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2098
a63027e5
L		 2099 Moved from ../ChangeLog
2100
faa7ef87
L		 2101 2005-04-12 Paul Brook <paul@codesourcery.com>
2102 * m88k.h: Rename psr macros to avoid conflicts.
2103
2104 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2105 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2106 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2107 and ARM_ARCH_V6ZKT2.
2108
2109 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2110 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2111 Remove redundant instruction types.
2112 (struct argument): X_op - new field.
2113 (struct cst4_entry): Remove.
2114 (no_op_insn): Declare.
2115
2116 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2117 * crx.h (enum argtype): Rename types, remove unused types.
2118
2119 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2120 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2121 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2122 (enum operand_type): Rearrange operands, edit comments.
2123 replace us<N> with ui<N> for unsigned immediate.
2124 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2125 displacements (respectively).
2126 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2127 (instruction type): Add NO_TYPE_INS.
2128 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2129 (operand_entry): New field - 'flags'.
2130 (operand flags): New.
2131
2132 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2133 * crx.h (operand_type): Remove redundant types i3, i4,
2134 i5, i8, i12.
2135 Add new unsigned immediate types us3, us4, us5, us16.
2136
bc4bd9ab
MK		 21372005-04-12 Mark Kettenis <kettenis@gnu.org>
2138
2139 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2140 adjust them accordingly.
2141
373ff435
JB		 21422005-04-01 Jan Beulich <jbeulich@novell.com>
2143
2144 * i386.h (i386_optab): Add rdtscp.
2145
4cc91dba
L		 21462005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2147
2148 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2149 between memory and segment register. Allow movq for moving between
2150 general-purpose register and segment register.
4cc91dba 2151
9ae09ff9
JB		 21522005-02-09 Jan Beulich <jbeulich@novell.com>
2153
2154 PR gas/707
2155 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2156 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2157 fnstsw.
2158
638e7a64
NS		 21592006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2160
2161 * m68k.h (m68008, m68ec030, m68882): Remove.
2162 (m68k_mask): New.
2163 (cpu_m68k, cpu_cf): New.
2164 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2165 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2166
90219bd0
AO		 21672005-01-25 Alexandre Oliva <aoliva@redhat.com>
2168
2169 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2170 * cgen.h (enum cgen_parse_operand_type): Add
2171 CGEN_PARSE_OPERAND_SYMBOLIC.
2172
239cb185
FF		 21732005-01-21 Fred Fish <fnf@specifixinc.com>
2174
2175 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2176 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2177 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2178
dc9a9f39
FF		 21792005-01-19 Fred Fish <fnf@specifixinc.com>
2180
2181 * mips.h (struct mips_opcode): Add new pinfo2 member.
2182 (INSN_ALIAS): New define for opcode table entries that are
2183 specific instances of another entry, such as 'move' for an 'or'
2184 with a zero operand.
2185 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2186 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2187
98e7aba8
ILT		 21882004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2189
2190 * mips.h (CPU_RM9000): Define.
2191 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2192
37edbb65
JB		 21932004-11-25 Jan Beulich <jbeulich@novell.com>
2194
2195 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2196 to/from test registers are illegal in 64-bit mode. Add missing
2197 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2198 (previously one had to explicitly encode a rex64 prefix). Re-enable
2199 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2200 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2201
22022004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2203
2204 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2205 available only with SSE2. Change the MMX additions introduced by SSE
2206 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2207 instructions by their now designated identifier (since combining i686
2208 and 3DNow! does not really imply 3DNow!A).
2209
f5c7edf4
AM		 22102004-11-19 Alan Modra <amodra@bigpond.net.au>
2211
2212 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2213 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2214
7499d566
NC		 22152004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2216 Vineet Sharma <vineets@noida.hcltech.com>
2217
2218 * maxq.h: New file: Disassembly information for the maxq port.
2219
bcb9eebe
L		 22202004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2221
2222 * i386.h (i386_optab): Put back "movzb".
2223
94bb3d38
HPN		 22242004-11-04 Hans-Peter Nilsson <hp@axis.com>
2225
2226 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2227 comments. Remove member cris_ver_sim. Add members
2228 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2229 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2230 (struct cris_support_reg, struct cris_cond15): New types.
2231 (cris_conds15): Declare.
2232 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2233 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2234 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2235 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2236 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2237 SIZE_FIELD_UNSIGNED.
2238
37edbb65 22392004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2240
2241 * i386.h (sldx_Suf): Remove.
2242 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2243 (q_FP): Define, implying no REX64.
2244 (x_FP, sl_FP): Imply FloatMF.
2245 (i386_optab): Split reg and mem forms of moving from segment registers
2246 so that the memory forms can ignore the 16-/32-bit operand size
2247 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2248 all non-floating-point instructions. Unite 32- and 64-bit forms of
2249 movsx, movzx, and movd. Adjust floating point operations for the above
2250 changes to the *FP macros. Add DefaultSize to floating point control
2251 insns operating on larger memory ranges. Remove left over comments
2252 hinting at certain insns being Intel-syntax ones where the ones
2253 actually meant are already gone.
2254
48c9f030
NC		 22552004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2256
2257 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2258 instruction type.
2259
0dd132b6
NC		 22602004-09-30 Paul Brook <paul@codesourcery.com>
2261
2262 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2263 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2264
23794b24
MM		 22652004-09-11 Theodore A. Roth <troth@openavr.org>
2266
2267 * avr.h: Add support for
2268 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2269
2a309db0
AM		 22702004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2271
2272 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2273
b18c562e
NC		 22742004-08-24 Dmitry Diky <diwil@spec.ru>
2275
2276 * msp430.h (msp430_opc): Add new instructions.
2277 (msp430_rcodes): Declare new instructions.
2278 (msp430_hcodes): Likewise..
2279
45d313cd
NC		 22802004-08-13 Nick Clifton <nickc@redhat.com>
2281
2282 PR/301
2283 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2284 processors.
2285
30d1c836
ML		 22862004-08-30 Michal Ludvig <mludvig@suse.cz>
2287
2288 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2289
9a45f1c2
L		 22902004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2291
2292 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2293
543613e9
NC		 22942004-07-21 Jan Beulich <jbeulich@novell.com>
2295
2296 * i386.h: Adjust instruction descriptions to better match the
2297 specification.
2298
b781e558
RE		 22992004-07-16 Richard Earnshaw <rearnsha@arm.com>
2300
2301 * arm.h: Remove all old content. Replace with architecture defines
2302 from gas/config/tc-arm.c.
2303
8577e690
AS		 23042004-07-09 Andreas Schwab <schwab@suse.de>
2305
2306 * m68k.h: Fix comment.
2307
1fe1f39c
NC		 23082004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2309
2310 * crx.h: New file.
2311
1d9f512f
AM		 23122004-06-24 Alan Modra <amodra@bigpond.net.au>
2313
2314 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2315
be8c092b
NC		 23162004-05-24 Peter Barada <peter@the-baradas.com>
2317
2318 * m68k.h: Add 'size' to m68k_opcode.
2319
6b6e92f4
NC		 23202004-05-05 Peter Barada <peter@the-baradas.com>
2321
2322 * m68k.h: Switch from ColdFire chip name to core variant.
2323
23242004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2325
2326 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2327 descriptions for new EMAC cases.
2328 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2329 handle Motorola MAC syntax.
2330 Allow disassembly of ColdFire V4e object files.
2331
fdd12ef3
AM		 23322004-03-16 Alan Modra <amodra@bigpond.net.au>
2333
2334 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2335
3922a64c
L		 23362004-03-12 Jakub Jelinek <jakub@redhat.com>
2337
2338 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2339
1f45d988
ML		 23402004-03-12 Michal Ludvig <mludvig@suse.cz>
2341
2342 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2343
0f10071e
ML		 23442004-03-12 Michal Ludvig <mludvig@suse.cz>
2345
2346 * i386.h (i386_optab): Added xstore/xcrypt insns.
2347
3255318a
NC		 23482004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2349
2350 * h8300.h (32bit ldc/stc): Add relaxing support.
2351
ca9a79a1 23522004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2353
ca9a79a1
NC		 2354 * h8300.h (BITOP): Pass MEMRELAX flag.
2355
875a0b14
NC		 23562004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2357
2358 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2359 except for the H8S.
252b5132 2360
c9e214e5 2361For older changes see ChangeLog-9103
252b5132 2362\f
b90efa5b 2363Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2364
2365Copying and distribution of this file, with or without modification,
2366are permitted in any medium without royalty provided the copyright
2367notice and this notice are preserved.
2368
252b5132 2369Local Variables:
c9e214e5
AM		 2370mode: change-log
2371left-margin: 8
2372fill-column: 74
252b5132
RH		 2373version-control: never
2374End:
GDB Binutils - Deliverables
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