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Fix recent STM324LXX patch to compile on 32-bit hosts.
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
875880c6
YQ		 12015-10-07 Yao Qi <yao.qi@linaro.org>
2
3 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
4 <name>: New field.
5
d3e12b29
YQ		 62015-10-07 Yao Qi <yao.qi@linaro.org>
7
8 * aarch64.h [__cplusplus]: Wrap in extern "C".
9
886a2506
NC		 102015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
11 Cupertino Miranda <cmiranda@synopsys.com>
12
13 * arc-func.h: New file.
14 * arc.h: Likewise.
15
e141d84e
YQ		 162015-10-02 Yao Qi <yao.qi@linaro.org>
17
18 * aarch64.h (aarch64_zero_register_p): Move the declaration
19 to column one.
20
36f4aab1
YQ		 212015-10-02 Yao Qi <yao.qi@linaro.org>
22
23 * aarch64.h (aarch64_decode_insn): Declare it.
24
7ecc513a
DV		 252015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
26
27 * s390.h (S390_INSTR_FLAG_HTM): New flag.
28 (S390_INSTR_FLAG_VX): New flag.
29 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
30
b6518b38
NC		 312015-09-23 Nick Clifton <nickc@redhat.com>
32
33 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
34 shifting.
35
f04265ec
NC		 362015-09-22 Nick Clifton <nickc@redhat.com>
37
38 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
39
7bdf96ef
NC		 402015-09-09 Daniel Santos <daniel.santos@pobox.com>
41
42 * visium.h (gen_reg_table): Make static.
43 (fp_reg_table): Likewise.
44 (cc_table): Likewise.
45
f33026a9
MW		 462015-07-20 Matthew Wahab <matthew.wahab@arm.com>
47
48 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
49 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
50 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
51 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
52
ef5a96d5
AM		 532015-07-03 Alan Modra <amodra@gmail.com>
54
55 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
56
c8c8175b
SL		 572015-07-01 Sandra Loosemore <sandra@codesourcery.com>
58 Cesar Philippidis <cesar@codesourcery.com>
59
60 * nios2.h (enum iw_format_type): Add R2 formats.
61 (enum overflow_type): Add signed_immed12_overflow and
62 enumeration_overflow for R2.
63 (struct nios2_opcode): Document new argument letters for R2.
64 (REG_3BIT, REG_LDWM, REG_POP): Define.
65 (includes): Include nios2r2.h.
66 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
67 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
68 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
69 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
70 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
71 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
72 Declare.
73 * nios2r2.h: New file.
74
11a0cf2e
PB		 752015-06-19 Peter Bergner <bergner@vnet.ibm.com>
76
77 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
78 (ppc_optional_operand_value): New inline function.
79
88f0ea34
MW		 802015-06-04 Matthew Wahab <matthew.wahab@arm.com>
81
82 * aarch64.h (AARCH64_V8_1): New.
83
a5932920
MW		 842015-06-03 Matthew Wahab <matthew.wahab@arm.com>
85
86 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
87 (ARM_ARCH_V8_1A): New.
88 (ARM_ARCH_V8_1A_FP): New.
89 (ARM_ARCH_V8_1A_SIMD): New.
90 (ARM_ARCH_V8_1A_CRYPTOV1): New.
91 (ARM_FEATURE_CORE): New.
92
ddfded2f
MW		 932015-06-02 Matthew Wahab <matthew.wahab@arm.com>
94
95 * arm.h (ARM_EXT2_PAN): New.
96 (ARM_FEATURE_CORE_HIGH): New.
97
1af1dd51
MW		 982015-06-02 Matthew Wahab <matthew.wahab@arm.com>
99
100 * arm.h (ARM_FEATURE_ALL): New.
101
9e1f0fa7
MW		 1022015-06-02 Matthew Wahab <matthew.wahab@arm.com>
103
104 * aarch64.h (AARCH64_FEATURE_RDMA): New.
105
290806fd
MW		 1062015-06-02 Matthew Wahab <matthew.wahab@arm.com>
107
108 * aarch64.h (AARCH64_FEATURE_LOR): New.
109
f21cce2c
MW		 1102015-06-01 Matthew Wahab <matthew.wahab@arm.com>
111
112 * aarch64.h (AARCH64_FEATURE_PAN): New.
113 (aarch64_sys_reg_supported_p): Declare.
114 (aarch64_pstatefield_supported_p): Declare.
115
0952813b
DD		 1162015-04-30 DJ Delorie <dj@redhat.com>
117
118 * rl78.h (RL78_Dis_Isa): New.
119 (rl78_decode_opcode): Add ISA parameter.
120
823d2571
TG		 1212015-03-24 Terry Guo <terry.guo@arm.com>
122
123 * arm.h (arm_feature_set): Extended to provide more available bits.
124 (ARM_ANY): Updated to follow above new definition.
125 (ARM_CPU_HAS_FEATURE): Likewise.
126 (ARM_CPU_IS_ANY): Likewise.
127 (ARM_MERGE_FEATURE_SETS): Likewise.
128 (ARM_CLEAR_FEATURE): Likewise.
129 (ARM_FEATURE): Likewise.
130 (ARM_FEATURE_COPY): New macro.
131 (ARM_FEATURE_EQUAL): Likewise.
132 (ARM_FEATURE_ZERO): Likewise.
133 (ARM_FEATURE_CORE_EQUAL): Likewise.
134 (ARM_FEATURE_LOW): Likewise.
135 (ARM_FEATURE_CORE_LOW): Likewise.
136 (ARM_FEATURE_CORE_COPROC): Likewise.
137
f63c1776
PA		 1382015-02-19 Pedro Alves <palves@redhat.com>
139
140 * cgen.h [__cplusplus]: Wrap in extern "C".
141 * msp430-decode.h [__cplusplus]: Likewise.
142 * nios2.h [__cplusplus]: Likewise.
143 * rl78.h [__cplusplus]: Likewise.
144 * rx.h [__cplusplus]: Likewise.
145 * tilegx.h [__cplusplus]: Likewise.
146
3f8107ab
AM		 1472015-01-28 James Bowman <james.bowman@ftdichip.com>
148
149 * ft32.h: New file.
150
1e2e8c52
AK		 1512015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
152
153 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
154
b90efa5b
AM		 1552015-01-01 Alan Modra <amodra@gmail.com>
156
157 Update year range in copyright notice of all files.
158
bffb6004
AG		 1592014-12-27 Anthony Green <green@moxielogic.com>
160
161 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
162 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
163
1945cfa5
EB		 1642014-12-06 Eric Botcazou <ebotcazou@adacore.com>
165
166 * visium.h: New file.
167
d306ce58
SL		 1682014-11-28 Sandra Loosemore <sandra@codesourcery.com>
169
170 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
171 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
172 (NIOS2_INSN_OPTARG): Renumber.
173
b4714c7c
SL		 1742014-11-06 Sandra Loosemore <sandra@codesourcery.com>
175
176 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
177 declaration. Fix obsolete comment.
178
96ba4233
SL		 1792014-10-23 Sandra Loosemore <sandra@codesourcery.com>
180
181 * nios2.h (enum iw_format_type): New.
182 (struct nios2_opcode): Update comments. Add size and format fields.
183 (NIOS2_INSN_OPTARG): New.
184 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
185 (struct nios2_reg): Add regtype field.
186 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
187 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
188 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
189 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
190 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
191 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
192 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
193 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
194 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
195 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
196 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
197 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
198 (OP_MASK_OP, OP_SH_OP): Delete.
199 (OP_MASK_IOP, OP_SH_IOP): Delete.
200 (OP_MASK_IRD, OP_SH_IRD): Delete.
201 (OP_MASK_IRT, OP_SH_IRT): Delete.
202 (OP_MASK_IRS, OP_SH_IRS): Delete.
203 (OP_MASK_ROP, OP_SH_ROP): Delete.
204 (OP_MASK_RRD, OP_SH_RRD): Delete.
205 (OP_MASK_RRT, OP_SH_RRT): Delete.
206 (OP_MASK_RRS, OP_SH_RRS): Delete.
207 (OP_MASK_JOP, OP_SH_JOP): Delete.
208 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
209 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
210 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
211 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
212 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
213 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
214 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
215 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
216 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
217 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
218 (OP_MASK_<insn>, OP_MASK): Delete.
219 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
220 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
221 Include nios2r1.h to define new instruction opcode constants
222 and accessors.
223 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
224 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
225 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
226 (NUMOPCODES, NUMREGISTERS): Delete.
227 * nios2r1.h: New file.
228
0b6be415
JM		 2292014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
230
231 * sparc.h (HWCAP2_VIS3B): Documentation improved.
232
3d68f91c
JM		 2332014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
234
235 * sparc.h (sparc_opcode): new field `hwcaps2'.
236 (HWCAP2_FJATHPLUS): New define.
237 (HWCAP2_VIS3B): Likewise.
238 (HWCAP2_ADP): Likewise.
239 (HWCAP2_SPARC5): Likewise.
240 (HWCAP2_MWAIT): Likewise.
241 (HWCAP2_XMPMUL): Likewise.
242 (HWCAP2_XMONT): Likewise.
243 (HWCAP2_NSEC): Likewise.
244 (HWCAP2_FJATHHPC): Likewise.
245 (HWCAP2_FJDES): Likewise.
246 (HWCAP2_FJAES): Likewise.
247 Document the new operand kind `{', corresponding to the mcdper
248 ancillary state register.
249 Document the new operand kind }, which represents frsd floating
250 point registers (double precision) which must be the same than
251 frs1 in its containing instruction.
252
40c7a7cb
KLC		 2532014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
254
72f4393d 255 * nds32.h: Add new opcode declaration.
40c7a7cb 256
7361da2c
AB		 2572014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
258 Matthew Fortune <matthew.fortune@imgtec.com>
259
260 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
261 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
262 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
263 +I, +O, +R, +:, +\, +", +;
264 (mips_check_prev_operand): New struct.
265 (INSN2_FORBIDDEN_SLOT): New define.
266 (INSN_ISA32R6): New define.
267 (INSN_ISA64R6): New define.
268 (INSN_UPTO32R6): New define.
269 (INSN_UPTO64R6): New define.
270 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
271 (ISA_MIPS32R6): New define.
272 (ISA_MIPS64R6): New define.
273 (CPU_MIPS32R6): New define.
274 (CPU_MIPS64R6): New define.
275 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
276
ee804238
JW		 2772014-09-03 Jiong Wang <jiong.wang@arm.com>
278
279 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
280 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
281 (aarch64_insn_class): Add lse_atomic.
282 (F_LSE_SZ): New field added.
283 (opcode_has_special_coder): Recognize F_LSE_SZ.
284
5575639b
MR		 2852014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
286
287 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
288 over to `+J'.
289
43885403
MF		 2902014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
291
292 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
293 (INSN_LOAD_COPROC): New define.
294 (INSN_COPROC_MOVE_DELAY): Rename to...
295 (INSN_COPROC_MOVE): New define.
296
f36e8886 2972014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 298 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
299 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
300 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 301
302 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
303 (AVR_ISA_2xxxa): Define ISA without LPM.
304 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
305 Add doc for contraint used in 16 bit lds/sts.
306 Adjust ISA group for icall, ijmp, pop and push.
307 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
308
00b32ff2
NC		 3092014-05-19 Nick Clifton <nickc@redhat.com>
310
311 * msp430.h (struct msp430_operand_s): Add vshift field.
312
ae52f483
AB		 3132014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
314
315 * mips.h (INSN_ISA_MASK): Updated.
316 (INSN_ISA32R3): New define.
317 (INSN_ISA32R5): New define.
318 (INSN_ISA64R3): New define.
319 (INSN_ISA64R5): New define.
320 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
321 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
322 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
323 mips64r5.
324 (INSN_UPTO32R3): New define.
325 (INSN_UPTO32R5): New define.
326 (INSN_UPTO64R3): New define.
327 (INSN_UPTO64R5): New define.
328 (ISA_MIPS32R3): New define.
329 (ISA_MIPS32R5): New define.
330 (ISA_MIPS64R3): New define.
331 (ISA_MIPS64R5): New define.
332 (CPU_MIPS32R3): New define.
333 (CPU_MIPS32R5): New define.
334 (CPU_MIPS64R3): New define.
335 (CPU_MIPS64R5): New define.
336
3efe9ec5
RS		 3372014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
338
339 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
340
73589c9d
CS		 3412014-04-22 Christian Svensson <blue@cmd.nu>
342
343 * or32.h: Delete.
344
4b95cf5c
AM		 3452014-03-05 Alan Modra <amodra@gmail.com>
346
347 Update copyright years.
348
e269fea7
AB		 3492013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
350
351 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
352 microMIPS.
353
35c08157
KLC		 3542013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
355 Wei-Cheng Wang <cole945@gmail.com>
356
357 * nds32.h: New file for Andes NDS32.
358
594d8fa8
MF		 3592013-12-07 Mike Frysinger <vapier@gentoo.org>
360
361 * bfin.h: Remove +x file mode.
362
87b8eed7
YZ		 3632013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
364
365 * aarch64.h (aarch64_pstatefields): Change element type to
366 aarch64_sys_reg.
367
c9fb6e58
YZ		 3682013-11-18 Renlin Li <Renlin.Li@arm.com>
369
370 * arm.h (ARM_AEXT_V7VE): New define.
371 (ARM_ARCH_V7VE): New define.
372 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
373
a203d9b7
YZ		 3742013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
375
376 Revert
377
378 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
379
380 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
381 (aarch64_sys_reg_writeonly_p): Ditto.
382
75468c93
YZ		 3832013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
384
385 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
386 (aarch64_sys_reg_writeonly_p): Ditto.
387
49eec193
YZ		 3882013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
389
390 * aarch64.h (aarch64_sys_reg): New typedef.
391 (aarch64_sys_regs): Change to define with the new type.
392 (aarch64_sys_reg_deprecated_p): Declare.
393
68a64283
YZ		 3942013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
395
396 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
397 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
398
387a82f1
CF		 3992013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
400
401 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
402 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
403 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
404 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
405 For MIPS, update extension character sequences after +.
406 (ASE_MSA): New define.
407 (ASE_MSA64): New define.
408 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
409 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
410 For microMIPS, update extension character sequences after +.
411
9aff4b7a
NC		 4122013-08-23 Yuri Chornoivan <yurchor@ukr.net>
413
414 PR binutils/15834
415 * i960.h: Fix typos.
416
e423441d
RS		 4172013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
418
419 * mips.h: Remove references to "+I" and imm2_expr.
420
5e0dc5ba
RS		 4212013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
422
423 * mips.h (M_DEXT, M_DINS): Delete.
424
0f35dbc4
RS		 4252013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
426
427 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
428 (mips_optional_operand_p): New function.
429
14daeee3
RS		 4302013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
431 Richard Sandiford <rdsandiford@googlemail.com>
432
433 * mips.h: Document new VU0 operand characters.
434 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
435 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
436 (OP_REG_R5900_ACC): New mips_reg_operand_types.
437 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
438 (mips_vu0_channel_mask): Declare.
439
3ccad066
RS		 4402013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
441
442 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
443 (mips_int_operand_min, mips_int_operand_max): New functions.
444 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
445
fc76e730
RS		 4462013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
447
448 * mips.h (mips_decode_reg_operand): New function.
449 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
450 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
451 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
452 New macros.
453 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
454 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
455 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
456 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
457 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
458 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
459 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
460 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
461 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
462 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
463 macros to cover the gaps.
464 (INSN2_MOD_SP): Replace with...
465 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
466 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
467 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
468 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
469 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
470 Delete.
471
26545944
RS		 4722013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
473
474 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
475 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
476 (MIPS16_INSN_COND_BRANCH): Delete.
477
7e8b059b
L		 4782013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
479 Kirill Yukhin <kirill.yukhin@intel.com>
480 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
481
482 * i386.h (BND_PREFIX_OPCODE): New.
483
c3c07478
RS		 4842013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
485
486 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
487 OP_SAVE_RESTORE_LIST.
488 (decode_mips16_operand): Declare.
489
ab902481
RS		 4902013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
491
492 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
493 (mips_operand, mips_int_operand, mips_mapped_int_operand)
494 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
495 (mips_pcrel_operand): New structures.
496 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
497 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
498 (decode_mips_operand, decode_micromips_operand): Declare.
499
cc537e56
RS		 5002013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
501
502 * mips.h: Document MIPS16 "I" opcode.
503
f2ae14a1
RS		 5042013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
505
506 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
507 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
508 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
509 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
510 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
511 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
512 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
513 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
514 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
515 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
516 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
517 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
518 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
519 Rename to...
520 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
521 (M_USD_AB): ...these.
522
5c324c16
RS		 5232013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
524
525 * mips.h: Remove documentation of "[" and "]". Update documentation
526 of "k" and the MDMX formats.
527
23e69e47
RS		 5282013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
529
530 * mips.h: Update documentation of "+s" and "+S".
531
27c5c572
RS		 5322013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
533
534 * mips.h: Document "+i".
535
e76ff5ab
RS		 5362013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
537
538 * mips.h: Remove "mi" documentation. Update "mh" documentation.
539 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
540 Delete.
541 (INSN2_WRITE_GPR_MHI): Rename to...
542 (INSN2_WRITE_GPR_MH): ...this.
543
fa7616a4
RS		 5442013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
545
546 * mips.h: Remove documentation of "+D" and "+T".
547
18870af7
RS		 5482013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
549
550 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
551 Use "source" rather than "destination" for microMIPS "G".
552
833794fc
MR		 5532013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
554
555 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
556 values.
557
c3678916
RS		 5582013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
559
560 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
561
7f3c4072
CM		 5622013-06-17 Catherine Moore <clm@codesourcery.com>
563 Maciej W. Rozycki <macro@codesourcery.com>
564 Chao-Ying Fu <fu@mips.com>
565
566 * mips.h (OP_SH_EVAOFFSET): Define.
567 (OP_MASK_EVAOFFSET): Define.
568 (INSN_ASE_MASK): Delete.
569 (ASE_EVA): Define.
570 (M_CACHEE_AB, M_CACHEE_OB): New.
571 (M_LBE_OB, M_LBE_AB): New.
572 (M_LBUE_OB, M_LBUE_AB): New.
573 (M_LHE_OB, M_LHE_AB): New.
574 (M_LHUE_OB, M_LHUE_AB): New.
575 (M_LLE_AB, M_LLE_OB): New.
576 (M_LWE_OB, M_LWE_AB): New.
577 (M_LWLE_AB, M_LWLE_OB): New.
578 (M_LWRE_AB, M_LWRE_OB): New.
579 (M_PREFE_AB, M_PREFE_OB): New.
580 (M_SCE_AB, M_SCE_OB): New.
581 (M_SBE_OB, M_SBE_AB): New.
582 (M_SHE_OB, M_SHE_AB): New.
583 (M_SWE_OB, M_SWE_AB): New.
584 (M_SWLE_AB, M_SWLE_OB): New.
585 (M_SWRE_AB, M_SWRE_OB): New.
586 (MICROMIPSOP_SH_EVAOFFSET): Define.
587 (MICROMIPSOP_MASK_EVAOFFSET): Define.
588
0c8fe7cf
SL		 5892013-06-12 Sandra Loosemore <sandra@codesourcery.com>
590
591 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
592
c77c0862
RS		 5932013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
594
595 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
596
b015e599
AP		 5972013-05-09 Andrew Pinski <apinski@cavium.com>
598
599 * mips.h (OP_MASK_CODE10): Correct definition.
600 (OP_SH_CODE10): Likewise.
601 Add a comment that "+J" is used now for OP_*CODE10.
602 (INSN_ASE_MASK): Update.
603 (INSN_VIRT): New macro.
604 (INSN_VIRT64): New macro
605
13761a11
NC		 6062013-05-02 Nick Clifton <nickc@redhat.com>
607
608 * msp430.h: Add patterns for MSP430X instructions.
609
0afd1215
DM		 6102013-04-06 David S. Miller <davem@davemloft.net>
611
612 * sparc.h (F_PREFERRED): Define.
613 (F_PREF_ALIAS): Define.
614
41702d50
NC		 6152013-04-03 Nick Clifton <nickc@redhat.com>
616
617 * v850.h (V850_INVERSE_PCREL): Define.
618
e21e1a51
NC		 6192013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
620
621 PR binutils/15068
622 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
623
51dcdd4d
NC		 6242013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
625
626 PR binutils/15068
627 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
628 Add 16-bit opcodes.
629 * tic6xc-opcode-table.h: Add 16-bit insns.
630 * tic6x.h: Add support for 16-bit insns.
631
81f5558e
NC		 6322013-03-21 Michael Schewe <michael.schewe@gmx.net>
633
634 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
635 and mov.b/w/l Rs,@(d:32,ERd).
636
165546ad
NC		 6372013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
638
639 PR gas/15082
640 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
641 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
642 tic6x_operand_xregpair operand coding type.
643 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
644 opcode field, usu ORXREGD1324 for the src2 operand and remove the
645 TIC6X_FLAG_NO_CROSS.
646
795b8e6b
NC		 6472013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
648
649 PR gas/15095
650 * tic6x.h (enum tic6x_coding_method): Add
651 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
652 separately the msb and lsb of a register pair. This is needed to
653 encode the opcodes in the same way as TI assembler does.
654 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
655 and rsqrdp opcodes to use the new field coding types.
656
dd5181d5
KT		 6572013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
658
659 * arm.h (CRC_EXT_ARMV8): New constant.
660 (ARCH_CRC_ARMV8): New macro.
661
e60bb1dd
YZ		 6622013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
663
664 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
665
36591ba1 6662013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 667 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 668
669 Based on patches from Altera Corporation.
670
671 * nios2.h: New file.
672
e30181a5
YZ		 6732013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
674
675 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
676
0c9573f4
NC		 6772013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
678
679 PR gas/15069
680 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
681
981dc7f1
NC		 6822013-01-24 Nick Clifton <nickc@redhat.com>
683
684 * v850.h: Add e3v5 support.
685
f5555712
YZ		 6862013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
687
688 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
689
5817ffd1
PB		 6902013-01-10 Peter Bergner <bergner@vnet.ibm.com>
691
692 * ppc.h (PPC_OPCODE_POWER8): New define.
693 (PPC_OPCODE_HTM): Likewise.
694
a3c62988
NC		 6952013-01-10 Will Newton <will.newton@imgtec.com>
696
697 * metag.h: New file.
698
73335eae
NC		 6992013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
700
701 * cr16.h (make_instruction): Rename to cr16_make_instruction.
702 (match_opcode): Rename to cr16_match_opcode.
703
e407c74b
NC		 7042013-01-04 Juergen Urban <JuergenUrban@gmx.de>
705
706 * mips.h: Add support for r5900 instructions including lq and sq.
707
bab4becb
NC		 7082013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
709
710 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
711 (make_instruction,match_opcode): Added function prototypes.
712 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
713
776fc418
AM		 7142012-11-23 Alan Modra <amodra@gmail.com>
715
716 * ppc.h (ppc_parse_cpu): Update prototype.
717
f05682d4
DA		 7182012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
719
720 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
721 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
722
cfc72779
AK		 7232012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
724
725 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
726
b3e14eda
L		 7272012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
728
729 * ia64.h (ia64_opnd): Add new operand types.
730
2c63854f
DM		 7312012-08-21 David S. Miller <davem@davemloft.net>
732
733 * sparc.h (F3F4): New macro.
734
a06ea964 7352012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 736 Laurent Desnogues <laurent.desnogues@arm.com>
737 Jim MacArthur <jim.macarthur@arm.com>
738 Marcus Shawcroft <marcus.shawcroft@arm.com>
739 Nigel Stephens <nigel.stephens@arm.com>
740 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
741 Richard Earnshaw <rearnsha@arm.com>
742 Sofiane Naci <sofiane.naci@arm.com>
743 Tejas Belagod <tejas.belagod@arm.com>
744 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 745
746 * aarch64.h: New file.
747
35d0a169 7482012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 749 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 750
751 * mips.h (mips_opcode): Add the exclusions field.
752 (OPCODE_IS_MEMBER): Remove macro.
753 (cpu_is_member): New inline function.
754 (opcode_is_member): Likewise.
755
03f66e8a 7562012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 757 Catherine Moore <clm@codesourcery.com>
758 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 759
760 * mips.h: Document microMIPS DSP ASE usage.
761 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
762 microMIPS DSP ASE support.
763 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
764 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
765 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
766 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
767 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
768 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
769 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
770
9d7b4c23
MR		 7712012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
772
773 * mips.h: Fix a typo in description.
774
76e879f8
NC		 7752012-06-07 Georg-Johann Lay <avr@gjlay.de>
776
777 * avr.h: (AVR_ISA_XCH): New define.
778 (AVR_ISA_XMEGA): Use it.
779 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
780
6927f982
NC		 7812012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
782
783 * m68hc11.h: Add XGate definitions.
784 (struct m68hc11_opcode): Add xg_mask field.
785
b9c361e0
JL		 7862012-05-14 Catherine Moore <clm@codesourcery.com>
787 Maciej W. Rozycki <macro@codesourcery.com>
788 Rhonda Wittels <rhonda@codesourcery.com>
789
6927f982 790 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 791 (PPC_OP_SA): New macro.
792 (PPC_OP_SE_VLE): New macro.
793 (PPC_OP): Use a variable shift amount.
794 (powerpc_operand): Update comments.
795 (PPC_OPSHIFT_INV): New macro.
796 (PPC_OPERAND_CR): Replace with...
797 (PPC_OPERAND_CR_BIT): ...this and
798 (PPC_OPERAND_CR_REG): ...this.
799
800
f6c1a2d5
NC		 8012012-05-03 Sean Keys <skeys@ipdatasys.com>
802
803 * xgate.h: Header file for XGATE assembler.
804
ec668d69
DM		 8052012-04-27 David S. Miller <davem@davemloft.net>
806
6cda1326
DM		 807 * sparc.h: Document new arg code' )' for crypto RS3
808 immediates.
809
ec668d69
DM		 810 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
811 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
812 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
813 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
814 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
815 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
816 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
817 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
818 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
819 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
820 HWCAP_CBCOND, HWCAP_CRC32): New defines.
821
aea77599
AM		 8222012-03-10 Edmar Wienskoski <edmar@freescale.com>
823
824 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
825
1f42f8b3
AM		 8262012-02-27 Alan Modra <amodra@gmail.com>
827
828 * crx.h (cst4_map): Update declaration.
829
6f7be959
WL		 8302012-02-25 Walter Lee <walt@tilera.com>
831
832 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
833 TILEGX_OPC_LD_TLS.
834 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
835 TILEPRO_OPC_LW_TLS_SN.
836
42164a71
L		 8372012-02-08 H.J. Lu <hongjiu.lu@intel.com>
838
839 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
840 (XRELEASE_PREFIX_OPCODE): Likewise.
841
432233b3 8422011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 843 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 844
845 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
846 (INSN_OCTEON2): New macro.
847 (CPU_OCTEON2): New macro.
848 (OPCODE_IS_MEMBER): Add Octeon2.
849
dd6a37e7
AP		 8502011-11-29 Andrew Pinski <apinski@cavium.com>
851
852 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
853 (INSN_OCTEONP): New macro.
854 (CPU_OCTEONP): New macro.
855 (OPCODE_IS_MEMBER): Add Octeon+.
856 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
857
99c513f6
DD		 8582011-11-01 DJ Delorie <dj@redhat.com>
859
860 * rl78.h: New file.
861
26f85d7a
MR		 8622011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
863
864 * mips.h: Fix a typo in description.
865
9e8c70f9
DM		 8662011-09-21 David S. Miller <davem@davemloft.net>
867
868 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
869 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
870 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
871 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
872
dec0624d 8732011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 874 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 875
876 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
877 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
878 (INSN_ASE_MASK): Add the MCU bit.
879 (INSN_MCU): New macro.
880 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
881 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
882
2b0c8b40
MR		 8832011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
884
885 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
886 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
887 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
888 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
889 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
890 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
891 (INSN2_READ_GPR_MMN): Likewise.
892 (INSN2_READ_FPR_D): Change the bit used.
893 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
894 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
895 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
896 (INSN2_COND_BRANCH): Likewise.
897 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
898 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
899 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
900 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
901 (INSN2_MOD_GPR_MN): Likewise.
902
ea783ef3
DM		 9032011-08-05 David S. Miller <davem@davemloft.net>
904
905 * sparc.h: Document new format codes '4', '5', and '('.
906 (OPF_LOW4, RS3): New macros.
907
7c176fa8
MR		 9082011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
909
910 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
911 order of flags documented.
912
2309ddf2
MR		 9132011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
914
915 * mips.h: Clarify the description of microMIPS instruction
916 manipulation macros.
917 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
918
df58fc94 9192011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 920 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 921
922 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
923 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
924 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
925 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
926 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
927 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
928 (OP_MASK_RS3, OP_SH_RS3): Likewise.
929 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
930 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
931 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
932 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
933 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
934 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
935 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
936 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
937 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
938 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
939 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
940 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
941 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
942 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
943 (INSN_WRITE_GPR_S): New macro.
944 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
945 (INSN2_READ_FPR_D): Likewise.
946 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
947 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
948 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
949 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
950 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
951 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
952 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
953 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
954 (CPU_MICROMIPS): New macro.
955 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
956 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
957 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
958 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
959 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
960 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
961 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
962 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
963 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
964 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
965 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
966 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
967 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
968 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
969 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
970 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
971 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
972 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
973 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
974 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
975 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
976 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
977 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
978 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
979 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
980 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
981 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
982 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
983 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
984 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
985 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
986 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
987 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
988 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
989 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
990 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
991 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
992 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
993 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
994 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
995 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
996 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
997 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
998 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
999 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1000 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1001 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1002 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1003 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1004 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1005 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1006 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1007 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1008 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1009 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1010 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1011 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1012 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1013 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1014 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1015 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1016 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1017 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1018 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1019 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1020 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1021 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1022 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1023 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1024 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1025 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1026 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1027 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1028 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1029 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1030 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1031 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1032 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1033 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1034 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1035 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1036 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1037 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1038 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1039 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1040 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1041 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1042 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1043 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1044 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1045 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1046 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1047 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1048 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1049 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1050 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1051 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1052 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1053 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1054 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1055 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1056 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1057 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1058 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1059 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1060 (micromips_opcodes): New declaration.
1061 (bfd_micromips_num_opcodes): Likewise.
1062
bcd530a7
RS		 10632011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1064
1065 * mips.h (INSN_TRAP): Rename to...
1066 (INSN_NO_DELAY_SLOT): ... this.
1067 (INSN_SYNC): Remove macro.
1068
2dad5a91
EW		 10692011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1070
1071 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1072 a duplicate of AVR_ISA_SPM.
1073
5d73b1f1
NC		 10742011-07-01 Nick Clifton <nickc@redhat.com>
1075
1076 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1077
ef26d60e
MF		 10782011-06-18 Robin Getz <robin.getz@analog.com>
1079
1080 * bfin.h (is_macmod_signed): New func
1081
8fb8dca7
MF		 10822011-06-18 Mike Frysinger <vapier@gentoo.org>
1083
1084 * bfin.h (is_macmod_pmove): Add missing space before func args.
1085 (is_macmod_hmove): Likewise.
1086
aa137e4d
NC		 10872011-06-13 Walter Lee <walt@tilera.com>
1088
1089 * tilegx.h: New file.
1090 * tilepro.h: New file.
1091
3b2f0793
PB		 10922011-05-31 Paul Brook <paul@codesourcery.com>
1093
aa137e4d
NC		 1094 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1095
10962011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1097
1098 * s390.h: Replace S390_OPERAND_REG_EVEN with
1099 S390_OPERAND_REG_PAIR.
1100
11012011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1102
1103 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1104
ac7f631b
NC		 11052011-04-18 Julian Brown <julian@codesourcery.com>
1106
1107 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1108
84701018
NC		 11092011-04-11 Dan McDonald <dan@wellkeeper.com>
1110
1111 PR gas/12296
1112 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1113
8cc66334
EW		 11142011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1115
1116 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1117 New instruction set flags.
1118 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1119
3eebd5eb
MR		 11202011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1121
1122 * mips.h (M_PREF_AB): New enum value.
1123
26bb3ddd
MF		 11242011-02-12 Mike Frysinger <vapier@gentoo.org>
1125
89c0d58c
MR		 1126 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1127 M_IU): Define.
1128 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1129
dd76fcb8
MF		 11302011-02-11 Mike Frysinger <vapier@gentoo.org>
1131
1132 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1133
98d23bef
BS		 11342011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1135
1136 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1137 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1138
3c853d93
DA		 11392010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1140
1141 PR gas/11395
1142 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1143 "bb" entries.
1144
79676006
DA		 11452010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1146
1147 PR gas/11395
1148 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1149
1bec78e9
RS		 11502010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1151
1152 * mips.h: Update commentary after last commit.
1153
98675402
RS		 11542010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1155
1156 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1157 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1158 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1159
aa137e4d
NC		 11602010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1161
1162 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1163
435b94a4
RS		 11642010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1165
1166 * mips.h: Fix previous commit.
1167
d051516a
NC		 11682010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1169
1170 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1171 (INSN_LOONGSON_3A): Clear bit 31.
1172
251665fc
MGD		 11732010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1174
1175 PR gas/12198
1176 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1177 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1178 (ARM_ARCH_V6M_ONLY): New define.
1179
fd503541
NC		 11802010-11-11 Mingming Sun <mingm.sun@gmail.com>
1181
1182 * mips.h (INSN_LOONGSON_3A): Defined.
1183 (CPU_LOONGSON_3A): Defined.
1184 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1185
4469d2be
AM		 11862010-10-09 Matt Rice <ratmice@gmail.com>
1187
1188 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1189 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1190
90ec0d68
MGD		 11912010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1192
1193 * arm.h (ARM_EXT_VIRT): New define.
1194 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1195 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1196 Extensions.
1197
eea54501 11982010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1199
eea54501
MGD		 1200 * arm.h (ARM_AEXT_ADIV): New define.
1201 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1202
b2a5fbdc
MGD		 12032010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1204
1205 * arm.h (ARM_EXT_OS): New define.
1206 (ARM_AEXT_V6SM): Likewise.
1207 (ARM_ARCH_V6SM): Likewise.
1208
60e5ef9f
MGD		 12092010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1210
1211 * arm.h (ARM_EXT_MP): Add.
1212 (ARM_ARCH_V7A_MP): Likewise.
1213
73a63ccf
MF		 12142010-09-22 Mike Frysinger <vapier@gentoo.org>
1215
1216 * bfin.h: Declare pseudoChr structs/defines.
1217
ee99860a
MF		 12182010-09-21 Mike Frysinger <vapier@gentoo.org>
1219
1220 * bfin.h: Strip trailing whitespace.
1221
f9c7014e
DD		 12222010-07-29 DJ Delorie <dj@redhat.com>
1223
1224 * rx.h (RX_Operand_Type): Add TwoReg.
1225 (RX_Opcode_ID): Remove ediv and ediv2.
1226
93378652
DD		 12272010-07-27 DJ Delorie <dj@redhat.com>
1228
1229 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1230
1cd986c5
NC		 12312010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1232 Ina Pandit <ina.pandit@kpitcummins.com>
1233
1234 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1235 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1236 PROCESSOR_V850E2_ALL.
1237 Remove PROCESSOR_V850EA support.
1238 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1239 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1240 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1241 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1242 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1243 V850_OPERAND_PERCENT.
1244 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1245 V850_NOT_R0.
1246 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1247 and V850E_PUSH_POP
1248
9a2c7088
MR		 12492010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1250
1251 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1252 (MIPS16_INSN_BRANCH): Rename to...
1253 (MIPS16_INSN_COND_BRANCH): ... this.
1254
bdc70b4a
AM		 12552010-07-03 Alan Modra <amodra@gmail.com>
1256
1257 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1258 Renumber other PPC_OPCODE defines.
1259
f2bae120
AM		 12602010-07-03 Alan Modra <amodra@gmail.com>
1261
1262 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1263
360cfc9c
AM		 12642010-06-29 Alan Modra <amodra@gmail.com>
1265
1266 * maxq.h: Delete file.
1267
e01d869a
AM		 12682010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1269
1270 * ppc.h (PPC_OPCODE_E500): Define.
1271
f79e2745
CM		 12722010-05-26 Catherine Moore <clm@codesourcery.com>
1273
1274 * opcode/mips.h (INSN_MIPS16): Remove.
1275
2462afa1
JM		 12762010-04-21 Joseph Myers <joseph@codesourcery.com>
1277
1278 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1279
e4e42b45
NC		 12802010-04-15 Nick Clifton <nickc@redhat.com>
1281
1282 * alpha.h: Update copyright notice to use GPLv3.
1283 * arc.h: Likewise.
1284 * arm.h: Likewise.
1285 * avr.h: Likewise.
1286 * bfin.h: Likewise.
1287 * cgen.h: Likewise.
1288 * convex.h: Likewise.
1289 * cr16.h: Likewise.
1290 * cris.h: Likewise.
1291 * crx.h: Likewise.
1292 * d10v.h: Likewise.
1293 * d30v.h: Likewise.
1294 * dlx.h: Likewise.
1295 * h8300.h: Likewise.
1296 * hppa.h: Likewise.
1297 * i370.h: Likewise.
1298 * i386.h: Likewise.
1299 * i860.h: Likewise.
1300 * i960.h: Likewise.
1301 * ia64.h: Likewise.
1302 * m68hc11.h: Likewise.
1303 * m68k.h: Likewise.
1304 * m88k.h: Likewise.
1305 * maxq.h: Likewise.
1306 * mips.h: Likewise.
1307 * mmix.h: Likewise.
1308 * mn10200.h: Likewise.
1309 * mn10300.h: Likewise.
1310 * msp430.h: Likewise.
1311 * np1.h: Likewise.
1312 * ns32k.h: Likewise.
1313 * or32.h: Likewise.
1314 * pdp11.h: Likewise.
1315 * pj.h: Likewise.
1316 * pn.h: Likewise.
1317 * ppc.h: Likewise.
1318 * pyr.h: Likewise.
1319 * rx.h: Likewise.
1320 * s390.h: Likewise.
1321 * score-datadep.h: Likewise.
1322 * score-inst.h: Likewise.
1323 * sparc.h: Likewise.
1324 * spu-insns.h: Likewise.
1325 * spu.h: Likewise.
1326 * tic30.h: Likewise.
1327 * tic4x.h: Likewise.
1328 * tic54x.h: Likewise.
1329 * tic80.h: Likewise.
1330 * v850.h: Likewise.
1331 * vax.h: Likewise.
1332
40b36596
JM		 13332010-03-25 Joseph Myers <joseph@codesourcery.com>
1334
1335 * tic6x-control-registers.h, tic6x-insn-formats.h,
1336 tic6x-opcode-table.h, tic6x.h: New.
1337
c67a084a
NC		 13382010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1339
1340 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1341
466ef64f
AM		 13422010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1343
1344 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1345
1319d143
L		 13462010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1347
1348 * ia64.h (ia64_find_opcode): Remove argument name.
1349 (ia64_find_next_opcode): Likewise.
1350 (ia64_dis_opcode): Likewise.
1351 (ia64_free_opcode): Likewise.
1352 (ia64_find_dependency): Likewise.
1353
1fbb9298
DE		 13542009-11-22 Doug Evans <dje@sebabeach.org>
1355
1356 * cgen.h: Include bfd_stdint.h.
1357 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1358
ada65aa3
PB		 13592009-11-18 Paul Brook <paul@codesourcery.com>
1360
1361 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1362
9e3c6df6
PB		 13632009-11-17 Paul Brook <paul@codesourcery.com>
1364 Daniel Jacobowitz <dan@codesourcery.com>
1365
1366 * arm.h (ARM_EXT_V6_DSP): Define.
1367 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1368 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1369
0d734b5d
DD		 13702009-11-04 DJ Delorie <dj@redhat.com>
1371
1372 * rx.h (rx_decode_opcode) (mvtipl): Add.
1373 (mvtcp, mvfcp, opecp): Remove.
1374
62f3b8c8
PB		 13752009-11-02 Paul Brook <paul@codesourcery.com>
1376
1377 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1378 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1379 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1380 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1381 FPU_ARCH_NEON_VFP_V4): Define.
1382
ac1e9eca
DE		 13832009-10-23 Doug Evans <dje@sebabeach.org>
1384
1385 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1386 * cgen.h: Update. Improve multi-inclusion macro name.
1387
9fe54b1c
PB		 13882009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1389
1390 * ppc.h (PPC_OPCODE_476): Define.
1391
634b50f2
PB		 13922009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1393
1394 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1395
c7927a3c
NC		 13962009-09-29 DJ Delorie <dj@redhat.com>
1397
1398 * rx.h: New file.
1399
b961e85b
AM		 14002009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1401
1402 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1403
e0d602ec
BE		 14042009-09-21 Ben Elliston <bje@au.ibm.com>
1405
1406 * ppc.h (PPC_OPCODE_PPCA2): New.
1407
96d56e9f
NC		 14082009-09-05 Martin Thuresson <martin@mtme.org>
1409
1410 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1411
d3ce72d0
NC		 14122009-08-29 Martin Thuresson <martin@mtme.org>
1413
1414 * tic30.h (template): Rename type template to
1415 insn_template. Updated code to use new name.
1416 * tic54x.h (template): Rename type template to
1417 insn_template.
1418
824b28db
NH		 14192009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1420
1421 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1422
f865a31d
AG		 14232009-06-11 Anthony Green <green@moxielogic.com>
1424
1425 * moxie.h (MOXIE_F3_PCREL): Define.
1426 (moxie_form3_opc_info): Grow.
1427
0e7c7f11
AG		 14282009-06-06 Anthony Green <green@moxielogic.com>
1429
1430 * moxie.h (MOXIE_F1_M): Define.
1431
20135e4c
NC		 14322009-04-15 Anthony Green <green@moxielogic.com>
1433
1434 * moxie.h: Created.
1435
bcb012d3
DD		 14362009-04-06 DJ Delorie <dj@redhat.com>
1437
1438 * h8300.h: Add relaxation attributes to MOVA opcodes.
1439
69fe9ce5
AM		 14402009-03-10 Alan Modra <amodra@bigpond.net.au>
1441
1442 * ppc.h (ppc_parse_cpu): Declare.
1443
c3b7224a
NC		 14442009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1445
1446 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1447 and _IMM11 for mbitclr and mbitset.
1448 * score-datadep.h: Update dependency information.
1449
066be9f7
PB		 14502009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1451
1452 * ppc.h (PPC_OPCODE_POWER7): New.
1453
fedc618e
DE		 14542009-02-06 Doug Evans <dje@google.com>
1455
1456 * i386.h: Add comment regarding sse* insns and prefixes.
1457
52b6b6b9
JM		 14582009-02-03 Sandip Matte <sandip@rmicorp.com>
1459
1460 * mips.h (INSN_XLR): Define.
1461 (INSN_CHIP_MASK): Update.
1462 (CPU_XLR): Define.
1463 (OPCODE_IS_MEMBER): Update.
1464 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1465
35669430
DE		 14662009-01-28 Doug Evans <dje@google.com>
1467
1468 * opcode/i386.h: Add multiple inclusion protection.
1469 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1470 (EDI_REG_NUM): New macros.
1471 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1472 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1473 (REX_PREFIX_P): New macro.
35669430 1474
1cb0a767
PB		 14752009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1476
1477 * ppc.h (struct powerpc_opcode): New field "deprecated".
1478 (PPC_OPCODE_NOPOWER4): Delete.
1479
3aa3176b
TS		 14802008-11-28 Joshua Kinard <kumba@gentoo.org>
1481
1482 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1483 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1484
8e79c3df
CM		 14852008-11-18 Catherine Moore <clm@codesourcery.com>
1486
1487 * arm.h (FPU_NEON_FP16): New.
1488 (FPU_ARCH_NEON_FP16): New.
1489
de9a3e51
CF		 14902008-11-06 Chao-ying Fu <fu@mips.com>
1491
1492 * mips.h: Doucument '1' for 5-bit sync type.
1493
1ca35711
L		 14942008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1495
1496 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1497 IA64_RS_CR.
1498
9b4e5766
PB		 14992008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1500
1501 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1502
081ba1b3
AM		 15032008-07-30 Michael J. Eager <eager@eagercon.com>
1504
1505 * ppc.h (PPC_OPCODE_405): Define.
1506 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1507
fa452fa6
PB		 15082008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1509
1510 * ppc.h (ppc_cpu_t): New typedef.
1511 (struct powerpc_opcode <flags>): Use it.
1512 (struct powerpc_operand <insert, extract>): Likewise.
1513 (struct powerpc_macro <flags>): Likewise.
1514
bb35fb24
NC		 15152008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1516
1517 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1518 Update comment before MIPS16 field descriptors to mention MIPS16.
1519 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1520 BBIT.
1521 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1522 New bit masks and shift counts for cins and exts.
1523
dd3cbb7e
NC		 1524 * mips.h: Document new field descriptors +Q.
1525 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1526
d0799671
AN		 15272008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1528
9aff4b7a 1529 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1530 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1531
19a6653c
AM		 15322008-04-14 Edmar Wienskoski <edmar@freescale.com>
1533
1534 * ppc.h: (PPC_OPCODE_E500MC): New.
1535
c0f3af97
L		 15362008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1537
1538 * i386.h (MAX_OPERANDS): Set to 5.
1539 (MAX_MNEM_SIZE): Changed to 20.
1540
e210c36b
NC		 15412008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1542
1543 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1544
b1cc4aeb
PB		 15452008-03-09 Paul Brook <paul@codesourcery.com>
1546
1547 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1548
7e806470
PB		 15492008-03-04 Paul Brook <paul@codesourcery.com>
1550
1551 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1552 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1553 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1554
7b2185f9 15552008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1556 Nick Clifton <nickc@redhat.com>
1557
1558 PR 3134
1559 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1560 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1561 set.
af7329f0 1562
796d5313
NC		 15632008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1564
1565 * cr16.h (cr16_num_optab): Declared.
1566
d669d37f
NC		 15672008-02-14 Hakan Ardo <hakan@debian.org>
1568
1569 PR gas/2626
1570 * avr.h (AVR_ISA_2xxe): Define.
1571
e6429699
AN		 15722008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1573
1574 * mips.h: Update copyright.
1575 (INSN_CHIP_MASK): New macro.
1576 (INSN_OCTEON): New macro.
1577 (CPU_OCTEON): New macro.
1578 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1579
e210c36b
NC		 15802008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1581
1582 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1583
15842008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1585
1586 * avr.h (AVR_ISA_USB162): Add new opcode set.
1587 (AVR_ISA_AVR3): Likewise.
1588
350cc38d
MS		 15892007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1590
1591 * mips.h (INSN_LOONGSON_2E): New.
1592 (INSN_LOONGSON_2F): New.
1593 (CPU_LOONGSON_2E): New.
1594 (CPU_LOONGSON_2F): New.
1595 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1596
56950294
MS		 15972007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1598
1599 * mips.h (INSN_ISA*): Redefine certain values as an
1600 enumeration. Update comments.
1601 (mips_isa_table): New.
1602 (ISA_MIPS*): Redefine to match enumeration.
1603 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1604 values.
1605
c3d65c1c
BE		 16062007-08-08 Ben Elliston <bje@au.ibm.com>
1607
1608 * ppc.h (PPC_OPCODE_PPCPS): New.
1609
0fdaa005
L		 16102007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1611
1612 * m68k.h: Document j K & E.
1613
16142007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1615
1616 * cr16.h: New file for CR16 target.
1617
3896c469
AM		 16182007-05-02 Alan Modra <amodra@bigpond.net.au>
1619
1620 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1621
9a2e615a
NS		 16222007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1623
1624 * m68k.h (mcfisa_c): New.
1625 (mcfusp, mcf_mask): Adjust.
1626
b84bf58a
AM		 16272007-04-20 Alan Modra <amodra@bigpond.net.au>
1628
1629 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1630 (num_powerpc_operands): Declare.
1631 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1632 (PPC_OPERAND_PLUS1): Define.
1633
831480e9 16342007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1635
1636 * i386.h (REX_MODE64): Renamed to ...
1637 (REX_W): This.
1638 (REX_EXTX): Renamed to ...
1639 (REX_R): This.
1640 (REX_EXTY): Renamed to ...
1641 (REX_X): This.
1642 (REX_EXTZ): Renamed to ...
1643 (REX_B): This.
1644
0b1cf022
L		 16452007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1646
1647 * i386.h: Add entries from config/tc-i386.h and move tables
1648 to opcodes/i386-opc.h.
1649
d796c0ad
L		 16502007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1651
1652 * i386.h (FloatDR): Removed.
1653 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1654
30ac7323
AM		 16552007-03-01 Alan Modra <amodra@bigpond.net.au>
1656
1657 * spu-insns.h: Add soma double-float insns.
1658
8b082fb1 16592007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1660 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1661
1662 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1663 (INSN_DSPR2): Add flag for DSP R2 instructions.
1664 (M_BALIGN): New macro.
1665
4eed87de
AM		 16662007-02-14 Alan Modra <amodra@bigpond.net.au>
1667
1668 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1669 and Seg3ShortFrom with Shortform.
1670
fda592e8
L		 16712007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1672
1673 PR gas/4027
1674 * i386.h (i386_optab): Put the real "test" before the pseudo
1675 one.
1676
3bdcfdf4
KH		 16772007-01-08 Kazu Hirata <kazu@codesourcery.com>
1678
1679 * m68k.h (m68010up): OR fido_a.
1680
9840d27e
KH		 16812006-12-25 Kazu Hirata <kazu@codesourcery.com>
1682
1683 * m68k.h (fido_a): New.
1684
c629cdac
KH		 16852006-12-24 Kazu Hirata <kazu@codesourcery.com>
1686
1687 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1688 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1689 values.
1690
b7d9ef37
L		 16912006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1692
1693 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1694
b138abaa
NC		 16952006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1696
1697 * score-inst.h (enum score_insn_type): Add Insn_internal.
1698
e9f53129
AM		 16992006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1700 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1701 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1702 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1703 Alan Modra <amodra@bigpond.net.au>
1704
1705 * spu-insns.h: New file.
1706 * spu.h: New file.
1707
ede602d7
AM		 17082006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1709
1710 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1711
7918206c
MM		 17122006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1713
e4e42b45 1714 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1715 in amdfam10 architecture.
1716
ef05d495
L		 17172006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1718
1719 * i386.h: Replace CpuMNI with CpuSSSE3.
1720
2d447fca 17212006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1722 Joseph Myers <joseph@codesourcery.com>
1723 Ian Lance Taylor <ian@wasabisystems.com>
1724 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1725
1726 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1727
1c0d3aa6
NC		 17282006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1729
1730 * score-datadep.h: New file.
1731 * score-inst.h: New file.
1732
c2f0420e
L		 17332006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1734
1735 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1736 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1737 movdq2q and movq2dq.
1738
050dfa73
MM		 17392006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1740 Michael Meissner <michael.meissner@amd.com>
1741
1742 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1743
15965411
L		 17442006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1745
1746 * i386.h (i386_optab): Add "nop" with memory reference.
1747
46e883c5
L		 17482006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1749
1750 * i386.h (i386_optab): Update comment for 64bit NOP.
1751
9622b051
AM		 17522006-06-06 Ben Elliston <bje@au.ibm.com>
1753 Anton Blanchard <anton@samba.org>
1754
1755 * ppc.h (PPC_OPCODE_POWER6): Define.
1756 Adjust whitespace.
1757
a9e24354
TS		 17582006-06-05 Thiemo Seufer <ths@mips.com>
1759
e4e42b45 1760 * mips.h: Improve description of MT flags.
a9e24354 1761
a596001e
RS		 17622006-05-25 Richard Sandiford <richard@codesourcery.com>
1763
1764 * m68k.h (mcf_mask): Define.
1765
d43b4baf 17662006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1767 David Ung <davidu@mips.com>
d43b4baf
TS		 1768
1769 * mips.h (enum): Add macro M_CACHE_AB.
1770
39a7806d 17712006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1772 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1773 David Ung <davidu@mips.com>
1774
1775 * mips.h: Add INSN_SMARTMIPS define.
1776
9bcd4f99 17772006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1778 David Ung <davidu@mips.com>
9bcd4f99
TS		 1779
1780 * mips.h: Defines udi bits and masks. Add description of
1781 characters which may appear in the args field of udi
1782 instructions.
1783
ef0ee844
TS		 17842006-04-26 Thiemo Seufer <ths@networkno.de>
1785
1786 * mips.h: Improve comments describing the bitfield instruction
1787 fields.
1788
f7675147
L		 17892006-04-26 Julian Brown <julian@codesourcery.com>
1790
1791 * arm.h (FPU_VFP_EXT_V3): Define constant.
1792 (FPU_NEON_EXT_V1): Likewise.
1793 (FPU_VFP_HARD): Update.
1794 (FPU_VFP_V3): Define macro.
1795 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1796
ef0ee844 17972006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1798
1799 * avr.h (AVR_ISA_PWMx): New.
1800
2da12c60
NS		 18012006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1802
1803 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1804 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1805 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1806 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1807 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1808
0715c387
PB		 18092006-03-10 Paul Brook <paul@codesourcery.com>
1810
1811 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1812
34bdd094
DA		 18132006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1814
1815 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1816 first. Correct mask of bb "B" opcode.
1817
331d2d0d
L		 18182006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1819
1820 * i386.h (i386_optab): Support Intel Merom New Instructions.
1821
62b3e311
PB		 18222006-02-24 Paul Brook <paul@codesourcery.com>
1823
1824 * arm.h: Add V7 feature bits.
1825
59cf82fe
L		 18262006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1827
1828 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1829
e74cfd16
PB		 18302006-01-31 Paul Brook <paul@codesourcery.com>
1831 Richard Earnshaw <rearnsha@arm.com>
1832
1833 * arm.h: Use ARM_CPU_FEATURE.
1834 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1835 (arm_feature_set): Change to a structure.
1836 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1837 ARM_FEATURE): New macros.
1838
5b3f8a92
HPN		 18392005-12-07 Hans-Peter Nilsson <hp@axis.com>
1840
1841 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1842 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1843 (ADD_PC_INCR_OPCODE): Don't define.
1844
cb712a9e
L		 18452005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1846
1847 PR gas/1874
1848 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1849
0499d65b
TS		 18502005-11-14 David Ung <davidu@mips.com>
1851
1852 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1853 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1854 save/restore encoding of the args field.
1855
ea5ca089
DB		 18562005-10-28 Dave Brolley <brolley@redhat.com>
1857
1858 Contribute the following changes:
1859 2005-02-16 Dave Brolley <brolley@redhat.com>
1860
1861 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1862 cgen_isa_mask_* to cgen_bitset_*.
1863 * cgen.h: Likewise.
1864
16175d96
DB		 1865 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1866
1867 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1868 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1869 (CGEN_CPU_TABLE): Make isas a ponter.
1870
1871 2003-09-29 Dave Brolley <brolley@redhat.com>
1872
1873 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1874 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1875 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1876
1877 2002-12-13 Dave Brolley <brolley@redhat.com>
1878
1879 * cgen.h (symcat.h): #include it.
1880 (cgen-bitset.h): #include it.
1881 (CGEN_ATTR_VALUE_TYPE): Now a union.
1882 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1883 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1884 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1885 * cgen-bitset.h: New file.
1886
3c9b82ba
NC		 18872005-09-30 Catherine Moore <clm@cm00re.com>
1888
1889 * bfin.h: New file.
1890
6a2375c6
JB		 18912005-10-24 Jan Beulich <jbeulich@novell.com>
1892
1893 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1894 indirect operands.
1895
c06a12f8
DA		 18962005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1897
1898 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1899 Add FLAG_STRICT to pa10 ftest opcode.
1900
4d443107
DA		 19012005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1902
1903 * hppa.h (pa_opcodes): Remove lha entries.
1904
f0a3b40f
DA		 19052005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1906
1907 * hppa.h (FLAG_STRICT): Revise comment.
1908 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1909 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1910 entries for "fdc".
1911
e210c36b
NC		 19122005-09-30 Catherine Moore <clm@cm00re.com>
1913
1914 * bfin.h: New file.
1915
1b7e1362
DA		 19162005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1917
1918 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1919
089b39de
CF		 19202005-09-06 Chao-ying Fu <fu@mips.com>
1921
1922 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1923 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1924 define.
1925 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1926 (INSN_ASE_MASK): Update to include INSN_MT.
1927 (INSN_MT): New define for MT ASE.
1928
93c34b9b
CF		 19292005-08-25 Chao-ying Fu <fu@mips.com>
1930
1931 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1932 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1933 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1934 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1935 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1936 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1937 instructions.
1938 (INSN_DSP): New define for DSP ASE.
1939
848cf006
AM		 19402005-08-18 Alan Modra <amodra@bigpond.net.au>
1941
1942 * a29k.h: Delete.
1943
36ae0db3
DJ		 19442005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1945
1946 * ppc.h (PPC_OPCODE_E300): Define.
1947
8c929562
MS		 19482005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1949
1950 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1951
f7b8cccc
DA		 19522005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1953
1954 PR gas/336
1955 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1956 and pitlb.
1957
8b5328ac
JB		 19582005-07-27 Jan Beulich <jbeulich@novell.com>
1959
1960 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1961 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1962 Add movq-s as 64-bit variants of movd-s.
1963
f417d200
DA		 19642005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1965
18b3bdfc
DA		 1966 * hppa.h: Fix punctuation in comment.
1967
f417d200
DA		 1968 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1969 implicit space-register addressing. Set space-register bits on opcodes
1970 using implicit space-register addressing. Add various missing pa20
1971 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1972 space-register addressing. Use "fE" instead of "fe" in various
1973 fstw opcodes.
1974
9a145ce6
JB		 19752005-07-18 Jan Beulich <jbeulich@novell.com>
1976
1977 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1978
90700ea2
L		 19792007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1980
1981 * i386.h (i386_optab): Support Intel VMX Instructions.
1982
48f130a8
DA		 19832005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1984
1985 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1986
30123838
JB		 19872005-07-05 Jan Beulich <jbeulich@novell.com>
1988
1989 * i386.h (i386_optab): Add new insns.
1990
47b0e7ad
NC		 19912005-07-01 Nick Clifton <nickc@redhat.com>
1992
1993 * sparc.h: Add typedefs to structure declarations.
1994
b300c311
L		 19952005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1996
1997 PR 1013
1998 * i386.h (i386_optab): Update comments for 64bit addressing on
1999 mov. Allow 64bit addressing for mov and movq.
2000
2db495be
DA		 20012005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2002
2003 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2004 respectively, in various floating-point load and store patterns.
2005
caa05036
DA		 20062005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2007
2008 * hppa.h (FLAG_STRICT): Correct comment.
2009 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2010 PA 2.0 mneumonics when equivalent. Entries with cache control
2011 completers now require PA 1.1. Adjust whitespace.
2012
f4411256
AM		 20132005-05-19 Anton Blanchard <anton@samba.org>
2014
2015 * ppc.h (PPC_OPCODE_POWER5): Define.
2016
e172dbf8
NC		 20172005-05-10 Nick Clifton <nickc@redhat.com>
2018
2019 * Update the address and phone number of the FSF organization in
2020 the GPL notices in the following files:
2021 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2022 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2023 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2024 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2025 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2026 tic54x.h, tic80.h, v850.h, vax.h
2027
e44823cf
JB		 20282005-05-09 Jan Beulich <jbeulich@novell.com>
2029
2030 * i386.h (i386_optab): Add ht and hnt.
2031
791fe849
MK		 20322005-04-18 Mark Kettenis <kettenis@gnu.org>
2033
2034 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2035 Add xcrypt-ctr. Provide aliases without hyphens.
2036
faa7ef87
L		 20372005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2038
a63027e5
L		 2039 Moved from ../ChangeLog
2040
faa7ef87
L		 2041 2005-04-12 Paul Brook <paul@codesourcery.com>
2042 * m88k.h: Rename psr macros to avoid conflicts.
2043
2044 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2045 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2046 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2047 and ARM_ARCH_V6ZKT2.
2048
2049 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2050 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2051 Remove redundant instruction types.
2052 (struct argument): X_op - new field.
2053 (struct cst4_entry): Remove.
2054 (no_op_insn): Declare.
2055
2056 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2057 * crx.h (enum argtype): Rename types, remove unused types.
2058
2059 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2060 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2061 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2062 (enum operand_type): Rearrange operands, edit comments.
2063 replace us<N> with ui<N> for unsigned immediate.
2064 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2065 displacements (respectively).
2066 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2067 (instruction type): Add NO_TYPE_INS.
2068 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2069 (operand_entry): New field - 'flags'.
2070 (operand flags): New.
2071
2072 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2073 * crx.h (operand_type): Remove redundant types i3, i4,
2074 i5, i8, i12.
2075 Add new unsigned immediate types us3, us4, us5, us16.
2076
bc4bd9ab
MK		 20772005-04-12 Mark Kettenis <kettenis@gnu.org>
2078
2079 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2080 adjust them accordingly.
2081
373ff435
JB		 20822005-04-01 Jan Beulich <jbeulich@novell.com>
2083
2084 * i386.h (i386_optab): Add rdtscp.
2085
4cc91dba
L		 20862005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2087
2088 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2089 between memory and segment register. Allow movq for moving between
2090 general-purpose register and segment register.
4cc91dba 2091
9ae09ff9
JB		 20922005-02-09 Jan Beulich <jbeulich@novell.com>
2093
2094 PR gas/707
2095 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2096 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2097 fnstsw.
2098
638e7a64
NS		 20992006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2100
2101 * m68k.h (m68008, m68ec030, m68882): Remove.
2102 (m68k_mask): New.
2103 (cpu_m68k, cpu_cf): New.
2104 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2105 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2106
90219bd0
AO		 21072005-01-25 Alexandre Oliva <aoliva@redhat.com>
2108
2109 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2110 * cgen.h (enum cgen_parse_operand_type): Add
2111 CGEN_PARSE_OPERAND_SYMBOLIC.
2112
239cb185
FF		 21132005-01-21 Fred Fish <fnf@specifixinc.com>
2114
2115 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2116 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2117 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2118
dc9a9f39
FF		 21192005-01-19 Fred Fish <fnf@specifixinc.com>
2120
2121 * mips.h (struct mips_opcode): Add new pinfo2 member.
2122 (INSN_ALIAS): New define for opcode table entries that are
2123 specific instances of another entry, such as 'move' for an 'or'
2124 with a zero operand.
2125 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2126 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2127
98e7aba8
ILT		 21282004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2129
2130 * mips.h (CPU_RM9000): Define.
2131 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2132
37edbb65
JB		 21332004-11-25 Jan Beulich <jbeulich@novell.com>
2134
2135 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2136 to/from test registers are illegal in 64-bit mode. Add missing
2137 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2138 (previously one had to explicitly encode a rex64 prefix). Re-enable
2139 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2140 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2141
21422004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2143
2144 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2145 available only with SSE2. Change the MMX additions introduced by SSE
2146 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2147 instructions by their now designated identifier (since combining i686
2148 and 3DNow! does not really imply 3DNow!A).
2149
f5c7edf4
AM		 21502004-11-19 Alan Modra <amodra@bigpond.net.au>
2151
2152 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2153 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2154
7499d566
NC		 21552004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2156 Vineet Sharma <vineets@noida.hcltech.com>
2157
2158 * maxq.h: New file: Disassembly information for the maxq port.
2159
bcb9eebe
L		 21602004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2161
2162 * i386.h (i386_optab): Put back "movzb".
2163
94bb3d38
HPN		 21642004-11-04 Hans-Peter Nilsson <hp@axis.com>
2165
2166 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2167 comments. Remove member cris_ver_sim. Add members
2168 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2169 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2170 (struct cris_support_reg, struct cris_cond15): New types.
2171 (cris_conds15): Declare.
2172 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2173 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2174 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2175 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2176 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2177 SIZE_FIELD_UNSIGNED.
2178
37edbb65 21792004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2180
2181 * i386.h (sldx_Suf): Remove.
2182 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2183 (q_FP): Define, implying no REX64.
2184 (x_FP, sl_FP): Imply FloatMF.
2185 (i386_optab): Split reg and mem forms of moving from segment registers
2186 so that the memory forms can ignore the 16-/32-bit operand size
2187 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2188 all non-floating-point instructions. Unite 32- and 64-bit forms of
2189 movsx, movzx, and movd. Adjust floating point operations for the above
2190 changes to the *FP macros. Add DefaultSize to floating point control
2191 insns operating on larger memory ranges. Remove left over comments
2192 hinting at certain insns being Intel-syntax ones where the ones
2193 actually meant are already gone.
2194
48c9f030
NC		 21952004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2196
2197 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2198 instruction type.
2199
0dd132b6
NC		 22002004-09-30 Paul Brook <paul@codesourcery.com>
2201
2202 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2203 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2204
23794b24
MM		 22052004-09-11 Theodore A. Roth <troth@openavr.org>
2206
2207 * avr.h: Add support for
2208 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2209
2a309db0
AM		 22102004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2211
2212 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2213
b18c562e
NC		 22142004-08-24 Dmitry Diky <diwil@spec.ru>
2215
2216 * msp430.h (msp430_opc): Add new instructions.
2217 (msp430_rcodes): Declare new instructions.
2218 (msp430_hcodes): Likewise..
2219
45d313cd
NC		 22202004-08-13 Nick Clifton <nickc@redhat.com>
2221
2222 PR/301
2223 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2224 processors.
2225
30d1c836
ML		 22262004-08-30 Michal Ludvig <mludvig@suse.cz>
2227
2228 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2229
9a45f1c2
L		 22302004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2231
2232 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2233
543613e9
NC		 22342004-07-21 Jan Beulich <jbeulich@novell.com>
2235
2236 * i386.h: Adjust instruction descriptions to better match the
2237 specification.
2238
b781e558
RE		 22392004-07-16 Richard Earnshaw <rearnsha@arm.com>
2240
2241 * arm.h: Remove all old content. Replace with architecture defines
2242 from gas/config/tc-arm.c.
2243
8577e690
AS		 22442004-07-09 Andreas Schwab <schwab@suse.de>
2245
2246 * m68k.h: Fix comment.
2247
1fe1f39c
NC		 22482004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2249
2250 * crx.h: New file.
2251
1d9f512f
AM		 22522004-06-24 Alan Modra <amodra@bigpond.net.au>
2253
2254 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2255
be8c092b
NC		 22562004-05-24 Peter Barada <peter@the-baradas.com>
2257
2258 * m68k.h: Add 'size' to m68k_opcode.
2259
6b6e92f4
NC		 22602004-05-05 Peter Barada <peter@the-baradas.com>
2261
2262 * m68k.h: Switch from ColdFire chip name to core variant.
2263
22642004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2265
2266 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2267 descriptions for new EMAC cases.
2268 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2269 handle Motorola MAC syntax.
2270 Allow disassembly of ColdFire V4e object files.
2271
fdd12ef3
AM		 22722004-03-16 Alan Modra <amodra@bigpond.net.au>
2273
2274 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2275
3922a64c
L		 22762004-03-12 Jakub Jelinek <jakub@redhat.com>
2277
2278 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2279
1f45d988
ML		 22802004-03-12 Michal Ludvig <mludvig@suse.cz>
2281
2282 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2283
0f10071e
ML		 22842004-03-12 Michal Ludvig <mludvig@suse.cz>
2285
2286 * i386.h (i386_optab): Added xstore/xcrypt insns.
2287
3255318a
NC		 22882004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2289
2290 * h8300.h (32bit ldc/stc): Add relaxing support.
2291
ca9a79a1 22922004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2293
ca9a79a1
NC		 2294 * h8300.h (BITOP): Pass MEMRELAX flag.
2295
875a0b14
NC		 22962004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2297
2298 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2299 except for the H8S.
252b5132 2300
c9e214e5 2301For older changes see ChangeLog-9103
252b5132 2302\f
b90efa5b 2303Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2304
2305Copying and distribution of this file, with or without modification,
2306are permitted in any medium without royalty provided the copyright
2307notice and this notice are preserved.
2308
252b5132 2309Local Variables:
c9e214e5
AM		 2310mode: change-log
2311left-margin: 8
2312fill-column: 74
252b5132
RH		 2313version-control: never
2314End:
GDB Binutils - Deliverables
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