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[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
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f33026a9
MW		 12015-07-20 Matthew Wahab <matthew.wahab@arm.com>
2
3 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
4 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
5 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
6 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
7
ef5a96d5
AM		 82015-07-03 Alan Modra <amodra@gmail.com>
9
10 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
11
c8c8175b
SL		 122015-07-01 Sandra Loosemore <sandra@codesourcery.com>
13 Cesar Philippidis <cesar@codesourcery.com>
14
15 * nios2.h (enum iw_format_type): Add R2 formats.
16 (enum overflow_type): Add signed_immed12_overflow and
17 enumeration_overflow for R2.
18 (struct nios2_opcode): Document new argument letters for R2.
19 (REG_3BIT, REG_LDWM, REG_POP): Define.
20 (includes): Include nios2r2.h.
21 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
22 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
23 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
24 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
25 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
26 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
27 Declare.
28 * nios2r2.h: New file.
29
11a0cf2e
PB		 302015-06-19 Peter Bergner <bergner@vnet.ibm.com>
31
32 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
33 (ppc_optional_operand_value): New inline function.
34
88f0ea34
MW		 352015-06-04 Matthew Wahab <matthew.wahab@arm.com>
36
37 * aarch64.h (AARCH64_V8_1): New.
38
a5932920
MW		 392015-06-03 Matthew Wahab <matthew.wahab@arm.com>
40
41 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
42 (ARM_ARCH_V8_1A): New.
43 (ARM_ARCH_V8_1A_FP): New.
44 (ARM_ARCH_V8_1A_SIMD): New.
45 (ARM_ARCH_V8_1A_CRYPTOV1): New.
46 (ARM_FEATURE_CORE): New.
47
ddfded2f
MW		 482015-06-02 Matthew Wahab <matthew.wahab@arm.com>
49
50 * arm.h (ARM_EXT2_PAN): New.
51 (ARM_FEATURE_CORE_HIGH): New.
52
1af1dd51
MW		 532015-06-02 Matthew Wahab <matthew.wahab@arm.com>
54
55 * arm.h (ARM_FEATURE_ALL): New.
56
9e1f0fa7
MW		 572015-06-02 Matthew Wahab <matthew.wahab@arm.com>
58
59 * aarch64.h (AARCH64_FEATURE_RDMA): New.
60
290806fd
MW		 612015-06-02 Matthew Wahab <matthew.wahab@arm.com>
62
63 * aarch64.h (AARCH64_FEATURE_LOR): New.
64
f21cce2c
MW		 652015-06-01 Matthew Wahab <matthew.wahab@arm.com>
66
67 * aarch64.h (AARCH64_FEATURE_PAN): New.
68 (aarch64_sys_reg_supported_p): Declare.
69 (aarch64_pstatefield_supported_p): Declare.
70
0952813b
DD		 712015-04-30 DJ Delorie <dj@redhat.com>
72
73 * rl78.h (RL78_Dis_Isa): New.
74 (rl78_decode_opcode): Add ISA parameter.
75
823d2571
TG		 762015-03-24 Terry Guo <terry.guo@arm.com>
77
78 * arm.h (arm_feature_set): Extended to provide more available bits.
79 (ARM_ANY): Updated to follow above new definition.
80 (ARM_CPU_HAS_FEATURE): Likewise.
81 (ARM_CPU_IS_ANY): Likewise.
82 (ARM_MERGE_FEATURE_SETS): Likewise.
83 (ARM_CLEAR_FEATURE): Likewise.
84 (ARM_FEATURE): Likewise.
85 (ARM_FEATURE_COPY): New macro.
86 (ARM_FEATURE_EQUAL): Likewise.
87 (ARM_FEATURE_ZERO): Likewise.
88 (ARM_FEATURE_CORE_EQUAL): Likewise.
89 (ARM_FEATURE_LOW): Likewise.
90 (ARM_FEATURE_CORE_LOW): Likewise.
91 (ARM_FEATURE_CORE_COPROC): Likewise.
92
f63c1776
PA		 932015-02-19 Pedro Alves <palves@redhat.com>
94
95 * cgen.h [__cplusplus]: Wrap in extern "C".
96 * msp430-decode.h [__cplusplus]: Likewise.
97 * nios2.h [__cplusplus]: Likewise.
98 * rl78.h [__cplusplus]: Likewise.
99 * rx.h [__cplusplus]: Likewise.
100 * tilegx.h [__cplusplus]: Likewise.
101
3f8107ab
AM		 1022015-01-28 James Bowman <james.bowman@ftdichip.com>
103
104 * ft32.h: New file.
105
1e2e8c52
AK		 1062015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
107
108 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
109
b90efa5b
AM		 1102015-01-01 Alan Modra <amodra@gmail.com>
111
112 Update year range in copyright notice of all files.
113
bffb6004
AG		 1142014-12-27 Anthony Green <green@moxielogic.com>
115
116 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
117 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
118
1945cfa5
EB		 1192014-12-06 Eric Botcazou <ebotcazou@adacore.com>
120
121 * visium.h: New file.
122
d306ce58
SL		 1232014-11-28 Sandra Loosemore <sandra@codesourcery.com>
124
125 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
126 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
127 (NIOS2_INSN_OPTARG): Renumber.
128
b4714c7c
SL		 1292014-11-06 Sandra Loosemore <sandra@codesourcery.com>
130
131 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
132 declaration. Fix obsolete comment.
133
96ba4233
SL		 1342014-10-23 Sandra Loosemore <sandra@codesourcery.com>
135
136 * nios2.h (enum iw_format_type): New.
137 (struct nios2_opcode): Update comments. Add size and format fields.
138 (NIOS2_INSN_OPTARG): New.
139 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
140 (struct nios2_reg): Add regtype field.
141 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
142 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
143 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
144 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
145 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
146 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
147 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
148 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
149 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
150 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
151 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
152 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
153 (OP_MASK_OP, OP_SH_OP): Delete.
154 (OP_MASK_IOP, OP_SH_IOP): Delete.
155 (OP_MASK_IRD, OP_SH_IRD): Delete.
156 (OP_MASK_IRT, OP_SH_IRT): Delete.
157 (OP_MASK_IRS, OP_SH_IRS): Delete.
158 (OP_MASK_ROP, OP_SH_ROP): Delete.
159 (OP_MASK_RRD, OP_SH_RRD): Delete.
160 (OP_MASK_RRT, OP_SH_RRT): Delete.
161 (OP_MASK_RRS, OP_SH_RRS): Delete.
162 (OP_MASK_JOP, OP_SH_JOP): Delete.
163 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
164 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
165 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
166 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
167 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
168 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
169 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
170 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
171 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
172 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
173 (OP_MASK_<insn>, OP_MASK): Delete.
174 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
175 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
176 Include nios2r1.h to define new instruction opcode constants
177 and accessors.
178 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
179 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
180 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
181 (NUMOPCODES, NUMREGISTERS): Delete.
182 * nios2r1.h: New file.
183
0b6be415
JM		 1842014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
185
186 * sparc.h (HWCAP2_VIS3B): Documentation improved.
187
3d68f91c
JM		 1882014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
189
190 * sparc.h (sparc_opcode): new field `hwcaps2'.
191 (HWCAP2_FJATHPLUS): New define.
192 (HWCAP2_VIS3B): Likewise.
193 (HWCAP2_ADP): Likewise.
194 (HWCAP2_SPARC5): Likewise.
195 (HWCAP2_MWAIT): Likewise.
196 (HWCAP2_XMPMUL): Likewise.
197 (HWCAP2_XMONT): Likewise.
198 (HWCAP2_NSEC): Likewise.
199 (HWCAP2_FJATHHPC): Likewise.
200 (HWCAP2_FJDES): Likewise.
201 (HWCAP2_FJAES): Likewise.
202 Document the new operand kind `{', corresponding to the mcdper
203 ancillary state register.
204 Document the new operand kind }, which represents frsd floating
205 point registers (double precision) which must be the same than
206 frs1 in its containing instruction.
207
40c7a7cb
KLC		 2082014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
209
210 * nds32.h: Add new opcode declaration.
211
7361da2c
AB		 2122014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
213 Matthew Fortune <matthew.fortune@imgtec.com>
214
215 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
216 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
217 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
218 +I, +O, +R, +:, +\, +", +;
219 (mips_check_prev_operand): New struct.
220 (INSN2_FORBIDDEN_SLOT): New define.
221 (INSN_ISA32R6): New define.
222 (INSN_ISA64R6): New define.
223 (INSN_UPTO32R6): New define.
224 (INSN_UPTO64R6): New define.
225 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
226 (ISA_MIPS32R6): New define.
227 (ISA_MIPS64R6): New define.
228 (CPU_MIPS32R6): New define.
229 (CPU_MIPS64R6): New define.
230 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
231
ee804238
JW		 2322014-09-03 Jiong Wang <jiong.wang@arm.com>
233
234 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
235 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
236 (aarch64_insn_class): Add lse_atomic.
237 (F_LSE_SZ): New field added.
238 (opcode_has_special_coder): Recognize F_LSE_SZ.
239
5575639b
MR		 2402014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
241
242 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
243 over to `+J'.
244
43885403
MF		 2452014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
246
247 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
248 (INSN_LOAD_COPROC): New define.
249 (INSN_COPROC_MOVE_DELAY): Rename to...
250 (INSN_COPROC_MOVE): New define.
251
f36e8886
BS		 2522014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
253 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
254 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
255 Soundararajan <Sounderarajan.D@atmel.com>
256
257 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
258 (AVR_ISA_2xxxa): Define ISA without LPM.
259 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
260 Add doc for contraint used in 16 bit lds/sts.
261 Adjust ISA group for icall, ijmp, pop and push.
262 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
263
00b32ff2
NC		 2642014-05-19 Nick Clifton <nickc@redhat.com>
265
266 * msp430.h (struct msp430_operand_s): Add vshift field.
267
ae52f483
AB		 2682014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
269
270 * mips.h (INSN_ISA_MASK): Updated.
271 (INSN_ISA32R3): New define.
272 (INSN_ISA32R5): New define.
273 (INSN_ISA64R3): New define.
274 (INSN_ISA64R5): New define.
275 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
276 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
277 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
278 mips64r5.
279 (INSN_UPTO32R3): New define.
280 (INSN_UPTO32R5): New define.
281 (INSN_UPTO64R3): New define.
282 (INSN_UPTO64R5): New define.
283 (ISA_MIPS32R3): New define.
284 (ISA_MIPS32R5): New define.
285 (ISA_MIPS64R3): New define.
286 (ISA_MIPS64R5): New define.
287 (CPU_MIPS32R3): New define.
288 (CPU_MIPS32R5): New define.
289 (CPU_MIPS64R3): New define.
290 (CPU_MIPS64R5): New define.
291
3efe9ec5
RS		 2922014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
293
294 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
295
73589c9d
CS		 2962014-04-22 Christian Svensson <blue@cmd.nu>
297
298 * or32.h: Delete.
299
4b95cf5c
AM		 3002014-03-05 Alan Modra <amodra@gmail.com>
301
302 Update copyright years.
303
e269fea7
AB		 3042013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
305
306 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
307 microMIPS.
308
35c08157
KLC		 3092013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
310 Wei-Cheng Wang <cole945@gmail.com>
311
312 * nds32.h: New file for Andes NDS32.
313
594d8fa8
MF		 3142013-12-07 Mike Frysinger <vapier@gentoo.org>
315
316 * bfin.h: Remove +x file mode.
317
87b8eed7
YZ		 3182013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
319
320 * aarch64.h (aarch64_pstatefields): Change element type to
321 aarch64_sys_reg.
322
c9fb6e58
YZ		 3232013-11-18 Renlin Li <Renlin.Li@arm.com>
324
325 * arm.h (ARM_AEXT_V7VE): New define.
326 (ARM_ARCH_V7VE): New define.
327 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
328
a203d9b7
YZ		 3292013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
330
331 Revert
332
333 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
334
335 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
336 (aarch64_sys_reg_writeonly_p): Ditto.
337
75468c93
YZ		 3382013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
339
340 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
341 (aarch64_sys_reg_writeonly_p): Ditto.
342
49eec193
YZ		 3432013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
344
345 * aarch64.h (aarch64_sys_reg): New typedef.
346 (aarch64_sys_regs): Change to define with the new type.
347 (aarch64_sys_reg_deprecated_p): Declare.
348
68a64283
YZ		 3492013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
350
351 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
352 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
353
387a82f1
CF		 3542013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
355
356 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
357 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
358 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
359 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
360 For MIPS, update extension character sequences after +.
361 (ASE_MSA): New define.
362 (ASE_MSA64): New define.
363 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
364 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
365 For microMIPS, update extension character sequences after +.
366
9aff4b7a
NC		 3672013-08-23 Yuri Chornoivan <yurchor@ukr.net>
368
369 PR binutils/15834
370 * i960.h: Fix typos.
371
e423441d
RS		 3722013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
373
374 * mips.h: Remove references to "+I" and imm2_expr.
375
5e0dc5ba
RS		 3762013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
377
378 * mips.h (M_DEXT, M_DINS): Delete.
379
0f35dbc4
RS		 3802013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
381
382 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
383 (mips_optional_operand_p): New function.
384
14daeee3
RS		 3852013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
386 Richard Sandiford <rdsandiford@googlemail.com>
387
388 * mips.h: Document new VU0 operand characters.
389 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
390 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
391 (OP_REG_R5900_ACC): New mips_reg_operand_types.
392 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
393 (mips_vu0_channel_mask): Declare.
394
3ccad066
RS		 3952013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
396
397 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
398 (mips_int_operand_min, mips_int_operand_max): New functions.
399 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
400
fc76e730
RS		 4012013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
402
403 * mips.h (mips_decode_reg_operand): New function.
404 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
405 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
406 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
407 New macros.
408 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
409 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
410 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
411 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
412 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
413 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
414 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
415 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
416 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
417 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
418 macros to cover the gaps.
419 (INSN2_MOD_SP): Replace with...
420 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
421 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
422 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
423 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
424 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
425 Delete.
426
26545944
RS		 4272013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
428
429 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
430 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
431 (MIPS16_INSN_COND_BRANCH): Delete.
432
7e8b059b
L		 4332013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
434 Kirill Yukhin <kirill.yukhin@intel.com>
435 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
436
437 * i386.h (BND_PREFIX_OPCODE): New.
438
c3c07478
RS		 4392013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
440
441 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
442 OP_SAVE_RESTORE_LIST.
443 (decode_mips16_operand): Declare.
444
ab902481
RS		 4452013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
446
447 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
448 (mips_operand, mips_int_operand, mips_mapped_int_operand)
449 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
450 (mips_pcrel_operand): New structures.
451 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
452 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
453 (decode_mips_operand, decode_micromips_operand): Declare.
454
cc537e56
RS		 4552013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
456
457 * mips.h: Document MIPS16 "I" opcode.
458
f2ae14a1
RS		 4592013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
460
461 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
462 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
463 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
464 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
465 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
466 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
467 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
468 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
469 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
470 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
471 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
472 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
473 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
474 Rename to...
475 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
476 (M_USD_AB): ...these.
477
5c324c16
RS		 4782013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
479
480 * mips.h: Remove documentation of "[" and "]". Update documentation
481 of "k" and the MDMX formats.
482
23e69e47
RS		 4832013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
484
485 * mips.h: Update documentation of "+s" and "+S".
486
27c5c572
RS		 4872013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
488
489 * mips.h: Document "+i".
490
e76ff5ab
RS		 4912013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
492
493 * mips.h: Remove "mi" documentation. Update "mh" documentation.
494 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
495 Delete.
496 (INSN2_WRITE_GPR_MHI): Rename to...
497 (INSN2_WRITE_GPR_MH): ...this.
498
fa7616a4
RS		 4992013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
500
501 * mips.h: Remove documentation of "+D" and "+T".
502
18870af7
RS		 5032013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
504
505 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
506 Use "source" rather than "destination" for microMIPS "G".
507
833794fc
MR		 5082013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
509
510 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
511 values.
512
c3678916
RS		 5132013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
514
515 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
516
7f3c4072
CM		 5172013-06-17 Catherine Moore <clm@codesourcery.com>
518 Maciej W. Rozycki <macro@codesourcery.com>
519 Chao-Ying Fu <fu@mips.com>
520
521 * mips.h (OP_SH_EVAOFFSET): Define.
522 (OP_MASK_EVAOFFSET): Define.
523 (INSN_ASE_MASK): Delete.
524 (ASE_EVA): Define.
525 (M_CACHEE_AB, M_CACHEE_OB): New.
526 (M_LBE_OB, M_LBE_AB): New.
527 (M_LBUE_OB, M_LBUE_AB): New.
528 (M_LHE_OB, M_LHE_AB): New.
529 (M_LHUE_OB, M_LHUE_AB): New.
530 (M_LLE_AB, M_LLE_OB): New.
531 (M_LWE_OB, M_LWE_AB): New.
532 (M_LWLE_AB, M_LWLE_OB): New.
533 (M_LWRE_AB, M_LWRE_OB): New.
534 (M_PREFE_AB, M_PREFE_OB): New.
535 (M_SCE_AB, M_SCE_OB): New.
536 (M_SBE_OB, M_SBE_AB): New.
537 (M_SHE_OB, M_SHE_AB): New.
538 (M_SWE_OB, M_SWE_AB): New.
539 (M_SWLE_AB, M_SWLE_OB): New.
540 (M_SWRE_AB, M_SWRE_OB): New.
541 (MICROMIPSOP_SH_EVAOFFSET): Define.
542 (MICROMIPSOP_MASK_EVAOFFSET): Define.
543
0c8fe7cf
SL		 5442013-06-12 Sandra Loosemore <sandra@codesourcery.com>
545
546 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
547
c77c0862
RS		 5482013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
549
550 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
551
b015e599
AP		 5522013-05-09 Andrew Pinski <apinski@cavium.com>
553
554 * mips.h (OP_MASK_CODE10): Correct definition.
555 (OP_SH_CODE10): Likewise.
556 Add a comment that "+J" is used now for OP_*CODE10.
557 (INSN_ASE_MASK): Update.
558 (INSN_VIRT): New macro.
559 (INSN_VIRT64): New macro
560
13761a11
NC		 5612013-05-02 Nick Clifton <nickc@redhat.com>
562
563 * msp430.h: Add patterns for MSP430X instructions.
564
0afd1215
DM		 5652013-04-06 David S. Miller <davem@davemloft.net>
566
567 * sparc.h (F_PREFERRED): Define.
568 (F_PREF_ALIAS): Define.
569
41702d50
NC		 5702013-04-03 Nick Clifton <nickc@redhat.com>
571
572 * v850.h (V850_INVERSE_PCREL): Define.
573
e21e1a51
NC		 5742013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
575
576 PR binutils/15068
577 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
578
51dcdd4d
NC		 5792013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
580
581 PR binutils/15068
582 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
583 Add 16-bit opcodes.
584 * tic6xc-opcode-table.h: Add 16-bit insns.
585 * tic6x.h: Add support for 16-bit insns.
586
81f5558e
NC		 5872013-03-21 Michael Schewe <michael.schewe@gmx.net>
588
589 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
590 and mov.b/w/l Rs,@(d:32,ERd).
591
165546ad
NC		 5922013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
593
594 PR gas/15082
595 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
596 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
597 tic6x_operand_xregpair operand coding type.
598 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
599 opcode field, usu ORXREGD1324 for the src2 operand and remove the
600 TIC6X_FLAG_NO_CROSS.
601
795b8e6b
NC		 6022013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
603
604 PR gas/15095
605 * tic6x.h (enum tic6x_coding_method): Add
606 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
607 separately the msb and lsb of a register pair. This is needed to
608 encode the opcodes in the same way as TI assembler does.
609 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
610 and rsqrdp opcodes to use the new field coding types.
611
dd5181d5
KT		 6122013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
613
614 * arm.h (CRC_EXT_ARMV8): New constant.
615 (ARCH_CRC_ARMV8): New macro.
616
e60bb1dd
YZ		 6172013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
618
619 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
620
36591ba1
SL		 6212013-02-06 Sandra Loosemore <sandra@codesourcery.com>
622 Andrew Jenner <andrew@codesourcery.com>
623
624 Based on patches from Altera Corporation.
625
626 * nios2.h: New file.
627
e30181a5
YZ		 6282013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
629
630 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
631
0c9573f4
NC		 6322013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
633
634 PR gas/15069
635 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
636
981dc7f1
NC		 6372013-01-24 Nick Clifton <nickc@redhat.com>
638
639 * v850.h: Add e3v5 support.
640
f5555712
YZ		 6412013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
642
643 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
644
5817ffd1
PB		 6452013-01-10 Peter Bergner <bergner@vnet.ibm.com>
646
647 * ppc.h (PPC_OPCODE_POWER8): New define.
648 (PPC_OPCODE_HTM): Likewise.
649
a3c62988
NC		 6502013-01-10 Will Newton <will.newton@imgtec.com>
651
652 * metag.h: New file.
653
73335eae
NC		 6542013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
655
656 * cr16.h (make_instruction): Rename to cr16_make_instruction.
657 (match_opcode): Rename to cr16_match_opcode.
658
e407c74b
NC		 6592013-01-04 Juergen Urban <JuergenUrban@gmx.de>
660
661 * mips.h: Add support for r5900 instructions including lq and sq.
662
bab4becb
NC		 6632013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
664
665 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
666 (make_instruction,match_opcode): Added function prototypes.
667 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
668
776fc418
AM		 6692012-11-23 Alan Modra <amodra@gmail.com>
670
671 * ppc.h (ppc_parse_cpu): Update prototype.
672
f05682d4
DA		 6732012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
674
675 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
676 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
677
cfc72779
AK		 6782012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
679
680 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
681
b3e14eda
L		 6822012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
683
684 * ia64.h (ia64_opnd): Add new operand types.
685
2c63854f
DM		 6862012-08-21 David S. Miller <davem@davemloft.net>
687
688 * sparc.h (F3F4): New macro.
689
a06ea964 6902012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 691 Laurent Desnogues <laurent.desnogues@arm.com>
692 Jim MacArthur <jim.macarthur@arm.com>
693 Marcus Shawcroft <marcus.shawcroft@arm.com>
694 Nigel Stephens <nigel.stephens@arm.com>
695 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
696 Richard Earnshaw <rearnsha@arm.com>
697 Sofiane Naci <sofiane.naci@arm.com>
698 Tejas Belagod <tejas.belagod@arm.com>
699 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 700
701 * aarch64.h: New file.
702
35d0a169 7032012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 704 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 705
706 * mips.h (mips_opcode): Add the exclusions field.
707 (OPCODE_IS_MEMBER): Remove macro.
708 (cpu_is_member): New inline function.
709 (opcode_is_member): Likewise.
710
03f66e8a 7112012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 712 Catherine Moore <clm@codesourcery.com>
713 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 714
715 * mips.h: Document microMIPS DSP ASE usage.
716 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
717 microMIPS DSP ASE support.
718 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
719 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
720 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
721 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
722 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
723 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
724 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
725
9d7b4c23
MR		 7262012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
727
728 * mips.h: Fix a typo in description.
729
76e879f8
NC		 7302012-06-07 Georg-Johann Lay <avr@gjlay.de>
731
732 * avr.h: (AVR_ISA_XCH): New define.
733 (AVR_ISA_XMEGA): Use it.
734 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
735
6927f982
NC		 7362012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
737
738 * m68hc11.h: Add XGate definitions.
739 (struct m68hc11_opcode): Add xg_mask field.
740
b9c361e0
JL		 7412012-05-14 Catherine Moore <clm@codesourcery.com>
742 Maciej W. Rozycki <macro@codesourcery.com>
743 Rhonda Wittels <rhonda@codesourcery.com>
744
6927f982 745 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 746 (PPC_OP_SA): New macro.
747 (PPC_OP_SE_VLE): New macro.
748 (PPC_OP): Use a variable shift amount.
749 (powerpc_operand): Update comments.
750 (PPC_OPSHIFT_INV): New macro.
751 (PPC_OPERAND_CR): Replace with...
752 (PPC_OPERAND_CR_BIT): ...this and
753 (PPC_OPERAND_CR_REG): ...this.
754
755
f6c1a2d5
NC		 7562012-05-03 Sean Keys <skeys@ipdatasys.com>
757
758 * xgate.h: Header file for XGATE assembler.
759
ec668d69
DM		 7602012-04-27 David S. Miller <davem@davemloft.net>
761
6cda1326
DM		 762 * sparc.h: Document new arg code' )' for crypto RS3
763 immediates.
764
ec668d69
DM		 765 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
766 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
767 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
768 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
769 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
770 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
771 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
772 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
773 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
774 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
775 HWCAP_CBCOND, HWCAP_CRC32): New defines.
776
aea77599
AM		 7772012-03-10 Edmar Wienskoski <edmar@freescale.com>
778
779 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
780
1f42f8b3
AM		 7812012-02-27 Alan Modra <amodra@gmail.com>
782
783 * crx.h (cst4_map): Update declaration.
784
6f7be959
WL		 7852012-02-25 Walter Lee <walt@tilera.com>
786
787 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
788 TILEGX_OPC_LD_TLS.
789 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
790 TILEPRO_OPC_LW_TLS_SN.
791
42164a71
L		 7922012-02-08 H.J. Lu <hongjiu.lu@intel.com>
793
794 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
795 (XRELEASE_PREFIX_OPCODE): Likewise.
796
432233b3 7972011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 798 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 799
800 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
801 (INSN_OCTEON2): New macro.
802 (CPU_OCTEON2): New macro.
803 (OPCODE_IS_MEMBER): Add Octeon2.
804
dd6a37e7
AP		 8052011-11-29 Andrew Pinski <apinski@cavium.com>
806
807 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
808 (INSN_OCTEONP): New macro.
809 (CPU_OCTEONP): New macro.
810 (OPCODE_IS_MEMBER): Add Octeon+.
811 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
812
99c513f6
DD		 8132011-11-01 DJ Delorie <dj@redhat.com>
814
815 * rl78.h: New file.
816
26f85d7a
MR		 8172011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
818
819 * mips.h: Fix a typo in description.
820
9e8c70f9
DM		 8212011-09-21 David S. Miller <davem@davemloft.net>
822
823 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
824 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
825 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
826 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
827
dec0624d 8282011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 829 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 830
831 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
832 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
833 (INSN_ASE_MASK): Add the MCU bit.
834 (INSN_MCU): New macro.
835 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
836 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
837
2b0c8b40
MR		 8382011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
839
840 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
841 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
842 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
843 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
844 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
845 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
846 (INSN2_READ_GPR_MMN): Likewise.
847 (INSN2_READ_FPR_D): Change the bit used.
848 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
849 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
850 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
851 (INSN2_COND_BRANCH): Likewise.
852 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
853 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
854 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
855 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
856 (INSN2_MOD_GPR_MN): Likewise.
857
ea783ef3
DM		 8582011-08-05 David S. Miller <davem@davemloft.net>
859
860 * sparc.h: Document new format codes '4', '5', and '('.
861 (OPF_LOW4, RS3): New macros.
862
7c176fa8
MR		 8632011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
864
865 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
866 order of flags documented.
867
2309ddf2
MR		 8682011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
869
870 * mips.h: Clarify the description of microMIPS instruction
871 manipulation macros.
872 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
873
df58fc94 8742011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 875 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 876
877 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
878 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
879 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
880 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
881 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
882 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
883 (OP_MASK_RS3, OP_SH_RS3): Likewise.
884 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
885 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
886 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
887 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
888 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
889 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
890 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
891 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
892 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
893 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
894 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
895 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
896 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
897 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
898 (INSN_WRITE_GPR_S): New macro.
899 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
900 (INSN2_READ_FPR_D): Likewise.
901 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
902 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
903 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
904 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
905 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
906 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
907 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
908 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
909 (CPU_MICROMIPS): New macro.
910 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
911 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
912 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
913 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
914 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
915 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
916 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
917 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
918 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
919 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
920 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
921 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
922 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
923 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
924 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
925 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
926 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
927 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
928 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
929 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
930 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
931 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
932 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
933 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
934 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
935 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
936 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
937 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
938 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
939 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
940 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
941 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
942 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
943 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
944 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
945 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
946 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
947 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
948 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
949 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
950 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
951 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
952 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
953 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
954 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
955 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
956 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
957 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
958 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
959 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
960 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
961 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
962 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
963 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
964 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
965 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
966 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
967 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
968 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
969 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
970 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
971 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
972 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
973 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
974 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
975 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
976 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
977 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
978 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
979 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
980 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
981 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
982 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
983 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
984 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
985 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
986 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
987 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
988 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
989 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
990 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
991 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
992 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
993 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
994 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
995 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
996 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
997 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
998 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
999 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1000 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1001 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1002 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1003 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1004 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1005 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1006 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1007 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1008 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1009 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1010 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1011 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1012 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1013 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1014 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1015 (micromips_opcodes): New declaration.
1016 (bfd_micromips_num_opcodes): Likewise.
1017
bcd530a7
RS		 10182011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1019
1020 * mips.h (INSN_TRAP): Rename to...
1021 (INSN_NO_DELAY_SLOT): ... this.
1022 (INSN_SYNC): Remove macro.
1023
2dad5a91
EW		 10242011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1025
1026 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1027 a duplicate of AVR_ISA_SPM.
1028
5d73b1f1
NC		 10292011-07-01 Nick Clifton <nickc@redhat.com>
1030
1031 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1032
ef26d60e
MF		 10332011-06-18 Robin Getz <robin.getz@analog.com>
1034
1035 * bfin.h (is_macmod_signed): New func
1036
8fb8dca7
MF		 10372011-06-18 Mike Frysinger <vapier@gentoo.org>
1038
1039 * bfin.h (is_macmod_pmove): Add missing space before func args.
1040 (is_macmod_hmove): Likewise.
1041
aa137e4d
NC		 10422011-06-13 Walter Lee <walt@tilera.com>
1043
1044 * tilegx.h: New file.
1045 * tilepro.h: New file.
1046
3b2f0793
PB		 10472011-05-31 Paul Brook <paul@codesourcery.com>
1048
aa137e4d
NC		 1049 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1050
10512011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1052
1053 * s390.h: Replace S390_OPERAND_REG_EVEN with
1054 S390_OPERAND_REG_PAIR.
1055
10562011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1057
1058 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1059
ac7f631b
NC		 10602011-04-18 Julian Brown <julian@codesourcery.com>
1061
1062 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1063
84701018
NC		 10642011-04-11 Dan McDonald <dan@wellkeeper.com>
1065
1066 PR gas/12296
1067 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1068
8cc66334
EW		 10692011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1070
1071 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1072 New instruction set flags.
1073 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1074
3eebd5eb
MR		 10752011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1076
1077 * mips.h (M_PREF_AB): New enum value.
1078
26bb3ddd
MF		 10792011-02-12 Mike Frysinger <vapier@gentoo.org>
1080
89c0d58c
MR		 1081 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1082 M_IU): Define.
1083 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1084
dd76fcb8
MF		 10852011-02-11 Mike Frysinger <vapier@gentoo.org>
1086
1087 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1088
98d23bef
BS		 10892011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1090
1091 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1092 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1093
3c853d93
DA		 10942010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1095
1096 PR gas/11395
1097 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1098 "bb" entries.
1099
79676006
DA		 11002010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1101
1102 PR gas/11395
1103 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1104
1bec78e9
RS		 11052010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1106
1107 * mips.h: Update commentary after last commit.
1108
98675402
RS		 11092010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1110
1111 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1112 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1113 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1114
aa137e4d
NC		 11152010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1116
1117 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1118
435b94a4
RS		 11192010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1120
1121 * mips.h: Fix previous commit.
1122
d051516a
NC		 11232010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1124
1125 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1126 (INSN_LOONGSON_3A): Clear bit 31.
1127
251665fc
MGD		 11282010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1129
1130 PR gas/12198
1131 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1132 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1133 (ARM_ARCH_V6M_ONLY): New define.
1134
fd503541
NC		 11352010-11-11 Mingming Sun <mingm.sun@gmail.com>
1136
1137 * mips.h (INSN_LOONGSON_3A): Defined.
1138 (CPU_LOONGSON_3A): Defined.
1139 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1140
4469d2be
AM		 11412010-10-09 Matt Rice <ratmice@gmail.com>
1142
1143 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1144 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1145
90ec0d68
MGD		 11462010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1147
1148 * arm.h (ARM_EXT_VIRT): New define.
1149 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1150 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1151 Extensions.
1152
eea54501 11532010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1154
eea54501
MGD		 1155 * arm.h (ARM_AEXT_ADIV): New define.
1156 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1157
b2a5fbdc
MGD		 11582010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1159
1160 * arm.h (ARM_EXT_OS): New define.
1161 (ARM_AEXT_V6SM): Likewise.
1162 (ARM_ARCH_V6SM): Likewise.
1163
60e5ef9f
MGD		 11642010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1165
1166 * arm.h (ARM_EXT_MP): Add.
1167 (ARM_ARCH_V7A_MP): Likewise.
1168
73a63ccf
MF		 11692010-09-22 Mike Frysinger <vapier@gentoo.org>
1170
1171 * bfin.h: Declare pseudoChr structs/defines.
1172
ee99860a
MF		 11732010-09-21 Mike Frysinger <vapier@gentoo.org>
1174
1175 * bfin.h: Strip trailing whitespace.
1176
f9c7014e
DD		 11772010-07-29 DJ Delorie <dj@redhat.com>
1178
1179 * rx.h (RX_Operand_Type): Add TwoReg.
1180 (RX_Opcode_ID): Remove ediv and ediv2.
1181
93378652
DD		 11822010-07-27 DJ Delorie <dj@redhat.com>
1183
1184 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1185
1cd986c5
NC		 11862010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1187 Ina Pandit <ina.pandit@kpitcummins.com>
1188
1189 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1190 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1191 PROCESSOR_V850E2_ALL.
1192 Remove PROCESSOR_V850EA support.
1193 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1194 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1195 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1196 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1197 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1198 V850_OPERAND_PERCENT.
1199 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1200 V850_NOT_R0.
1201 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1202 and V850E_PUSH_POP
1203
9a2c7088
MR		 12042010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1205
1206 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1207 (MIPS16_INSN_BRANCH): Rename to...
1208 (MIPS16_INSN_COND_BRANCH): ... this.
1209
bdc70b4a
AM		 12102010-07-03 Alan Modra <amodra@gmail.com>
1211
1212 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1213 Renumber other PPC_OPCODE defines.
1214
f2bae120
AM		 12152010-07-03 Alan Modra <amodra@gmail.com>
1216
1217 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1218
360cfc9c
AM		 12192010-06-29 Alan Modra <amodra@gmail.com>
1220
1221 * maxq.h: Delete file.
1222
e01d869a
AM		 12232010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1224
1225 * ppc.h (PPC_OPCODE_E500): Define.
1226
f79e2745
CM		 12272010-05-26 Catherine Moore <clm@codesourcery.com>
1228
1229 * opcode/mips.h (INSN_MIPS16): Remove.
1230
2462afa1
JM		 12312010-04-21 Joseph Myers <joseph@codesourcery.com>
1232
1233 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1234
e4e42b45
NC		 12352010-04-15 Nick Clifton <nickc@redhat.com>
1236
1237 * alpha.h: Update copyright notice to use GPLv3.
1238 * arc.h: Likewise.
1239 * arm.h: Likewise.
1240 * avr.h: Likewise.
1241 * bfin.h: Likewise.
1242 * cgen.h: Likewise.
1243 * convex.h: Likewise.
1244 * cr16.h: Likewise.
1245 * cris.h: Likewise.
1246 * crx.h: Likewise.
1247 * d10v.h: Likewise.
1248 * d30v.h: Likewise.
1249 * dlx.h: Likewise.
1250 * h8300.h: Likewise.
1251 * hppa.h: Likewise.
1252 * i370.h: Likewise.
1253 * i386.h: Likewise.
1254 * i860.h: Likewise.
1255 * i960.h: Likewise.
1256 * ia64.h: Likewise.
1257 * m68hc11.h: Likewise.
1258 * m68k.h: Likewise.
1259 * m88k.h: Likewise.
1260 * maxq.h: Likewise.
1261 * mips.h: Likewise.
1262 * mmix.h: Likewise.
1263 * mn10200.h: Likewise.
1264 * mn10300.h: Likewise.
1265 * msp430.h: Likewise.
1266 * np1.h: Likewise.
1267 * ns32k.h: Likewise.
1268 * or32.h: Likewise.
1269 * pdp11.h: Likewise.
1270 * pj.h: Likewise.
1271 * pn.h: Likewise.
1272 * ppc.h: Likewise.
1273 * pyr.h: Likewise.
1274 * rx.h: Likewise.
1275 * s390.h: Likewise.
1276 * score-datadep.h: Likewise.
1277 * score-inst.h: Likewise.
1278 * sparc.h: Likewise.
1279 * spu-insns.h: Likewise.
1280 * spu.h: Likewise.
1281 * tic30.h: Likewise.
1282 * tic4x.h: Likewise.
1283 * tic54x.h: Likewise.
1284 * tic80.h: Likewise.
1285 * v850.h: Likewise.
1286 * vax.h: Likewise.
1287
40b36596
JM		 12882010-03-25 Joseph Myers <joseph@codesourcery.com>
1289
1290 * tic6x-control-registers.h, tic6x-insn-formats.h,
1291 tic6x-opcode-table.h, tic6x.h: New.
1292
c67a084a
NC		 12932010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1294
1295 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1296
466ef64f
AM		 12972010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1298
1299 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1300
1319d143
L		 13012010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1302
1303 * ia64.h (ia64_find_opcode): Remove argument name.
1304 (ia64_find_next_opcode): Likewise.
1305 (ia64_dis_opcode): Likewise.
1306 (ia64_free_opcode): Likewise.
1307 (ia64_find_dependency): Likewise.
1308
1fbb9298
DE		 13092009-11-22 Doug Evans <dje@sebabeach.org>
1310
1311 * cgen.h: Include bfd_stdint.h.
1312 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1313
ada65aa3
PB		 13142009-11-18 Paul Brook <paul@codesourcery.com>
1315
1316 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1317
9e3c6df6
PB		 13182009-11-17 Paul Brook <paul@codesourcery.com>
1319 Daniel Jacobowitz <dan@codesourcery.com>
1320
1321 * arm.h (ARM_EXT_V6_DSP): Define.
1322 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1323 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1324
0d734b5d
DD		 13252009-11-04 DJ Delorie <dj@redhat.com>
1326
1327 * rx.h (rx_decode_opcode) (mvtipl): Add.
1328 (mvtcp, mvfcp, opecp): Remove.
1329
62f3b8c8
PB		 13302009-11-02 Paul Brook <paul@codesourcery.com>
1331
1332 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1333 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1334 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1335 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1336 FPU_ARCH_NEON_VFP_V4): Define.
1337
ac1e9eca
DE		 13382009-10-23 Doug Evans <dje@sebabeach.org>
1339
1340 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1341 * cgen.h: Update. Improve multi-inclusion macro name.
1342
9fe54b1c
PB		 13432009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1344
1345 * ppc.h (PPC_OPCODE_476): Define.
1346
634b50f2
PB		 13472009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1348
1349 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1350
c7927a3c
NC		 13512009-09-29 DJ Delorie <dj@redhat.com>
1352
1353 * rx.h: New file.
1354
b961e85b
AM		 13552009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1356
1357 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1358
e0d602ec
BE		 13592009-09-21 Ben Elliston <bje@au.ibm.com>
1360
1361 * ppc.h (PPC_OPCODE_PPCA2): New.
1362
96d56e9f
NC		 13632009-09-05 Martin Thuresson <martin@mtme.org>
1364
1365 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1366
d3ce72d0
NC		 13672009-08-29 Martin Thuresson <martin@mtme.org>
1368
1369 * tic30.h (template): Rename type template to
1370 insn_template. Updated code to use new name.
1371 * tic54x.h (template): Rename type template to
1372 insn_template.
1373
824b28db
NH		 13742009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1375
1376 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1377
f865a31d
AG		 13782009-06-11 Anthony Green <green@moxielogic.com>
1379
1380 * moxie.h (MOXIE_F3_PCREL): Define.
1381 (moxie_form3_opc_info): Grow.
1382
0e7c7f11
AG		 13832009-06-06 Anthony Green <green@moxielogic.com>
1384
1385 * moxie.h (MOXIE_F1_M): Define.
1386
20135e4c
NC		 13872009-04-15 Anthony Green <green@moxielogic.com>
1388
1389 * moxie.h: Created.
1390
bcb012d3
DD		 13912009-04-06 DJ Delorie <dj@redhat.com>
1392
1393 * h8300.h: Add relaxation attributes to MOVA opcodes.
1394
69fe9ce5
AM		 13952009-03-10 Alan Modra <amodra@bigpond.net.au>
1396
1397 * ppc.h (ppc_parse_cpu): Declare.
1398
c3b7224a
NC		 13992009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1400
1401 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1402 and _IMM11 for mbitclr and mbitset.
1403 * score-datadep.h: Update dependency information.
1404
066be9f7
PB		 14052009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1406
1407 * ppc.h (PPC_OPCODE_POWER7): New.
1408
fedc618e
DE		 14092009-02-06 Doug Evans <dje@google.com>
1410
1411 * i386.h: Add comment regarding sse* insns and prefixes.
1412
52b6b6b9
JM		 14132009-02-03 Sandip Matte <sandip@rmicorp.com>
1414
1415 * mips.h (INSN_XLR): Define.
1416 (INSN_CHIP_MASK): Update.
1417 (CPU_XLR): Define.
1418 (OPCODE_IS_MEMBER): Update.
1419 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1420
35669430
DE		 14212009-01-28 Doug Evans <dje@google.com>
1422
1423 * opcode/i386.h: Add multiple inclusion protection.
1424 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1425 (EDI_REG_NUM): New macros.
1426 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1427 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1428 (REX_PREFIX_P): New macro.
35669430 1429
1cb0a767
PB		 14302009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1431
1432 * ppc.h (struct powerpc_opcode): New field "deprecated".
1433 (PPC_OPCODE_NOPOWER4): Delete.
1434
3aa3176b
TS		 14352008-11-28 Joshua Kinard <kumba@gentoo.org>
1436
1437 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1438 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1439
8e79c3df
CM		 14402008-11-18 Catherine Moore <clm@codesourcery.com>
1441
1442 * arm.h (FPU_NEON_FP16): New.
1443 (FPU_ARCH_NEON_FP16): New.
1444
de9a3e51
CF		 14452008-11-06 Chao-ying Fu <fu@mips.com>
1446
1447 * mips.h: Doucument '1' for 5-bit sync type.
1448
1ca35711
L		 14492008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1450
1451 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1452 IA64_RS_CR.
1453
9b4e5766
PB		 14542008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1455
1456 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1457
081ba1b3
AM		 14582008-07-30 Michael J. Eager <eager@eagercon.com>
1459
1460 * ppc.h (PPC_OPCODE_405): Define.
1461 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1462
fa452fa6
PB		 14632008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1464
1465 * ppc.h (ppc_cpu_t): New typedef.
1466 (struct powerpc_opcode <flags>): Use it.
1467 (struct powerpc_operand <insert, extract>): Likewise.
1468 (struct powerpc_macro <flags>): Likewise.
1469
bb35fb24
NC		 14702008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1471
1472 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1473 Update comment before MIPS16 field descriptors to mention MIPS16.
1474 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1475 BBIT.
1476 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1477 New bit masks and shift counts for cins and exts.
1478
dd3cbb7e
NC		 1479 * mips.h: Document new field descriptors +Q.
1480 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1481
d0799671
AN		 14822008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1483
9aff4b7a 1484 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1485 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1486
19a6653c
AM		 14872008-04-14 Edmar Wienskoski <edmar@freescale.com>
1488
1489 * ppc.h: (PPC_OPCODE_E500MC): New.
1490
c0f3af97
L		 14912008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1492
1493 * i386.h (MAX_OPERANDS): Set to 5.
1494 (MAX_MNEM_SIZE): Changed to 20.
1495
e210c36b
NC		 14962008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1497
1498 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1499
b1cc4aeb
PB		 15002008-03-09 Paul Brook <paul@codesourcery.com>
1501
1502 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1503
7e806470
PB		 15042008-03-04 Paul Brook <paul@codesourcery.com>
1505
1506 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1507 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1508 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1509
7b2185f9 15102008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1511 Nick Clifton <nickc@redhat.com>
1512
1513 PR 3134
1514 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1515 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1516 set.
af7329f0 1517
796d5313
NC		 15182008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1519
1520 * cr16.h (cr16_num_optab): Declared.
1521
d669d37f
NC		 15222008-02-14 Hakan Ardo <hakan@debian.org>
1523
1524 PR gas/2626
1525 * avr.h (AVR_ISA_2xxe): Define.
1526
e6429699
AN		 15272008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1528
1529 * mips.h: Update copyright.
1530 (INSN_CHIP_MASK): New macro.
1531 (INSN_OCTEON): New macro.
1532 (CPU_OCTEON): New macro.
1533 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1534
e210c36b
NC		 15352008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1536
1537 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1538
15392008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1540
1541 * avr.h (AVR_ISA_USB162): Add new opcode set.
1542 (AVR_ISA_AVR3): Likewise.
1543
350cc38d
MS		 15442007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1545
1546 * mips.h (INSN_LOONGSON_2E): New.
1547 (INSN_LOONGSON_2F): New.
1548 (CPU_LOONGSON_2E): New.
1549 (CPU_LOONGSON_2F): New.
1550 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1551
56950294
MS		 15522007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1553
1554 * mips.h (INSN_ISA*): Redefine certain values as an
1555 enumeration. Update comments.
1556 (mips_isa_table): New.
1557 (ISA_MIPS*): Redefine to match enumeration.
1558 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1559 values.
1560
c3d65c1c
BE		 15612007-08-08 Ben Elliston <bje@au.ibm.com>
1562
1563 * ppc.h (PPC_OPCODE_PPCPS): New.
1564
0fdaa005
L		 15652007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1566
1567 * m68k.h: Document j K & E.
1568
15692007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1570
1571 * cr16.h: New file for CR16 target.
1572
3896c469
AM		 15732007-05-02 Alan Modra <amodra@bigpond.net.au>
1574
1575 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1576
9a2e615a
NS		 15772007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1578
1579 * m68k.h (mcfisa_c): New.
1580 (mcfusp, mcf_mask): Adjust.
1581
b84bf58a
AM		 15822007-04-20 Alan Modra <amodra@bigpond.net.au>
1583
1584 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1585 (num_powerpc_operands): Declare.
1586 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1587 (PPC_OPERAND_PLUS1): Define.
1588
831480e9 15892007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1590
1591 * i386.h (REX_MODE64): Renamed to ...
1592 (REX_W): This.
1593 (REX_EXTX): Renamed to ...
1594 (REX_R): This.
1595 (REX_EXTY): Renamed to ...
1596 (REX_X): This.
1597 (REX_EXTZ): Renamed to ...
1598 (REX_B): This.
1599
0b1cf022
L		 16002007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1601
1602 * i386.h: Add entries from config/tc-i386.h and move tables
1603 to opcodes/i386-opc.h.
1604
d796c0ad
L		 16052007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1606
1607 * i386.h (FloatDR): Removed.
1608 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1609
30ac7323
AM		 16102007-03-01 Alan Modra <amodra@bigpond.net.au>
1611
1612 * spu-insns.h: Add soma double-float insns.
1613
8b082fb1 16142007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1615 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1616
1617 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1618 (INSN_DSPR2): Add flag for DSP R2 instructions.
1619 (M_BALIGN): New macro.
1620
4eed87de
AM		 16212007-02-14 Alan Modra <amodra@bigpond.net.au>
1622
1623 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1624 and Seg3ShortFrom with Shortform.
1625
fda592e8
L		 16262007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1627
1628 PR gas/4027
1629 * i386.h (i386_optab): Put the real "test" before the pseudo
1630 one.
1631
3bdcfdf4
KH		 16322007-01-08 Kazu Hirata <kazu@codesourcery.com>
1633
1634 * m68k.h (m68010up): OR fido_a.
1635
9840d27e
KH		 16362006-12-25 Kazu Hirata <kazu@codesourcery.com>
1637
1638 * m68k.h (fido_a): New.
1639
c629cdac
KH		 16402006-12-24 Kazu Hirata <kazu@codesourcery.com>
1641
1642 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1643 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1644 values.
1645
b7d9ef37
L		 16462006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1647
1648 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1649
b138abaa
NC		 16502006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1651
1652 * score-inst.h (enum score_insn_type): Add Insn_internal.
1653
e9f53129
AM		 16542006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1655 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1656 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1657 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1658 Alan Modra <amodra@bigpond.net.au>
1659
1660 * spu-insns.h: New file.
1661 * spu.h: New file.
1662
ede602d7
AM		 16632006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1664
1665 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1666
7918206c
MM		 16672006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1668
e4e42b45 1669 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1670 in amdfam10 architecture.
1671
ef05d495
L		 16722006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1673
1674 * i386.h: Replace CpuMNI with CpuSSSE3.
1675
2d447fca 16762006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1677 Joseph Myers <joseph@codesourcery.com>
1678 Ian Lance Taylor <ian@wasabisystems.com>
1679 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1680
1681 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1682
1c0d3aa6
NC		 16832006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1684
1685 * score-datadep.h: New file.
1686 * score-inst.h: New file.
1687
c2f0420e
L		 16882006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1689
1690 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1691 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1692 movdq2q and movq2dq.
1693
050dfa73
MM		 16942006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1695 Michael Meissner <michael.meissner@amd.com>
1696
1697 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1698
15965411
L		 16992006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1700
1701 * i386.h (i386_optab): Add "nop" with memory reference.
1702
46e883c5
L		 17032006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1704
1705 * i386.h (i386_optab): Update comment for 64bit NOP.
1706
9622b051
AM		 17072006-06-06 Ben Elliston <bje@au.ibm.com>
1708 Anton Blanchard <anton@samba.org>
1709
1710 * ppc.h (PPC_OPCODE_POWER6): Define.
1711 Adjust whitespace.
1712
a9e24354
TS		 17132006-06-05 Thiemo Seufer <ths@mips.com>
1714
e4e42b45 1715 * mips.h: Improve description of MT flags.
a9e24354 1716
a596001e
RS		 17172006-05-25 Richard Sandiford <richard@codesourcery.com>
1718
1719 * m68k.h (mcf_mask): Define.
1720
d43b4baf 17212006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1722 David Ung <davidu@mips.com>
d43b4baf
TS		 1723
1724 * mips.h (enum): Add macro M_CACHE_AB.
1725
39a7806d 17262006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1727 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1728 David Ung <davidu@mips.com>
1729
1730 * mips.h: Add INSN_SMARTMIPS define.
1731
9bcd4f99 17322006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1733 David Ung <davidu@mips.com>
9bcd4f99
TS		 1734
1735 * mips.h: Defines udi bits and masks. Add description of
1736 characters which may appear in the args field of udi
1737 instructions.
1738
ef0ee844
TS		 17392006-04-26 Thiemo Seufer <ths@networkno.de>
1740
1741 * mips.h: Improve comments describing the bitfield instruction
1742 fields.
1743
f7675147
L		 17442006-04-26 Julian Brown <julian@codesourcery.com>
1745
1746 * arm.h (FPU_VFP_EXT_V3): Define constant.
1747 (FPU_NEON_EXT_V1): Likewise.
1748 (FPU_VFP_HARD): Update.
1749 (FPU_VFP_V3): Define macro.
1750 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1751
ef0ee844 17522006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1753
1754 * avr.h (AVR_ISA_PWMx): New.
1755
2da12c60
NS		 17562006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1757
1758 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1759 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1760 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1761 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1762 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1763
0715c387
PB		 17642006-03-10 Paul Brook <paul@codesourcery.com>
1765
1766 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1767
34bdd094
DA		 17682006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1769
1770 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1771 first. Correct mask of bb "B" opcode.
1772
331d2d0d
L		 17732006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1774
1775 * i386.h (i386_optab): Support Intel Merom New Instructions.
1776
62b3e311
PB		 17772006-02-24 Paul Brook <paul@codesourcery.com>
1778
1779 * arm.h: Add V7 feature bits.
1780
59cf82fe
L		 17812006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1782
1783 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1784
e74cfd16
PB		 17852006-01-31 Paul Brook <paul@codesourcery.com>
1786 Richard Earnshaw <rearnsha@arm.com>
1787
1788 * arm.h: Use ARM_CPU_FEATURE.
1789 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1790 (arm_feature_set): Change to a structure.
1791 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1792 ARM_FEATURE): New macros.
1793
5b3f8a92
HPN		 17942005-12-07 Hans-Peter Nilsson <hp@axis.com>
1795
1796 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1797 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1798 (ADD_PC_INCR_OPCODE): Don't define.
1799
cb712a9e
L		 18002005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1801
1802 PR gas/1874
1803 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1804
0499d65b
TS		 18052005-11-14 David Ung <davidu@mips.com>
1806
1807 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1808 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1809 save/restore encoding of the args field.
1810
ea5ca089
DB		 18112005-10-28 Dave Brolley <brolley@redhat.com>
1812
1813 Contribute the following changes:
1814 2005-02-16 Dave Brolley <brolley@redhat.com>
1815
1816 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1817 cgen_isa_mask_* to cgen_bitset_*.
1818 * cgen.h: Likewise.
1819
16175d96
DB		 1820 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1821
1822 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1823 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1824 (CGEN_CPU_TABLE): Make isas a ponter.
1825
1826 2003-09-29 Dave Brolley <brolley@redhat.com>
1827
1828 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1829 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1830 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1831
1832 2002-12-13 Dave Brolley <brolley@redhat.com>
1833
1834 * cgen.h (symcat.h): #include it.
1835 (cgen-bitset.h): #include it.
1836 (CGEN_ATTR_VALUE_TYPE): Now a union.
1837 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1838 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1839 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1840 * cgen-bitset.h: New file.
1841
3c9b82ba
NC		 18422005-09-30 Catherine Moore <clm@cm00re.com>
1843
1844 * bfin.h: New file.
1845
6a2375c6
JB		 18462005-10-24 Jan Beulich <jbeulich@novell.com>
1847
1848 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1849 indirect operands.
1850
c06a12f8
DA		 18512005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1852
1853 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1854 Add FLAG_STRICT to pa10 ftest opcode.
1855
4d443107
DA		 18562005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1857
1858 * hppa.h (pa_opcodes): Remove lha entries.
1859
f0a3b40f
DA		 18602005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1861
1862 * hppa.h (FLAG_STRICT): Revise comment.
1863 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1864 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1865 entries for "fdc".
1866
e210c36b
NC		 18672005-09-30 Catherine Moore <clm@cm00re.com>
1868
1869 * bfin.h: New file.
1870
1b7e1362
DA		 18712005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1872
1873 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1874
089b39de
CF		 18752005-09-06 Chao-ying Fu <fu@mips.com>
1876
1877 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1878 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1879 define.
1880 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1881 (INSN_ASE_MASK): Update to include INSN_MT.
1882 (INSN_MT): New define for MT ASE.
1883
93c34b9b
CF		 18842005-08-25 Chao-ying Fu <fu@mips.com>
1885
1886 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1887 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1888 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1889 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1890 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1891 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1892 instructions.
1893 (INSN_DSP): New define for DSP ASE.
1894
848cf006
AM		 18952005-08-18 Alan Modra <amodra@bigpond.net.au>
1896
1897 * a29k.h: Delete.
1898
36ae0db3
DJ		 18992005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1900
1901 * ppc.h (PPC_OPCODE_E300): Define.
1902
8c929562
MS		 19032005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1904
1905 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1906
f7b8cccc
DA		 19072005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1908
1909 PR gas/336
1910 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1911 and pitlb.
1912
8b5328ac
JB		 19132005-07-27 Jan Beulich <jbeulich@novell.com>
1914
1915 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1916 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1917 Add movq-s as 64-bit variants of movd-s.
1918
f417d200
DA		 19192005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1920
18b3bdfc
DA		 1921 * hppa.h: Fix punctuation in comment.
1922
f417d200
DA		 1923 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1924 implicit space-register addressing. Set space-register bits on opcodes
1925 using implicit space-register addressing. Add various missing pa20
1926 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1927 space-register addressing. Use "fE" instead of "fe" in various
1928 fstw opcodes.
1929
9a145ce6
JB		 19302005-07-18 Jan Beulich <jbeulich@novell.com>
1931
1932 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1933
90700ea2
L		 19342007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1935
1936 * i386.h (i386_optab): Support Intel VMX Instructions.
1937
48f130a8
DA		 19382005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1939
1940 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1941
30123838
JB		 19422005-07-05 Jan Beulich <jbeulich@novell.com>
1943
1944 * i386.h (i386_optab): Add new insns.
1945
47b0e7ad
NC		 19462005-07-01 Nick Clifton <nickc@redhat.com>
1947
1948 * sparc.h: Add typedefs to structure declarations.
1949
b300c311
L		 19502005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1951
1952 PR 1013
1953 * i386.h (i386_optab): Update comments for 64bit addressing on
1954 mov. Allow 64bit addressing for mov and movq.
1955
2db495be
DA		 19562005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1957
1958 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1959 respectively, in various floating-point load and store patterns.
1960
caa05036
DA		 19612005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1962
1963 * hppa.h (FLAG_STRICT): Correct comment.
1964 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1965 PA 2.0 mneumonics when equivalent. Entries with cache control
1966 completers now require PA 1.1. Adjust whitespace.
1967
f4411256
AM		 19682005-05-19 Anton Blanchard <anton@samba.org>
1969
1970 * ppc.h (PPC_OPCODE_POWER5): Define.
1971
e172dbf8
NC		 19722005-05-10 Nick Clifton <nickc@redhat.com>
1973
1974 * Update the address and phone number of the FSF organization in
1975 the GPL notices in the following files:
1976 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1977 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1978 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1979 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1980 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1981 tic54x.h, tic80.h, v850.h, vax.h
1982
e44823cf
JB		 19832005-05-09 Jan Beulich <jbeulich@novell.com>
1984
1985 * i386.h (i386_optab): Add ht and hnt.
1986
791fe849
MK		 19872005-04-18 Mark Kettenis <kettenis@gnu.org>
1988
1989 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1990 Add xcrypt-ctr. Provide aliases without hyphens.
1991
faa7ef87
L		 19922005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1993
a63027e5
L		 1994 Moved from ../ChangeLog
1995
faa7ef87
L		 1996 2005-04-12 Paul Brook <paul@codesourcery.com>
1997 * m88k.h: Rename psr macros to avoid conflicts.
1998
1999 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2000 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2001 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2002 and ARM_ARCH_V6ZKT2.
2003
2004 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2005 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2006 Remove redundant instruction types.
2007 (struct argument): X_op - new field.
2008 (struct cst4_entry): Remove.
2009 (no_op_insn): Declare.
2010
2011 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2012 * crx.h (enum argtype): Rename types, remove unused types.
2013
2014 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2015 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2016 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2017 (enum operand_type): Rearrange operands, edit comments.
2018 replace us<N> with ui<N> for unsigned immediate.
2019 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2020 displacements (respectively).
2021 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2022 (instruction type): Add NO_TYPE_INS.
2023 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2024 (operand_entry): New field - 'flags'.
2025 (operand flags): New.
2026
2027 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2028 * crx.h (operand_type): Remove redundant types i3, i4,
2029 i5, i8, i12.
2030 Add new unsigned immediate types us3, us4, us5, us16.
2031
bc4bd9ab
MK		 20322005-04-12 Mark Kettenis <kettenis@gnu.org>
2033
2034 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2035 adjust them accordingly.
2036
373ff435
JB		 20372005-04-01 Jan Beulich <jbeulich@novell.com>
2038
2039 * i386.h (i386_optab): Add rdtscp.
2040
4cc91dba
L		 20412005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2042
2043 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2044 between memory and segment register. Allow movq for moving between
2045 general-purpose register and segment register.
4cc91dba 2046
9ae09ff9
JB		 20472005-02-09 Jan Beulich <jbeulich@novell.com>
2048
2049 PR gas/707
2050 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2051 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2052 fnstsw.
2053
638e7a64
NS		 20542006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2055
2056 * m68k.h (m68008, m68ec030, m68882): Remove.
2057 (m68k_mask): New.
2058 (cpu_m68k, cpu_cf): New.
2059 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2060 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2061
90219bd0
AO		 20622005-01-25 Alexandre Oliva <aoliva@redhat.com>
2063
2064 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2065 * cgen.h (enum cgen_parse_operand_type): Add
2066 CGEN_PARSE_OPERAND_SYMBOLIC.
2067
239cb185
FF		 20682005-01-21 Fred Fish <fnf@specifixinc.com>
2069
2070 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2071 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2072 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2073
dc9a9f39
FF		 20742005-01-19 Fred Fish <fnf@specifixinc.com>
2075
2076 * mips.h (struct mips_opcode): Add new pinfo2 member.
2077 (INSN_ALIAS): New define for opcode table entries that are
2078 specific instances of another entry, such as 'move' for an 'or'
2079 with a zero operand.
2080 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2081 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2082
98e7aba8
ILT		 20832004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2084
2085 * mips.h (CPU_RM9000): Define.
2086 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2087
37edbb65
JB		 20882004-11-25 Jan Beulich <jbeulich@novell.com>
2089
2090 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2091 to/from test registers are illegal in 64-bit mode. Add missing
2092 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2093 (previously one had to explicitly encode a rex64 prefix). Re-enable
2094 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2095 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2096
20972004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2098
2099 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2100 available only with SSE2. Change the MMX additions introduced by SSE
2101 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2102 instructions by their now designated identifier (since combining i686
2103 and 3DNow! does not really imply 3DNow!A).
2104
f5c7edf4
AM		 21052004-11-19 Alan Modra <amodra@bigpond.net.au>
2106
2107 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2108 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2109
7499d566
NC		 21102004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2111 Vineet Sharma <vineets@noida.hcltech.com>
2112
2113 * maxq.h: New file: Disassembly information for the maxq port.
2114
bcb9eebe
L		 21152004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2116
2117 * i386.h (i386_optab): Put back "movzb".
2118
94bb3d38
HPN		 21192004-11-04 Hans-Peter Nilsson <hp@axis.com>
2120
2121 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2122 comments. Remove member cris_ver_sim. Add members
2123 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2124 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2125 (struct cris_support_reg, struct cris_cond15): New types.
2126 (cris_conds15): Declare.
2127 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2128 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2129 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2130 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2131 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2132 SIZE_FIELD_UNSIGNED.
2133
37edbb65 21342004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2135
2136 * i386.h (sldx_Suf): Remove.
2137 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2138 (q_FP): Define, implying no REX64.
2139 (x_FP, sl_FP): Imply FloatMF.
2140 (i386_optab): Split reg and mem forms of moving from segment registers
2141 so that the memory forms can ignore the 16-/32-bit operand size
2142 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2143 all non-floating-point instructions. Unite 32- and 64-bit forms of
2144 movsx, movzx, and movd. Adjust floating point operations for the above
2145 changes to the *FP macros. Add DefaultSize to floating point control
2146 insns operating on larger memory ranges. Remove left over comments
2147 hinting at certain insns being Intel-syntax ones where the ones
2148 actually meant are already gone.
2149
48c9f030
NC		 21502004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2151
2152 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2153 instruction type.
2154
0dd132b6
NC		 21552004-09-30 Paul Brook <paul@codesourcery.com>
2156
2157 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2158 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2159
23794b24
MM		 21602004-09-11 Theodore A. Roth <troth@openavr.org>
2161
2162 * avr.h: Add support for
2163 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2164
2a309db0
AM		 21652004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2166
2167 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2168
b18c562e
NC		 21692004-08-24 Dmitry Diky <diwil@spec.ru>
2170
2171 * msp430.h (msp430_opc): Add new instructions.
2172 (msp430_rcodes): Declare new instructions.
2173 (msp430_hcodes): Likewise..
2174
45d313cd
NC		 21752004-08-13 Nick Clifton <nickc@redhat.com>
2176
2177 PR/301
2178 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2179 processors.
2180
30d1c836
ML		 21812004-08-30 Michal Ludvig <mludvig@suse.cz>
2182
2183 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2184
9a45f1c2
L		 21852004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2186
2187 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2188
543613e9
NC		 21892004-07-21 Jan Beulich <jbeulich@novell.com>
2190
2191 * i386.h: Adjust instruction descriptions to better match the
2192 specification.
2193
b781e558
RE		 21942004-07-16 Richard Earnshaw <rearnsha@arm.com>
2195
2196 * arm.h: Remove all old content. Replace with architecture defines
2197 from gas/config/tc-arm.c.
2198
8577e690
AS		 21992004-07-09 Andreas Schwab <schwab@suse.de>
2200
2201 * m68k.h: Fix comment.
2202
1fe1f39c
NC		 22032004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2204
2205 * crx.h: New file.
2206
1d9f512f
AM		 22072004-06-24 Alan Modra <amodra@bigpond.net.au>
2208
2209 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2210
be8c092b
NC		 22112004-05-24 Peter Barada <peter@the-baradas.com>
2212
2213 * m68k.h: Add 'size' to m68k_opcode.
2214
6b6e92f4
NC		 22152004-05-05 Peter Barada <peter@the-baradas.com>
2216
2217 * m68k.h: Switch from ColdFire chip name to core variant.
2218
22192004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2220
2221 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2222 descriptions for new EMAC cases.
2223 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2224 handle Motorola MAC syntax.
2225 Allow disassembly of ColdFire V4e object files.
2226
fdd12ef3
AM		 22272004-03-16 Alan Modra <amodra@bigpond.net.au>
2228
2229 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2230
3922a64c
L		 22312004-03-12 Jakub Jelinek <jakub@redhat.com>
2232
2233 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2234
1f45d988
ML		 22352004-03-12 Michal Ludvig <mludvig@suse.cz>
2236
2237 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2238
0f10071e
ML		 22392004-03-12 Michal Ludvig <mludvig@suse.cz>
2240
2241 * i386.h (i386_optab): Added xstore/xcrypt insns.
2242
3255318a
NC		 22432004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2244
2245 * h8300.h (32bit ldc/stc): Add relaxing support.
2246
ca9a79a1 22472004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2248
ca9a79a1
NC		 2249 * h8300.h (BITOP): Pass MEMRELAX flag.
2250
875a0b14
NC		 22512004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2252
2253 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2254 except for the H8S.
252b5132 2255
c9e214e5 2256For older changes see ChangeLog-9103
252b5132 2257\f
b90efa5b 2258Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2259
2260Copying and distribution of this file, with or without modification,
2261are permitted in any medium without royalty provided the copyright
2262notice and this notice are preserved.
2263
252b5132 2264Local Variables:
c9e214e5
AM		 2265mode: change-log
2266left-margin: 8
2267fill-column: 74
252b5132
RH		 2268version-control: never
2269End:
GDB Binutils - Deliverables
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