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[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
d6bf7ce6
MW		 12015-12-10 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
4
ea2deeec
MW		 52015-12-10 Matthew Wahab <matthew.wahab@arm.com>
6
7 * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
8 (aarch64_sys_ins_reg_has_xt): Declare.
9
c8a6db6f
MW		 102015-12-10 Matthew Wahab <matthew.wahab@arm.com>
11
12 * aarch64.h (AARCH64_FEATURE_RAS): New.
13 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
14
af117b3c
MW		 152015-12-10 Matthew Wahab <matthew.wahab@arm.com>
16
17 * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
18 AARCH64_FEATURE_V8_1.
19 (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
20 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
21 AARCH64_FEATURE_V8_1.
22
24b368f8
CZ		 232015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
24
25 * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
26
d685192a
MW		 272015-11-27 Matthew Wahab <matthew.wahab@arm.com>
28
29 * aarch64.h (aarch64_op): Add OP_BFC.
30
87018195
MW		 312015-11-27 Matthew Wahab <matthew.wahab@arm.com>
32
33 * aarch64.h (AARCH64_FEATURE_F16): New.
34 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
35 features.
36
250aafa4
MW		 372015-11-20 Matthew Wahab <matthew.wahab@arm.com>
38
39 * aarch64.h (AARCH64_FEATURE_V8_1): New.
40 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
41
56a1b672
MW		 422015-11-19 Matthew Wahab <matthew.wahab@arm.com>
43
44 * arm.h (ARM_EXT2_V8_2A): New.
45 (ARM_ARCH_V8_2A): New.
46
acb787b0
MW		 472015-11-19 Matthew Wahab <matthew.wahab@arm.com>
48
49 * aarch64.h (AARCH64_FEATURE_V8_2): New.
50 (AARCH64_ARCH_V8_2): New.
51
a680de9a
PB		 522015-11-11 Alan Modra <amodra@gmail.com>
53 Peter Bergner <bergner@vnet.ibm.com>
54
55 * ppc.h (PPC_OPCODE_POWER9): New define.
56 (PPC_OPCODE_VSX3): Likewise.
57
854eb72b
NC		 582015-11-02 Nick Clifton <nickc@redhat.com>
59
60 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
61
e292aa7a
NC		 622015-11-02 Nick Clifton <nickc@redhat.com>
63
64 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
65
43cdf5ae
YQ		 662015-10-28 Yao Qi <yao.qi@linaro.org>
67
68 * aarch64.h (aarch64_decode_insn): Update declaration.
69
875880c6
YQ		 702015-10-07 Yao Qi <yao.qi@linaro.org>
71
72 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
73 <name>: New field.
74
d3e12b29
YQ		 752015-10-07 Yao Qi <yao.qi@linaro.org>
76
77 * aarch64.h [__cplusplus]: Wrap in extern "C".
78
886a2506
NC		 792015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
80 Cupertino Miranda <cmiranda@synopsys.com>
81
82 * arc-func.h: New file.
83 * arc.h: Likewise.
84
e141d84e
YQ		 852015-10-02 Yao Qi <yao.qi@linaro.org>
86
87 * aarch64.h (aarch64_zero_register_p): Move the declaration
88 to column one.
89
36f4aab1
YQ		 902015-10-02 Yao Qi <yao.qi@linaro.org>
91
92 * aarch64.h (aarch64_decode_insn): Declare it.
93
7ecc513a
DV		 942015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
95
96 * s390.h (S390_INSTR_FLAG_HTM): New flag.
97 (S390_INSTR_FLAG_VX): New flag.
98 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
99
b6518b38
NC		 1002015-09-23 Nick Clifton <nickc@redhat.com>
101
102 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
103 shifting.
104
f04265ec
NC		 1052015-09-22 Nick Clifton <nickc@redhat.com>
106
107 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
108
7bdf96ef
NC		 1092015-09-09 Daniel Santos <daniel.santos@pobox.com>
110
111 * visium.h (gen_reg_table): Make static.
112 (fp_reg_table): Likewise.
113 (cc_table): Likewise.
114
f33026a9
MW		 1152015-07-20 Matthew Wahab <matthew.wahab@arm.com>
116
117 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
118 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
119 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
120 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
121
ef5a96d5
AM		 1222015-07-03 Alan Modra <amodra@gmail.com>
123
124 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
125
c8c8175b
SL		 1262015-07-01 Sandra Loosemore <sandra@codesourcery.com>
127 Cesar Philippidis <cesar@codesourcery.com>
128
129 * nios2.h (enum iw_format_type): Add R2 formats.
130 (enum overflow_type): Add signed_immed12_overflow and
131 enumeration_overflow for R2.
132 (struct nios2_opcode): Document new argument letters for R2.
133 (REG_3BIT, REG_LDWM, REG_POP): Define.
134 (includes): Include nios2r2.h.
135 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
136 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
137 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
138 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
139 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
140 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
141 Declare.
142 * nios2r2.h: New file.
143
11a0cf2e
PB		 1442015-06-19 Peter Bergner <bergner@vnet.ibm.com>
145
146 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
147 (ppc_optional_operand_value): New inline function.
148
88f0ea34
MW		 1492015-06-04 Matthew Wahab <matthew.wahab@arm.com>
150
151 * aarch64.h (AARCH64_V8_1): New.
152
a5932920
MW		 1532015-06-03 Matthew Wahab <matthew.wahab@arm.com>
154
155 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
156 (ARM_ARCH_V8_1A): New.
157 (ARM_ARCH_V8_1A_FP): New.
158 (ARM_ARCH_V8_1A_SIMD): New.
159 (ARM_ARCH_V8_1A_CRYPTOV1): New.
160 (ARM_FEATURE_CORE): New.
161
ddfded2f
MW		 1622015-06-02 Matthew Wahab <matthew.wahab@arm.com>
163
164 * arm.h (ARM_EXT2_PAN): New.
165 (ARM_FEATURE_CORE_HIGH): New.
166
1af1dd51
MW		 1672015-06-02 Matthew Wahab <matthew.wahab@arm.com>
168
169 * arm.h (ARM_FEATURE_ALL): New.
170
9e1f0fa7
MW		 1712015-06-02 Matthew Wahab <matthew.wahab@arm.com>
172
173 * aarch64.h (AARCH64_FEATURE_RDMA): New.
174
290806fd
MW		 1752015-06-02 Matthew Wahab <matthew.wahab@arm.com>
176
177 * aarch64.h (AARCH64_FEATURE_LOR): New.
178
f21cce2c
MW		 1792015-06-01 Matthew Wahab <matthew.wahab@arm.com>
180
181 * aarch64.h (AARCH64_FEATURE_PAN): New.
182 (aarch64_sys_reg_supported_p): Declare.
183 (aarch64_pstatefield_supported_p): Declare.
184
0952813b
DD		 1852015-04-30 DJ Delorie <dj@redhat.com>
186
187 * rl78.h (RL78_Dis_Isa): New.
188 (rl78_decode_opcode): Add ISA parameter.
189
823d2571
TG		 1902015-03-24 Terry Guo <terry.guo@arm.com>
191
192 * arm.h (arm_feature_set): Extended to provide more available bits.
193 (ARM_ANY): Updated to follow above new definition.
194 (ARM_CPU_HAS_FEATURE): Likewise.
195 (ARM_CPU_IS_ANY): Likewise.
196 (ARM_MERGE_FEATURE_SETS): Likewise.
197 (ARM_CLEAR_FEATURE): Likewise.
198 (ARM_FEATURE): Likewise.
199 (ARM_FEATURE_COPY): New macro.
200 (ARM_FEATURE_EQUAL): Likewise.
201 (ARM_FEATURE_ZERO): Likewise.
202 (ARM_FEATURE_CORE_EQUAL): Likewise.
203 (ARM_FEATURE_LOW): Likewise.
204 (ARM_FEATURE_CORE_LOW): Likewise.
205 (ARM_FEATURE_CORE_COPROC): Likewise.
206
f63c1776
PA		 2072015-02-19 Pedro Alves <palves@redhat.com>
208
209 * cgen.h [__cplusplus]: Wrap in extern "C".
210 * msp430-decode.h [__cplusplus]: Likewise.
211 * nios2.h [__cplusplus]: Likewise.
212 * rl78.h [__cplusplus]: Likewise.
213 * rx.h [__cplusplus]: Likewise.
214 * tilegx.h [__cplusplus]: Likewise.
215
3f8107ab
AM		 2162015-01-28 James Bowman <james.bowman@ftdichip.com>
217
218 * ft32.h: New file.
219
1e2e8c52
AK		 2202015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
221
222 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
223
b90efa5b
AM		 2242015-01-01 Alan Modra <amodra@gmail.com>
225
226 Update year range in copyright notice of all files.
227
bffb6004
AG		 2282014-12-27 Anthony Green <green@moxielogic.com>
229
230 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
231 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
232
1945cfa5
EB		 2332014-12-06 Eric Botcazou <ebotcazou@adacore.com>
234
235 * visium.h: New file.
236
d306ce58
SL		 2372014-11-28 Sandra Loosemore <sandra@codesourcery.com>
238
239 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
240 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
241 (NIOS2_INSN_OPTARG): Renumber.
242
b4714c7c
SL		 2432014-11-06 Sandra Loosemore <sandra@codesourcery.com>
244
245 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
246 declaration. Fix obsolete comment.
247
96ba4233
SL		 2482014-10-23 Sandra Loosemore <sandra@codesourcery.com>
249
250 * nios2.h (enum iw_format_type): New.
251 (struct nios2_opcode): Update comments. Add size and format fields.
252 (NIOS2_INSN_OPTARG): New.
253 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
254 (struct nios2_reg): Add regtype field.
255 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
256 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
257 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
258 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
259 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
260 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
261 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
262 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
263 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
264 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
265 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
266 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
267 (OP_MASK_OP, OP_SH_OP): Delete.
268 (OP_MASK_IOP, OP_SH_IOP): Delete.
269 (OP_MASK_IRD, OP_SH_IRD): Delete.
270 (OP_MASK_IRT, OP_SH_IRT): Delete.
271 (OP_MASK_IRS, OP_SH_IRS): Delete.
272 (OP_MASK_ROP, OP_SH_ROP): Delete.
273 (OP_MASK_RRD, OP_SH_RRD): Delete.
274 (OP_MASK_RRT, OP_SH_RRT): Delete.
275 (OP_MASK_RRS, OP_SH_RRS): Delete.
276 (OP_MASK_JOP, OP_SH_JOP): Delete.
277 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
278 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
279 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
280 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
281 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
282 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
283 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
284 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
285 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
286 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
287 (OP_MASK_<insn>, OP_MASK): Delete.
288 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
289 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
290 Include nios2r1.h to define new instruction opcode constants
291 and accessors.
292 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
293 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
294 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
295 (NUMOPCODES, NUMREGISTERS): Delete.
296 * nios2r1.h: New file.
297
0b6be415
JM		 2982014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
299
300 * sparc.h (HWCAP2_VIS3B): Documentation improved.
301
3d68f91c
JM		 3022014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
303
304 * sparc.h (sparc_opcode): new field `hwcaps2'.
305 (HWCAP2_FJATHPLUS): New define.
306 (HWCAP2_VIS3B): Likewise.
307 (HWCAP2_ADP): Likewise.
308 (HWCAP2_SPARC5): Likewise.
309 (HWCAP2_MWAIT): Likewise.
310 (HWCAP2_XMPMUL): Likewise.
311 (HWCAP2_XMONT): Likewise.
312 (HWCAP2_NSEC): Likewise.
313 (HWCAP2_FJATHHPC): Likewise.
314 (HWCAP2_FJDES): Likewise.
315 (HWCAP2_FJAES): Likewise.
316 Document the new operand kind `{', corresponding to the mcdper
317 ancillary state register.
318 Document the new operand kind }, which represents frsd floating
319 point registers (double precision) which must be the same than
320 frs1 in its containing instruction.
321
40c7a7cb
KLC		 3222014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
323
72f4393d 324 * nds32.h: Add new opcode declaration.
40c7a7cb 325
7361da2c
AB		 3262014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
327 Matthew Fortune <matthew.fortune@imgtec.com>
328
329 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
330 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
331 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
332 +I, +O, +R, +:, +\, +", +;
333 (mips_check_prev_operand): New struct.
334 (INSN2_FORBIDDEN_SLOT): New define.
335 (INSN_ISA32R6): New define.
336 (INSN_ISA64R6): New define.
337 (INSN_UPTO32R6): New define.
338 (INSN_UPTO64R6): New define.
339 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
340 (ISA_MIPS32R6): New define.
341 (ISA_MIPS64R6): New define.
342 (CPU_MIPS32R6): New define.
343 (CPU_MIPS64R6): New define.
344 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
345
ee804238
JW		 3462014-09-03 Jiong Wang <jiong.wang@arm.com>
347
348 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
349 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
350 (aarch64_insn_class): Add lse_atomic.
351 (F_LSE_SZ): New field added.
352 (opcode_has_special_coder): Recognize F_LSE_SZ.
353
5575639b
MR		 3542014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
355
356 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
357 over to `+J'.
358
43885403
MF		 3592014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
360
361 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
362 (INSN_LOAD_COPROC): New define.
363 (INSN_COPROC_MOVE_DELAY): Rename to...
364 (INSN_COPROC_MOVE): New define.
365
f36e8886 3662014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 367 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
368 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
369 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 370
371 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
372 (AVR_ISA_2xxxa): Define ISA without LPM.
373 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
374 Add doc for contraint used in 16 bit lds/sts.
375 Adjust ISA group for icall, ijmp, pop and push.
376 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
377
00b32ff2
NC		 3782014-05-19 Nick Clifton <nickc@redhat.com>
379
380 * msp430.h (struct msp430_operand_s): Add vshift field.
381
ae52f483
AB		 3822014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
383
384 * mips.h (INSN_ISA_MASK): Updated.
385 (INSN_ISA32R3): New define.
386 (INSN_ISA32R5): New define.
387 (INSN_ISA64R3): New define.
388 (INSN_ISA64R5): New define.
389 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
390 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
391 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
392 mips64r5.
393 (INSN_UPTO32R3): New define.
394 (INSN_UPTO32R5): New define.
395 (INSN_UPTO64R3): New define.
396 (INSN_UPTO64R5): New define.
397 (ISA_MIPS32R3): New define.
398 (ISA_MIPS32R5): New define.
399 (ISA_MIPS64R3): New define.
400 (ISA_MIPS64R5): New define.
401 (CPU_MIPS32R3): New define.
402 (CPU_MIPS32R5): New define.
403 (CPU_MIPS64R3): New define.
404 (CPU_MIPS64R5): New define.
405
3efe9ec5
RS		 4062014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
407
408 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
409
73589c9d
CS		 4102014-04-22 Christian Svensson <blue@cmd.nu>
411
412 * or32.h: Delete.
413
4b95cf5c
AM		 4142014-03-05 Alan Modra <amodra@gmail.com>
415
416 Update copyright years.
417
e269fea7
AB		 4182013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
419
420 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
421 microMIPS.
422
35c08157
KLC		 4232013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
424 Wei-Cheng Wang <cole945@gmail.com>
425
426 * nds32.h: New file for Andes NDS32.
427
594d8fa8
MF		 4282013-12-07 Mike Frysinger <vapier@gentoo.org>
429
430 * bfin.h: Remove +x file mode.
431
87b8eed7
YZ		 4322013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
433
434 * aarch64.h (aarch64_pstatefields): Change element type to
435 aarch64_sys_reg.
436
c9fb6e58
YZ		 4372013-11-18 Renlin Li <Renlin.Li@arm.com>
438
439 * arm.h (ARM_AEXT_V7VE): New define.
440 (ARM_ARCH_V7VE): New define.
441 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
442
a203d9b7
YZ		 4432013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
444
445 Revert
446
447 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
448
449 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
450 (aarch64_sys_reg_writeonly_p): Ditto.
451
75468c93
YZ		 4522013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
453
454 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
455 (aarch64_sys_reg_writeonly_p): Ditto.
456
49eec193
YZ		 4572013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
458
459 * aarch64.h (aarch64_sys_reg): New typedef.
460 (aarch64_sys_regs): Change to define with the new type.
461 (aarch64_sys_reg_deprecated_p): Declare.
462
68a64283
YZ		 4632013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
464
465 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
466 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
467
387a82f1
CF		 4682013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
469
470 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
471 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
472 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
473 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
474 For MIPS, update extension character sequences after +.
475 (ASE_MSA): New define.
476 (ASE_MSA64): New define.
477 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
478 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
479 For microMIPS, update extension character sequences after +.
480
9aff4b7a
NC		 4812013-08-23 Yuri Chornoivan <yurchor@ukr.net>
482
483 PR binutils/15834
484 * i960.h: Fix typos.
485
e423441d
RS		 4862013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
487
488 * mips.h: Remove references to "+I" and imm2_expr.
489
5e0dc5ba
RS		 4902013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
491
492 * mips.h (M_DEXT, M_DINS): Delete.
493
0f35dbc4
RS		 4942013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
495
496 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
497 (mips_optional_operand_p): New function.
498
14daeee3
RS		 4992013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
500 Richard Sandiford <rdsandiford@googlemail.com>
501
502 * mips.h: Document new VU0 operand characters.
503 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
504 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
505 (OP_REG_R5900_ACC): New mips_reg_operand_types.
506 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
507 (mips_vu0_channel_mask): Declare.
508
3ccad066
RS		 5092013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
510
511 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
512 (mips_int_operand_min, mips_int_operand_max): New functions.
513 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
514
fc76e730
RS		 5152013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
516
517 * mips.h (mips_decode_reg_operand): New function.
518 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
519 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
520 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
521 New macros.
522 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
523 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
524 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
525 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
526 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
527 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
528 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
529 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
530 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
531 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
532 macros to cover the gaps.
533 (INSN2_MOD_SP): Replace with...
534 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
535 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
536 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
537 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
538 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
539 Delete.
540
26545944
RS		 5412013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
542
543 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
544 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
545 (MIPS16_INSN_COND_BRANCH): Delete.
546
7e8b059b
L		 5472013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
548 Kirill Yukhin <kirill.yukhin@intel.com>
549 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
550
551 * i386.h (BND_PREFIX_OPCODE): New.
552
c3c07478
RS		 5532013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
554
555 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
556 OP_SAVE_RESTORE_LIST.
557 (decode_mips16_operand): Declare.
558
ab902481
RS		 5592013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
560
561 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
562 (mips_operand, mips_int_operand, mips_mapped_int_operand)
563 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
564 (mips_pcrel_operand): New structures.
565 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
566 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
567 (decode_mips_operand, decode_micromips_operand): Declare.
568
cc537e56
RS		 5692013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
570
571 * mips.h: Document MIPS16 "I" opcode.
572
f2ae14a1
RS		 5732013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
574
575 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
576 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
577 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
578 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
579 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
580 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
581 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
582 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
583 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
584 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
585 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
586 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
587 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
588 Rename to...
589 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
590 (M_USD_AB): ...these.
591
5c324c16
RS		 5922013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
593
594 * mips.h: Remove documentation of "[" and "]". Update documentation
595 of "k" and the MDMX formats.
596
23e69e47
RS		 5972013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
598
599 * mips.h: Update documentation of "+s" and "+S".
600
27c5c572
RS		 6012013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
602
603 * mips.h: Document "+i".
604
e76ff5ab
RS		 6052013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
606
607 * mips.h: Remove "mi" documentation. Update "mh" documentation.
608 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
609 Delete.
610 (INSN2_WRITE_GPR_MHI): Rename to...
611 (INSN2_WRITE_GPR_MH): ...this.
612
fa7616a4
RS		 6132013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
614
615 * mips.h: Remove documentation of "+D" and "+T".
616
18870af7
RS		 6172013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
618
619 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
620 Use "source" rather than "destination" for microMIPS "G".
621
833794fc
MR		 6222013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
623
624 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
625 values.
626
c3678916
RS		 6272013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
628
629 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
630
7f3c4072
CM		 6312013-06-17 Catherine Moore <clm@codesourcery.com>
632 Maciej W. Rozycki <macro@codesourcery.com>
633 Chao-Ying Fu <fu@mips.com>
634
635 * mips.h (OP_SH_EVAOFFSET): Define.
636 (OP_MASK_EVAOFFSET): Define.
637 (INSN_ASE_MASK): Delete.
638 (ASE_EVA): Define.
639 (M_CACHEE_AB, M_CACHEE_OB): New.
640 (M_LBE_OB, M_LBE_AB): New.
641 (M_LBUE_OB, M_LBUE_AB): New.
642 (M_LHE_OB, M_LHE_AB): New.
643 (M_LHUE_OB, M_LHUE_AB): New.
644 (M_LLE_AB, M_LLE_OB): New.
645 (M_LWE_OB, M_LWE_AB): New.
646 (M_LWLE_AB, M_LWLE_OB): New.
647 (M_LWRE_AB, M_LWRE_OB): New.
648 (M_PREFE_AB, M_PREFE_OB): New.
649 (M_SCE_AB, M_SCE_OB): New.
650 (M_SBE_OB, M_SBE_AB): New.
651 (M_SHE_OB, M_SHE_AB): New.
652 (M_SWE_OB, M_SWE_AB): New.
653 (M_SWLE_AB, M_SWLE_OB): New.
654 (M_SWRE_AB, M_SWRE_OB): New.
655 (MICROMIPSOP_SH_EVAOFFSET): Define.
656 (MICROMIPSOP_MASK_EVAOFFSET): Define.
657
0c8fe7cf
SL		 6582013-06-12 Sandra Loosemore <sandra@codesourcery.com>
659
660 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
661
c77c0862
RS		 6622013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
663
664 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
665
b015e599
AP		 6662013-05-09 Andrew Pinski <apinski@cavium.com>
667
668 * mips.h (OP_MASK_CODE10): Correct definition.
669 (OP_SH_CODE10): Likewise.
670 Add a comment that "+J" is used now for OP_*CODE10.
671 (INSN_ASE_MASK): Update.
672 (INSN_VIRT): New macro.
673 (INSN_VIRT64): New macro
674
13761a11
NC		 6752013-05-02 Nick Clifton <nickc@redhat.com>
676
677 * msp430.h: Add patterns for MSP430X instructions.
678
0afd1215
DM		 6792013-04-06 David S. Miller <davem@davemloft.net>
680
681 * sparc.h (F_PREFERRED): Define.
682 (F_PREF_ALIAS): Define.
683
41702d50
NC		 6842013-04-03 Nick Clifton <nickc@redhat.com>
685
686 * v850.h (V850_INVERSE_PCREL): Define.
687
e21e1a51
NC		 6882013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
689
690 PR binutils/15068
691 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
692
51dcdd4d
NC		 6932013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
694
695 PR binutils/15068
696 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
697 Add 16-bit opcodes.
698 * tic6xc-opcode-table.h: Add 16-bit insns.
699 * tic6x.h: Add support for 16-bit insns.
700
81f5558e
NC		 7012013-03-21 Michael Schewe <michael.schewe@gmx.net>
702
703 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
704 and mov.b/w/l Rs,@(d:32,ERd).
705
165546ad
NC		 7062013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
707
708 PR gas/15082
709 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
710 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
711 tic6x_operand_xregpair operand coding type.
712 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
713 opcode field, usu ORXREGD1324 for the src2 operand and remove the
714 TIC6X_FLAG_NO_CROSS.
715
795b8e6b
NC		 7162013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
717
718 PR gas/15095
719 * tic6x.h (enum tic6x_coding_method): Add
720 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
721 separately the msb and lsb of a register pair. This is needed to
722 encode the opcodes in the same way as TI assembler does.
723 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
724 and rsqrdp opcodes to use the new field coding types.
725
dd5181d5
KT		 7262013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
727
728 * arm.h (CRC_EXT_ARMV8): New constant.
729 (ARCH_CRC_ARMV8): New macro.
730
e60bb1dd
YZ		 7312013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
732
733 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
734
36591ba1 7352013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 736 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 737
738 Based on patches from Altera Corporation.
739
740 * nios2.h: New file.
741
e30181a5
YZ		 7422013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
743
744 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
745
0c9573f4
NC		 7462013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
747
748 PR gas/15069
749 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
750
981dc7f1
NC		 7512013-01-24 Nick Clifton <nickc@redhat.com>
752
753 * v850.h: Add e3v5 support.
754
f5555712
YZ		 7552013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
756
757 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
758
5817ffd1
PB		 7592013-01-10 Peter Bergner <bergner@vnet.ibm.com>
760
761 * ppc.h (PPC_OPCODE_POWER8): New define.
762 (PPC_OPCODE_HTM): Likewise.
763
a3c62988
NC		 7642013-01-10 Will Newton <will.newton@imgtec.com>
765
766 * metag.h: New file.
767
73335eae
NC		 7682013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
769
770 * cr16.h (make_instruction): Rename to cr16_make_instruction.
771 (match_opcode): Rename to cr16_match_opcode.
772
e407c74b
NC		 7732013-01-04 Juergen Urban <JuergenUrban@gmx.de>
774
775 * mips.h: Add support for r5900 instructions including lq and sq.
776
bab4becb
NC		 7772013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
778
779 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
780 (make_instruction,match_opcode): Added function prototypes.
781 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
782
776fc418
AM		 7832012-11-23 Alan Modra <amodra@gmail.com>
784
785 * ppc.h (ppc_parse_cpu): Update prototype.
786
f05682d4
DA		 7872012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
788
789 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
790 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
791
cfc72779
AK		 7922012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
793
794 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
795
b3e14eda
L		 7962012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
797
798 * ia64.h (ia64_opnd): Add new operand types.
799
2c63854f
DM		 8002012-08-21 David S. Miller <davem@davemloft.net>
801
802 * sparc.h (F3F4): New macro.
803
a06ea964 8042012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 805 Laurent Desnogues <laurent.desnogues@arm.com>
806 Jim MacArthur <jim.macarthur@arm.com>
807 Marcus Shawcroft <marcus.shawcroft@arm.com>
808 Nigel Stephens <nigel.stephens@arm.com>
809 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
810 Richard Earnshaw <rearnsha@arm.com>
811 Sofiane Naci <sofiane.naci@arm.com>
812 Tejas Belagod <tejas.belagod@arm.com>
813 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 814
815 * aarch64.h: New file.
816
35d0a169 8172012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 818 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 819
820 * mips.h (mips_opcode): Add the exclusions field.
821 (OPCODE_IS_MEMBER): Remove macro.
822 (cpu_is_member): New inline function.
823 (opcode_is_member): Likewise.
824
03f66e8a 8252012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 826 Catherine Moore <clm@codesourcery.com>
827 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 828
829 * mips.h: Document microMIPS DSP ASE usage.
830 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
831 microMIPS DSP ASE support.
832 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
833 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
834 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
835 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
836 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
837 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
838 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
839
9d7b4c23
MR		 8402012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
841
842 * mips.h: Fix a typo in description.
843
76e879f8
NC		 8442012-06-07 Georg-Johann Lay <avr@gjlay.de>
845
846 * avr.h: (AVR_ISA_XCH): New define.
847 (AVR_ISA_XMEGA): Use it.
848 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
849
6927f982
NC		 8502012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
851
852 * m68hc11.h: Add XGate definitions.
853 (struct m68hc11_opcode): Add xg_mask field.
854
b9c361e0
JL		 8552012-05-14 Catherine Moore <clm@codesourcery.com>
856 Maciej W. Rozycki <macro@codesourcery.com>
857 Rhonda Wittels <rhonda@codesourcery.com>
858
6927f982 859 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 860 (PPC_OP_SA): New macro.
861 (PPC_OP_SE_VLE): New macro.
862 (PPC_OP): Use a variable shift amount.
863 (powerpc_operand): Update comments.
864 (PPC_OPSHIFT_INV): New macro.
865 (PPC_OPERAND_CR): Replace with...
866 (PPC_OPERAND_CR_BIT): ...this and
867 (PPC_OPERAND_CR_REG): ...this.
868
869
f6c1a2d5
NC		 8702012-05-03 Sean Keys <skeys@ipdatasys.com>
871
872 * xgate.h: Header file for XGATE assembler.
873
ec668d69
DM		 8742012-04-27 David S. Miller <davem@davemloft.net>
875
6cda1326
DM		 876 * sparc.h: Document new arg code' )' for crypto RS3
877 immediates.
878
ec668d69
DM		 879 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
880 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
881 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
882 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
883 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
884 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
885 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
886 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
887 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
888 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
889 HWCAP_CBCOND, HWCAP_CRC32): New defines.
890
aea77599
AM		 8912012-03-10 Edmar Wienskoski <edmar@freescale.com>
892
893 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
894
1f42f8b3
AM		 8952012-02-27 Alan Modra <amodra@gmail.com>
896
897 * crx.h (cst4_map): Update declaration.
898
6f7be959
WL		 8992012-02-25 Walter Lee <walt@tilera.com>
900
901 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
902 TILEGX_OPC_LD_TLS.
903 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
904 TILEPRO_OPC_LW_TLS_SN.
905
42164a71
L		 9062012-02-08 H.J. Lu <hongjiu.lu@intel.com>
907
908 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
909 (XRELEASE_PREFIX_OPCODE): Likewise.
910
432233b3 9112011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 912 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 913
914 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
915 (INSN_OCTEON2): New macro.
916 (CPU_OCTEON2): New macro.
917 (OPCODE_IS_MEMBER): Add Octeon2.
918
dd6a37e7
AP		 9192011-11-29 Andrew Pinski <apinski@cavium.com>
920
921 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
922 (INSN_OCTEONP): New macro.
923 (CPU_OCTEONP): New macro.
924 (OPCODE_IS_MEMBER): Add Octeon+.
925 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
926
99c513f6
DD		 9272011-11-01 DJ Delorie <dj@redhat.com>
928
929 * rl78.h: New file.
930
26f85d7a
MR		 9312011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
932
933 * mips.h: Fix a typo in description.
934
9e8c70f9
DM		 9352011-09-21 David S. Miller <davem@davemloft.net>
936
937 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
938 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
939 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
940 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
941
dec0624d 9422011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 943 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 944
945 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
946 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
947 (INSN_ASE_MASK): Add the MCU bit.
948 (INSN_MCU): New macro.
949 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
950 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
951
2b0c8b40
MR		 9522011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
953
954 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
955 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
956 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
957 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
958 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
959 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
960 (INSN2_READ_GPR_MMN): Likewise.
961 (INSN2_READ_FPR_D): Change the bit used.
962 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
963 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
964 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
965 (INSN2_COND_BRANCH): Likewise.
966 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
967 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
968 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
969 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
970 (INSN2_MOD_GPR_MN): Likewise.
971
ea783ef3
DM		 9722011-08-05 David S. Miller <davem@davemloft.net>
973
974 * sparc.h: Document new format codes '4', '5', and '('.
975 (OPF_LOW4, RS3): New macros.
976
7c176fa8
MR		 9772011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
978
979 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
980 order of flags documented.
981
2309ddf2
MR		 9822011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
983
984 * mips.h: Clarify the description of microMIPS instruction
985 manipulation macros.
986 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
987
df58fc94 9882011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 989 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 990
991 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
992 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
993 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
994 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
995 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
996 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
997 (OP_MASK_RS3, OP_SH_RS3): Likewise.
998 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
999 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
1000 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
1001 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
1002 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
1003 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
1004 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
1005 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
1006 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
1007 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
1008 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
1009 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
1010 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
1011 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
1012 (INSN_WRITE_GPR_S): New macro.
1013 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
1014 (INSN2_READ_FPR_D): Likewise.
1015 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
1016 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
1017 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
1018 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
1019 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
1020 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
1021 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
1022 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
1023 (CPU_MICROMIPS): New macro.
1024 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
1025 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1026 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1027 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1028 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1029 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1030 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1031 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1032 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1033 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1034 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1035 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1036 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1037 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1038 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1039 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1040 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1041 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1042 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1043 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1044 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1045 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1046 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1047 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1048 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1049 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1050 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1051 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1052 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1053 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1054 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1055 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1056 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1057 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1058 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1059 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1060 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1061 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1062 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1063 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1064 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1065 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1066 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1067 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1068 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1069 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1070 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1071 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1072 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1073 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1074 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1075 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1076 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1077 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1078 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1079 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1080 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1081 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1082 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1083 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1084 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1085 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1086 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1087 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1088 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1089 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1090 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1091 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1092 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1093 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1094 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1095 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1096 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1097 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1098 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1099 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1100 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1101 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1102 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1103 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1104 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1105 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1106 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1107 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1108 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1109 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1110 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1111 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1112 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1113 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1114 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1115 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1116 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1117 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1118 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1119 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1120 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1121 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1122 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1123 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1124 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1125 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1126 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1127 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1128 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1129 (micromips_opcodes): New declaration.
1130 (bfd_micromips_num_opcodes): Likewise.
1131
bcd530a7
RS		 11322011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1133
1134 * mips.h (INSN_TRAP): Rename to...
1135 (INSN_NO_DELAY_SLOT): ... this.
1136 (INSN_SYNC): Remove macro.
1137
2dad5a91
EW		 11382011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1139
1140 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1141 a duplicate of AVR_ISA_SPM.
1142
5d73b1f1
NC		 11432011-07-01 Nick Clifton <nickc@redhat.com>
1144
1145 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1146
ef26d60e
MF		 11472011-06-18 Robin Getz <robin.getz@analog.com>
1148
1149 * bfin.h (is_macmod_signed): New func
1150
8fb8dca7
MF		 11512011-06-18 Mike Frysinger <vapier@gentoo.org>
1152
1153 * bfin.h (is_macmod_pmove): Add missing space before func args.
1154 (is_macmod_hmove): Likewise.
1155
aa137e4d
NC		 11562011-06-13 Walter Lee <walt@tilera.com>
1157
1158 * tilegx.h: New file.
1159 * tilepro.h: New file.
1160
3b2f0793
PB		 11612011-05-31 Paul Brook <paul@codesourcery.com>
1162
aa137e4d
NC		 1163 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1164
11652011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1166
1167 * s390.h: Replace S390_OPERAND_REG_EVEN with
1168 S390_OPERAND_REG_PAIR.
1169
11702011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1171
1172 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1173
ac7f631b
NC		 11742011-04-18 Julian Brown <julian@codesourcery.com>
1175
1176 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1177
84701018
NC		 11782011-04-11 Dan McDonald <dan@wellkeeper.com>
1179
1180 PR gas/12296
1181 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1182
8cc66334
EW		 11832011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1184
1185 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1186 New instruction set flags.
1187 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1188
3eebd5eb
MR		 11892011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1190
1191 * mips.h (M_PREF_AB): New enum value.
1192
26bb3ddd
MF		 11932011-02-12 Mike Frysinger <vapier@gentoo.org>
1194
89c0d58c
MR		 1195 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1196 M_IU): Define.
1197 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1198
dd76fcb8
MF		 11992011-02-11 Mike Frysinger <vapier@gentoo.org>
1200
1201 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1202
98d23bef
BS		 12032011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1204
1205 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1206 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1207
3c853d93
DA		 12082010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1209
1210 PR gas/11395
1211 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1212 "bb" entries.
1213
79676006
DA		 12142010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1215
1216 PR gas/11395
1217 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1218
1bec78e9
RS		 12192010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1220
1221 * mips.h: Update commentary after last commit.
1222
98675402
RS		 12232010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1224
1225 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1226 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1227 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1228
aa137e4d
NC		 12292010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1230
1231 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1232
435b94a4
RS		 12332010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1234
1235 * mips.h: Fix previous commit.
1236
d051516a
NC		 12372010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1238
1239 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1240 (INSN_LOONGSON_3A): Clear bit 31.
1241
251665fc
MGD		 12422010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1243
1244 PR gas/12198
1245 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1246 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1247 (ARM_ARCH_V6M_ONLY): New define.
1248
fd503541
NC		 12492010-11-11 Mingming Sun <mingm.sun@gmail.com>
1250
1251 * mips.h (INSN_LOONGSON_3A): Defined.
1252 (CPU_LOONGSON_3A): Defined.
1253 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1254
4469d2be
AM		 12552010-10-09 Matt Rice <ratmice@gmail.com>
1256
1257 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1258 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1259
90ec0d68
MGD		 12602010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1261
1262 * arm.h (ARM_EXT_VIRT): New define.
1263 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1264 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1265 Extensions.
1266
eea54501 12672010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1268
eea54501
MGD		 1269 * arm.h (ARM_AEXT_ADIV): New define.
1270 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1271
b2a5fbdc
MGD		 12722010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1273
1274 * arm.h (ARM_EXT_OS): New define.
1275 (ARM_AEXT_V6SM): Likewise.
1276 (ARM_ARCH_V6SM): Likewise.
1277
60e5ef9f
MGD		 12782010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1279
1280 * arm.h (ARM_EXT_MP): Add.
1281 (ARM_ARCH_V7A_MP): Likewise.
1282
73a63ccf
MF		 12832010-09-22 Mike Frysinger <vapier@gentoo.org>
1284
1285 * bfin.h: Declare pseudoChr structs/defines.
1286
ee99860a
MF		 12872010-09-21 Mike Frysinger <vapier@gentoo.org>
1288
1289 * bfin.h: Strip trailing whitespace.
1290
f9c7014e
DD		 12912010-07-29 DJ Delorie <dj@redhat.com>
1292
1293 * rx.h (RX_Operand_Type): Add TwoReg.
1294 (RX_Opcode_ID): Remove ediv and ediv2.
1295
93378652
DD		 12962010-07-27 DJ Delorie <dj@redhat.com>
1297
1298 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1299
1cd986c5
NC		 13002010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1301 Ina Pandit <ina.pandit@kpitcummins.com>
1302
1303 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1304 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1305 PROCESSOR_V850E2_ALL.
1306 Remove PROCESSOR_V850EA support.
1307 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1308 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1309 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1310 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1311 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1312 V850_OPERAND_PERCENT.
1313 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1314 V850_NOT_R0.
1315 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1316 and V850E_PUSH_POP
1317
9a2c7088
MR		 13182010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1319
1320 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1321 (MIPS16_INSN_BRANCH): Rename to...
1322 (MIPS16_INSN_COND_BRANCH): ... this.
1323
bdc70b4a
AM		 13242010-07-03 Alan Modra <amodra@gmail.com>
1325
1326 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1327 Renumber other PPC_OPCODE defines.
1328
f2bae120
AM		 13292010-07-03 Alan Modra <amodra@gmail.com>
1330
1331 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1332
360cfc9c
AM		 13332010-06-29 Alan Modra <amodra@gmail.com>
1334
1335 * maxq.h: Delete file.
1336
e01d869a
AM		 13372010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1338
1339 * ppc.h (PPC_OPCODE_E500): Define.
1340
f79e2745
CM		 13412010-05-26 Catherine Moore <clm@codesourcery.com>
1342
1343 * opcode/mips.h (INSN_MIPS16): Remove.
1344
2462afa1
JM		 13452010-04-21 Joseph Myers <joseph@codesourcery.com>
1346
1347 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1348
e4e42b45
NC		 13492010-04-15 Nick Clifton <nickc@redhat.com>
1350
1351 * alpha.h: Update copyright notice to use GPLv3.
1352 * arc.h: Likewise.
1353 * arm.h: Likewise.
1354 * avr.h: Likewise.
1355 * bfin.h: Likewise.
1356 * cgen.h: Likewise.
1357 * convex.h: Likewise.
1358 * cr16.h: Likewise.
1359 * cris.h: Likewise.
1360 * crx.h: Likewise.
1361 * d10v.h: Likewise.
1362 * d30v.h: Likewise.
1363 * dlx.h: Likewise.
1364 * h8300.h: Likewise.
1365 * hppa.h: Likewise.
1366 * i370.h: Likewise.
1367 * i386.h: Likewise.
1368 * i860.h: Likewise.
1369 * i960.h: Likewise.
1370 * ia64.h: Likewise.
1371 * m68hc11.h: Likewise.
1372 * m68k.h: Likewise.
1373 * m88k.h: Likewise.
1374 * maxq.h: Likewise.
1375 * mips.h: Likewise.
1376 * mmix.h: Likewise.
1377 * mn10200.h: Likewise.
1378 * mn10300.h: Likewise.
1379 * msp430.h: Likewise.
1380 * np1.h: Likewise.
1381 * ns32k.h: Likewise.
1382 * or32.h: Likewise.
1383 * pdp11.h: Likewise.
1384 * pj.h: Likewise.
1385 * pn.h: Likewise.
1386 * ppc.h: Likewise.
1387 * pyr.h: Likewise.
1388 * rx.h: Likewise.
1389 * s390.h: Likewise.
1390 * score-datadep.h: Likewise.
1391 * score-inst.h: Likewise.
1392 * sparc.h: Likewise.
1393 * spu-insns.h: Likewise.
1394 * spu.h: Likewise.
1395 * tic30.h: Likewise.
1396 * tic4x.h: Likewise.
1397 * tic54x.h: Likewise.
1398 * tic80.h: Likewise.
1399 * v850.h: Likewise.
1400 * vax.h: Likewise.
1401
40b36596
JM		 14022010-03-25 Joseph Myers <joseph@codesourcery.com>
1403
1404 * tic6x-control-registers.h, tic6x-insn-formats.h,
1405 tic6x-opcode-table.h, tic6x.h: New.
1406
c67a084a
NC		 14072010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1408
1409 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1410
466ef64f
AM		 14112010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1412
1413 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1414
1319d143
L		 14152010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1416
1417 * ia64.h (ia64_find_opcode): Remove argument name.
1418 (ia64_find_next_opcode): Likewise.
1419 (ia64_dis_opcode): Likewise.
1420 (ia64_free_opcode): Likewise.
1421 (ia64_find_dependency): Likewise.
1422
1fbb9298
DE		 14232009-11-22 Doug Evans <dje@sebabeach.org>
1424
1425 * cgen.h: Include bfd_stdint.h.
1426 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1427
ada65aa3
PB		 14282009-11-18 Paul Brook <paul@codesourcery.com>
1429
1430 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1431
9e3c6df6
PB		 14322009-11-17 Paul Brook <paul@codesourcery.com>
1433 Daniel Jacobowitz <dan@codesourcery.com>
1434
1435 * arm.h (ARM_EXT_V6_DSP): Define.
1436 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1437 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1438
0d734b5d
DD		 14392009-11-04 DJ Delorie <dj@redhat.com>
1440
1441 * rx.h (rx_decode_opcode) (mvtipl): Add.
1442 (mvtcp, mvfcp, opecp): Remove.
1443
62f3b8c8
PB		 14442009-11-02 Paul Brook <paul@codesourcery.com>
1445
1446 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1447 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1448 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1449 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1450 FPU_ARCH_NEON_VFP_V4): Define.
1451
ac1e9eca
DE		 14522009-10-23 Doug Evans <dje@sebabeach.org>
1453
1454 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1455 * cgen.h: Update. Improve multi-inclusion macro name.
1456
9fe54b1c
PB		 14572009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1458
1459 * ppc.h (PPC_OPCODE_476): Define.
1460
634b50f2
PB		 14612009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1462
1463 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1464
c7927a3c
NC		 14652009-09-29 DJ Delorie <dj@redhat.com>
1466
1467 * rx.h: New file.
1468
b961e85b
AM		 14692009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1470
1471 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1472
e0d602ec
BE		 14732009-09-21 Ben Elliston <bje@au.ibm.com>
1474
1475 * ppc.h (PPC_OPCODE_PPCA2): New.
1476
96d56e9f
NC		 14772009-09-05 Martin Thuresson <martin@mtme.org>
1478
1479 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1480
d3ce72d0
NC		 14812009-08-29 Martin Thuresson <martin@mtme.org>
1482
1483 * tic30.h (template): Rename type template to
1484 insn_template. Updated code to use new name.
1485 * tic54x.h (template): Rename type template to
1486 insn_template.
1487
824b28db
NH		 14882009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1489
1490 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1491
f865a31d
AG		 14922009-06-11 Anthony Green <green@moxielogic.com>
1493
1494 * moxie.h (MOXIE_F3_PCREL): Define.
1495 (moxie_form3_opc_info): Grow.
1496
0e7c7f11
AG		 14972009-06-06 Anthony Green <green@moxielogic.com>
1498
1499 * moxie.h (MOXIE_F1_M): Define.
1500
20135e4c
NC		 15012009-04-15 Anthony Green <green@moxielogic.com>
1502
1503 * moxie.h: Created.
1504
bcb012d3
DD		 15052009-04-06 DJ Delorie <dj@redhat.com>
1506
1507 * h8300.h: Add relaxation attributes to MOVA opcodes.
1508
69fe9ce5
AM		 15092009-03-10 Alan Modra <amodra@bigpond.net.au>
1510
1511 * ppc.h (ppc_parse_cpu): Declare.
1512
c3b7224a
NC		 15132009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1514
1515 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1516 and _IMM11 for mbitclr and mbitset.
1517 * score-datadep.h: Update dependency information.
1518
066be9f7
PB		 15192009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1520
1521 * ppc.h (PPC_OPCODE_POWER7): New.
1522
fedc618e
DE		 15232009-02-06 Doug Evans <dje@google.com>
1524
1525 * i386.h: Add comment regarding sse* insns and prefixes.
1526
52b6b6b9
JM		 15272009-02-03 Sandip Matte <sandip@rmicorp.com>
1528
1529 * mips.h (INSN_XLR): Define.
1530 (INSN_CHIP_MASK): Update.
1531 (CPU_XLR): Define.
1532 (OPCODE_IS_MEMBER): Update.
1533 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1534
35669430
DE		 15352009-01-28 Doug Evans <dje@google.com>
1536
1537 * opcode/i386.h: Add multiple inclusion protection.
1538 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1539 (EDI_REG_NUM): New macros.
1540 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1541 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1542 (REX_PREFIX_P): New macro.
35669430 1543
1cb0a767
PB		 15442009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1545
1546 * ppc.h (struct powerpc_opcode): New field "deprecated".
1547 (PPC_OPCODE_NOPOWER4): Delete.
1548
3aa3176b
TS		 15492008-11-28 Joshua Kinard <kumba@gentoo.org>
1550
1551 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1552 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1553
8e79c3df
CM		 15542008-11-18 Catherine Moore <clm@codesourcery.com>
1555
1556 * arm.h (FPU_NEON_FP16): New.
1557 (FPU_ARCH_NEON_FP16): New.
1558
de9a3e51
CF		 15592008-11-06 Chao-ying Fu <fu@mips.com>
1560
1561 * mips.h: Doucument '1' for 5-bit sync type.
1562
1ca35711
L		 15632008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1564
1565 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1566 IA64_RS_CR.
1567
9b4e5766
PB		 15682008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1569
1570 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1571
081ba1b3
AM		 15722008-07-30 Michael J. Eager <eager@eagercon.com>
1573
1574 * ppc.h (PPC_OPCODE_405): Define.
1575 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1576
fa452fa6
PB		 15772008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1578
1579 * ppc.h (ppc_cpu_t): New typedef.
1580 (struct powerpc_opcode <flags>): Use it.
1581 (struct powerpc_operand <insert, extract>): Likewise.
1582 (struct powerpc_macro <flags>): Likewise.
1583
bb35fb24
NC		 15842008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1585
1586 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1587 Update comment before MIPS16 field descriptors to mention MIPS16.
1588 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1589 BBIT.
1590 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1591 New bit masks and shift counts for cins and exts.
1592
dd3cbb7e
NC		 1593 * mips.h: Document new field descriptors +Q.
1594 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1595
d0799671
AN		 15962008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1597
9aff4b7a 1598 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1599 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1600
19a6653c
AM		 16012008-04-14 Edmar Wienskoski <edmar@freescale.com>
1602
1603 * ppc.h: (PPC_OPCODE_E500MC): New.
1604
c0f3af97
L		 16052008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1606
1607 * i386.h (MAX_OPERANDS): Set to 5.
1608 (MAX_MNEM_SIZE): Changed to 20.
1609
e210c36b
NC		 16102008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1611
1612 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1613
b1cc4aeb
PB		 16142008-03-09 Paul Brook <paul@codesourcery.com>
1615
1616 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1617
7e806470
PB		 16182008-03-04 Paul Brook <paul@codesourcery.com>
1619
1620 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1621 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1622 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1623
7b2185f9 16242008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1625 Nick Clifton <nickc@redhat.com>
1626
1627 PR 3134
1628 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1629 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1630 set.
af7329f0 1631
796d5313
NC		 16322008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1633
1634 * cr16.h (cr16_num_optab): Declared.
1635
d669d37f
NC		 16362008-02-14 Hakan Ardo <hakan@debian.org>
1637
1638 PR gas/2626
1639 * avr.h (AVR_ISA_2xxe): Define.
1640
e6429699
AN		 16412008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1642
1643 * mips.h: Update copyright.
1644 (INSN_CHIP_MASK): New macro.
1645 (INSN_OCTEON): New macro.
1646 (CPU_OCTEON): New macro.
1647 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1648
e210c36b
NC		 16492008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1650
1651 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1652
16532008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1654
1655 * avr.h (AVR_ISA_USB162): Add new opcode set.
1656 (AVR_ISA_AVR3): Likewise.
1657
350cc38d
MS		 16582007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1659
1660 * mips.h (INSN_LOONGSON_2E): New.
1661 (INSN_LOONGSON_2F): New.
1662 (CPU_LOONGSON_2E): New.
1663 (CPU_LOONGSON_2F): New.
1664 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1665
56950294
MS		 16662007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1667
1668 * mips.h (INSN_ISA*): Redefine certain values as an
1669 enumeration. Update comments.
1670 (mips_isa_table): New.
1671 (ISA_MIPS*): Redefine to match enumeration.
1672 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1673 values.
1674
c3d65c1c
BE		 16752007-08-08 Ben Elliston <bje@au.ibm.com>
1676
1677 * ppc.h (PPC_OPCODE_PPCPS): New.
1678
0fdaa005
L		 16792007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1680
1681 * m68k.h: Document j K & E.
1682
16832007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1684
1685 * cr16.h: New file for CR16 target.
1686
3896c469
AM		 16872007-05-02 Alan Modra <amodra@bigpond.net.au>
1688
1689 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1690
9a2e615a
NS		 16912007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1692
1693 * m68k.h (mcfisa_c): New.
1694 (mcfusp, mcf_mask): Adjust.
1695
b84bf58a
AM		 16962007-04-20 Alan Modra <amodra@bigpond.net.au>
1697
1698 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1699 (num_powerpc_operands): Declare.
1700 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1701 (PPC_OPERAND_PLUS1): Define.
1702
831480e9 17032007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1704
1705 * i386.h (REX_MODE64): Renamed to ...
1706 (REX_W): This.
1707 (REX_EXTX): Renamed to ...
1708 (REX_R): This.
1709 (REX_EXTY): Renamed to ...
1710 (REX_X): This.
1711 (REX_EXTZ): Renamed to ...
1712 (REX_B): This.
1713
0b1cf022
L		 17142007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1715
1716 * i386.h: Add entries from config/tc-i386.h and move tables
1717 to opcodes/i386-opc.h.
1718
d796c0ad
L		 17192007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1720
1721 * i386.h (FloatDR): Removed.
1722 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1723
30ac7323
AM		 17242007-03-01 Alan Modra <amodra@bigpond.net.au>
1725
1726 * spu-insns.h: Add soma double-float insns.
1727
8b082fb1 17282007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1729 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1730
1731 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1732 (INSN_DSPR2): Add flag for DSP R2 instructions.
1733 (M_BALIGN): New macro.
1734
4eed87de
AM		 17352007-02-14 Alan Modra <amodra@bigpond.net.au>
1736
1737 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1738 and Seg3ShortFrom with Shortform.
1739
fda592e8
L		 17402007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1741
1742 PR gas/4027
1743 * i386.h (i386_optab): Put the real "test" before the pseudo
1744 one.
1745
3bdcfdf4
KH		 17462007-01-08 Kazu Hirata <kazu@codesourcery.com>
1747
1748 * m68k.h (m68010up): OR fido_a.
1749
9840d27e
KH		 17502006-12-25 Kazu Hirata <kazu@codesourcery.com>
1751
1752 * m68k.h (fido_a): New.
1753
c629cdac
KH		 17542006-12-24 Kazu Hirata <kazu@codesourcery.com>
1755
1756 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1757 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1758 values.
1759
b7d9ef37
L		 17602006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1761
1762 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1763
b138abaa
NC		 17642006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1765
1766 * score-inst.h (enum score_insn_type): Add Insn_internal.
1767
e9f53129
AM		 17682006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1769 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1770 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1771 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1772 Alan Modra <amodra@bigpond.net.au>
1773
1774 * spu-insns.h: New file.
1775 * spu.h: New file.
1776
ede602d7
AM		 17772006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1778
1779 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1780
7918206c
MM		 17812006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1782
e4e42b45 1783 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1784 in amdfam10 architecture.
1785
ef05d495
L		 17862006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1787
1788 * i386.h: Replace CpuMNI with CpuSSSE3.
1789
2d447fca 17902006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1791 Joseph Myers <joseph@codesourcery.com>
1792 Ian Lance Taylor <ian@wasabisystems.com>
1793 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1794
1795 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1796
1c0d3aa6
NC		 17972006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1798
1799 * score-datadep.h: New file.
1800 * score-inst.h: New file.
1801
c2f0420e
L		 18022006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1803
1804 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1805 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1806 movdq2q and movq2dq.
1807
050dfa73
MM		 18082006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1809 Michael Meissner <michael.meissner@amd.com>
1810
1811 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1812
15965411
L		 18132006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1814
1815 * i386.h (i386_optab): Add "nop" with memory reference.
1816
46e883c5
L		 18172006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1818
1819 * i386.h (i386_optab): Update comment for 64bit NOP.
1820
9622b051
AM		 18212006-06-06 Ben Elliston <bje@au.ibm.com>
1822 Anton Blanchard <anton@samba.org>
1823
1824 * ppc.h (PPC_OPCODE_POWER6): Define.
1825 Adjust whitespace.
1826
a9e24354
TS		 18272006-06-05 Thiemo Seufer <ths@mips.com>
1828
e4e42b45 1829 * mips.h: Improve description of MT flags.
a9e24354 1830
a596001e
RS		 18312006-05-25 Richard Sandiford <richard@codesourcery.com>
1832
1833 * m68k.h (mcf_mask): Define.
1834
d43b4baf 18352006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1836 David Ung <davidu@mips.com>
d43b4baf
TS		 1837
1838 * mips.h (enum): Add macro M_CACHE_AB.
1839
39a7806d 18402006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1841 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1842 David Ung <davidu@mips.com>
1843
1844 * mips.h: Add INSN_SMARTMIPS define.
1845
9bcd4f99 18462006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1847 David Ung <davidu@mips.com>
9bcd4f99
TS		 1848
1849 * mips.h: Defines udi bits and masks. Add description of
1850 characters which may appear in the args field of udi
1851 instructions.
1852
ef0ee844
TS		 18532006-04-26 Thiemo Seufer <ths@networkno.de>
1854
1855 * mips.h: Improve comments describing the bitfield instruction
1856 fields.
1857
f7675147
L		 18582006-04-26 Julian Brown <julian@codesourcery.com>
1859
1860 * arm.h (FPU_VFP_EXT_V3): Define constant.
1861 (FPU_NEON_EXT_V1): Likewise.
1862 (FPU_VFP_HARD): Update.
1863 (FPU_VFP_V3): Define macro.
1864 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1865
ef0ee844 18662006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1867
1868 * avr.h (AVR_ISA_PWMx): New.
1869
2da12c60
NS		 18702006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1871
1872 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1873 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1874 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1875 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1876 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1877
0715c387
PB		 18782006-03-10 Paul Brook <paul@codesourcery.com>
1879
1880 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1881
34bdd094
DA		 18822006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1883
1884 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1885 first. Correct mask of bb "B" opcode.
1886
331d2d0d
L		 18872006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1888
1889 * i386.h (i386_optab): Support Intel Merom New Instructions.
1890
62b3e311
PB		 18912006-02-24 Paul Brook <paul@codesourcery.com>
1892
1893 * arm.h: Add V7 feature bits.
1894
59cf82fe
L		 18952006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1896
1897 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1898
e74cfd16
PB		 18992006-01-31 Paul Brook <paul@codesourcery.com>
1900 Richard Earnshaw <rearnsha@arm.com>
1901
1902 * arm.h: Use ARM_CPU_FEATURE.
1903 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1904 (arm_feature_set): Change to a structure.
1905 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1906 ARM_FEATURE): New macros.
1907
5b3f8a92
HPN		 19082005-12-07 Hans-Peter Nilsson <hp@axis.com>
1909
1910 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1911 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1912 (ADD_PC_INCR_OPCODE): Don't define.
1913
cb712a9e
L		 19142005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1915
1916 PR gas/1874
1917 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1918
0499d65b
TS		 19192005-11-14 David Ung <davidu@mips.com>
1920
1921 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1922 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1923 save/restore encoding of the args field.
1924
ea5ca089
DB		 19252005-10-28 Dave Brolley <brolley@redhat.com>
1926
1927 Contribute the following changes:
1928 2005-02-16 Dave Brolley <brolley@redhat.com>
1929
1930 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1931 cgen_isa_mask_* to cgen_bitset_*.
1932 * cgen.h: Likewise.
1933
16175d96
DB		 1934 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1935
1936 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1937 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1938 (CGEN_CPU_TABLE): Make isas a ponter.
1939
1940 2003-09-29 Dave Brolley <brolley@redhat.com>
1941
1942 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1943 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1944 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1945
1946 2002-12-13 Dave Brolley <brolley@redhat.com>
1947
1948 * cgen.h (symcat.h): #include it.
1949 (cgen-bitset.h): #include it.
1950 (CGEN_ATTR_VALUE_TYPE): Now a union.
1951 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1952 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1953 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1954 * cgen-bitset.h: New file.
1955
3c9b82ba
NC		 19562005-09-30 Catherine Moore <clm@cm00re.com>
1957
1958 * bfin.h: New file.
1959
6a2375c6
JB		 19602005-10-24 Jan Beulich <jbeulich@novell.com>
1961
1962 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1963 indirect operands.
1964
c06a12f8
DA		 19652005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1966
1967 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1968 Add FLAG_STRICT to pa10 ftest opcode.
1969
4d443107
DA		 19702005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1971
1972 * hppa.h (pa_opcodes): Remove lha entries.
1973
f0a3b40f
DA		 19742005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1975
1976 * hppa.h (FLAG_STRICT): Revise comment.
1977 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1978 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1979 entries for "fdc".
1980
e210c36b
NC		 19812005-09-30 Catherine Moore <clm@cm00re.com>
1982
1983 * bfin.h: New file.
1984
1b7e1362
DA		 19852005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1986
1987 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1988
089b39de
CF		 19892005-09-06 Chao-ying Fu <fu@mips.com>
1990
1991 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1992 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1993 define.
1994 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1995 (INSN_ASE_MASK): Update to include INSN_MT.
1996 (INSN_MT): New define for MT ASE.
1997
93c34b9b
CF		 19982005-08-25 Chao-ying Fu <fu@mips.com>
1999
2000 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
2001 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
2002 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
2003 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
2004 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
2005 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
2006 instructions.
2007 (INSN_DSP): New define for DSP ASE.
2008
848cf006
AM		 20092005-08-18 Alan Modra <amodra@bigpond.net.au>
2010
2011 * a29k.h: Delete.
2012
36ae0db3
DJ		 20132005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
2014
2015 * ppc.h (PPC_OPCODE_E300): Define.
2016
8c929562
MS		 20172005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
2018
2019 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
2020
f7b8cccc
DA		 20212005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2022
2023 PR gas/336
2024 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
2025 and pitlb.
2026
8b5328ac
JB		 20272005-07-27 Jan Beulich <jbeulich@novell.com>
2028
2029 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2030 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2031 Add movq-s as 64-bit variants of movd-s.
2032
f417d200
DA		 20332005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2034
18b3bdfc
DA		 2035 * hppa.h: Fix punctuation in comment.
2036
f417d200
DA		 2037 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2038 implicit space-register addressing. Set space-register bits on opcodes
2039 using implicit space-register addressing. Add various missing pa20
2040 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2041 space-register addressing. Use "fE" instead of "fe" in various
2042 fstw opcodes.
2043
9a145ce6
JB		 20442005-07-18 Jan Beulich <jbeulich@novell.com>
2045
2046 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2047
90700ea2
L		 20482007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2049
2050 * i386.h (i386_optab): Support Intel VMX Instructions.
2051
48f130a8
DA		 20522005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2053
2054 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2055
30123838
JB		 20562005-07-05 Jan Beulich <jbeulich@novell.com>
2057
2058 * i386.h (i386_optab): Add new insns.
2059
47b0e7ad
NC		 20602005-07-01 Nick Clifton <nickc@redhat.com>
2061
2062 * sparc.h: Add typedefs to structure declarations.
2063
b300c311
L		 20642005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2065
2066 PR 1013
2067 * i386.h (i386_optab): Update comments for 64bit addressing on
2068 mov. Allow 64bit addressing for mov and movq.
2069
2db495be
DA		 20702005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2071
2072 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2073 respectively, in various floating-point load and store patterns.
2074
caa05036
DA		 20752005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2076
2077 * hppa.h (FLAG_STRICT): Correct comment.
2078 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2079 PA 2.0 mneumonics when equivalent. Entries with cache control
2080 completers now require PA 1.1. Adjust whitespace.
2081
f4411256
AM		 20822005-05-19 Anton Blanchard <anton@samba.org>
2083
2084 * ppc.h (PPC_OPCODE_POWER5): Define.
2085
e172dbf8
NC		 20862005-05-10 Nick Clifton <nickc@redhat.com>
2087
2088 * Update the address and phone number of the FSF organization in
2089 the GPL notices in the following files:
2090 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2091 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2092 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2093 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2094 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2095 tic54x.h, tic80.h, v850.h, vax.h
2096
e44823cf
JB		 20972005-05-09 Jan Beulich <jbeulich@novell.com>
2098
2099 * i386.h (i386_optab): Add ht and hnt.
2100
791fe849
MK		 21012005-04-18 Mark Kettenis <kettenis@gnu.org>
2102
2103 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2104 Add xcrypt-ctr. Provide aliases without hyphens.
2105
faa7ef87
L		 21062005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2107
a63027e5
L		 2108 Moved from ../ChangeLog
2109
faa7ef87
L		 2110 2005-04-12 Paul Brook <paul@codesourcery.com>
2111 * m88k.h: Rename psr macros to avoid conflicts.
2112
2113 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2114 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2115 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2116 and ARM_ARCH_V6ZKT2.
2117
2118 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2119 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2120 Remove redundant instruction types.
2121 (struct argument): X_op - new field.
2122 (struct cst4_entry): Remove.
2123 (no_op_insn): Declare.
2124
2125 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2126 * crx.h (enum argtype): Rename types, remove unused types.
2127
2128 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2129 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2130 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2131 (enum operand_type): Rearrange operands, edit comments.
2132 replace us<N> with ui<N> for unsigned immediate.
2133 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2134 displacements (respectively).
2135 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2136 (instruction type): Add NO_TYPE_INS.
2137 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2138 (operand_entry): New field - 'flags'.
2139 (operand flags): New.
2140
2141 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2142 * crx.h (operand_type): Remove redundant types i3, i4,
2143 i5, i8, i12.
2144 Add new unsigned immediate types us3, us4, us5, us16.
2145
bc4bd9ab
MK		 21462005-04-12 Mark Kettenis <kettenis@gnu.org>
2147
2148 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2149 adjust them accordingly.
2150
373ff435
JB		 21512005-04-01 Jan Beulich <jbeulich@novell.com>
2152
2153 * i386.h (i386_optab): Add rdtscp.
2154
4cc91dba
L		 21552005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2156
2157 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2158 between memory and segment register. Allow movq for moving between
2159 general-purpose register and segment register.
4cc91dba 2160
9ae09ff9
JB		 21612005-02-09 Jan Beulich <jbeulich@novell.com>
2162
2163 PR gas/707
2164 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2165 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2166 fnstsw.
2167
638e7a64
NS		 21682006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2169
2170 * m68k.h (m68008, m68ec030, m68882): Remove.
2171 (m68k_mask): New.
2172 (cpu_m68k, cpu_cf): New.
2173 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2174 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2175
90219bd0
AO		 21762005-01-25 Alexandre Oliva <aoliva@redhat.com>
2177
2178 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2179 * cgen.h (enum cgen_parse_operand_type): Add
2180 CGEN_PARSE_OPERAND_SYMBOLIC.
2181
239cb185
FF		 21822005-01-21 Fred Fish <fnf@specifixinc.com>
2183
2184 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2185 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2186 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2187
dc9a9f39
FF		 21882005-01-19 Fred Fish <fnf@specifixinc.com>
2189
2190 * mips.h (struct mips_opcode): Add new pinfo2 member.
2191 (INSN_ALIAS): New define for opcode table entries that are
2192 specific instances of another entry, such as 'move' for an 'or'
2193 with a zero operand.
2194 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2195 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2196
98e7aba8
ILT		 21972004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2198
2199 * mips.h (CPU_RM9000): Define.
2200 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2201
37edbb65
JB		 22022004-11-25 Jan Beulich <jbeulich@novell.com>
2203
2204 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2205 to/from test registers are illegal in 64-bit mode. Add missing
2206 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2207 (previously one had to explicitly encode a rex64 prefix). Re-enable
2208 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2209 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2210
22112004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2212
2213 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2214 available only with SSE2. Change the MMX additions introduced by SSE
2215 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2216 instructions by their now designated identifier (since combining i686
2217 and 3DNow! does not really imply 3DNow!A).
2218
f5c7edf4
AM		 22192004-11-19 Alan Modra <amodra@bigpond.net.au>
2220
2221 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2222 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2223
7499d566
NC		 22242004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2225 Vineet Sharma <vineets@noida.hcltech.com>
2226
2227 * maxq.h: New file: Disassembly information for the maxq port.
2228
bcb9eebe
L		 22292004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2230
2231 * i386.h (i386_optab): Put back "movzb".
2232
94bb3d38
HPN		 22332004-11-04 Hans-Peter Nilsson <hp@axis.com>
2234
2235 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2236 comments. Remove member cris_ver_sim. Add members
2237 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2238 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2239 (struct cris_support_reg, struct cris_cond15): New types.
2240 (cris_conds15): Declare.
2241 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2242 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2243 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2244 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2245 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2246 SIZE_FIELD_UNSIGNED.
2247
37edbb65 22482004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2249
2250 * i386.h (sldx_Suf): Remove.
2251 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2252 (q_FP): Define, implying no REX64.
2253 (x_FP, sl_FP): Imply FloatMF.
2254 (i386_optab): Split reg and mem forms of moving from segment registers
2255 so that the memory forms can ignore the 16-/32-bit operand size
2256 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2257 all non-floating-point instructions. Unite 32- and 64-bit forms of
2258 movsx, movzx, and movd. Adjust floating point operations for the above
2259 changes to the *FP macros. Add DefaultSize to floating point control
2260 insns operating on larger memory ranges. Remove left over comments
2261 hinting at certain insns being Intel-syntax ones where the ones
2262 actually meant are already gone.
2263
48c9f030
NC		 22642004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2265
2266 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2267 instruction type.
2268
0dd132b6
NC		 22692004-09-30 Paul Brook <paul@codesourcery.com>
2270
2271 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2272 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2273
23794b24
MM		 22742004-09-11 Theodore A. Roth <troth@openavr.org>
2275
2276 * avr.h: Add support for
2277 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2278
2a309db0
AM		 22792004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2280
2281 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2282
b18c562e
NC		 22832004-08-24 Dmitry Diky <diwil@spec.ru>
2284
2285 * msp430.h (msp430_opc): Add new instructions.
2286 (msp430_rcodes): Declare new instructions.
2287 (msp430_hcodes): Likewise..
2288
45d313cd
NC		 22892004-08-13 Nick Clifton <nickc@redhat.com>
2290
2291 PR/301
2292 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2293 processors.
2294
30d1c836
ML		 22952004-08-30 Michal Ludvig <mludvig@suse.cz>
2296
2297 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2298
9a45f1c2
L		 22992004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2300
2301 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2302
543613e9
NC		 23032004-07-21 Jan Beulich <jbeulich@novell.com>
2304
2305 * i386.h: Adjust instruction descriptions to better match the
2306 specification.
2307
b781e558
RE		 23082004-07-16 Richard Earnshaw <rearnsha@arm.com>
2309
2310 * arm.h: Remove all old content. Replace with architecture defines
2311 from gas/config/tc-arm.c.
2312
8577e690
AS		 23132004-07-09 Andreas Schwab <schwab@suse.de>
2314
2315 * m68k.h: Fix comment.
2316
1fe1f39c
NC		 23172004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2318
2319 * crx.h: New file.
2320
1d9f512f
AM		 23212004-06-24 Alan Modra <amodra@bigpond.net.au>
2322
2323 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2324
be8c092b
NC		 23252004-05-24 Peter Barada <peter@the-baradas.com>
2326
2327 * m68k.h: Add 'size' to m68k_opcode.
2328
6b6e92f4
NC		 23292004-05-05 Peter Barada <peter@the-baradas.com>
2330
2331 * m68k.h: Switch from ColdFire chip name to core variant.
2332
23332004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2334
2335 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2336 descriptions for new EMAC cases.
2337 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2338 handle Motorola MAC syntax.
2339 Allow disassembly of ColdFire V4e object files.
2340
fdd12ef3
AM		 23412004-03-16 Alan Modra <amodra@bigpond.net.au>
2342
2343 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2344
3922a64c
L		 23452004-03-12 Jakub Jelinek <jakub@redhat.com>
2346
2347 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2348
1f45d988
ML		 23492004-03-12 Michal Ludvig <mludvig@suse.cz>
2350
2351 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2352
0f10071e
ML		 23532004-03-12 Michal Ludvig <mludvig@suse.cz>
2354
2355 * i386.h (i386_optab): Added xstore/xcrypt insns.
2356
3255318a
NC		 23572004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2358
2359 * h8300.h (32bit ldc/stc): Add relaxing support.
2360
ca9a79a1 23612004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2362
ca9a79a1
NC		 2363 * h8300.h (BITOP): Pass MEMRELAX flag.
2364
875a0b14
NC		 23652004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2366
2367 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2368 except for the H8S.
252b5132 2369
c9e214e5 2370For older changes see ChangeLog-9103
252b5132 2371\f
b90efa5b 2372Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2373
2374Copying and distribution of this file, with or without modification,
2375are permitted in any medium without royalty provided the copyright
2376notice and this notice are preserved.
2377
252b5132 2378Local Variables:
c9e214e5
AM		 2379mode: change-log
2380left-margin: 8
2381fill-column: 74
252b5132
RH		 2382version-control: never
2383End:
GDB Binutils - Deliverables
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