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Revert "Do not issue error messages when parsing a PSTATE register".
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
c9fb6e58
YZ		 12013-11-18 Renlin Li <Renlin.Li@arm.com>
2
3 * arm.h (ARM_AEXT_V7VE): New define.
4 (ARM_ARCH_V7VE): New define.
5 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
6
a203d9b7
YZ		 72013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
8
9 Revert
10
11 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
12
13 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
14 (aarch64_sys_reg_writeonly_p): Ditto.
15
75468c93
YZ		 162013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
17
18 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
19 (aarch64_sys_reg_writeonly_p): Ditto.
20
49eec193
YZ		 212013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
22
23 * aarch64.h (aarch64_sys_reg): New typedef.
24 (aarch64_sys_regs): Change to define with the new type.
25 (aarch64_sys_reg_deprecated_p): Declare.
26
68a64283
YZ		 272013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
28
29 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
30 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
31
387a82f1
CF		 322013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
33
34 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
35 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
36 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
37 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
38 For MIPS, update extension character sequences after +.
39 (ASE_MSA): New define.
40 (ASE_MSA64): New define.
41 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
42 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
43 For microMIPS, update extension character sequences after +.
44
9aff4b7a
NC		 452013-08-23 Yuri Chornoivan <yurchor@ukr.net>
46
47 PR binutils/15834
48 * i960.h: Fix typos.
49
e423441d
RS		 502013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
51
52 * mips.h: Remove references to "+I" and imm2_expr.
53
5e0dc5ba
RS		 542013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
55
56 * mips.h (M_DEXT, M_DINS): Delete.
57
0f35dbc4
RS		 582013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
59
60 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
61 (mips_optional_operand_p): New function.
62
14daeee3
RS		 632013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
64 Richard Sandiford <rdsandiford@googlemail.com>
65
66 * mips.h: Document new VU0 operand characters.
67 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
68 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
69 (OP_REG_R5900_ACC): New mips_reg_operand_types.
70 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
71 (mips_vu0_channel_mask): Declare.
72
3ccad066
RS		 732013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
74
75 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
76 (mips_int_operand_min, mips_int_operand_max): New functions.
77 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
78
fc76e730
RS		 792013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
80
81 * mips.h (mips_decode_reg_operand): New function.
82 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
83 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
84 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
85 New macros.
86 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
87 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
88 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
89 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
90 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
91 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
92 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
93 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
94 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
95 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
96 macros to cover the gaps.
97 (INSN2_MOD_SP): Replace with...
98 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
99 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
100 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
101 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
102 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
103 Delete.
104
26545944
RS		 1052013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
106
107 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
108 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
109 (MIPS16_INSN_COND_BRANCH): Delete.
110
7e8b059b
L		 1112013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
112 Kirill Yukhin <kirill.yukhin@intel.com>
113 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
114
115 * i386.h (BND_PREFIX_OPCODE): New.
116
c3c07478
RS		 1172013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
118
119 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
120 OP_SAVE_RESTORE_LIST.
121 (decode_mips16_operand): Declare.
122
ab902481
RS		 1232013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
124
125 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
126 (mips_operand, mips_int_operand, mips_mapped_int_operand)
127 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
128 (mips_pcrel_operand): New structures.
129 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
130 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
131 (decode_mips_operand, decode_micromips_operand): Declare.
132
cc537e56
RS		 1332013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
134
135 * mips.h: Document MIPS16 "I" opcode.
136
f2ae14a1
RS		 1372013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
138
139 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
140 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
141 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
142 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
143 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
144 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
145 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
146 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
147 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
148 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
149 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
150 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
151 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
152 Rename to...
153 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
154 (M_USD_AB): ...these.
155
5c324c16
RS		 1562013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
157
158 * mips.h: Remove documentation of "[" and "]". Update documentation
159 of "k" and the MDMX formats.
160
23e69e47
RS		 1612013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
162
163 * mips.h: Update documentation of "+s" and "+S".
164
27c5c572
RS		 1652013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
166
167 * mips.h: Document "+i".
168
e76ff5ab
RS		 1692013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
170
171 * mips.h: Remove "mi" documentation. Update "mh" documentation.
172 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
173 Delete.
174 (INSN2_WRITE_GPR_MHI): Rename to...
175 (INSN2_WRITE_GPR_MH): ...this.
176
fa7616a4
RS		 1772013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
178
179 * mips.h: Remove documentation of "+D" and "+T".
180
18870af7
RS		 1812013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
182
183 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
184 Use "source" rather than "destination" for microMIPS "G".
185
833794fc
MR		 1862013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
187
188 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
189 values.
190
c3678916
RS		 1912013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
192
193 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
194
7f3c4072
CM		 1952013-06-17 Catherine Moore <clm@codesourcery.com>
196 Maciej W. Rozycki <macro@codesourcery.com>
197 Chao-Ying Fu <fu@mips.com>
198
199 * mips.h (OP_SH_EVAOFFSET): Define.
200 (OP_MASK_EVAOFFSET): Define.
201 (INSN_ASE_MASK): Delete.
202 (ASE_EVA): Define.
203 (M_CACHEE_AB, M_CACHEE_OB): New.
204 (M_LBE_OB, M_LBE_AB): New.
205 (M_LBUE_OB, M_LBUE_AB): New.
206 (M_LHE_OB, M_LHE_AB): New.
207 (M_LHUE_OB, M_LHUE_AB): New.
208 (M_LLE_AB, M_LLE_OB): New.
209 (M_LWE_OB, M_LWE_AB): New.
210 (M_LWLE_AB, M_LWLE_OB): New.
211 (M_LWRE_AB, M_LWRE_OB): New.
212 (M_PREFE_AB, M_PREFE_OB): New.
213 (M_SCE_AB, M_SCE_OB): New.
214 (M_SBE_OB, M_SBE_AB): New.
215 (M_SHE_OB, M_SHE_AB): New.
216 (M_SWE_OB, M_SWE_AB): New.
217 (M_SWLE_AB, M_SWLE_OB): New.
218 (M_SWRE_AB, M_SWRE_OB): New.
219 (MICROMIPSOP_SH_EVAOFFSET): Define.
220 (MICROMIPSOP_MASK_EVAOFFSET): Define.
221
0c8fe7cf
SL		 2222013-06-12 Sandra Loosemore <sandra@codesourcery.com>
223
224 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
225
c77c0862
RS		 2262013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
227
228 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
229
b015e599
AP		 2302013-05-09 Andrew Pinski <apinski@cavium.com>
231
232 * mips.h (OP_MASK_CODE10): Correct definition.
233 (OP_SH_CODE10): Likewise.
234 Add a comment that "+J" is used now for OP_*CODE10.
235 (INSN_ASE_MASK): Update.
236 (INSN_VIRT): New macro.
237 (INSN_VIRT64): New macro
238
13761a11
NC		 2392013-05-02 Nick Clifton <nickc@redhat.com>
240
241 * msp430.h: Add patterns for MSP430X instructions.
242
0afd1215
DM		 2432013-04-06 David S. Miller <davem@davemloft.net>
244
245 * sparc.h (F_PREFERRED): Define.
246 (F_PREF_ALIAS): Define.
247
41702d50
NC		 2482013-04-03 Nick Clifton <nickc@redhat.com>
249
250 * v850.h (V850_INVERSE_PCREL): Define.
251
e21e1a51
NC		 2522013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
253
254 PR binutils/15068
255 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
256
51dcdd4d
NC		 2572013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
258
259 PR binutils/15068
260 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
261 Add 16-bit opcodes.
262 * tic6xc-opcode-table.h: Add 16-bit insns.
263 * tic6x.h: Add support for 16-bit insns.
264
81f5558e
NC		 2652013-03-21 Michael Schewe <michael.schewe@gmx.net>
266
267 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
268 and mov.b/w/l Rs,@(d:32,ERd).
269
165546ad
NC		 2702013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
271
272 PR gas/15082
273 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
274 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
275 tic6x_operand_xregpair operand coding type.
276 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
277 opcode field, usu ORXREGD1324 for the src2 operand and remove the
278 TIC6X_FLAG_NO_CROSS.
279
795b8e6b
NC		 2802013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
281
282 PR gas/15095
283 * tic6x.h (enum tic6x_coding_method): Add
284 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
285 separately the msb and lsb of a register pair. This is needed to
286 encode the opcodes in the same way as TI assembler does.
287 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
288 and rsqrdp opcodes to use the new field coding types.
289
dd5181d5
KT		 2902013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
291
292 * arm.h (CRC_EXT_ARMV8): New constant.
293 (ARCH_CRC_ARMV8): New macro.
294
e60bb1dd
YZ		 2952013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
296
297 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
298
36591ba1
SL		 2992013-02-06 Sandra Loosemore <sandra@codesourcery.com>
300 Andrew Jenner <andrew@codesourcery.com>
301
302 Based on patches from Altera Corporation.
303
304 * nios2.h: New file.
305
e30181a5
YZ		 3062013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
307
308 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
309
0c9573f4
NC		 3102013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
311
312 PR gas/15069
313 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
314
981dc7f1
NC		 3152013-01-24 Nick Clifton <nickc@redhat.com>
316
317 * v850.h: Add e3v5 support.
318
f5555712
YZ		 3192013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
320
321 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
322
5817ffd1
PB		 3232013-01-10 Peter Bergner <bergner@vnet.ibm.com>
324
325 * ppc.h (PPC_OPCODE_POWER8): New define.
326 (PPC_OPCODE_HTM): Likewise.
327
a3c62988
NC		 3282013-01-10 Will Newton <will.newton@imgtec.com>
329
330 * metag.h: New file.
331
73335eae
NC		 3322013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
333
334 * cr16.h (make_instruction): Rename to cr16_make_instruction.
335 (match_opcode): Rename to cr16_match_opcode.
336
e407c74b
NC		 3372013-01-04 Juergen Urban <JuergenUrban@gmx.de>
338
339 * mips.h: Add support for r5900 instructions including lq and sq.
340
bab4becb
NC		 3412013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
342
343 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
344 (make_instruction,match_opcode): Added function prototypes.
345 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
346
776fc418
AM		 3472012-11-23 Alan Modra <amodra@gmail.com>
348
349 * ppc.h (ppc_parse_cpu): Update prototype.
350
f05682d4
DA		 3512012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
352
353 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
354 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
355
cfc72779
AK		 3562012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
357
358 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
359
b3e14eda
L		 3602012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
361
362 * ia64.h (ia64_opnd): Add new operand types.
363
2c63854f
DM		 3642012-08-21 David S. Miller <davem@davemloft.net>
365
366 * sparc.h (F3F4): New macro.
367
a06ea964 3682012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 369 Laurent Desnogues <laurent.desnogues@arm.com>
370 Jim MacArthur <jim.macarthur@arm.com>
371 Marcus Shawcroft <marcus.shawcroft@arm.com>
372 Nigel Stephens <nigel.stephens@arm.com>
373 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
374 Richard Earnshaw <rearnsha@arm.com>
375 Sofiane Naci <sofiane.naci@arm.com>
376 Tejas Belagod <tejas.belagod@arm.com>
377 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 378
379 * aarch64.h: New file.
380
35d0a169 3812012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 382 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 383
384 * mips.h (mips_opcode): Add the exclusions field.
385 (OPCODE_IS_MEMBER): Remove macro.
386 (cpu_is_member): New inline function.
387 (opcode_is_member): Likewise.
388
03f66e8a 3892012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 390 Catherine Moore <clm@codesourcery.com>
391 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 392
393 * mips.h: Document microMIPS DSP ASE usage.
394 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
395 microMIPS DSP ASE support.
396 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
397 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
398 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
399 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
400 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
401 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
402 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
403
9d7b4c23
MR		 4042012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
405
406 * mips.h: Fix a typo in description.
407
76e879f8
NC		 4082012-06-07 Georg-Johann Lay <avr@gjlay.de>
409
410 * avr.h: (AVR_ISA_XCH): New define.
411 (AVR_ISA_XMEGA): Use it.
412 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
413
6927f982
NC		 4142012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
415
416 * m68hc11.h: Add XGate definitions.
417 (struct m68hc11_opcode): Add xg_mask field.
418
b9c361e0
JL		 4192012-05-14 Catherine Moore <clm@codesourcery.com>
420 Maciej W. Rozycki <macro@codesourcery.com>
421 Rhonda Wittels <rhonda@codesourcery.com>
422
6927f982 423 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 424 (PPC_OP_SA): New macro.
425 (PPC_OP_SE_VLE): New macro.
426 (PPC_OP): Use a variable shift amount.
427 (powerpc_operand): Update comments.
428 (PPC_OPSHIFT_INV): New macro.
429 (PPC_OPERAND_CR): Replace with...
430 (PPC_OPERAND_CR_BIT): ...this and
431 (PPC_OPERAND_CR_REG): ...this.
432
433
f6c1a2d5
NC		 4342012-05-03 Sean Keys <skeys@ipdatasys.com>
435
436 * xgate.h: Header file for XGATE assembler.
437
ec668d69
DM		 4382012-04-27 David S. Miller <davem@davemloft.net>
439
6cda1326
DM		 440 * sparc.h: Document new arg code' )' for crypto RS3
441 immediates.
442
ec668d69
DM		 443 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
444 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
445 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
446 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
447 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
448 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
449 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
450 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
451 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
452 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
453 HWCAP_CBCOND, HWCAP_CRC32): New defines.
454
aea77599
AM		 4552012-03-10 Edmar Wienskoski <edmar@freescale.com>
456
457 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
458
1f42f8b3
AM		 4592012-02-27 Alan Modra <amodra@gmail.com>
460
461 * crx.h (cst4_map): Update declaration.
462
6f7be959
WL		 4632012-02-25 Walter Lee <walt@tilera.com>
464
465 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
466 TILEGX_OPC_LD_TLS.
467 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
468 TILEPRO_OPC_LW_TLS_SN.
469
42164a71
L		 4702012-02-08 H.J. Lu <hongjiu.lu@intel.com>
471
472 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
473 (XRELEASE_PREFIX_OPCODE): Likewise.
474
432233b3 4752011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 476 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 477
478 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
479 (INSN_OCTEON2): New macro.
480 (CPU_OCTEON2): New macro.
481 (OPCODE_IS_MEMBER): Add Octeon2.
482
dd6a37e7
AP		 4832011-11-29 Andrew Pinski <apinski@cavium.com>
484
485 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
486 (INSN_OCTEONP): New macro.
487 (CPU_OCTEONP): New macro.
488 (OPCODE_IS_MEMBER): Add Octeon+.
489 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
490
99c513f6
DD		 4912011-11-01 DJ Delorie <dj@redhat.com>
492
493 * rl78.h: New file.
494
26f85d7a
MR		 4952011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
496
497 * mips.h: Fix a typo in description.
498
9e8c70f9
DM		 4992011-09-21 David S. Miller <davem@davemloft.net>
500
501 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
502 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
503 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
504 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
505
dec0624d 5062011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 507 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 508
509 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
510 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
511 (INSN_ASE_MASK): Add the MCU bit.
512 (INSN_MCU): New macro.
513 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
514 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
515
2b0c8b40
MR		 5162011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
517
518 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
519 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
520 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
521 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
522 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
523 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
524 (INSN2_READ_GPR_MMN): Likewise.
525 (INSN2_READ_FPR_D): Change the bit used.
526 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
527 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
528 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
529 (INSN2_COND_BRANCH): Likewise.
530 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
531 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
532 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
533 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
534 (INSN2_MOD_GPR_MN): Likewise.
535
ea783ef3
DM		 5362011-08-05 David S. Miller <davem@davemloft.net>
537
538 * sparc.h: Document new format codes '4', '5', and '('.
539 (OPF_LOW4, RS3): New macros.
540
7c176fa8
MR		 5412011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
542
543 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
544 order of flags documented.
545
2309ddf2
MR		 5462011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
547
548 * mips.h: Clarify the description of microMIPS instruction
549 manipulation macros.
550 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
551
df58fc94 5522011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 553 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 554
555 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
556 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
557 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
558 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
559 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
560 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
561 (OP_MASK_RS3, OP_SH_RS3): Likewise.
562 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
563 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
564 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
565 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
566 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
567 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
568 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
569 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
570 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
571 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
572 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
573 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
574 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
575 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
576 (INSN_WRITE_GPR_S): New macro.
577 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
578 (INSN2_READ_FPR_D): Likewise.
579 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
580 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
581 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
582 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
583 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
584 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
585 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
586 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
587 (CPU_MICROMIPS): New macro.
588 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
589 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
590 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
591 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
592 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
593 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
594 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
595 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
596 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
597 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
598 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
599 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
600 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
601 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
602 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
603 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
604 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
605 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
606 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
607 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
608 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
609 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
610 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
611 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
612 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
613 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
614 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
615 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
616 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
617 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
618 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
619 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
620 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
621 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
622 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
623 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
624 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
625 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
626 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
627 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
628 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
629 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
630 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
631 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
632 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
633 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
634 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
635 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
636 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
637 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
638 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
639 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
640 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
641 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
642 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
643 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
644 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
645 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
646 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
647 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
648 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
649 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
650 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
651 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
652 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
653 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
654 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
655 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
656 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
657 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
658 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
659 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
660 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
661 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
662 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
663 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
664 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
665 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
666 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
667 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
668 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
669 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
670 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
671 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
672 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
673 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
674 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
675 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
676 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
677 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
678 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
679 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
680 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
681 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
682 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
683 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
684 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
685 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
686 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
687 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
688 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
689 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
690 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
691 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
692 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
693 (micromips_opcodes): New declaration.
694 (bfd_micromips_num_opcodes): Likewise.
695
bcd530a7
RS		 6962011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
697
698 * mips.h (INSN_TRAP): Rename to...
699 (INSN_NO_DELAY_SLOT): ... this.
700 (INSN_SYNC): Remove macro.
701
2dad5a91
EW		 7022011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
703
704 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
705 a duplicate of AVR_ISA_SPM.
706
5d73b1f1
NC		 7072011-07-01 Nick Clifton <nickc@redhat.com>
708
709 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
710
ef26d60e
MF		 7112011-06-18 Robin Getz <robin.getz@analog.com>
712
713 * bfin.h (is_macmod_signed): New func
714
8fb8dca7
MF		 7152011-06-18 Mike Frysinger <vapier@gentoo.org>
716
717 * bfin.h (is_macmod_pmove): Add missing space before func args.
718 (is_macmod_hmove): Likewise.
719
aa137e4d
NC		 7202011-06-13 Walter Lee <walt@tilera.com>
721
722 * tilegx.h: New file.
723 * tilepro.h: New file.
724
3b2f0793
PB		 7252011-05-31 Paul Brook <paul@codesourcery.com>
726
aa137e4d
NC		 727 * arm.h (ARM_ARCH_V7R_IDIV): Define.
728
7292011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
730
731 * s390.h: Replace S390_OPERAND_REG_EVEN with
732 S390_OPERAND_REG_PAIR.
733
7342011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
735
736 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 737
ac7f631b
NC		 7382011-04-18 Julian Brown <julian@codesourcery.com>
739
740 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
741
84701018
NC		 7422011-04-11 Dan McDonald <dan@wellkeeper.com>
743
744 PR gas/12296
745 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
746
8cc66334
EW		 7472011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
748
749 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
750 New instruction set flags.
751 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
752
3eebd5eb
MR		 7532011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
754
755 * mips.h (M_PREF_AB): New enum value.
756
26bb3ddd
MF		 7572011-02-12 Mike Frysinger <vapier@gentoo.org>
758
89c0d58c
MR		 759 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
760 M_IU): Define.
761 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 762
dd76fcb8
MF		 7632011-02-11 Mike Frysinger <vapier@gentoo.org>
764
765 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
766
98d23bef
BS		 7672011-02-04 Bernd Schmidt <bernds@codesourcery.com>
768
769 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
770 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
771
3c853d93
DA		 7722010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
773
774 PR gas/11395
775 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
776 "bb" entries.
777
79676006
DA		 7782010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
779
780 PR gas/11395
781 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
782
1bec78e9
RS		 7832010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
784
785 * mips.h: Update commentary after last commit.
786
98675402
RS		 7872010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
788
789 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
790 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
791 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
792
aa137e4d
NC		 7932010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
794
795 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
796
435b94a4
RS		 7972010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
798
799 * mips.h: Fix previous commit.
800
d051516a
NC		 8012010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
802
803 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
804 (INSN_LOONGSON_3A): Clear bit 31.
805
251665fc
MGD		 8062010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
807
808 PR gas/12198
809 * arm.h (ARM_AEXT_V6M_ONLY): New define.
810 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
811 (ARM_ARCH_V6M_ONLY): New define.
812
fd503541
NC		 8132010-11-11 Mingming Sun <mingm.sun@gmail.com>
814
815 * mips.h (INSN_LOONGSON_3A): Defined.
816 (CPU_LOONGSON_3A): Defined.
817 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
818
4469d2be
AM		 8192010-10-09 Matt Rice <ratmice@gmail.com>
820
821 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
822 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
823
90ec0d68
MGD		 8242010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
825
826 * arm.h (ARM_EXT_VIRT): New define.
827 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
828 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
829 Extensions.
830
eea54501 8312010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 832
eea54501
MGD		 833 * arm.h (ARM_AEXT_ADIV): New define.
834 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
835
b2a5fbdc
MGD		 8362010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
837
838 * arm.h (ARM_EXT_OS): New define.
839 (ARM_AEXT_V6SM): Likewise.
840 (ARM_ARCH_V6SM): Likewise.
841
60e5ef9f
MGD		 8422010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
843
844 * arm.h (ARM_EXT_MP): Add.
845 (ARM_ARCH_V7A_MP): Likewise.
846
73a63ccf
MF		 8472010-09-22 Mike Frysinger <vapier@gentoo.org>
848
849 * bfin.h: Declare pseudoChr structs/defines.
850
ee99860a
MF		 8512010-09-21 Mike Frysinger <vapier@gentoo.org>
852
853 * bfin.h: Strip trailing whitespace.
854
f9c7014e
DD		 8552010-07-29 DJ Delorie <dj@redhat.com>
856
857 * rx.h (RX_Operand_Type): Add TwoReg.
858 (RX_Opcode_ID): Remove ediv and ediv2.
859
93378652
DD		 8602010-07-27 DJ Delorie <dj@redhat.com>
861
862 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
863
1cd986c5
NC		 8642010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
865 Ina Pandit <ina.pandit@kpitcummins.com>
866
867 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
868 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
869 PROCESSOR_V850E2_ALL.
870 Remove PROCESSOR_V850EA support.
871 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
872 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
873 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
874 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
875 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
876 V850_OPERAND_PERCENT.
877 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
878 V850_NOT_R0.
879 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
880 and V850E_PUSH_POP
881
9a2c7088
MR		 8822010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
883
884 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
885 (MIPS16_INSN_BRANCH): Rename to...
886 (MIPS16_INSN_COND_BRANCH): ... this.
887
bdc70b4a
AM		 8882010-07-03 Alan Modra <amodra@gmail.com>
889
890 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
891 Renumber other PPC_OPCODE defines.
892
f2bae120
AM		 8932010-07-03 Alan Modra <amodra@gmail.com>
894
895 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
896
360cfc9c
AM		 8972010-06-29 Alan Modra <amodra@gmail.com>
898
899 * maxq.h: Delete file.
900
e01d869a
AM		 9012010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
902
903 * ppc.h (PPC_OPCODE_E500): Define.
904
f79e2745
CM		 9052010-05-26 Catherine Moore <clm@codesourcery.com>
906
907 * opcode/mips.h (INSN_MIPS16): Remove.
908
2462afa1
JM		 9092010-04-21 Joseph Myers <joseph@codesourcery.com>
910
911 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
912
e4e42b45
NC		 9132010-04-15 Nick Clifton <nickc@redhat.com>
914
915 * alpha.h: Update copyright notice to use GPLv3.
916 * arc.h: Likewise.
917 * arm.h: Likewise.
918 * avr.h: Likewise.
919 * bfin.h: Likewise.
920 * cgen.h: Likewise.
921 * convex.h: Likewise.
922 * cr16.h: Likewise.
923 * cris.h: Likewise.
924 * crx.h: Likewise.
925 * d10v.h: Likewise.
926 * d30v.h: Likewise.
927 * dlx.h: Likewise.
928 * h8300.h: Likewise.
929 * hppa.h: Likewise.
930 * i370.h: Likewise.
931 * i386.h: Likewise.
932 * i860.h: Likewise.
933 * i960.h: Likewise.
934 * ia64.h: Likewise.
935 * m68hc11.h: Likewise.
936 * m68k.h: Likewise.
937 * m88k.h: Likewise.
938 * maxq.h: Likewise.
939 * mips.h: Likewise.
940 * mmix.h: Likewise.
941 * mn10200.h: Likewise.
942 * mn10300.h: Likewise.
943 * msp430.h: Likewise.
944 * np1.h: Likewise.
945 * ns32k.h: Likewise.
946 * or32.h: Likewise.
947 * pdp11.h: Likewise.
948 * pj.h: Likewise.
949 * pn.h: Likewise.
950 * ppc.h: Likewise.
951 * pyr.h: Likewise.
952 * rx.h: Likewise.
953 * s390.h: Likewise.
954 * score-datadep.h: Likewise.
955 * score-inst.h: Likewise.
956 * sparc.h: Likewise.
957 * spu-insns.h: Likewise.
958 * spu.h: Likewise.
959 * tic30.h: Likewise.
960 * tic4x.h: Likewise.
961 * tic54x.h: Likewise.
962 * tic80.h: Likewise.
963 * v850.h: Likewise.
964 * vax.h: Likewise.
965
40b36596
JM		 9662010-03-25 Joseph Myers <joseph@codesourcery.com>
967
968 * tic6x-control-registers.h, tic6x-insn-formats.h,
969 tic6x-opcode-table.h, tic6x.h: New.
970
c67a084a
NC		 9712010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
972
973 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
974
466ef64f
AM		 9752010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
976
977 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
978
1319d143
L		 9792010-01-14 H.J. Lu <hongjiu.lu@intel.com>
980
981 * ia64.h (ia64_find_opcode): Remove argument name.
982 (ia64_find_next_opcode): Likewise.
983 (ia64_dis_opcode): Likewise.
984 (ia64_free_opcode): Likewise.
985 (ia64_find_dependency): Likewise.
986
1fbb9298
DE		 9872009-11-22 Doug Evans <dje@sebabeach.org>
988
989 * cgen.h: Include bfd_stdint.h.
990 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
991
ada65aa3
PB		 9922009-11-18 Paul Brook <paul@codesourcery.com>
993
994 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
995
9e3c6df6
PB		 9962009-11-17 Paul Brook <paul@codesourcery.com>
997 Daniel Jacobowitz <dan@codesourcery.com>
998
999 * arm.h (ARM_EXT_V6_DSP): Define.
1000 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1001 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1002
0d734b5d
DD		 10032009-11-04 DJ Delorie <dj@redhat.com>
1004
1005 * rx.h (rx_decode_opcode) (mvtipl): Add.
1006 (mvtcp, mvfcp, opecp): Remove.
1007
62f3b8c8
PB		 10082009-11-02 Paul Brook <paul@codesourcery.com>
1009
1010 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1011 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1012 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1013 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1014 FPU_ARCH_NEON_VFP_V4): Define.
1015
ac1e9eca
DE		 10162009-10-23 Doug Evans <dje@sebabeach.org>
1017
1018 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1019 * cgen.h: Update. Improve multi-inclusion macro name.
1020
9fe54b1c
PB		 10212009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1022
1023 * ppc.h (PPC_OPCODE_476): Define.
1024
634b50f2
PB		 10252009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1026
1027 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1028
c7927a3c
NC		 10292009-09-29 DJ Delorie <dj@redhat.com>
1030
1031 * rx.h: New file.
1032
b961e85b
AM		 10332009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1034
1035 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1036
e0d602ec
BE		 10372009-09-21 Ben Elliston <bje@au.ibm.com>
1038
1039 * ppc.h (PPC_OPCODE_PPCA2): New.
1040
96d56e9f
NC		 10412009-09-05 Martin Thuresson <martin@mtme.org>
1042
1043 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1044
d3ce72d0
NC		 10452009-08-29 Martin Thuresson <martin@mtme.org>
1046
1047 * tic30.h (template): Rename type template to
1048 insn_template. Updated code to use new name.
1049 * tic54x.h (template): Rename type template to
1050 insn_template.
1051
824b28db
NH		 10522009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1053
1054 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1055
f865a31d
AG		 10562009-06-11 Anthony Green <green@moxielogic.com>
1057
1058 * moxie.h (MOXIE_F3_PCREL): Define.
1059 (moxie_form3_opc_info): Grow.
1060
0e7c7f11
AG		 10612009-06-06 Anthony Green <green@moxielogic.com>
1062
1063 * moxie.h (MOXIE_F1_M): Define.
1064
20135e4c
NC		 10652009-04-15 Anthony Green <green@moxielogic.com>
1066
1067 * moxie.h: Created.
1068
bcb012d3
DD		 10692009-04-06 DJ Delorie <dj@redhat.com>
1070
1071 * h8300.h: Add relaxation attributes to MOVA opcodes.
1072
69fe9ce5
AM		 10732009-03-10 Alan Modra <amodra@bigpond.net.au>
1074
1075 * ppc.h (ppc_parse_cpu): Declare.
1076
c3b7224a
NC		 10772009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1078
1079 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1080 and _IMM11 for mbitclr and mbitset.
1081 * score-datadep.h: Update dependency information.
1082
066be9f7
PB		 10832009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1084
1085 * ppc.h (PPC_OPCODE_POWER7): New.
1086
fedc618e
DE		 10872009-02-06 Doug Evans <dje@google.com>
1088
1089 * i386.h: Add comment regarding sse* insns and prefixes.
1090
52b6b6b9
JM		 10912009-02-03 Sandip Matte <sandip@rmicorp.com>
1092
1093 * mips.h (INSN_XLR): Define.
1094 (INSN_CHIP_MASK): Update.
1095 (CPU_XLR): Define.
1096 (OPCODE_IS_MEMBER): Update.
1097 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1098
35669430
DE		 10992009-01-28 Doug Evans <dje@google.com>
1100
1101 * opcode/i386.h: Add multiple inclusion protection.
1102 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1103 (EDI_REG_NUM): New macros.
1104 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1105 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1106 (REX_PREFIX_P): New macro.
35669430 1107
1cb0a767
PB		 11082009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1109
1110 * ppc.h (struct powerpc_opcode): New field "deprecated".
1111 (PPC_OPCODE_NOPOWER4): Delete.
1112
3aa3176b
TS		 11132008-11-28 Joshua Kinard <kumba@gentoo.org>
1114
1115 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1116 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1117
8e79c3df
CM		 11182008-11-18 Catherine Moore <clm@codesourcery.com>
1119
1120 * arm.h (FPU_NEON_FP16): New.
1121 (FPU_ARCH_NEON_FP16): New.
1122
de9a3e51
CF		 11232008-11-06 Chao-ying Fu <fu@mips.com>
1124
1125 * mips.h: Doucument '1' for 5-bit sync type.
1126
1ca35711
L		 11272008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1128
1129 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1130 IA64_RS_CR.
1131
9b4e5766
PB		 11322008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1133
1134 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1135
081ba1b3
AM		 11362008-07-30 Michael J. Eager <eager@eagercon.com>
1137
1138 * ppc.h (PPC_OPCODE_405): Define.
1139 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1140
fa452fa6
PB		 11412008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1142
1143 * ppc.h (ppc_cpu_t): New typedef.
1144 (struct powerpc_opcode <flags>): Use it.
1145 (struct powerpc_operand <insert, extract>): Likewise.
1146 (struct powerpc_macro <flags>): Likewise.
1147
bb35fb24
NC		 11482008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1149
1150 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1151 Update comment before MIPS16 field descriptors to mention MIPS16.
1152 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1153 BBIT.
1154 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1155 New bit masks and shift counts for cins and exts.
1156
dd3cbb7e
NC		 1157 * mips.h: Document new field descriptors +Q.
1158 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1159
d0799671
AN		 11602008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1161
9aff4b7a 1162 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1163 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1164
19a6653c
AM		 11652008-04-14 Edmar Wienskoski <edmar@freescale.com>
1166
1167 * ppc.h: (PPC_OPCODE_E500MC): New.
1168
c0f3af97
L		 11692008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1170
1171 * i386.h (MAX_OPERANDS): Set to 5.
1172 (MAX_MNEM_SIZE): Changed to 20.
1173
e210c36b
NC		 11742008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1175
1176 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1177
b1cc4aeb
PB		 11782008-03-09 Paul Brook <paul@codesourcery.com>
1179
1180 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1181
7e806470
PB		 11822008-03-04 Paul Brook <paul@codesourcery.com>
1183
1184 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1185 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1186 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1187
7b2185f9 11882008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1189 Nick Clifton <nickc@redhat.com>
1190
1191 PR 3134
1192 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1193 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1194 set.
af7329f0 1195
796d5313
NC		 11962008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1197
1198 * cr16.h (cr16_num_optab): Declared.
1199
d669d37f
NC		 12002008-02-14 Hakan Ardo <hakan@debian.org>
1201
1202 PR gas/2626
1203 * avr.h (AVR_ISA_2xxe): Define.
1204
e6429699
AN		 12052008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1206
1207 * mips.h: Update copyright.
1208 (INSN_CHIP_MASK): New macro.
1209 (INSN_OCTEON): New macro.
1210 (CPU_OCTEON): New macro.
1211 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1212
e210c36b
NC		 12132008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1214
1215 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1216
12172008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1218
1219 * avr.h (AVR_ISA_USB162): Add new opcode set.
1220 (AVR_ISA_AVR3): Likewise.
1221
350cc38d
MS		 12222007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1223
1224 * mips.h (INSN_LOONGSON_2E): New.
1225 (INSN_LOONGSON_2F): New.
1226 (CPU_LOONGSON_2E): New.
1227 (CPU_LOONGSON_2F): New.
1228 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1229
56950294
MS		 12302007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1231
1232 * mips.h (INSN_ISA*): Redefine certain values as an
1233 enumeration. Update comments.
1234 (mips_isa_table): New.
1235 (ISA_MIPS*): Redefine to match enumeration.
1236 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1237 values.
1238
c3d65c1c
BE		 12392007-08-08 Ben Elliston <bje@au.ibm.com>
1240
1241 * ppc.h (PPC_OPCODE_PPCPS): New.
1242
0fdaa005
L		 12432007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1244
1245 * m68k.h: Document j K & E.
1246
12472007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1248
1249 * cr16.h: New file for CR16 target.
1250
3896c469
AM		 12512007-05-02 Alan Modra <amodra@bigpond.net.au>
1252
1253 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1254
9a2e615a
NS		 12552007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1256
1257 * m68k.h (mcfisa_c): New.
1258 (mcfusp, mcf_mask): Adjust.
1259
b84bf58a
AM		 12602007-04-20 Alan Modra <amodra@bigpond.net.au>
1261
1262 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1263 (num_powerpc_operands): Declare.
1264 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1265 (PPC_OPERAND_PLUS1): Define.
1266
831480e9 12672007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1268
1269 * i386.h (REX_MODE64): Renamed to ...
1270 (REX_W): This.
1271 (REX_EXTX): Renamed to ...
1272 (REX_R): This.
1273 (REX_EXTY): Renamed to ...
1274 (REX_X): This.
1275 (REX_EXTZ): Renamed to ...
1276 (REX_B): This.
1277
0b1cf022
L		 12782007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1279
1280 * i386.h: Add entries from config/tc-i386.h and move tables
1281 to opcodes/i386-opc.h.
1282
d796c0ad
L		 12832007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1284
1285 * i386.h (FloatDR): Removed.
1286 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1287
30ac7323
AM		 12882007-03-01 Alan Modra <amodra@bigpond.net.au>
1289
1290 * spu-insns.h: Add soma double-float insns.
1291
8b082fb1 12922007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1293 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1294
1295 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1296 (INSN_DSPR2): Add flag for DSP R2 instructions.
1297 (M_BALIGN): New macro.
1298
4eed87de
AM		 12992007-02-14 Alan Modra <amodra@bigpond.net.au>
1300
1301 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1302 and Seg3ShortFrom with Shortform.
1303
fda592e8
L		 13042007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1305
1306 PR gas/4027
1307 * i386.h (i386_optab): Put the real "test" before the pseudo
1308 one.
1309
3bdcfdf4
KH		 13102007-01-08 Kazu Hirata <kazu@codesourcery.com>
1311
1312 * m68k.h (m68010up): OR fido_a.
1313
9840d27e
KH		 13142006-12-25 Kazu Hirata <kazu@codesourcery.com>
1315
1316 * m68k.h (fido_a): New.
1317
c629cdac
KH		 13182006-12-24 Kazu Hirata <kazu@codesourcery.com>
1319
1320 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1321 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1322 values.
1323
b7d9ef37
L		 13242006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1325
1326 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1327
b138abaa
NC		 13282006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1329
1330 * score-inst.h (enum score_insn_type): Add Insn_internal.
1331
e9f53129
AM		 13322006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1333 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1334 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1335 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1336 Alan Modra <amodra@bigpond.net.au>
1337
1338 * spu-insns.h: New file.
1339 * spu.h: New file.
1340
ede602d7
AM		 13412006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1342
1343 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1344
7918206c
MM		 13452006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1346
e4e42b45 1347 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1348 in amdfam10 architecture.
1349
ef05d495
L		 13502006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1351
1352 * i386.h: Replace CpuMNI with CpuSSSE3.
1353
2d447fca 13542006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1355 Joseph Myers <joseph@codesourcery.com>
1356 Ian Lance Taylor <ian@wasabisystems.com>
1357 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1358
1359 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1360
1c0d3aa6
NC		 13612006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1362
1363 * score-datadep.h: New file.
1364 * score-inst.h: New file.
1365
c2f0420e
L		 13662006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1367
1368 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1369 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1370 movdq2q and movq2dq.
1371
050dfa73
MM		 13722006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1373 Michael Meissner <michael.meissner@amd.com>
1374
1375 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1376
15965411
L		 13772006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1378
1379 * i386.h (i386_optab): Add "nop" with memory reference.
1380
46e883c5
L		 13812006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1382
1383 * i386.h (i386_optab): Update comment for 64bit NOP.
1384
9622b051
AM		 13852006-06-06 Ben Elliston <bje@au.ibm.com>
1386 Anton Blanchard <anton@samba.org>
1387
1388 * ppc.h (PPC_OPCODE_POWER6): Define.
1389 Adjust whitespace.
1390
a9e24354
TS		 13912006-06-05 Thiemo Seufer <ths@mips.com>
1392
e4e42b45 1393 * mips.h: Improve description of MT flags.
a9e24354 1394
a596001e
RS		 13952006-05-25 Richard Sandiford <richard@codesourcery.com>
1396
1397 * m68k.h (mcf_mask): Define.
1398
d43b4baf 13992006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1400 David Ung <davidu@mips.com>
d43b4baf
TS		 1401
1402 * mips.h (enum): Add macro M_CACHE_AB.
1403
39a7806d 14042006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1405 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1406 David Ung <davidu@mips.com>
1407
1408 * mips.h: Add INSN_SMARTMIPS define.
1409
9bcd4f99 14102006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1411 David Ung <davidu@mips.com>
9bcd4f99
TS		 1412
1413 * mips.h: Defines udi bits and masks. Add description of
1414 characters which may appear in the args field of udi
1415 instructions.
1416
ef0ee844
TS		 14172006-04-26 Thiemo Seufer <ths@networkno.de>
1418
1419 * mips.h: Improve comments describing the bitfield instruction
1420 fields.
1421
f7675147
L		 14222006-04-26 Julian Brown <julian@codesourcery.com>
1423
1424 * arm.h (FPU_VFP_EXT_V3): Define constant.
1425 (FPU_NEON_EXT_V1): Likewise.
1426 (FPU_VFP_HARD): Update.
1427 (FPU_VFP_V3): Define macro.
1428 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1429
ef0ee844 14302006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1431
1432 * avr.h (AVR_ISA_PWMx): New.
1433
2da12c60
NS		 14342006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1435
1436 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1437 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1438 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1439 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1440 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1441
0715c387
PB		 14422006-03-10 Paul Brook <paul@codesourcery.com>
1443
1444 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1445
34bdd094
DA		 14462006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1447
1448 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1449 first. Correct mask of bb "B" opcode.
1450
331d2d0d
L		 14512006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1452
1453 * i386.h (i386_optab): Support Intel Merom New Instructions.
1454
62b3e311
PB		 14552006-02-24 Paul Brook <paul@codesourcery.com>
1456
1457 * arm.h: Add V7 feature bits.
1458
59cf82fe
L		 14592006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1460
1461 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1462
e74cfd16
PB		 14632006-01-31 Paul Brook <paul@codesourcery.com>
1464 Richard Earnshaw <rearnsha@arm.com>
1465
1466 * arm.h: Use ARM_CPU_FEATURE.
1467 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1468 (arm_feature_set): Change to a structure.
1469 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1470 ARM_FEATURE): New macros.
1471
5b3f8a92
HPN		 14722005-12-07 Hans-Peter Nilsson <hp@axis.com>
1473
1474 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1475 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1476 (ADD_PC_INCR_OPCODE): Don't define.
1477
cb712a9e
L		 14782005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1479
1480 PR gas/1874
1481 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1482
0499d65b
TS		 14832005-11-14 David Ung <davidu@mips.com>
1484
1485 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1486 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1487 save/restore encoding of the args field.
1488
ea5ca089
DB		 14892005-10-28 Dave Brolley <brolley@redhat.com>
1490
1491 Contribute the following changes:
1492 2005-02-16 Dave Brolley <brolley@redhat.com>
1493
1494 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1495 cgen_isa_mask_* to cgen_bitset_*.
1496 * cgen.h: Likewise.
1497
16175d96
DB		 1498 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1499
1500 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1501 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1502 (CGEN_CPU_TABLE): Make isas a ponter.
1503
1504 2003-09-29 Dave Brolley <brolley@redhat.com>
1505
1506 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1507 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1508 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1509
1510 2002-12-13 Dave Brolley <brolley@redhat.com>
1511
1512 * cgen.h (symcat.h): #include it.
1513 (cgen-bitset.h): #include it.
1514 (CGEN_ATTR_VALUE_TYPE): Now a union.
1515 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1516 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1517 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1518 * cgen-bitset.h: New file.
1519
3c9b82ba
NC		 15202005-09-30 Catherine Moore <clm@cm00re.com>
1521
1522 * bfin.h: New file.
1523
6a2375c6
JB		 15242005-10-24 Jan Beulich <jbeulich@novell.com>
1525
1526 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1527 indirect operands.
1528
c06a12f8
DA		 15292005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1530
1531 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1532 Add FLAG_STRICT to pa10 ftest opcode.
1533
4d443107
DA		 15342005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1535
1536 * hppa.h (pa_opcodes): Remove lha entries.
1537
f0a3b40f
DA		 15382005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1539
1540 * hppa.h (FLAG_STRICT): Revise comment.
1541 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1542 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1543 entries for "fdc".
1544
e210c36b
NC		 15452005-09-30 Catherine Moore <clm@cm00re.com>
1546
1547 * bfin.h: New file.
1548
1b7e1362
DA		 15492005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1550
1551 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1552
089b39de
CF		 15532005-09-06 Chao-ying Fu <fu@mips.com>
1554
1555 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1556 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1557 define.
1558 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1559 (INSN_ASE_MASK): Update to include INSN_MT.
1560 (INSN_MT): New define for MT ASE.
1561
93c34b9b
CF		 15622005-08-25 Chao-ying Fu <fu@mips.com>
1563
1564 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1565 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1566 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1567 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1568 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1569 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1570 instructions.
1571 (INSN_DSP): New define for DSP ASE.
1572
848cf006
AM		 15732005-08-18 Alan Modra <amodra@bigpond.net.au>
1574
1575 * a29k.h: Delete.
1576
36ae0db3
DJ		 15772005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1578
1579 * ppc.h (PPC_OPCODE_E300): Define.
1580
8c929562
MS		 15812005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1582
1583 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1584
f7b8cccc
DA		 15852005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1586
1587 PR gas/336
1588 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1589 and pitlb.
1590
8b5328ac
JB		 15912005-07-27 Jan Beulich <jbeulich@novell.com>
1592
1593 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1594 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1595 Add movq-s as 64-bit variants of movd-s.
1596
f417d200
DA		 15972005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1598
18b3bdfc
DA		 1599 * hppa.h: Fix punctuation in comment.
1600
f417d200
DA		 1601 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1602 implicit space-register addressing. Set space-register bits on opcodes
1603 using implicit space-register addressing. Add various missing pa20
1604 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1605 space-register addressing. Use "fE" instead of "fe" in various
1606 fstw opcodes.
1607
9a145ce6
JB		 16082005-07-18 Jan Beulich <jbeulich@novell.com>
1609
1610 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1611
90700ea2
L		 16122007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1613
1614 * i386.h (i386_optab): Support Intel VMX Instructions.
1615
48f130a8
DA		 16162005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1617
1618 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1619
30123838
JB		 16202005-07-05 Jan Beulich <jbeulich@novell.com>
1621
1622 * i386.h (i386_optab): Add new insns.
1623
47b0e7ad
NC		 16242005-07-01 Nick Clifton <nickc@redhat.com>
1625
1626 * sparc.h: Add typedefs to structure declarations.
1627
b300c311
L		 16282005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1629
1630 PR 1013
1631 * i386.h (i386_optab): Update comments for 64bit addressing on
1632 mov. Allow 64bit addressing for mov and movq.
1633
2db495be
DA		 16342005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1635
1636 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1637 respectively, in various floating-point load and store patterns.
1638
caa05036
DA		 16392005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1640
1641 * hppa.h (FLAG_STRICT): Correct comment.
1642 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1643 PA 2.0 mneumonics when equivalent. Entries with cache control
1644 completers now require PA 1.1. Adjust whitespace.
1645
f4411256
AM		 16462005-05-19 Anton Blanchard <anton@samba.org>
1647
1648 * ppc.h (PPC_OPCODE_POWER5): Define.
1649
e172dbf8
NC		 16502005-05-10 Nick Clifton <nickc@redhat.com>
1651
1652 * Update the address and phone number of the FSF organization in
1653 the GPL notices in the following files:
1654 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1655 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1656 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1657 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1658 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1659 tic54x.h, tic80.h, v850.h, vax.h
1660
e44823cf
JB		 16612005-05-09 Jan Beulich <jbeulich@novell.com>
1662
1663 * i386.h (i386_optab): Add ht and hnt.
1664
791fe849
MK		 16652005-04-18 Mark Kettenis <kettenis@gnu.org>
1666
1667 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1668 Add xcrypt-ctr. Provide aliases without hyphens.
1669
faa7ef87
L		 16702005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1671
a63027e5
L		 1672 Moved from ../ChangeLog
1673
faa7ef87
L		 1674 2005-04-12 Paul Brook <paul@codesourcery.com>
1675 * m88k.h: Rename psr macros to avoid conflicts.
1676
1677 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1678 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1679 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1680 and ARM_ARCH_V6ZKT2.
1681
1682 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1683 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1684 Remove redundant instruction types.
1685 (struct argument): X_op - new field.
1686 (struct cst4_entry): Remove.
1687 (no_op_insn): Declare.
1688
1689 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1690 * crx.h (enum argtype): Rename types, remove unused types.
1691
1692 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1693 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1694 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1695 (enum operand_type): Rearrange operands, edit comments.
1696 replace us<N> with ui<N> for unsigned immediate.
1697 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1698 displacements (respectively).
1699 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1700 (instruction type): Add NO_TYPE_INS.
1701 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1702 (operand_entry): New field - 'flags'.
1703 (operand flags): New.
1704
1705 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1706 * crx.h (operand_type): Remove redundant types i3, i4,
1707 i5, i8, i12.
1708 Add new unsigned immediate types us3, us4, us5, us16.
1709
bc4bd9ab
MK		 17102005-04-12 Mark Kettenis <kettenis@gnu.org>
1711
1712 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1713 adjust them accordingly.
1714
373ff435
JB		 17152005-04-01 Jan Beulich <jbeulich@novell.com>
1716
1717 * i386.h (i386_optab): Add rdtscp.
1718
4cc91dba
L		 17192005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1720
1721 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1722 between memory and segment register. Allow movq for moving between
1723 general-purpose register and segment register.
4cc91dba 1724
9ae09ff9
JB		 17252005-02-09 Jan Beulich <jbeulich@novell.com>
1726
1727 PR gas/707
1728 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1729 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1730 fnstsw.
1731
638e7a64
NS		 17322006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1733
1734 * m68k.h (m68008, m68ec030, m68882): Remove.
1735 (m68k_mask): New.
1736 (cpu_m68k, cpu_cf): New.
1737 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1738 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1739
90219bd0
AO		 17402005-01-25 Alexandre Oliva <aoliva@redhat.com>
1741
1742 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1743 * cgen.h (enum cgen_parse_operand_type): Add
1744 CGEN_PARSE_OPERAND_SYMBOLIC.
1745
239cb185
FF		 17462005-01-21 Fred Fish <fnf@specifixinc.com>
1747
1748 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1749 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1750 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1751
dc9a9f39
FF		 17522005-01-19 Fred Fish <fnf@specifixinc.com>
1753
1754 * mips.h (struct mips_opcode): Add new pinfo2 member.
1755 (INSN_ALIAS): New define for opcode table entries that are
1756 specific instances of another entry, such as 'move' for an 'or'
1757 with a zero operand.
1758 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1759 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1760
98e7aba8
ILT		 17612004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1762
1763 * mips.h (CPU_RM9000): Define.
1764 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1765
37edbb65
JB		 17662004-11-25 Jan Beulich <jbeulich@novell.com>
1767
1768 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1769 to/from test registers are illegal in 64-bit mode. Add missing
1770 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1771 (previously one had to explicitly encode a rex64 prefix). Re-enable
1772 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1773 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1774
17752004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 1776
1777 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1778 available only with SSE2. Change the MMX additions introduced by SSE
1779 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1780 instructions by their now designated identifier (since combining i686
1781 and 3DNow! does not really imply 3DNow!A).
1782
f5c7edf4
AM		 17832004-11-19 Alan Modra <amodra@bigpond.net.au>
1784
1785 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1786 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1787
7499d566
NC		 17882004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1789 Vineet Sharma <vineets@noida.hcltech.com>
1790
1791 * maxq.h: New file: Disassembly information for the maxq port.
1792
bcb9eebe
L		 17932004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1794
1795 * i386.h (i386_optab): Put back "movzb".
1796
94bb3d38
HPN		 17972004-11-04 Hans-Peter Nilsson <hp@axis.com>
1798
1799 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1800 comments. Remove member cris_ver_sim. Add members
1801 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1802 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1803 (struct cris_support_reg, struct cris_cond15): New types.
1804 (cris_conds15): Declare.
1805 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1806 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1807 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1808 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1809 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1810 SIZE_FIELD_UNSIGNED.
1811
37edbb65 18122004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 1813
1814 * i386.h (sldx_Suf): Remove.
1815 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1816 (q_FP): Define, implying no REX64.
1817 (x_FP, sl_FP): Imply FloatMF.
1818 (i386_optab): Split reg and mem forms of moving from segment registers
1819 so that the memory forms can ignore the 16-/32-bit operand size
1820 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1821 all non-floating-point instructions. Unite 32- and 64-bit forms of
1822 movsx, movzx, and movd. Adjust floating point operations for the above
1823 changes to the *FP macros. Add DefaultSize to floating point control
1824 insns operating on larger memory ranges. Remove left over comments
1825 hinting at certain insns being Intel-syntax ones where the ones
1826 actually meant are already gone.
1827
48c9f030
NC		 18282004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1829
1830 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1831 instruction type.
1832
0dd132b6
NC		 18332004-09-30 Paul Brook <paul@codesourcery.com>
1834
1835 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1836 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1837
23794b24
MM		 18382004-09-11 Theodore A. Roth <troth@openavr.org>
1839
1840 * avr.h: Add support for
1841 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1842
2a309db0
AM		 18432004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1844
1845 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1846
b18c562e
NC		 18472004-08-24 Dmitry Diky <diwil@spec.ru>
1848
1849 * msp430.h (msp430_opc): Add new instructions.
1850 (msp430_rcodes): Declare new instructions.
1851 (msp430_hcodes): Likewise..
1852
45d313cd
NC		 18532004-08-13 Nick Clifton <nickc@redhat.com>
1854
1855 PR/301
1856 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1857 processors.
1858
30d1c836
ML		 18592004-08-30 Michal Ludvig <mludvig@suse.cz>
1860
1861 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1862
9a45f1c2
L		 18632004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1864
1865 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1866
543613e9
NC		 18672004-07-21 Jan Beulich <jbeulich@novell.com>
1868
1869 * i386.h: Adjust instruction descriptions to better match the
1870 specification.
1871
b781e558
RE		 18722004-07-16 Richard Earnshaw <rearnsha@arm.com>
1873
1874 * arm.h: Remove all old content. Replace with architecture defines
1875 from gas/config/tc-arm.c.
1876
8577e690
AS		 18772004-07-09 Andreas Schwab <schwab@suse.de>
1878
1879 * m68k.h: Fix comment.
1880
1fe1f39c
NC		 18812004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1882
1883 * crx.h: New file.
1884
1d9f512f
AM		 18852004-06-24 Alan Modra <amodra@bigpond.net.au>
1886
1887 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1888
be8c092b
NC		 18892004-05-24 Peter Barada <peter@the-baradas.com>
1890
1891 * m68k.h: Add 'size' to m68k_opcode.
1892
6b6e92f4
NC		 18932004-05-05 Peter Barada <peter@the-baradas.com>
1894
1895 * m68k.h: Switch from ColdFire chip name to core variant.
1896
18972004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 1898
1899 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1900 descriptions for new EMAC cases.
1901 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1902 handle Motorola MAC syntax.
1903 Allow disassembly of ColdFire V4e object files.
1904
fdd12ef3
AM		 19052004-03-16 Alan Modra <amodra@bigpond.net.au>
1906
1907 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1908
3922a64c
L		 19092004-03-12 Jakub Jelinek <jakub@redhat.com>
1910
1911 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1912
1f45d988
ML		 19132004-03-12 Michal Ludvig <mludvig@suse.cz>
1914
1915 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1916
0f10071e
ML		 19172004-03-12 Michal Ludvig <mludvig@suse.cz>
1918
1919 * i386.h (i386_optab): Added xstore/xcrypt insns.
1920
3255318a
NC		 19212004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1922
1923 * h8300.h (32bit ldc/stc): Add relaxing support.
1924
ca9a79a1 19252004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 1926
ca9a79a1
NC		 1927 * h8300.h (BITOP): Pass MEMRELAX flag.
1928
875a0b14
NC		 19292004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1930
1931 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1932 except for the H8S.
252b5132 1933
c9e214e5 1934For older changes see ChangeLog-9103
252b5132 1935\f
752937aa
NC		 1936Copyright (C) 2004-2012 Free Software Foundation, Inc.
1937
1938Copying and distribution of this file, with or without modification,
1939are permitted in any medium without royalty provided the copyright
1940notice and this notice are preserved.
1941
252b5132 1942Local Variables:
c9e214e5
AM		 1943mode: change-log
1944left-margin: 8
1945fill-column: 74
252b5132
RH		 1946version-control: never
1947End:
GDB Binutils - Deliverables
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