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[AArch64] Support for ARMv8.1a Adv.SIMD instructions
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
9e1f0fa7
MW		 12015-06-02 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64.h (AARCH64_FEATURE_RDMA): New.
4
290806fd
MW		 52015-06-02 Matthew Wahab <matthew.wahab@arm.com>
6
7 * aarch64.h (AARCH64_FEATURE_LOR): New.
8
f21cce2c
MW		 92015-06-01 Matthew Wahab <matthew.wahab@arm.com>
10
11 * aarch64.h (AARCH64_FEATURE_PAN): New.
12 (aarch64_sys_reg_supported_p): Declare.
13 (aarch64_pstatefield_supported_p): Declare.
14
0952813b
DD		 152015-04-30 DJ Delorie <dj@redhat.com>
16
17 * rl78.h (RL78_Dis_Isa): New.
18 (rl78_decode_opcode): Add ISA parameter.
19
823d2571
TG		 202015-03-24 Terry Guo <terry.guo@arm.com>
21
22 * arm.h (arm_feature_set): Extended to provide more available bits.
23 (ARM_ANY): Updated to follow above new definition.
24 (ARM_CPU_HAS_FEATURE): Likewise.
25 (ARM_CPU_IS_ANY): Likewise.
26 (ARM_MERGE_FEATURE_SETS): Likewise.
27 (ARM_CLEAR_FEATURE): Likewise.
28 (ARM_FEATURE): Likewise.
29 (ARM_FEATURE_COPY): New macro.
30 (ARM_FEATURE_EQUAL): Likewise.
31 (ARM_FEATURE_ZERO): Likewise.
32 (ARM_FEATURE_CORE_EQUAL): Likewise.
33 (ARM_FEATURE_LOW): Likewise.
34 (ARM_FEATURE_CORE_LOW): Likewise.
35 (ARM_FEATURE_CORE_COPROC): Likewise.
36
f63c1776
PA		 372015-02-19 Pedro Alves <palves@redhat.com>
38
39 * cgen.h [__cplusplus]: Wrap in extern "C".
40 * msp430-decode.h [__cplusplus]: Likewise.
41 * nios2.h [__cplusplus]: Likewise.
42 * rl78.h [__cplusplus]: Likewise.
43 * rx.h [__cplusplus]: Likewise.
44 * tilegx.h [__cplusplus]: Likewise.
45
3f8107ab
AM		 462015-01-28 James Bowman <james.bowman@ftdichip.com>
47
48 * ft32.h: New file.
49
1e2e8c52
AK		 502015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
51
52 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
53
b90efa5b
AM		 542015-01-01 Alan Modra <amodra@gmail.com>
55
56 Update year range in copyright notice of all files.
57
bffb6004
AG		 582014-12-27 Anthony Green <green@moxielogic.com>
59
60 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
61 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
62
1945cfa5
EB		 632014-12-06 Eric Botcazou <ebotcazou@adacore.com>
64
65 * visium.h: New file.
66
d306ce58
SL		 672014-11-28 Sandra Loosemore <sandra@codesourcery.com>
68
69 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
70 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
71 (NIOS2_INSN_OPTARG): Renumber.
72
b4714c7c
SL		 732014-11-06 Sandra Loosemore <sandra@codesourcery.com>
74
75 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
76 declaration. Fix obsolete comment.
77
96ba4233
SL		 782014-10-23 Sandra Loosemore <sandra@codesourcery.com>
79
80 * nios2.h (enum iw_format_type): New.
81 (struct nios2_opcode): Update comments. Add size and format fields.
82 (NIOS2_INSN_OPTARG): New.
83 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
84 (struct nios2_reg): Add regtype field.
85 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
86 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
87 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
88 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
89 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
90 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
91 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
92 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
93 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
94 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
95 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
96 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
97 (OP_MASK_OP, OP_SH_OP): Delete.
98 (OP_MASK_IOP, OP_SH_IOP): Delete.
99 (OP_MASK_IRD, OP_SH_IRD): Delete.
100 (OP_MASK_IRT, OP_SH_IRT): Delete.
101 (OP_MASK_IRS, OP_SH_IRS): Delete.
102 (OP_MASK_ROP, OP_SH_ROP): Delete.
103 (OP_MASK_RRD, OP_SH_RRD): Delete.
104 (OP_MASK_RRT, OP_SH_RRT): Delete.
105 (OP_MASK_RRS, OP_SH_RRS): Delete.
106 (OP_MASK_JOP, OP_SH_JOP): Delete.
107 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
108 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
109 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
110 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
111 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
112 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
113 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
114 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
115 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
116 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
117 (OP_MASK_<insn>, OP_MASK): Delete.
118 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
119 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
120 Include nios2r1.h to define new instruction opcode constants
121 and accessors.
122 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
123 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
124 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
125 (NUMOPCODES, NUMREGISTERS): Delete.
126 * nios2r1.h: New file.
127
0b6be415
JM		 1282014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
129
130 * sparc.h (HWCAP2_VIS3B): Documentation improved.
131
3d68f91c
JM		 1322014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
133
134 * sparc.h (sparc_opcode): new field `hwcaps2'.
135 (HWCAP2_FJATHPLUS): New define.
136 (HWCAP2_VIS3B): Likewise.
137 (HWCAP2_ADP): Likewise.
138 (HWCAP2_SPARC5): Likewise.
139 (HWCAP2_MWAIT): Likewise.
140 (HWCAP2_XMPMUL): Likewise.
141 (HWCAP2_XMONT): Likewise.
142 (HWCAP2_NSEC): Likewise.
143 (HWCAP2_FJATHHPC): Likewise.
144 (HWCAP2_FJDES): Likewise.
145 (HWCAP2_FJAES): Likewise.
146 Document the new operand kind `{', corresponding to the mcdper
147 ancillary state register.
148 Document the new operand kind }, which represents frsd floating
149 point registers (double precision) which must be the same than
150 frs1 in its containing instruction.
151
40c7a7cb
KLC		 1522014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
153
154 * nds32.h: Add new opcode declaration.
155
7361da2c
AB		 1562014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
157 Matthew Fortune <matthew.fortune@imgtec.com>
158
159 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
160 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
161 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
162 +I, +O, +R, +:, +\, +", +;
163 (mips_check_prev_operand): New struct.
164 (INSN2_FORBIDDEN_SLOT): New define.
165 (INSN_ISA32R6): New define.
166 (INSN_ISA64R6): New define.
167 (INSN_UPTO32R6): New define.
168 (INSN_UPTO64R6): New define.
169 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
170 (ISA_MIPS32R6): New define.
171 (ISA_MIPS64R6): New define.
172 (CPU_MIPS32R6): New define.
173 (CPU_MIPS64R6): New define.
174 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
175
ee804238
JW		 1762014-09-03 Jiong Wang <jiong.wang@arm.com>
177
178 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
179 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
180 (aarch64_insn_class): Add lse_atomic.
181 (F_LSE_SZ): New field added.
182 (opcode_has_special_coder): Recognize F_LSE_SZ.
183
5575639b
MR		 1842014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
185
186 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
187 over to `+J'.
188
43885403
MF		 1892014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
190
191 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
192 (INSN_LOAD_COPROC): New define.
193 (INSN_COPROC_MOVE_DELAY): Rename to...
194 (INSN_COPROC_MOVE): New define.
195
f36e8886
BS		 1962014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
197 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
198 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
199 Soundararajan <Sounderarajan.D@atmel.com>
200
201 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
202 (AVR_ISA_2xxxa): Define ISA without LPM.
203 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
204 Add doc for contraint used in 16 bit lds/sts.
205 Adjust ISA group for icall, ijmp, pop and push.
206 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
207
00b32ff2
NC		 2082014-05-19 Nick Clifton <nickc@redhat.com>
209
210 * msp430.h (struct msp430_operand_s): Add vshift field.
211
ae52f483
AB		 2122014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
213
214 * mips.h (INSN_ISA_MASK): Updated.
215 (INSN_ISA32R3): New define.
216 (INSN_ISA32R5): New define.
217 (INSN_ISA64R3): New define.
218 (INSN_ISA64R5): New define.
219 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
220 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
221 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
222 mips64r5.
223 (INSN_UPTO32R3): New define.
224 (INSN_UPTO32R5): New define.
225 (INSN_UPTO64R3): New define.
226 (INSN_UPTO64R5): New define.
227 (ISA_MIPS32R3): New define.
228 (ISA_MIPS32R5): New define.
229 (ISA_MIPS64R3): New define.
230 (ISA_MIPS64R5): New define.
231 (CPU_MIPS32R3): New define.
232 (CPU_MIPS32R5): New define.
233 (CPU_MIPS64R3): New define.
234 (CPU_MIPS64R5): New define.
235
3efe9ec5
RS		 2362014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
237
238 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
239
73589c9d
CS		 2402014-04-22 Christian Svensson <blue@cmd.nu>
241
242 * or32.h: Delete.
243
4b95cf5c
AM		 2442014-03-05 Alan Modra <amodra@gmail.com>
245
246 Update copyright years.
247
e269fea7
AB		 2482013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
249
250 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
251 microMIPS.
252
35c08157
KLC		 2532013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
254 Wei-Cheng Wang <cole945@gmail.com>
255
256 * nds32.h: New file for Andes NDS32.
257
594d8fa8
MF		 2582013-12-07 Mike Frysinger <vapier@gentoo.org>
259
260 * bfin.h: Remove +x file mode.
261
87b8eed7
YZ		 2622013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
263
264 * aarch64.h (aarch64_pstatefields): Change element type to
265 aarch64_sys_reg.
266
c9fb6e58
YZ		 2672013-11-18 Renlin Li <Renlin.Li@arm.com>
268
269 * arm.h (ARM_AEXT_V7VE): New define.
270 (ARM_ARCH_V7VE): New define.
271 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
272
a203d9b7
YZ		 2732013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
274
275 Revert
276
277 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
278
279 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
280 (aarch64_sys_reg_writeonly_p): Ditto.
281
75468c93
YZ		 2822013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
283
284 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
285 (aarch64_sys_reg_writeonly_p): Ditto.
286
49eec193
YZ		 2872013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
288
289 * aarch64.h (aarch64_sys_reg): New typedef.
290 (aarch64_sys_regs): Change to define with the new type.
291 (aarch64_sys_reg_deprecated_p): Declare.
292
68a64283
YZ		 2932013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
294
295 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
296 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
297
387a82f1
CF		 2982013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
299
300 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
301 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
302 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
303 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
304 For MIPS, update extension character sequences after +.
305 (ASE_MSA): New define.
306 (ASE_MSA64): New define.
307 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
308 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
309 For microMIPS, update extension character sequences after +.
310
9aff4b7a
NC		 3112013-08-23 Yuri Chornoivan <yurchor@ukr.net>
312
313 PR binutils/15834
314 * i960.h: Fix typos.
315
e423441d
RS		 3162013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
317
318 * mips.h: Remove references to "+I" and imm2_expr.
319
5e0dc5ba
RS		 3202013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
321
322 * mips.h (M_DEXT, M_DINS): Delete.
323
0f35dbc4
RS		 3242013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
325
326 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
327 (mips_optional_operand_p): New function.
328
14daeee3
RS		 3292013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
330 Richard Sandiford <rdsandiford@googlemail.com>
331
332 * mips.h: Document new VU0 operand characters.
333 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
334 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
335 (OP_REG_R5900_ACC): New mips_reg_operand_types.
336 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
337 (mips_vu0_channel_mask): Declare.
338
3ccad066
RS		 3392013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
340
341 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
342 (mips_int_operand_min, mips_int_operand_max): New functions.
343 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
344
fc76e730
RS		 3452013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
346
347 * mips.h (mips_decode_reg_operand): New function.
348 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
349 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
350 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
351 New macros.
352 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
353 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
354 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
355 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
356 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
357 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
358 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
359 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
360 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
361 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
362 macros to cover the gaps.
363 (INSN2_MOD_SP): Replace with...
364 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
365 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
366 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
367 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
368 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
369 Delete.
370
26545944
RS		 3712013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
372
373 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
374 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
375 (MIPS16_INSN_COND_BRANCH): Delete.
376
7e8b059b
L		 3772013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
378 Kirill Yukhin <kirill.yukhin@intel.com>
379 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
380
381 * i386.h (BND_PREFIX_OPCODE): New.
382
c3c07478
RS		 3832013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
384
385 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
386 OP_SAVE_RESTORE_LIST.
387 (decode_mips16_operand): Declare.
388
ab902481
RS		 3892013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
390
391 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
392 (mips_operand, mips_int_operand, mips_mapped_int_operand)
393 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
394 (mips_pcrel_operand): New structures.
395 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
396 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
397 (decode_mips_operand, decode_micromips_operand): Declare.
398
cc537e56
RS		 3992013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
400
401 * mips.h: Document MIPS16 "I" opcode.
402
f2ae14a1
RS		 4032013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
404
405 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
406 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
407 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
408 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
409 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
410 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
411 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
412 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
413 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
414 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
415 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
416 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
417 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
418 Rename to...
419 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
420 (M_USD_AB): ...these.
421
5c324c16
RS		 4222013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
423
424 * mips.h: Remove documentation of "[" and "]". Update documentation
425 of "k" and the MDMX formats.
426
23e69e47
RS		 4272013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
428
429 * mips.h: Update documentation of "+s" and "+S".
430
27c5c572
RS		 4312013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
432
433 * mips.h: Document "+i".
434
e76ff5ab
RS		 4352013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
436
437 * mips.h: Remove "mi" documentation. Update "mh" documentation.
438 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
439 Delete.
440 (INSN2_WRITE_GPR_MHI): Rename to...
441 (INSN2_WRITE_GPR_MH): ...this.
442
fa7616a4
RS		 4432013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
444
445 * mips.h: Remove documentation of "+D" and "+T".
446
18870af7
RS		 4472013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
448
449 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
450 Use "source" rather than "destination" for microMIPS "G".
451
833794fc
MR		 4522013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
453
454 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
455 values.
456
c3678916
RS		 4572013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
458
459 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
460
7f3c4072
CM		 4612013-06-17 Catherine Moore <clm@codesourcery.com>
462 Maciej W. Rozycki <macro@codesourcery.com>
463 Chao-Ying Fu <fu@mips.com>
464
465 * mips.h (OP_SH_EVAOFFSET): Define.
466 (OP_MASK_EVAOFFSET): Define.
467 (INSN_ASE_MASK): Delete.
468 (ASE_EVA): Define.
469 (M_CACHEE_AB, M_CACHEE_OB): New.
470 (M_LBE_OB, M_LBE_AB): New.
471 (M_LBUE_OB, M_LBUE_AB): New.
472 (M_LHE_OB, M_LHE_AB): New.
473 (M_LHUE_OB, M_LHUE_AB): New.
474 (M_LLE_AB, M_LLE_OB): New.
475 (M_LWE_OB, M_LWE_AB): New.
476 (M_LWLE_AB, M_LWLE_OB): New.
477 (M_LWRE_AB, M_LWRE_OB): New.
478 (M_PREFE_AB, M_PREFE_OB): New.
479 (M_SCE_AB, M_SCE_OB): New.
480 (M_SBE_OB, M_SBE_AB): New.
481 (M_SHE_OB, M_SHE_AB): New.
482 (M_SWE_OB, M_SWE_AB): New.
483 (M_SWLE_AB, M_SWLE_OB): New.
484 (M_SWRE_AB, M_SWRE_OB): New.
485 (MICROMIPSOP_SH_EVAOFFSET): Define.
486 (MICROMIPSOP_MASK_EVAOFFSET): Define.
487
0c8fe7cf
SL		 4882013-06-12 Sandra Loosemore <sandra@codesourcery.com>
489
490 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
491
c77c0862
RS		 4922013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
493
494 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
495
b015e599
AP		 4962013-05-09 Andrew Pinski <apinski@cavium.com>
497
498 * mips.h (OP_MASK_CODE10): Correct definition.
499 (OP_SH_CODE10): Likewise.
500 Add a comment that "+J" is used now for OP_*CODE10.
501 (INSN_ASE_MASK): Update.
502 (INSN_VIRT): New macro.
503 (INSN_VIRT64): New macro
504
13761a11
NC		 5052013-05-02 Nick Clifton <nickc@redhat.com>
506
507 * msp430.h: Add patterns for MSP430X instructions.
508
0afd1215
DM		 5092013-04-06 David S. Miller <davem@davemloft.net>
510
511 * sparc.h (F_PREFERRED): Define.
512 (F_PREF_ALIAS): Define.
513
41702d50
NC		 5142013-04-03 Nick Clifton <nickc@redhat.com>
515
516 * v850.h (V850_INVERSE_PCREL): Define.
517
e21e1a51
NC		 5182013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
519
520 PR binutils/15068
521 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
522
51dcdd4d
NC		 5232013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
524
525 PR binutils/15068
526 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
527 Add 16-bit opcodes.
528 * tic6xc-opcode-table.h: Add 16-bit insns.
529 * tic6x.h: Add support for 16-bit insns.
530
81f5558e
NC		 5312013-03-21 Michael Schewe <michael.schewe@gmx.net>
532
533 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
534 and mov.b/w/l Rs,@(d:32,ERd).
535
165546ad
NC		 5362013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
537
538 PR gas/15082
539 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
540 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
541 tic6x_operand_xregpair operand coding type.
542 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
543 opcode field, usu ORXREGD1324 for the src2 operand and remove the
544 TIC6X_FLAG_NO_CROSS.
545
795b8e6b
NC		 5462013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
547
548 PR gas/15095
549 * tic6x.h (enum tic6x_coding_method): Add
550 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
551 separately the msb and lsb of a register pair. This is needed to
552 encode the opcodes in the same way as TI assembler does.
553 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
554 and rsqrdp opcodes to use the new field coding types.
555
dd5181d5
KT		 5562013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
557
558 * arm.h (CRC_EXT_ARMV8): New constant.
559 (ARCH_CRC_ARMV8): New macro.
560
e60bb1dd
YZ		 5612013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
562
563 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
564
36591ba1
SL		 5652013-02-06 Sandra Loosemore <sandra@codesourcery.com>
566 Andrew Jenner <andrew@codesourcery.com>
567
568 Based on patches from Altera Corporation.
569
570 * nios2.h: New file.
571
e30181a5
YZ		 5722013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
573
574 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
575
0c9573f4
NC		 5762013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
577
578 PR gas/15069
579 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
580
981dc7f1
NC		 5812013-01-24 Nick Clifton <nickc@redhat.com>
582
583 * v850.h: Add e3v5 support.
584
f5555712
YZ		 5852013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
586
587 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
588
5817ffd1
PB		 5892013-01-10 Peter Bergner <bergner@vnet.ibm.com>
590
591 * ppc.h (PPC_OPCODE_POWER8): New define.
592 (PPC_OPCODE_HTM): Likewise.
593
a3c62988
NC		 5942013-01-10 Will Newton <will.newton@imgtec.com>
595
596 * metag.h: New file.
597
73335eae
NC		 5982013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
599
600 * cr16.h (make_instruction): Rename to cr16_make_instruction.
601 (match_opcode): Rename to cr16_match_opcode.
602
e407c74b
NC		 6032013-01-04 Juergen Urban <JuergenUrban@gmx.de>
604
605 * mips.h: Add support for r5900 instructions including lq and sq.
606
bab4becb
NC		 6072013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
608
609 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
610 (make_instruction,match_opcode): Added function prototypes.
611 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
612
776fc418
AM		 6132012-11-23 Alan Modra <amodra@gmail.com>
614
615 * ppc.h (ppc_parse_cpu): Update prototype.
616
f05682d4
DA		 6172012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
618
619 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
620 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
621
cfc72779
AK		 6222012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
623
624 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
625
b3e14eda
L		 6262012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
627
628 * ia64.h (ia64_opnd): Add new operand types.
629
2c63854f
DM		 6302012-08-21 David S. Miller <davem@davemloft.net>
631
632 * sparc.h (F3F4): New macro.
633
a06ea964 6342012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 635 Laurent Desnogues <laurent.desnogues@arm.com>
636 Jim MacArthur <jim.macarthur@arm.com>
637 Marcus Shawcroft <marcus.shawcroft@arm.com>
638 Nigel Stephens <nigel.stephens@arm.com>
639 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
640 Richard Earnshaw <rearnsha@arm.com>
641 Sofiane Naci <sofiane.naci@arm.com>
642 Tejas Belagod <tejas.belagod@arm.com>
643 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 644
645 * aarch64.h: New file.
646
35d0a169 6472012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 648 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 649
650 * mips.h (mips_opcode): Add the exclusions field.
651 (OPCODE_IS_MEMBER): Remove macro.
652 (cpu_is_member): New inline function.
653 (opcode_is_member): Likewise.
654
03f66e8a 6552012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 656 Catherine Moore <clm@codesourcery.com>
657 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 658
659 * mips.h: Document microMIPS DSP ASE usage.
660 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
661 microMIPS DSP ASE support.
662 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
663 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
664 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
665 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
666 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
667 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
668 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
669
9d7b4c23
MR		 6702012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
671
672 * mips.h: Fix a typo in description.
673
76e879f8
NC		 6742012-06-07 Georg-Johann Lay <avr@gjlay.de>
675
676 * avr.h: (AVR_ISA_XCH): New define.
677 (AVR_ISA_XMEGA): Use it.
678 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
679
6927f982
NC		 6802012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
681
682 * m68hc11.h: Add XGate definitions.
683 (struct m68hc11_opcode): Add xg_mask field.
684
b9c361e0
JL		 6852012-05-14 Catherine Moore <clm@codesourcery.com>
686 Maciej W. Rozycki <macro@codesourcery.com>
687 Rhonda Wittels <rhonda@codesourcery.com>
688
6927f982 689 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 690 (PPC_OP_SA): New macro.
691 (PPC_OP_SE_VLE): New macro.
692 (PPC_OP): Use a variable shift amount.
693 (powerpc_operand): Update comments.
694 (PPC_OPSHIFT_INV): New macro.
695 (PPC_OPERAND_CR): Replace with...
696 (PPC_OPERAND_CR_BIT): ...this and
697 (PPC_OPERAND_CR_REG): ...this.
698
699
f6c1a2d5
NC		 7002012-05-03 Sean Keys <skeys@ipdatasys.com>
701
702 * xgate.h: Header file for XGATE assembler.
703
ec668d69
DM		 7042012-04-27 David S. Miller <davem@davemloft.net>
705
6cda1326
DM		 706 * sparc.h: Document new arg code' )' for crypto RS3
707 immediates.
708
ec668d69
DM		 709 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
710 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
711 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
712 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
713 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
714 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
715 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
716 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
717 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
718 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
719 HWCAP_CBCOND, HWCAP_CRC32): New defines.
720
aea77599
AM		 7212012-03-10 Edmar Wienskoski <edmar@freescale.com>
722
723 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
724
1f42f8b3
AM		 7252012-02-27 Alan Modra <amodra@gmail.com>
726
727 * crx.h (cst4_map): Update declaration.
728
6f7be959
WL		 7292012-02-25 Walter Lee <walt@tilera.com>
730
731 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
732 TILEGX_OPC_LD_TLS.
733 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
734 TILEPRO_OPC_LW_TLS_SN.
735
42164a71
L		 7362012-02-08 H.J. Lu <hongjiu.lu@intel.com>
737
738 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
739 (XRELEASE_PREFIX_OPCODE): Likewise.
740
432233b3 7412011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 742 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 743
744 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
745 (INSN_OCTEON2): New macro.
746 (CPU_OCTEON2): New macro.
747 (OPCODE_IS_MEMBER): Add Octeon2.
748
dd6a37e7
AP		 7492011-11-29 Andrew Pinski <apinski@cavium.com>
750
751 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
752 (INSN_OCTEONP): New macro.
753 (CPU_OCTEONP): New macro.
754 (OPCODE_IS_MEMBER): Add Octeon+.
755 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
756
99c513f6
DD		 7572011-11-01 DJ Delorie <dj@redhat.com>
758
759 * rl78.h: New file.
760
26f85d7a
MR		 7612011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
762
763 * mips.h: Fix a typo in description.
764
9e8c70f9
DM		 7652011-09-21 David S. Miller <davem@davemloft.net>
766
767 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
768 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
769 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
770 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
771
dec0624d 7722011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 773 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 774
775 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
776 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
777 (INSN_ASE_MASK): Add the MCU bit.
778 (INSN_MCU): New macro.
779 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
780 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
781
2b0c8b40
MR		 7822011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
783
784 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
785 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
786 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
787 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
788 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
789 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
790 (INSN2_READ_GPR_MMN): Likewise.
791 (INSN2_READ_FPR_D): Change the bit used.
792 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
793 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
794 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
795 (INSN2_COND_BRANCH): Likewise.
796 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
797 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
798 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
799 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
800 (INSN2_MOD_GPR_MN): Likewise.
801
ea783ef3
DM		 8022011-08-05 David S. Miller <davem@davemloft.net>
803
804 * sparc.h: Document new format codes '4', '5', and '('.
805 (OPF_LOW4, RS3): New macros.
806
7c176fa8
MR		 8072011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
808
809 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
810 order of flags documented.
811
2309ddf2
MR		 8122011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
813
814 * mips.h: Clarify the description of microMIPS instruction
815 manipulation macros.
816 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
817
df58fc94 8182011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 819 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 820
821 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
822 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
823 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
824 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
825 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
826 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
827 (OP_MASK_RS3, OP_SH_RS3): Likewise.
828 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
829 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
830 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
831 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
832 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
833 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
834 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
835 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
836 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
837 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
838 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
839 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
840 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
841 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
842 (INSN_WRITE_GPR_S): New macro.
843 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
844 (INSN2_READ_FPR_D): Likewise.
845 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
846 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
847 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
848 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
849 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
850 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
851 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
852 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
853 (CPU_MICROMIPS): New macro.
854 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
855 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
856 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
857 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
858 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
859 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
860 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
861 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
862 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
863 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
864 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
865 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
866 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
867 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
868 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
869 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
870 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
871 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
872 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
873 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
874 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
875 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
876 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
877 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
878 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
879 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
880 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
881 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
882 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
883 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
884 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
885 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
886 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
887 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
888 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
889 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
890 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
891 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
892 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
893 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
894 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
895 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
896 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
897 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
898 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
899 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
900 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
901 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
902 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
903 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
904 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
905 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
906 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
907 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
908 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
909 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
910 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
911 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
912 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
913 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
914 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
915 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
916 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
917 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
918 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
919 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
920 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
921 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
922 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
923 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
924 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
925 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
926 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
927 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
928 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
929 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
930 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
931 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
932 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
933 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
934 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
935 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
936 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
937 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
938 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
939 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
940 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
941 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
942 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
943 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
944 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
945 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
946 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
947 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
948 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
949 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
950 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
951 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
952 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
953 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
954 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
955 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
956 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
957 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
958 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
959 (micromips_opcodes): New declaration.
960 (bfd_micromips_num_opcodes): Likewise.
961
bcd530a7
RS		 9622011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
963
964 * mips.h (INSN_TRAP): Rename to...
965 (INSN_NO_DELAY_SLOT): ... this.
966 (INSN_SYNC): Remove macro.
967
2dad5a91
EW		 9682011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
969
970 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
971 a duplicate of AVR_ISA_SPM.
972
5d73b1f1
NC		 9732011-07-01 Nick Clifton <nickc@redhat.com>
974
975 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
976
ef26d60e
MF		 9772011-06-18 Robin Getz <robin.getz@analog.com>
978
979 * bfin.h (is_macmod_signed): New func
980
8fb8dca7
MF		 9812011-06-18 Mike Frysinger <vapier@gentoo.org>
982
983 * bfin.h (is_macmod_pmove): Add missing space before func args.
984 (is_macmod_hmove): Likewise.
985
aa137e4d
NC		 9862011-06-13 Walter Lee <walt@tilera.com>
987
988 * tilegx.h: New file.
989 * tilepro.h: New file.
990
3b2f0793
PB		 9912011-05-31 Paul Brook <paul@codesourcery.com>
992
aa137e4d
NC		 993 * arm.h (ARM_ARCH_V7R_IDIV): Define.
994
9952011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
996
997 * s390.h: Replace S390_OPERAND_REG_EVEN with
998 S390_OPERAND_REG_PAIR.
999
10002011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1001
1002 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1003
ac7f631b
NC		 10042011-04-18 Julian Brown <julian@codesourcery.com>
1005
1006 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1007
84701018
NC		 10082011-04-11 Dan McDonald <dan@wellkeeper.com>
1009
1010 PR gas/12296
1011 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1012
8cc66334
EW		 10132011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1014
1015 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1016 New instruction set flags.
1017 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1018
3eebd5eb
MR		 10192011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1020
1021 * mips.h (M_PREF_AB): New enum value.
1022
26bb3ddd
MF		 10232011-02-12 Mike Frysinger <vapier@gentoo.org>
1024
89c0d58c
MR		 1025 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1026 M_IU): Define.
1027 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1028
dd76fcb8
MF		 10292011-02-11 Mike Frysinger <vapier@gentoo.org>
1030
1031 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1032
98d23bef
BS		 10332011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1034
1035 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1036 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1037
3c853d93
DA		 10382010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1039
1040 PR gas/11395
1041 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1042 "bb" entries.
1043
79676006
DA		 10442010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1045
1046 PR gas/11395
1047 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1048
1bec78e9
RS		 10492010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1050
1051 * mips.h: Update commentary after last commit.
1052
98675402
RS		 10532010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1054
1055 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1056 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1057 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1058
aa137e4d
NC		 10592010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1060
1061 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1062
435b94a4
RS		 10632010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1064
1065 * mips.h: Fix previous commit.
1066
d051516a
NC		 10672010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1068
1069 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1070 (INSN_LOONGSON_3A): Clear bit 31.
1071
251665fc
MGD		 10722010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1073
1074 PR gas/12198
1075 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1076 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1077 (ARM_ARCH_V6M_ONLY): New define.
1078
fd503541
NC		 10792010-11-11 Mingming Sun <mingm.sun@gmail.com>
1080
1081 * mips.h (INSN_LOONGSON_3A): Defined.
1082 (CPU_LOONGSON_3A): Defined.
1083 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1084
4469d2be
AM		 10852010-10-09 Matt Rice <ratmice@gmail.com>
1086
1087 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1088 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1089
90ec0d68
MGD		 10902010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1091
1092 * arm.h (ARM_EXT_VIRT): New define.
1093 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1094 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1095 Extensions.
1096
eea54501 10972010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1098
eea54501
MGD		 1099 * arm.h (ARM_AEXT_ADIV): New define.
1100 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1101
b2a5fbdc
MGD		 11022010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1103
1104 * arm.h (ARM_EXT_OS): New define.
1105 (ARM_AEXT_V6SM): Likewise.
1106 (ARM_ARCH_V6SM): Likewise.
1107
60e5ef9f
MGD		 11082010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1109
1110 * arm.h (ARM_EXT_MP): Add.
1111 (ARM_ARCH_V7A_MP): Likewise.
1112
73a63ccf
MF		 11132010-09-22 Mike Frysinger <vapier@gentoo.org>
1114
1115 * bfin.h: Declare pseudoChr structs/defines.
1116
ee99860a
MF		 11172010-09-21 Mike Frysinger <vapier@gentoo.org>
1118
1119 * bfin.h: Strip trailing whitespace.
1120
f9c7014e
DD		 11212010-07-29 DJ Delorie <dj@redhat.com>
1122
1123 * rx.h (RX_Operand_Type): Add TwoReg.
1124 (RX_Opcode_ID): Remove ediv and ediv2.
1125
93378652
DD		 11262010-07-27 DJ Delorie <dj@redhat.com>
1127
1128 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1129
1cd986c5
NC		 11302010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1131 Ina Pandit <ina.pandit@kpitcummins.com>
1132
1133 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1134 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1135 PROCESSOR_V850E2_ALL.
1136 Remove PROCESSOR_V850EA support.
1137 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1138 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1139 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1140 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1141 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1142 V850_OPERAND_PERCENT.
1143 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1144 V850_NOT_R0.
1145 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1146 and V850E_PUSH_POP
1147
9a2c7088
MR		 11482010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1149
1150 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1151 (MIPS16_INSN_BRANCH): Rename to...
1152 (MIPS16_INSN_COND_BRANCH): ... this.
1153
bdc70b4a
AM		 11542010-07-03 Alan Modra <amodra@gmail.com>
1155
1156 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1157 Renumber other PPC_OPCODE defines.
1158
f2bae120
AM		 11592010-07-03 Alan Modra <amodra@gmail.com>
1160
1161 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1162
360cfc9c
AM		 11632010-06-29 Alan Modra <amodra@gmail.com>
1164
1165 * maxq.h: Delete file.
1166
e01d869a
AM		 11672010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1168
1169 * ppc.h (PPC_OPCODE_E500): Define.
1170
f79e2745
CM		 11712010-05-26 Catherine Moore <clm@codesourcery.com>
1172
1173 * opcode/mips.h (INSN_MIPS16): Remove.
1174
2462afa1
JM		 11752010-04-21 Joseph Myers <joseph@codesourcery.com>
1176
1177 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1178
e4e42b45
NC		 11792010-04-15 Nick Clifton <nickc@redhat.com>
1180
1181 * alpha.h: Update copyright notice to use GPLv3.
1182 * arc.h: Likewise.
1183 * arm.h: Likewise.
1184 * avr.h: Likewise.
1185 * bfin.h: Likewise.
1186 * cgen.h: Likewise.
1187 * convex.h: Likewise.
1188 * cr16.h: Likewise.
1189 * cris.h: Likewise.
1190 * crx.h: Likewise.
1191 * d10v.h: Likewise.
1192 * d30v.h: Likewise.
1193 * dlx.h: Likewise.
1194 * h8300.h: Likewise.
1195 * hppa.h: Likewise.
1196 * i370.h: Likewise.
1197 * i386.h: Likewise.
1198 * i860.h: Likewise.
1199 * i960.h: Likewise.
1200 * ia64.h: Likewise.
1201 * m68hc11.h: Likewise.
1202 * m68k.h: Likewise.
1203 * m88k.h: Likewise.
1204 * maxq.h: Likewise.
1205 * mips.h: Likewise.
1206 * mmix.h: Likewise.
1207 * mn10200.h: Likewise.
1208 * mn10300.h: Likewise.
1209 * msp430.h: Likewise.
1210 * np1.h: Likewise.
1211 * ns32k.h: Likewise.
1212 * or32.h: Likewise.
1213 * pdp11.h: Likewise.
1214 * pj.h: Likewise.
1215 * pn.h: Likewise.
1216 * ppc.h: Likewise.
1217 * pyr.h: Likewise.
1218 * rx.h: Likewise.
1219 * s390.h: Likewise.
1220 * score-datadep.h: Likewise.
1221 * score-inst.h: Likewise.
1222 * sparc.h: Likewise.
1223 * spu-insns.h: Likewise.
1224 * spu.h: Likewise.
1225 * tic30.h: Likewise.
1226 * tic4x.h: Likewise.
1227 * tic54x.h: Likewise.
1228 * tic80.h: Likewise.
1229 * v850.h: Likewise.
1230 * vax.h: Likewise.
1231
40b36596
JM		 12322010-03-25 Joseph Myers <joseph@codesourcery.com>
1233
1234 * tic6x-control-registers.h, tic6x-insn-formats.h,
1235 tic6x-opcode-table.h, tic6x.h: New.
1236
c67a084a
NC		 12372010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1238
1239 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1240
466ef64f
AM		 12412010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1242
1243 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1244
1319d143
L		 12452010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1246
1247 * ia64.h (ia64_find_opcode): Remove argument name.
1248 (ia64_find_next_opcode): Likewise.
1249 (ia64_dis_opcode): Likewise.
1250 (ia64_free_opcode): Likewise.
1251 (ia64_find_dependency): Likewise.
1252
1fbb9298
DE		 12532009-11-22 Doug Evans <dje@sebabeach.org>
1254
1255 * cgen.h: Include bfd_stdint.h.
1256 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1257
ada65aa3
PB		 12582009-11-18 Paul Brook <paul@codesourcery.com>
1259
1260 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1261
9e3c6df6
PB		 12622009-11-17 Paul Brook <paul@codesourcery.com>
1263 Daniel Jacobowitz <dan@codesourcery.com>
1264
1265 * arm.h (ARM_EXT_V6_DSP): Define.
1266 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1267 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1268
0d734b5d
DD		 12692009-11-04 DJ Delorie <dj@redhat.com>
1270
1271 * rx.h (rx_decode_opcode) (mvtipl): Add.
1272 (mvtcp, mvfcp, opecp): Remove.
1273
62f3b8c8
PB		 12742009-11-02 Paul Brook <paul@codesourcery.com>
1275
1276 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1277 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1278 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1279 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1280 FPU_ARCH_NEON_VFP_V4): Define.
1281
ac1e9eca
DE		 12822009-10-23 Doug Evans <dje@sebabeach.org>
1283
1284 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1285 * cgen.h: Update. Improve multi-inclusion macro name.
1286
9fe54b1c
PB		 12872009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1288
1289 * ppc.h (PPC_OPCODE_476): Define.
1290
634b50f2
PB		 12912009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1292
1293 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1294
c7927a3c
NC		 12952009-09-29 DJ Delorie <dj@redhat.com>
1296
1297 * rx.h: New file.
1298
b961e85b
AM		 12992009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1300
1301 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1302
e0d602ec
BE		 13032009-09-21 Ben Elliston <bje@au.ibm.com>
1304
1305 * ppc.h (PPC_OPCODE_PPCA2): New.
1306
96d56e9f
NC		 13072009-09-05 Martin Thuresson <martin@mtme.org>
1308
1309 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1310
d3ce72d0
NC		 13112009-08-29 Martin Thuresson <martin@mtme.org>
1312
1313 * tic30.h (template): Rename type template to
1314 insn_template. Updated code to use new name.
1315 * tic54x.h (template): Rename type template to
1316 insn_template.
1317
824b28db
NH		 13182009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1319
1320 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1321
f865a31d
AG		 13222009-06-11 Anthony Green <green@moxielogic.com>
1323
1324 * moxie.h (MOXIE_F3_PCREL): Define.
1325 (moxie_form3_opc_info): Grow.
1326
0e7c7f11
AG		 13272009-06-06 Anthony Green <green@moxielogic.com>
1328
1329 * moxie.h (MOXIE_F1_M): Define.
1330
20135e4c
NC		 13312009-04-15 Anthony Green <green@moxielogic.com>
1332
1333 * moxie.h: Created.
1334
bcb012d3
DD		 13352009-04-06 DJ Delorie <dj@redhat.com>
1336
1337 * h8300.h: Add relaxation attributes to MOVA opcodes.
1338
69fe9ce5
AM		 13392009-03-10 Alan Modra <amodra@bigpond.net.au>
1340
1341 * ppc.h (ppc_parse_cpu): Declare.
1342
c3b7224a
NC		 13432009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1344
1345 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1346 and _IMM11 for mbitclr and mbitset.
1347 * score-datadep.h: Update dependency information.
1348
066be9f7
PB		 13492009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1350
1351 * ppc.h (PPC_OPCODE_POWER7): New.
1352
fedc618e
DE		 13532009-02-06 Doug Evans <dje@google.com>
1354
1355 * i386.h: Add comment regarding sse* insns and prefixes.
1356
52b6b6b9
JM		 13572009-02-03 Sandip Matte <sandip@rmicorp.com>
1358
1359 * mips.h (INSN_XLR): Define.
1360 (INSN_CHIP_MASK): Update.
1361 (CPU_XLR): Define.
1362 (OPCODE_IS_MEMBER): Update.
1363 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1364
35669430
DE		 13652009-01-28 Doug Evans <dje@google.com>
1366
1367 * opcode/i386.h: Add multiple inclusion protection.
1368 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1369 (EDI_REG_NUM): New macros.
1370 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1371 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1372 (REX_PREFIX_P): New macro.
35669430 1373
1cb0a767
PB		 13742009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1375
1376 * ppc.h (struct powerpc_opcode): New field "deprecated".
1377 (PPC_OPCODE_NOPOWER4): Delete.
1378
3aa3176b
TS		 13792008-11-28 Joshua Kinard <kumba@gentoo.org>
1380
1381 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1382 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1383
8e79c3df
CM		 13842008-11-18 Catherine Moore <clm@codesourcery.com>
1385
1386 * arm.h (FPU_NEON_FP16): New.
1387 (FPU_ARCH_NEON_FP16): New.
1388
de9a3e51
CF		 13892008-11-06 Chao-ying Fu <fu@mips.com>
1390
1391 * mips.h: Doucument '1' for 5-bit sync type.
1392
1ca35711
L		 13932008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1394
1395 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1396 IA64_RS_CR.
1397
9b4e5766
PB		 13982008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1399
1400 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1401
081ba1b3
AM		 14022008-07-30 Michael J. Eager <eager@eagercon.com>
1403
1404 * ppc.h (PPC_OPCODE_405): Define.
1405 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1406
fa452fa6
PB		 14072008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1408
1409 * ppc.h (ppc_cpu_t): New typedef.
1410 (struct powerpc_opcode <flags>): Use it.
1411 (struct powerpc_operand <insert, extract>): Likewise.
1412 (struct powerpc_macro <flags>): Likewise.
1413
bb35fb24
NC		 14142008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1415
1416 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1417 Update comment before MIPS16 field descriptors to mention MIPS16.
1418 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1419 BBIT.
1420 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1421 New bit masks and shift counts for cins and exts.
1422
dd3cbb7e
NC		 1423 * mips.h: Document new field descriptors +Q.
1424 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1425
d0799671
AN		 14262008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1427
9aff4b7a 1428 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1429 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1430
19a6653c
AM		 14312008-04-14 Edmar Wienskoski <edmar@freescale.com>
1432
1433 * ppc.h: (PPC_OPCODE_E500MC): New.
1434
c0f3af97
L		 14352008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1436
1437 * i386.h (MAX_OPERANDS): Set to 5.
1438 (MAX_MNEM_SIZE): Changed to 20.
1439
e210c36b
NC		 14402008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1441
1442 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1443
b1cc4aeb
PB		 14442008-03-09 Paul Brook <paul@codesourcery.com>
1445
1446 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1447
7e806470
PB		 14482008-03-04 Paul Brook <paul@codesourcery.com>
1449
1450 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1451 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1452 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1453
7b2185f9 14542008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1455 Nick Clifton <nickc@redhat.com>
1456
1457 PR 3134
1458 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1459 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1460 set.
af7329f0 1461
796d5313
NC		 14622008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1463
1464 * cr16.h (cr16_num_optab): Declared.
1465
d669d37f
NC		 14662008-02-14 Hakan Ardo <hakan@debian.org>
1467
1468 PR gas/2626
1469 * avr.h (AVR_ISA_2xxe): Define.
1470
e6429699
AN		 14712008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1472
1473 * mips.h: Update copyright.
1474 (INSN_CHIP_MASK): New macro.
1475 (INSN_OCTEON): New macro.
1476 (CPU_OCTEON): New macro.
1477 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1478
e210c36b
NC		 14792008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1480
1481 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1482
14832008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1484
1485 * avr.h (AVR_ISA_USB162): Add new opcode set.
1486 (AVR_ISA_AVR3): Likewise.
1487
350cc38d
MS		 14882007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1489
1490 * mips.h (INSN_LOONGSON_2E): New.
1491 (INSN_LOONGSON_2F): New.
1492 (CPU_LOONGSON_2E): New.
1493 (CPU_LOONGSON_2F): New.
1494 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1495
56950294
MS		 14962007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1497
1498 * mips.h (INSN_ISA*): Redefine certain values as an
1499 enumeration. Update comments.
1500 (mips_isa_table): New.
1501 (ISA_MIPS*): Redefine to match enumeration.
1502 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1503 values.
1504
c3d65c1c
BE		 15052007-08-08 Ben Elliston <bje@au.ibm.com>
1506
1507 * ppc.h (PPC_OPCODE_PPCPS): New.
1508
0fdaa005
L		 15092007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1510
1511 * m68k.h: Document j K & E.
1512
15132007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1514
1515 * cr16.h: New file for CR16 target.
1516
3896c469
AM		 15172007-05-02 Alan Modra <amodra@bigpond.net.au>
1518
1519 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1520
9a2e615a
NS		 15212007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1522
1523 * m68k.h (mcfisa_c): New.
1524 (mcfusp, mcf_mask): Adjust.
1525
b84bf58a
AM		 15262007-04-20 Alan Modra <amodra@bigpond.net.au>
1527
1528 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1529 (num_powerpc_operands): Declare.
1530 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1531 (PPC_OPERAND_PLUS1): Define.
1532
831480e9 15332007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1534
1535 * i386.h (REX_MODE64): Renamed to ...
1536 (REX_W): This.
1537 (REX_EXTX): Renamed to ...
1538 (REX_R): This.
1539 (REX_EXTY): Renamed to ...
1540 (REX_X): This.
1541 (REX_EXTZ): Renamed to ...
1542 (REX_B): This.
1543
0b1cf022
L		 15442007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1545
1546 * i386.h: Add entries from config/tc-i386.h and move tables
1547 to opcodes/i386-opc.h.
1548
d796c0ad
L		 15492007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1550
1551 * i386.h (FloatDR): Removed.
1552 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1553
30ac7323
AM		 15542007-03-01 Alan Modra <amodra@bigpond.net.au>
1555
1556 * spu-insns.h: Add soma double-float insns.
1557
8b082fb1 15582007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1559 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1560
1561 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1562 (INSN_DSPR2): Add flag for DSP R2 instructions.
1563 (M_BALIGN): New macro.
1564
4eed87de
AM		 15652007-02-14 Alan Modra <amodra@bigpond.net.au>
1566
1567 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1568 and Seg3ShortFrom with Shortform.
1569
fda592e8
L		 15702007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1571
1572 PR gas/4027
1573 * i386.h (i386_optab): Put the real "test" before the pseudo
1574 one.
1575
3bdcfdf4
KH		 15762007-01-08 Kazu Hirata <kazu@codesourcery.com>
1577
1578 * m68k.h (m68010up): OR fido_a.
1579
9840d27e
KH		 15802006-12-25 Kazu Hirata <kazu@codesourcery.com>
1581
1582 * m68k.h (fido_a): New.
1583
c629cdac
KH		 15842006-12-24 Kazu Hirata <kazu@codesourcery.com>
1585
1586 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1587 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1588 values.
1589
b7d9ef37
L		 15902006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1591
1592 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1593
b138abaa
NC		 15942006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1595
1596 * score-inst.h (enum score_insn_type): Add Insn_internal.
1597
e9f53129
AM		 15982006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1599 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1600 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1601 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1602 Alan Modra <amodra@bigpond.net.au>
1603
1604 * spu-insns.h: New file.
1605 * spu.h: New file.
1606
ede602d7
AM		 16072006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1608
1609 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1610
7918206c
MM		 16112006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1612
e4e42b45 1613 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1614 in amdfam10 architecture.
1615
ef05d495
L		 16162006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1617
1618 * i386.h: Replace CpuMNI with CpuSSSE3.
1619
2d447fca 16202006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1621 Joseph Myers <joseph@codesourcery.com>
1622 Ian Lance Taylor <ian@wasabisystems.com>
1623 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1624
1625 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1626
1c0d3aa6
NC		 16272006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1628
1629 * score-datadep.h: New file.
1630 * score-inst.h: New file.
1631
c2f0420e
L		 16322006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1633
1634 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1635 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1636 movdq2q and movq2dq.
1637
050dfa73
MM		 16382006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1639 Michael Meissner <michael.meissner@amd.com>
1640
1641 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1642
15965411
L		 16432006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1644
1645 * i386.h (i386_optab): Add "nop" with memory reference.
1646
46e883c5
L		 16472006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1648
1649 * i386.h (i386_optab): Update comment for 64bit NOP.
1650
9622b051
AM		 16512006-06-06 Ben Elliston <bje@au.ibm.com>
1652 Anton Blanchard <anton@samba.org>
1653
1654 * ppc.h (PPC_OPCODE_POWER6): Define.
1655 Adjust whitespace.
1656
a9e24354
TS		 16572006-06-05 Thiemo Seufer <ths@mips.com>
1658
e4e42b45 1659 * mips.h: Improve description of MT flags.
a9e24354 1660
a596001e
RS		 16612006-05-25 Richard Sandiford <richard@codesourcery.com>
1662
1663 * m68k.h (mcf_mask): Define.
1664
d43b4baf 16652006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1666 David Ung <davidu@mips.com>
d43b4baf
TS		 1667
1668 * mips.h (enum): Add macro M_CACHE_AB.
1669
39a7806d 16702006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1671 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1672 David Ung <davidu@mips.com>
1673
1674 * mips.h: Add INSN_SMARTMIPS define.
1675
9bcd4f99 16762006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1677 David Ung <davidu@mips.com>
9bcd4f99
TS		 1678
1679 * mips.h: Defines udi bits and masks. Add description of
1680 characters which may appear in the args field of udi
1681 instructions.
1682
ef0ee844
TS		 16832006-04-26 Thiemo Seufer <ths@networkno.de>
1684
1685 * mips.h: Improve comments describing the bitfield instruction
1686 fields.
1687
f7675147
L		 16882006-04-26 Julian Brown <julian@codesourcery.com>
1689
1690 * arm.h (FPU_VFP_EXT_V3): Define constant.
1691 (FPU_NEON_EXT_V1): Likewise.
1692 (FPU_VFP_HARD): Update.
1693 (FPU_VFP_V3): Define macro.
1694 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1695
ef0ee844 16962006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1697
1698 * avr.h (AVR_ISA_PWMx): New.
1699
2da12c60
NS		 17002006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1701
1702 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1703 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1704 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1705 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1706 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1707
0715c387
PB		 17082006-03-10 Paul Brook <paul@codesourcery.com>
1709
1710 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1711
34bdd094
DA		 17122006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1713
1714 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1715 first. Correct mask of bb "B" opcode.
1716
331d2d0d
L		 17172006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1718
1719 * i386.h (i386_optab): Support Intel Merom New Instructions.
1720
62b3e311
PB		 17212006-02-24 Paul Brook <paul@codesourcery.com>
1722
1723 * arm.h: Add V7 feature bits.
1724
59cf82fe
L		 17252006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1726
1727 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1728
e74cfd16
PB		 17292006-01-31 Paul Brook <paul@codesourcery.com>
1730 Richard Earnshaw <rearnsha@arm.com>
1731
1732 * arm.h: Use ARM_CPU_FEATURE.
1733 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1734 (arm_feature_set): Change to a structure.
1735 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1736 ARM_FEATURE): New macros.
1737
5b3f8a92
HPN		 17382005-12-07 Hans-Peter Nilsson <hp@axis.com>
1739
1740 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1741 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1742 (ADD_PC_INCR_OPCODE): Don't define.
1743
cb712a9e
L		 17442005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1745
1746 PR gas/1874
1747 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1748
0499d65b
TS		 17492005-11-14 David Ung <davidu@mips.com>
1750
1751 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1752 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1753 save/restore encoding of the args field.
1754
ea5ca089
DB		 17552005-10-28 Dave Brolley <brolley@redhat.com>
1756
1757 Contribute the following changes:
1758 2005-02-16 Dave Brolley <brolley@redhat.com>
1759
1760 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1761 cgen_isa_mask_* to cgen_bitset_*.
1762 * cgen.h: Likewise.
1763
16175d96
DB		 1764 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1765
1766 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1767 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1768 (CGEN_CPU_TABLE): Make isas a ponter.
1769
1770 2003-09-29 Dave Brolley <brolley@redhat.com>
1771
1772 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1773 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1774 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1775
1776 2002-12-13 Dave Brolley <brolley@redhat.com>
1777
1778 * cgen.h (symcat.h): #include it.
1779 (cgen-bitset.h): #include it.
1780 (CGEN_ATTR_VALUE_TYPE): Now a union.
1781 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1782 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1783 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1784 * cgen-bitset.h: New file.
1785
3c9b82ba
NC		 17862005-09-30 Catherine Moore <clm@cm00re.com>
1787
1788 * bfin.h: New file.
1789
6a2375c6
JB		 17902005-10-24 Jan Beulich <jbeulich@novell.com>
1791
1792 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1793 indirect operands.
1794
c06a12f8
DA		 17952005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1796
1797 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1798 Add FLAG_STRICT to pa10 ftest opcode.
1799
4d443107
DA		 18002005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1801
1802 * hppa.h (pa_opcodes): Remove lha entries.
1803
f0a3b40f
DA		 18042005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1805
1806 * hppa.h (FLAG_STRICT): Revise comment.
1807 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1808 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1809 entries for "fdc".
1810
e210c36b
NC		 18112005-09-30 Catherine Moore <clm@cm00re.com>
1812
1813 * bfin.h: New file.
1814
1b7e1362
DA		 18152005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1816
1817 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1818
089b39de
CF		 18192005-09-06 Chao-ying Fu <fu@mips.com>
1820
1821 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1822 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1823 define.
1824 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1825 (INSN_ASE_MASK): Update to include INSN_MT.
1826 (INSN_MT): New define for MT ASE.
1827
93c34b9b
CF		 18282005-08-25 Chao-ying Fu <fu@mips.com>
1829
1830 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1831 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1832 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1833 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1834 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1835 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1836 instructions.
1837 (INSN_DSP): New define for DSP ASE.
1838
848cf006
AM		 18392005-08-18 Alan Modra <amodra@bigpond.net.au>
1840
1841 * a29k.h: Delete.
1842
36ae0db3
DJ		 18432005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1844
1845 * ppc.h (PPC_OPCODE_E300): Define.
1846
8c929562
MS		 18472005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1848
1849 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1850
f7b8cccc
DA		 18512005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1852
1853 PR gas/336
1854 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1855 and pitlb.
1856
8b5328ac
JB		 18572005-07-27 Jan Beulich <jbeulich@novell.com>
1858
1859 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1860 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1861 Add movq-s as 64-bit variants of movd-s.
1862
f417d200
DA		 18632005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1864
18b3bdfc
DA		 1865 * hppa.h: Fix punctuation in comment.
1866
f417d200
DA		 1867 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1868 implicit space-register addressing. Set space-register bits on opcodes
1869 using implicit space-register addressing. Add various missing pa20
1870 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1871 space-register addressing. Use "fE" instead of "fe" in various
1872 fstw opcodes.
1873
9a145ce6
JB		 18742005-07-18 Jan Beulich <jbeulich@novell.com>
1875
1876 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1877
90700ea2
L		 18782007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1879
1880 * i386.h (i386_optab): Support Intel VMX Instructions.
1881
48f130a8
DA		 18822005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1883
1884 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1885
30123838
JB		 18862005-07-05 Jan Beulich <jbeulich@novell.com>
1887
1888 * i386.h (i386_optab): Add new insns.
1889
47b0e7ad
NC		 18902005-07-01 Nick Clifton <nickc@redhat.com>
1891
1892 * sparc.h: Add typedefs to structure declarations.
1893
b300c311
L		 18942005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1895
1896 PR 1013
1897 * i386.h (i386_optab): Update comments for 64bit addressing on
1898 mov. Allow 64bit addressing for mov and movq.
1899
2db495be
DA		 19002005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1901
1902 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1903 respectively, in various floating-point load and store patterns.
1904
caa05036
DA		 19052005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1906
1907 * hppa.h (FLAG_STRICT): Correct comment.
1908 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1909 PA 2.0 mneumonics when equivalent. Entries with cache control
1910 completers now require PA 1.1. Adjust whitespace.
1911
f4411256
AM		 19122005-05-19 Anton Blanchard <anton@samba.org>
1913
1914 * ppc.h (PPC_OPCODE_POWER5): Define.
1915
e172dbf8
NC		 19162005-05-10 Nick Clifton <nickc@redhat.com>
1917
1918 * Update the address and phone number of the FSF organization in
1919 the GPL notices in the following files:
1920 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1921 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1922 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1923 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1924 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1925 tic54x.h, tic80.h, v850.h, vax.h
1926
e44823cf
JB		 19272005-05-09 Jan Beulich <jbeulich@novell.com>
1928
1929 * i386.h (i386_optab): Add ht and hnt.
1930
791fe849
MK		 19312005-04-18 Mark Kettenis <kettenis@gnu.org>
1932
1933 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1934 Add xcrypt-ctr. Provide aliases without hyphens.
1935
faa7ef87
L		 19362005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1937
a63027e5
L		 1938 Moved from ../ChangeLog
1939
faa7ef87
L		 1940 2005-04-12 Paul Brook <paul@codesourcery.com>
1941 * m88k.h: Rename psr macros to avoid conflicts.
1942
1943 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1944 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1945 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1946 and ARM_ARCH_V6ZKT2.
1947
1948 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1949 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1950 Remove redundant instruction types.
1951 (struct argument): X_op - new field.
1952 (struct cst4_entry): Remove.
1953 (no_op_insn): Declare.
1954
1955 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1956 * crx.h (enum argtype): Rename types, remove unused types.
1957
1958 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1959 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1960 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1961 (enum operand_type): Rearrange operands, edit comments.
1962 replace us<N> with ui<N> for unsigned immediate.
1963 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1964 displacements (respectively).
1965 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1966 (instruction type): Add NO_TYPE_INS.
1967 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1968 (operand_entry): New field - 'flags'.
1969 (operand flags): New.
1970
1971 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1972 * crx.h (operand_type): Remove redundant types i3, i4,
1973 i5, i8, i12.
1974 Add new unsigned immediate types us3, us4, us5, us16.
1975
bc4bd9ab
MK		 19762005-04-12 Mark Kettenis <kettenis@gnu.org>
1977
1978 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1979 adjust them accordingly.
1980
373ff435
JB		 19812005-04-01 Jan Beulich <jbeulich@novell.com>
1982
1983 * i386.h (i386_optab): Add rdtscp.
1984
4cc91dba
L		 19852005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1986
1987 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1988 between memory and segment register. Allow movq for moving between
1989 general-purpose register and segment register.
4cc91dba 1990
9ae09ff9
JB		 19912005-02-09 Jan Beulich <jbeulich@novell.com>
1992
1993 PR gas/707
1994 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1995 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1996 fnstsw.
1997
638e7a64
NS		 19982006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1999
2000 * m68k.h (m68008, m68ec030, m68882): Remove.
2001 (m68k_mask): New.
2002 (cpu_m68k, cpu_cf): New.
2003 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2004 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2005
90219bd0
AO		 20062005-01-25 Alexandre Oliva <aoliva@redhat.com>
2007
2008 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2009 * cgen.h (enum cgen_parse_operand_type): Add
2010 CGEN_PARSE_OPERAND_SYMBOLIC.
2011
239cb185
FF		 20122005-01-21 Fred Fish <fnf@specifixinc.com>
2013
2014 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2015 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2016 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2017
dc9a9f39
FF		 20182005-01-19 Fred Fish <fnf@specifixinc.com>
2019
2020 * mips.h (struct mips_opcode): Add new pinfo2 member.
2021 (INSN_ALIAS): New define for opcode table entries that are
2022 specific instances of another entry, such as 'move' for an 'or'
2023 with a zero operand.
2024 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2025 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2026
98e7aba8
ILT		 20272004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2028
2029 * mips.h (CPU_RM9000): Define.
2030 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2031
37edbb65
JB		 20322004-11-25 Jan Beulich <jbeulich@novell.com>
2033
2034 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2035 to/from test registers are illegal in 64-bit mode. Add missing
2036 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2037 (previously one had to explicitly encode a rex64 prefix). Re-enable
2038 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2039 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2040
20412004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2042
2043 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2044 available only with SSE2. Change the MMX additions introduced by SSE
2045 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2046 instructions by their now designated identifier (since combining i686
2047 and 3DNow! does not really imply 3DNow!A).
2048
f5c7edf4
AM		 20492004-11-19 Alan Modra <amodra@bigpond.net.au>
2050
2051 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2052 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2053
7499d566
NC		 20542004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2055 Vineet Sharma <vineets@noida.hcltech.com>
2056
2057 * maxq.h: New file: Disassembly information for the maxq port.
2058
bcb9eebe
L		 20592004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2060
2061 * i386.h (i386_optab): Put back "movzb".
2062
94bb3d38
HPN		 20632004-11-04 Hans-Peter Nilsson <hp@axis.com>
2064
2065 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2066 comments. Remove member cris_ver_sim. Add members
2067 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2068 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2069 (struct cris_support_reg, struct cris_cond15): New types.
2070 (cris_conds15): Declare.
2071 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2072 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2073 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2074 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2075 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2076 SIZE_FIELD_UNSIGNED.
2077
37edbb65 20782004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2079
2080 * i386.h (sldx_Suf): Remove.
2081 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2082 (q_FP): Define, implying no REX64.
2083 (x_FP, sl_FP): Imply FloatMF.
2084 (i386_optab): Split reg and mem forms of moving from segment registers
2085 so that the memory forms can ignore the 16-/32-bit operand size
2086 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2087 all non-floating-point instructions. Unite 32- and 64-bit forms of
2088 movsx, movzx, and movd. Adjust floating point operations for the above
2089 changes to the *FP macros. Add DefaultSize to floating point control
2090 insns operating on larger memory ranges. Remove left over comments
2091 hinting at certain insns being Intel-syntax ones where the ones
2092 actually meant are already gone.
2093
48c9f030
NC		 20942004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2095
2096 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2097 instruction type.
2098
0dd132b6
NC		 20992004-09-30 Paul Brook <paul@codesourcery.com>
2100
2101 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2102 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2103
23794b24
MM		 21042004-09-11 Theodore A. Roth <troth@openavr.org>
2105
2106 * avr.h: Add support for
2107 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2108
2a309db0
AM		 21092004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2110
2111 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2112
b18c562e
NC		 21132004-08-24 Dmitry Diky <diwil@spec.ru>
2114
2115 * msp430.h (msp430_opc): Add new instructions.
2116 (msp430_rcodes): Declare new instructions.
2117 (msp430_hcodes): Likewise..
2118
45d313cd
NC		 21192004-08-13 Nick Clifton <nickc@redhat.com>
2120
2121 PR/301
2122 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2123 processors.
2124
30d1c836
ML		 21252004-08-30 Michal Ludvig <mludvig@suse.cz>
2126
2127 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2128
9a45f1c2
L		 21292004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2130
2131 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2132
543613e9
NC		 21332004-07-21 Jan Beulich <jbeulich@novell.com>
2134
2135 * i386.h: Adjust instruction descriptions to better match the
2136 specification.
2137
b781e558
RE		 21382004-07-16 Richard Earnshaw <rearnsha@arm.com>
2139
2140 * arm.h: Remove all old content. Replace with architecture defines
2141 from gas/config/tc-arm.c.
2142
8577e690
AS		 21432004-07-09 Andreas Schwab <schwab@suse.de>
2144
2145 * m68k.h: Fix comment.
2146
1fe1f39c
NC		 21472004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2148
2149 * crx.h: New file.
2150
1d9f512f
AM		 21512004-06-24 Alan Modra <amodra@bigpond.net.au>
2152
2153 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2154
be8c092b
NC		 21552004-05-24 Peter Barada <peter@the-baradas.com>
2156
2157 * m68k.h: Add 'size' to m68k_opcode.
2158
6b6e92f4
NC		 21592004-05-05 Peter Barada <peter@the-baradas.com>
2160
2161 * m68k.h: Switch from ColdFire chip name to core variant.
2162
21632004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2164
2165 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2166 descriptions for new EMAC cases.
2167 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2168 handle Motorola MAC syntax.
2169 Allow disassembly of ColdFire V4e object files.
2170
fdd12ef3
AM		 21712004-03-16 Alan Modra <amodra@bigpond.net.au>
2172
2173 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2174
3922a64c
L		 21752004-03-12 Jakub Jelinek <jakub@redhat.com>
2176
2177 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2178
1f45d988
ML		 21792004-03-12 Michal Ludvig <mludvig@suse.cz>
2180
2181 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2182
0f10071e
ML		 21832004-03-12 Michal Ludvig <mludvig@suse.cz>
2184
2185 * i386.h (i386_optab): Added xstore/xcrypt insns.
2186
3255318a
NC		 21872004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2188
2189 * h8300.h (32bit ldc/stc): Add relaxing support.
2190
ca9a79a1 21912004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2192
ca9a79a1
NC		 2193 * h8300.h (BITOP): Pass MEMRELAX flag.
2194
875a0b14
NC		 21952004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2196
2197 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2198 except for the H8S.
252b5132 2199
c9e214e5 2200For older changes see ChangeLog-9103
252b5132 2201\f
b90efa5b 2202Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2203
2204Copying and distribution of this file, with or without modification,
2205are permitted in any medium without royalty provided the copyright
2206notice and this notice are preserved.
2207
252b5132 2208Local Variables:
c9e214e5
AM		 2209mode: change-log
2210left-margin: 8
2211fill-column: 74
252b5132
RH		 2212version-control: never
2213End:
GDB Binutils - Deliverables
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