projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Revert "Add support for AArch64 trace unit registers."
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
a203d9b7
YZ		 12013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
2
3 Revert
4
5 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
6
7 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
8 (aarch64_sys_reg_writeonly_p): Ditto.
9
75468c93
YZ		 102013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
11
12 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
13 (aarch64_sys_reg_writeonly_p): Ditto.
14
49eec193
YZ		 152013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
16
17 * aarch64.h (aarch64_sys_reg): New typedef.
18 (aarch64_sys_regs): Change to define with the new type.
19 (aarch64_sys_reg_deprecated_p): Declare.
20
68a64283
YZ		 212013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
22
23 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
24 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
25
387a82f1
CF		 262013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
27
28 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
29 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
30 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
31 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
32 For MIPS, update extension character sequences after +.
33 (ASE_MSA): New define.
34 (ASE_MSA64): New define.
35 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
36 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
37 For microMIPS, update extension character sequences after +.
38
9aff4b7a
NC		 392013-08-23 Yuri Chornoivan <yurchor@ukr.net>
40
41 PR binutils/15834
42 * i960.h: Fix typos.
43
e423441d
RS		 442013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
45
46 * mips.h: Remove references to "+I" and imm2_expr.
47
5e0dc5ba
RS		 482013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
49
50 * mips.h (M_DEXT, M_DINS): Delete.
51
0f35dbc4
RS		 522013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
53
54 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
55 (mips_optional_operand_p): New function.
56
14daeee3
RS		 572013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
58 Richard Sandiford <rdsandiford@googlemail.com>
59
60 * mips.h: Document new VU0 operand characters.
61 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
62 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
63 (OP_REG_R5900_ACC): New mips_reg_operand_types.
64 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
65 (mips_vu0_channel_mask): Declare.
66
3ccad066
RS		 672013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
68
69 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
70 (mips_int_operand_min, mips_int_operand_max): New functions.
71 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
72
fc76e730
RS		 732013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
74
75 * mips.h (mips_decode_reg_operand): New function.
76 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
77 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
78 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
79 New macros.
80 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
81 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
82 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
83 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
84 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
85 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
86 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
87 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
88 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
89 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
90 macros to cover the gaps.
91 (INSN2_MOD_SP): Replace with...
92 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
93 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
94 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
95 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
96 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
97 Delete.
98
26545944
RS		 992013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
100
101 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
102 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
103 (MIPS16_INSN_COND_BRANCH): Delete.
104
7e8b059b
L		 1052013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
106 Kirill Yukhin <kirill.yukhin@intel.com>
107 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
108
109 * i386.h (BND_PREFIX_OPCODE): New.
110
c3c07478
RS		 1112013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
112
113 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
114 OP_SAVE_RESTORE_LIST.
115 (decode_mips16_operand): Declare.
116
ab902481
RS		 1172013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
118
119 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
120 (mips_operand, mips_int_operand, mips_mapped_int_operand)
121 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
122 (mips_pcrel_operand): New structures.
123 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
124 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
125 (decode_mips_operand, decode_micromips_operand): Declare.
126
cc537e56
RS		 1272013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
128
129 * mips.h: Document MIPS16 "I" opcode.
130
f2ae14a1
RS		 1312013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
132
133 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
134 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
135 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
136 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
137 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
138 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
139 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
140 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
141 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
142 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
143 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
144 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
145 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
146 Rename to...
147 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
148 (M_USD_AB): ...these.
149
5c324c16
RS		 1502013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
151
152 * mips.h: Remove documentation of "[" and "]". Update documentation
153 of "k" and the MDMX formats.
154
23e69e47
RS		 1552013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
156
157 * mips.h: Update documentation of "+s" and "+S".
158
27c5c572
RS		 1592013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
160
161 * mips.h: Document "+i".
162
e76ff5ab
RS		 1632013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
164
165 * mips.h: Remove "mi" documentation. Update "mh" documentation.
166 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
167 Delete.
168 (INSN2_WRITE_GPR_MHI): Rename to...
169 (INSN2_WRITE_GPR_MH): ...this.
170
fa7616a4
RS		 1712013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
172
173 * mips.h: Remove documentation of "+D" and "+T".
174
18870af7
RS		 1752013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
176
177 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
178 Use "source" rather than "destination" for microMIPS "G".
179
833794fc
MR		 1802013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
181
182 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
183 values.
184
c3678916
RS		 1852013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
186
187 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
188
7f3c4072
CM		 1892013-06-17 Catherine Moore <clm@codesourcery.com>
190 Maciej W. Rozycki <macro@codesourcery.com>
191 Chao-Ying Fu <fu@mips.com>
192
193 * mips.h (OP_SH_EVAOFFSET): Define.
194 (OP_MASK_EVAOFFSET): Define.
195 (INSN_ASE_MASK): Delete.
196 (ASE_EVA): Define.
197 (M_CACHEE_AB, M_CACHEE_OB): New.
198 (M_LBE_OB, M_LBE_AB): New.
199 (M_LBUE_OB, M_LBUE_AB): New.
200 (M_LHE_OB, M_LHE_AB): New.
201 (M_LHUE_OB, M_LHUE_AB): New.
202 (M_LLE_AB, M_LLE_OB): New.
203 (M_LWE_OB, M_LWE_AB): New.
204 (M_LWLE_AB, M_LWLE_OB): New.
205 (M_LWRE_AB, M_LWRE_OB): New.
206 (M_PREFE_AB, M_PREFE_OB): New.
207 (M_SCE_AB, M_SCE_OB): New.
208 (M_SBE_OB, M_SBE_AB): New.
209 (M_SHE_OB, M_SHE_AB): New.
210 (M_SWE_OB, M_SWE_AB): New.
211 (M_SWLE_AB, M_SWLE_OB): New.
212 (M_SWRE_AB, M_SWRE_OB): New.
213 (MICROMIPSOP_SH_EVAOFFSET): Define.
214 (MICROMIPSOP_MASK_EVAOFFSET): Define.
215
0c8fe7cf
SL		 2162013-06-12 Sandra Loosemore <sandra@codesourcery.com>
217
218 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
219
c77c0862
RS		 2202013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
221
222 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
223
b015e599
AP		 2242013-05-09 Andrew Pinski <apinski@cavium.com>
225
226 * mips.h (OP_MASK_CODE10): Correct definition.
227 (OP_SH_CODE10): Likewise.
228 Add a comment that "+J" is used now for OP_*CODE10.
229 (INSN_ASE_MASK): Update.
230 (INSN_VIRT): New macro.
231 (INSN_VIRT64): New macro
232
13761a11
NC		 2332013-05-02 Nick Clifton <nickc@redhat.com>
234
235 * msp430.h: Add patterns for MSP430X instructions.
236
0afd1215
DM		 2372013-04-06 David S. Miller <davem@davemloft.net>
238
239 * sparc.h (F_PREFERRED): Define.
240 (F_PREF_ALIAS): Define.
241
41702d50
NC		 2422013-04-03 Nick Clifton <nickc@redhat.com>
243
244 * v850.h (V850_INVERSE_PCREL): Define.
245
e21e1a51
NC		 2462013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
247
248 PR binutils/15068
249 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
250
51dcdd4d
NC		 2512013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
252
253 PR binutils/15068
254 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
255 Add 16-bit opcodes.
256 * tic6xc-opcode-table.h: Add 16-bit insns.
257 * tic6x.h: Add support for 16-bit insns.
258
81f5558e
NC		 2592013-03-21 Michael Schewe <michael.schewe@gmx.net>
260
261 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
262 and mov.b/w/l Rs,@(d:32,ERd).
263
165546ad
NC		 2642013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
265
266 PR gas/15082
267 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
268 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
269 tic6x_operand_xregpair operand coding type.
270 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
271 opcode field, usu ORXREGD1324 for the src2 operand and remove the
272 TIC6X_FLAG_NO_CROSS.
273
795b8e6b
NC		 2742013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
275
276 PR gas/15095
277 * tic6x.h (enum tic6x_coding_method): Add
278 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
279 separately the msb and lsb of a register pair. This is needed to
280 encode the opcodes in the same way as TI assembler does.
281 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
282 and rsqrdp opcodes to use the new field coding types.
283
dd5181d5
KT		 2842013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
285
286 * arm.h (CRC_EXT_ARMV8): New constant.
287 (ARCH_CRC_ARMV8): New macro.
288
e60bb1dd
YZ		 2892013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
290
291 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
292
36591ba1
SL		 2932013-02-06 Sandra Loosemore <sandra@codesourcery.com>
294 Andrew Jenner <andrew@codesourcery.com>
295
296 Based on patches from Altera Corporation.
297
298 * nios2.h: New file.
299
e30181a5
YZ		 3002013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
301
302 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
303
0c9573f4
NC		 3042013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
305
306 PR gas/15069
307 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
308
981dc7f1
NC		 3092013-01-24 Nick Clifton <nickc@redhat.com>
310
311 * v850.h: Add e3v5 support.
312
f5555712
YZ		 3132013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
314
315 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
316
5817ffd1
PB		 3172013-01-10 Peter Bergner <bergner@vnet.ibm.com>
318
319 * ppc.h (PPC_OPCODE_POWER8): New define.
320 (PPC_OPCODE_HTM): Likewise.
321
a3c62988
NC		 3222013-01-10 Will Newton <will.newton@imgtec.com>
323
324 * metag.h: New file.
325
73335eae
NC		 3262013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
327
328 * cr16.h (make_instruction): Rename to cr16_make_instruction.
329 (match_opcode): Rename to cr16_match_opcode.
330
e407c74b
NC		 3312013-01-04 Juergen Urban <JuergenUrban@gmx.de>
332
333 * mips.h: Add support for r5900 instructions including lq and sq.
334
bab4becb
NC		 3352013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
336
337 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
338 (make_instruction,match_opcode): Added function prototypes.
339 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
340
776fc418
AM		 3412012-11-23 Alan Modra <amodra@gmail.com>
342
343 * ppc.h (ppc_parse_cpu): Update prototype.
344
f05682d4
DA		 3452012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
346
347 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
348 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
349
cfc72779
AK		 3502012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
351
352 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
353
b3e14eda
L		 3542012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
355
356 * ia64.h (ia64_opnd): Add new operand types.
357
2c63854f
DM		 3582012-08-21 David S. Miller <davem@davemloft.net>
359
360 * sparc.h (F3F4): New macro.
361
a06ea964 3622012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 363 Laurent Desnogues <laurent.desnogues@arm.com>
364 Jim MacArthur <jim.macarthur@arm.com>
365 Marcus Shawcroft <marcus.shawcroft@arm.com>
366 Nigel Stephens <nigel.stephens@arm.com>
367 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
368 Richard Earnshaw <rearnsha@arm.com>
369 Sofiane Naci <sofiane.naci@arm.com>
370 Tejas Belagod <tejas.belagod@arm.com>
371 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 372
373 * aarch64.h: New file.
374
35d0a169 3752012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 376 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 377
378 * mips.h (mips_opcode): Add the exclusions field.
379 (OPCODE_IS_MEMBER): Remove macro.
380 (cpu_is_member): New inline function.
381 (opcode_is_member): Likewise.
382
03f66e8a 3832012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 384 Catherine Moore <clm@codesourcery.com>
385 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 386
387 * mips.h: Document microMIPS DSP ASE usage.
388 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
389 microMIPS DSP ASE support.
390 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
391 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
392 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
393 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
394 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
395 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
396 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
397
9d7b4c23
MR		 3982012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
399
400 * mips.h: Fix a typo in description.
401
76e879f8
NC		 4022012-06-07 Georg-Johann Lay <avr@gjlay.de>
403
404 * avr.h: (AVR_ISA_XCH): New define.
405 (AVR_ISA_XMEGA): Use it.
406 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
407
6927f982
NC		 4082012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
409
410 * m68hc11.h: Add XGate definitions.
411 (struct m68hc11_opcode): Add xg_mask field.
412
b9c361e0
JL		 4132012-05-14 Catherine Moore <clm@codesourcery.com>
414 Maciej W. Rozycki <macro@codesourcery.com>
415 Rhonda Wittels <rhonda@codesourcery.com>
416
6927f982 417 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 418 (PPC_OP_SA): New macro.
419 (PPC_OP_SE_VLE): New macro.
420 (PPC_OP): Use a variable shift amount.
421 (powerpc_operand): Update comments.
422 (PPC_OPSHIFT_INV): New macro.
423 (PPC_OPERAND_CR): Replace with...
424 (PPC_OPERAND_CR_BIT): ...this and
425 (PPC_OPERAND_CR_REG): ...this.
426
427
f6c1a2d5
NC		 4282012-05-03 Sean Keys <skeys@ipdatasys.com>
429
430 * xgate.h: Header file for XGATE assembler.
431
ec668d69
DM		 4322012-04-27 David S. Miller <davem@davemloft.net>
433
6cda1326
DM		 434 * sparc.h: Document new arg code' )' for crypto RS3
435 immediates.
436
ec668d69
DM		 437 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
438 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
439 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
440 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
441 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
442 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
443 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
444 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
445 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
446 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
447 HWCAP_CBCOND, HWCAP_CRC32): New defines.
448
aea77599
AM		 4492012-03-10 Edmar Wienskoski <edmar@freescale.com>
450
451 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
452
1f42f8b3
AM		 4532012-02-27 Alan Modra <amodra@gmail.com>
454
455 * crx.h (cst4_map): Update declaration.
456
6f7be959
WL		 4572012-02-25 Walter Lee <walt@tilera.com>
458
459 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
460 TILEGX_OPC_LD_TLS.
461 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
462 TILEPRO_OPC_LW_TLS_SN.
463
42164a71
L		 4642012-02-08 H.J. Lu <hongjiu.lu@intel.com>
465
466 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
467 (XRELEASE_PREFIX_OPCODE): Likewise.
468
432233b3 4692011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 470 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 471
472 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
473 (INSN_OCTEON2): New macro.
474 (CPU_OCTEON2): New macro.
475 (OPCODE_IS_MEMBER): Add Octeon2.
476
dd6a37e7
AP		 4772011-11-29 Andrew Pinski <apinski@cavium.com>
478
479 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
480 (INSN_OCTEONP): New macro.
481 (CPU_OCTEONP): New macro.
482 (OPCODE_IS_MEMBER): Add Octeon+.
483 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
484
99c513f6
DD		 4852011-11-01 DJ Delorie <dj@redhat.com>
486
487 * rl78.h: New file.
488
26f85d7a
MR		 4892011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
490
491 * mips.h: Fix a typo in description.
492
9e8c70f9
DM		 4932011-09-21 David S. Miller <davem@davemloft.net>
494
495 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
496 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
497 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
498 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
499
dec0624d 5002011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 501 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 502
503 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
504 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
505 (INSN_ASE_MASK): Add the MCU bit.
506 (INSN_MCU): New macro.
507 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
508 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
509
2b0c8b40
MR		 5102011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
511
512 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
513 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
514 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
515 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
516 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
517 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
518 (INSN2_READ_GPR_MMN): Likewise.
519 (INSN2_READ_FPR_D): Change the bit used.
520 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
521 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
522 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
523 (INSN2_COND_BRANCH): Likewise.
524 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
525 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
526 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
527 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
528 (INSN2_MOD_GPR_MN): Likewise.
529
ea783ef3
DM		 5302011-08-05 David S. Miller <davem@davemloft.net>
531
532 * sparc.h: Document new format codes '4', '5', and '('.
533 (OPF_LOW4, RS3): New macros.
534
7c176fa8
MR		 5352011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
536
537 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
538 order of flags documented.
539
2309ddf2
MR		 5402011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
541
542 * mips.h: Clarify the description of microMIPS instruction
543 manipulation macros.
544 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
545
df58fc94 5462011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 547 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 548
549 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
550 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
551 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
552 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
553 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
554 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
555 (OP_MASK_RS3, OP_SH_RS3): Likewise.
556 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
557 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
558 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
559 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
560 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
561 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
562 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
563 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
564 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
565 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
566 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
567 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
568 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
569 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
570 (INSN_WRITE_GPR_S): New macro.
571 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
572 (INSN2_READ_FPR_D): Likewise.
573 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
574 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
575 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
576 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
577 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
578 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
579 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
580 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
581 (CPU_MICROMIPS): New macro.
582 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
583 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
584 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
585 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
586 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
587 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
588 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
589 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
590 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
591 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
592 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
593 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
594 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
595 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
596 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
597 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
598 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
599 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
600 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
601 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
602 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
603 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
604 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
605 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
606 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
607 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
608 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
609 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
610 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
611 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
612 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
613 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
614 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
615 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
616 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
617 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
618 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
619 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
620 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
621 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
622 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
623 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
624 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
625 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
626 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
627 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
628 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
629 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
630 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
631 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
632 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
633 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
634 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
635 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
636 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
637 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
638 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
639 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
640 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
641 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
642 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
643 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
644 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
645 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
646 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
647 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
648 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
649 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
650 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
651 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
652 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
653 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
654 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
655 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
656 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
657 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
658 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
659 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
660 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
661 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
662 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
663 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
664 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
665 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
666 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
667 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
668 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
669 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
670 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
671 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
672 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
673 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
674 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
675 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
676 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
677 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
678 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
679 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
680 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
681 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
682 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
683 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
684 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
685 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
686 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
687 (micromips_opcodes): New declaration.
688 (bfd_micromips_num_opcodes): Likewise.
689
bcd530a7
RS		 6902011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
691
692 * mips.h (INSN_TRAP): Rename to...
693 (INSN_NO_DELAY_SLOT): ... this.
694 (INSN_SYNC): Remove macro.
695
2dad5a91
EW		 6962011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
697
698 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
699 a duplicate of AVR_ISA_SPM.
700
5d73b1f1
NC		 7012011-07-01 Nick Clifton <nickc@redhat.com>
702
703 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
704
ef26d60e
MF		 7052011-06-18 Robin Getz <robin.getz@analog.com>
706
707 * bfin.h (is_macmod_signed): New func
708
8fb8dca7
MF		 7092011-06-18 Mike Frysinger <vapier@gentoo.org>
710
711 * bfin.h (is_macmod_pmove): Add missing space before func args.
712 (is_macmod_hmove): Likewise.
713
aa137e4d
NC		 7142011-06-13 Walter Lee <walt@tilera.com>
715
716 * tilegx.h: New file.
717 * tilepro.h: New file.
718
3b2f0793
PB		 7192011-05-31 Paul Brook <paul@codesourcery.com>
720
aa137e4d
NC		 721 * arm.h (ARM_ARCH_V7R_IDIV): Define.
722
7232011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
724
725 * s390.h: Replace S390_OPERAND_REG_EVEN with
726 S390_OPERAND_REG_PAIR.
727
7282011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
729
730 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 731
ac7f631b
NC		 7322011-04-18 Julian Brown <julian@codesourcery.com>
733
734 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
735
84701018
NC		 7362011-04-11 Dan McDonald <dan@wellkeeper.com>
737
738 PR gas/12296
739 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
740
8cc66334
EW		 7412011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
742
743 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
744 New instruction set flags.
745 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
746
3eebd5eb
MR		 7472011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
748
749 * mips.h (M_PREF_AB): New enum value.
750
26bb3ddd
MF		 7512011-02-12 Mike Frysinger <vapier@gentoo.org>
752
89c0d58c
MR		 753 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
754 M_IU): Define.
755 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 756
dd76fcb8
MF		 7572011-02-11 Mike Frysinger <vapier@gentoo.org>
758
759 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
760
98d23bef
BS		 7612011-02-04 Bernd Schmidt <bernds@codesourcery.com>
762
763 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
764 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
765
3c853d93
DA		 7662010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
767
768 PR gas/11395
769 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
770 "bb" entries.
771
79676006
DA		 7722010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
773
774 PR gas/11395
775 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
776
1bec78e9
RS		 7772010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
778
779 * mips.h: Update commentary after last commit.
780
98675402
RS		 7812010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
782
783 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
784 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
785 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
786
aa137e4d
NC		 7872010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
788
789 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
790
435b94a4
RS		 7912010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
792
793 * mips.h: Fix previous commit.
794
d051516a
NC		 7952010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
796
797 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
798 (INSN_LOONGSON_3A): Clear bit 31.
799
251665fc
MGD		 8002010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
801
802 PR gas/12198
803 * arm.h (ARM_AEXT_V6M_ONLY): New define.
804 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
805 (ARM_ARCH_V6M_ONLY): New define.
806
fd503541
NC		 8072010-11-11 Mingming Sun <mingm.sun@gmail.com>
808
809 * mips.h (INSN_LOONGSON_3A): Defined.
810 (CPU_LOONGSON_3A): Defined.
811 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
812
4469d2be
AM		 8132010-10-09 Matt Rice <ratmice@gmail.com>
814
815 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
816 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
817
90ec0d68
MGD		 8182010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
819
820 * arm.h (ARM_EXT_VIRT): New define.
821 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
822 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
823 Extensions.
824
eea54501 8252010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 826
eea54501
MGD		 827 * arm.h (ARM_AEXT_ADIV): New define.
828 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
829
b2a5fbdc
MGD		 8302010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
831
832 * arm.h (ARM_EXT_OS): New define.
833 (ARM_AEXT_V6SM): Likewise.
834 (ARM_ARCH_V6SM): Likewise.
835
60e5ef9f
MGD		 8362010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
837
838 * arm.h (ARM_EXT_MP): Add.
839 (ARM_ARCH_V7A_MP): Likewise.
840
73a63ccf
MF		 8412010-09-22 Mike Frysinger <vapier@gentoo.org>
842
843 * bfin.h: Declare pseudoChr structs/defines.
844
ee99860a
MF		 8452010-09-21 Mike Frysinger <vapier@gentoo.org>
846
847 * bfin.h: Strip trailing whitespace.
848
f9c7014e
DD		 8492010-07-29 DJ Delorie <dj@redhat.com>
850
851 * rx.h (RX_Operand_Type): Add TwoReg.
852 (RX_Opcode_ID): Remove ediv and ediv2.
853
93378652
DD		 8542010-07-27 DJ Delorie <dj@redhat.com>
855
856 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
857
1cd986c5
NC		 8582010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
859 Ina Pandit <ina.pandit@kpitcummins.com>
860
861 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
862 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
863 PROCESSOR_V850E2_ALL.
864 Remove PROCESSOR_V850EA support.
865 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
866 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
867 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
868 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
869 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
870 V850_OPERAND_PERCENT.
871 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
872 V850_NOT_R0.
873 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
874 and V850E_PUSH_POP
875
9a2c7088
MR		 8762010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
877
878 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
879 (MIPS16_INSN_BRANCH): Rename to...
880 (MIPS16_INSN_COND_BRANCH): ... this.
881
bdc70b4a
AM		 8822010-07-03 Alan Modra <amodra@gmail.com>
883
884 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
885 Renumber other PPC_OPCODE defines.
886
f2bae120
AM		 8872010-07-03 Alan Modra <amodra@gmail.com>
888
889 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
890
360cfc9c
AM		 8912010-06-29 Alan Modra <amodra@gmail.com>
892
893 * maxq.h: Delete file.
894
e01d869a
AM		 8952010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
896
897 * ppc.h (PPC_OPCODE_E500): Define.
898
f79e2745
CM		 8992010-05-26 Catherine Moore <clm@codesourcery.com>
900
901 * opcode/mips.h (INSN_MIPS16): Remove.
902
2462afa1
JM		 9032010-04-21 Joseph Myers <joseph@codesourcery.com>
904
905 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
906
e4e42b45
NC		 9072010-04-15 Nick Clifton <nickc@redhat.com>
908
909 * alpha.h: Update copyright notice to use GPLv3.
910 * arc.h: Likewise.
911 * arm.h: Likewise.
912 * avr.h: Likewise.
913 * bfin.h: Likewise.
914 * cgen.h: Likewise.
915 * convex.h: Likewise.
916 * cr16.h: Likewise.
917 * cris.h: Likewise.
918 * crx.h: Likewise.
919 * d10v.h: Likewise.
920 * d30v.h: Likewise.
921 * dlx.h: Likewise.
922 * h8300.h: Likewise.
923 * hppa.h: Likewise.
924 * i370.h: Likewise.
925 * i386.h: Likewise.
926 * i860.h: Likewise.
927 * i960.h: Likewise.
928 * ia64.h: Likewise.
929 * m68hc11.h: Likewise.
930 * m68k.h: Likewise.
931 * m88k.h: Likewise.
932 * maxq.h: Likewise.
933 * mips.h: Likewise.
934 * mmix.h: Likewise.
935 * mn10200.h: Likewise.
936 * mn10300.h: Likewise.
937 * msp430.h: Likewise.
938 * np1.h: Likewise.
939 * ns32k.h: Likewise.
940 * or32.h: Likewise.
941 * pdp11.h: Likewise.
942 * pj.h: Likewise.
943 * pn.h: Likewise.
944 * ppc.h: Likewise.
945 * pyr.h: Likewise.
946 * rx.h: Likewise.
947 * s390.h: Likewise.
948 * score-datadep.h: Likewise.
949 * score-inst.h: Likewise.
950 * sparc.h: Likewise.
951 * spu-insns.h: Likewise.
952 * spu.h: Likewise.
953 * tic30.h: Likewise.
954 * tic4x.h: Likewise.
955 * tic54x.h: Likewise.
956 * tic80.h: Likewise.
957 * v850.h: Likewise.
958 * vax.h: Likewise.
959
40b36596
JM		 9602010-03-25 Joseph Myers <joseph@codesourcery.com>
961
962 * tic6x-control-registers.h, tic6x-insn-formats.h,
963 tic6x-opcode-table.h, tic6x.h: New.
964
c67a084a
NC		 9652010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
966
967 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
968
466ef64f
AM		 9692010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
970
971 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
972
1319d143
L		 9732010-01-14 H.J. Lu <hongjiu.lu@intel.com>
974
975 * ia64.h (ia64_find_opcode): Remove argument name.
976 (ia64_find_next_opcode): Likewise.
977 (ia64_dis_opcode): Likewise.
978 (ia64_free_opcode): Likewise.
979 (ia64_find_dependency): Likewise.
980
1fbb9298
DE		 9812009-11-22 Doug Evans <dje@sebabeach.org>
982
983 * cgen.h: Include bfd_stdint.h.
984 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
985
ada65aa3
PB		 9862009-11-18 Paul Brook <paul@codesourcery.com>
987
988 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
989
9e3c6df6
PB		 9902009-11-17 Paul Brook <paul@codesourcery.com>
991 Daniel Jacobowitz <dan@codesourcery.com>
992
993 * arm.h (ARM_EXT_V6_DSP): Define.
994 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
995 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
996
0d734b5d
DD		 9972009-11-04 DJ Delorie <dj@redhat.com>
998
999 * rx.h (rx_decode_opcode) (mvtipl): Add.
1000 (mvtcp, mvfcp, opecp): Remove.
1001
62f3b8c8
PB		 10022009-11-02 Paul Brook <paul@codesourcery.com>
1003
1004 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1005 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1006 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1007 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1008 FPU_ARCH_NEON_VFP_V4): Define.
1009
ac1e9eca
DE		 10102009-10-23 Doug Evans <dje@sebabeach.org>
1011
1012 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1013 * cgen.h: Update. Improve multi-inclusion macro name.
1014
9fe54b1c
PB		 10152009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1016
1017 * ppc.h (PPC_OPCODE_476): Define.
1018
634b50f2
PB		 10192009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1020
1021 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1022
c7927a3c
NC		 10232009-09-29 DJ Delorie <dj@redhat.com>
1024
1025 * rx.h: New file.
1026
b961e85b
AM		 10272009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1028
1029 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1030
e0d602ec
BE		 10312009-09-21 Ben Elliston <bje@au.ibm.com>
1032
1033 * ppc.h (PPC_OPCODE_PPCA2): New.
1034
96d56e9f
NC		 10352009-09-05 Martin Thuresson <martin@mtme.org>
1036
1037 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1038
d3ce72d0
NC		 10392009-08-29 Martin Thuresson <martin@mtme.org>
1040
1041 * tic30.h (template): Rename type template to
1042 insn_template. Updated code to use new name.
1043 * tic54x.h (template): Rename type template to
1044 insn_template.
1045
824b28db
NH		 10462009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1047
1048 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1049
f865a31d
AG		 10502009-06-11 Anthony Green <green@moxielogic.com>
1051
1052 * moxie.h (MOXIE_F3_PCREL): Define.
1053 (moxie_form3_opc_info): Grow.
1054
0e7c7f11
AG		 10552009-06-06 Anthony Green <green@moxielogic.com>
1056
1057 * moxie.h (MOXIE_F1_M): Define.
1058
20135e4c
NC		 10592009-04-15 Anthony Green <green@moxielogic.com>
1060
1061 * moxie.h: Created.
1062
bcb012d3
DD		 10632009-04-06 DJ Delorie <dj@redhat.com>
1064
1065 * h8300.h: Add relaxation attributes to MOVA opcodes.
1066
69fe9ce5
AM		 10672009-03-10 Alan Modra <amodra@bigpond.net.au>
1068
1069 * ppc.h (ppc_parse_cpu): Declare.
1070
c3b7224a
NC		 10712009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1072
1073 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1074 and _IMM11 for mbitclr and mbitset.
1075 * score-datadep.h: Update dependency information.
1076
066be9f7
PB		 10772009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1078
1079 * ppc.h (PPC_OPCODE_POWER7): New.
1080
fedc618e
DE		 10812009-02-06 Doug Evans <dje@google.com>
1082
1083 * i386.h: Add comment regarding sse* insns and prefixes.
1084
52b6b6b9
JM		 10852009-02-03 Sandip Matte <sandip@rmicorp.com>
1086
1087 * mips.h (INSN_XLR): Define.
1088 (INSN_CHIP_MASK): Update.
1089 (CPU_XLR): Define.
1090 (OPCODE_IS_MEMBER): Update.
1091 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1092
35669430
DE		 10932009-01-28 Doug Evans <dje@google.com>
1094
1095 * opcode/i386.h: Add multiple inclusion protection.
1096 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1097 (EDI_REG_NUM): New macros.
1098 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1099 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1100 (REX_PREFIX_P): New macro.
35669430 1101
1cb0a767
PB		 11022009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1103
1104 * ppc.h (struct powerpc_opcode): New field "deprecated".
1105 (PPC_OPCODE_NOPOWER4): Delete.
1106
3aa3176b
TS		 11072008-11-28 Joshua Kinard <kumba@gentoo.org>
1108
1109 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1110 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1111
8e79c3df
CM		 11122008-11-18 Catherine Moore <clm@codesourcery.com>
1113
1114 * arm.h (FPU_NEON_FP16): New.
1115 (FPU_ARCH_NEON_FP16): New.
1116
de9a3e51
CF		 11172008-11-06 Chao-ying Fu <fu@mips.com>
1118
1119 * mips.h: Doucument '1' for 5-bit sync type.
1120
1ca35711
L		 11212008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1122
1123 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1124 IA64_RS_CR.
1125
9b4e5766
PB		 11262008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1127
1128 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1129
081ba1b3
AM		 11302008-07-30 Michael J. Eager <eager@eagercon.com>
1131
1132 * ppc.h (PPC_OPCODE_405): Define.
1133 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1134
fa452fa6
PB		 11352008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1136
1137 * ppc.h (ppc_cpu_t): New typedef.
1138 (struct powerpc_opcode <flags>): Use it.
1139 (struct powerpc_operand <insert, extract>): Likewise.
1140 (struct powerpc_macro <flags>): Likewise.
1141
bb35fb24
NC		 11422008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1143
1144 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1145 Update comment before MIPS16 field descriptors to mention MIPS16.
1146 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1147 BBIT.
1148 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1149 New bit masks and shift counts for cins and exts.
1150
dd3cbb7e
NC		 1151 * mips.h: Document new field descriptors +Q.
1152 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1153
d0799671
AN		 11542008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1155
9aff4b7a 1156 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1157 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1158
19a6653c
AM		 11592008-04-14 Edmar Wienskoski <edmar@freescale.com>
1160
1161 * ppc.h: (PPC_OPCODE_E500MC): New.
1162
c0f3af97
L		 11632008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1164
1165 * i386.h (MAX_OPERANDS): Set to 5.
1166 (MAX_MNEM_SIZE): Changed to 20.
1167
e210c36b
NC		 11682008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1169
1170 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1171
b1cc4aeb
PB		 11722008-03-09 Paul Brook <paul@codesourcery.com>
1173
1174 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1175
7e806470
PB		 11762008-03-04 Paul Brook <paul@codesourcery.com>
1177
1178 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1179 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1180 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1181
7b2185f9 11822008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1183 Nick Clifton <nickc@redhat.com>
1184
1185 PR 3134
1186 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1187 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1188 set.
af7329f0 1189
796d5313
NC		 11902008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1191
1192 * cr16.h (cr16_num_optab): Declared.
1193
d669d37f
NC		 11942008-02-14 Hakan Ardo <hakan@debian.org>
1195
1196 PR gas/2626
1197 * avr.h (AVR_ISA_2xxe): Define.
1198
e6429699
AN		 11992008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1200
1201 * mips.h: Update copyright.
1202 (INSN_CHIP_MASK): New macro.
1203 (INSN_OCTEON): New macro.
1204 (CPU_OCTEON): New macro.
1205 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1206
e210c36b
NC		 12072008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1208
1209 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1210
12112008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1212
1213 * avr.h (AVR_ISA_USB162): Add new opcode set.
1214 (AVR_ISA_AVR3): Likewise.
1215
350cc38d
MS		 12162007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1217
1218 * mips.h (INSN_LOONGSON_2E): New.
1219 (INSN_LOONGSON_2F): New.
1220 (CPU_LOONGSON_2E): New.
1221 (CPU_LOONGSON_2F): New.
1222 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1223
56950294
MS		 12242007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1225
1226 * mips.h (INSN_ISA*): Redefine certain values as an
1227 enumeration. Update comments.
1228 (mips_isa_table): New.
1229 (ISA_MIPS*): Redefine to match enumeration.
1230 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1231 values.
1232
c3d65c1c
BE		 12332007-08-08 Ben Elliston <bje@au.ibm.com>
1234
1235 * ppc.h (PPC_OPCODE_PPCPS): New.
1236
0fdaa005
L		 12372007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1238
1239 * m68k.h: Document j K & E.
1240
12412007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1242
1243 * cr16.h: New file for CR16 target.
1244
3896c469
AM		 12452007-05-02 Alan Modra <amodra@bigpond.net.au>
1246
1247 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1248
9a2e615a
NS		 12492007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1250
1251 * m68k.h (mcfisa_c): New.
1252 (mcfusp, mcf_mask): Adjust.
1253
b84bf58a
AM		 12542007-04-20 Alan Modra <amodra@bigpond.net.au>
1255
1256 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1257 (num_powerpc_operands): Declare.
1258 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1259 (PPC_OPERAND_PLUS1): Define.
1260
831480e9 12612007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1262
1263 * i386.h (REX_MODE64): Renamed to ...
1264 (REX_W): This.
1265 (REX_EXTX): Renamed to ...
1266 (REX_R): This.
1267 (REX_EXTY): Renamed to ...
1268 (REX_X): This.
1269 (REX_EXTZ): Renamed to ...
1270 (REX_B): This.
1271
0b1cf022
L		 12722007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1273
1274 * i386.h: Add entries from config/tc-i386.h and move tables
1275 to opcodes/i386-opc.h.
1276
d796c0ad
L		 12772007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1278
1279 * i386.h (FloatDR): Removed.
1280 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1281
30ac7323
AM		 12822007-03-01 Alan Modra <amodra@bigpond.net.au>
1283
1284 * spu-insns.h: Add soma double-float insns.
1285
8b082fb1 12862007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1287 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1288
1289 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1290 (INSN_DSPR2): Add flag for DSP R2 instructions.
1291 (M_BALIGN): New macro.
1292
4eed87de
AM		 12932007-02-14 Alan Modra <amodra@bigpond.net.au>
1294
1295 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1296 and Seg3ShortFrom with Shortform.
1297
fda592e8
L		 12982007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1299
1300 PR gas/4027
1301 * i386.h (i386_optab): Put the real "test" before the pseudo
1302 one.
1303
3bdcfdf4
KH		 13042007-01-08 Kazu Hirata <kazu@codesourcery.com>
1305
1306 * m68k.h (m68010up): OR fido_a.
1307
9840d27e
KH		 13082006-12-25 Kazu Hirata <kazu@codesourcery.com>
1309
1310 * m68k.h (fido_a): New.
1311
c629cdac
KH		 13122006-12-24 Kazu Hirata <kazu@codesourcery.com>
1313
1314 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1315 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1316 values.
1317
b7d9ef37
L		 13182006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1319
1320 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1321
b138abaa
NC		 13222006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1323
1324 * score-inst.h (enum score_insn_type): Add Insn_internal.
1325
e9f53129
AM		 13262006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1327 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1328 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1329 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1330 Alan Modra <amodra@bigpond.net.au>
1331
1332 * spu-insns.h: New file.
1333 * spu.h: New file.
1334
ede602d7
AM		 13352006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1336
1337 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1338
7918206c
MM		 13392006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1340
e4e42b45 1341 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1342 in amdfam10 architecture.
1343
ef05d495
L		 13442006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1345
1346 * i386.h: Replace CpuMNI with CpuSSSE3.
1347
2d447fca 13482006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1349 Joseph Myers <joseph@codesourcery.com>
1350 Ian Lance Taylor <ian@wasabisystems.com>
1351 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1352
1353 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1354
1c0d3aa6
NC		 13552006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1356
1357 * score-datadep.h: New file.
1358 * score-inst.h: New file.
1359
c2f0420e
L		 13602006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1361
1362 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1363 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1364 movdq2q and movq2dq.
1365
050dfa73
MM		 13662006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1367 Michael Meissner <michael.meissner@amd.com>
1368
1369 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1370
15965411
L		 13712006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1372
1373 * i386.h (i386_optab): Add "nop" with memory reference.
1374
46e883c5
L		 13752006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1376
1377 * i386.h (i386_optab): Update comment for 64bit NOP.
1378
9622b051
AM		 13792006-06-06 Ben Elliston <bje@au.ibm.com>
1380 Anton Blanchard <anton@samba.org>
1381
1382 * ppc.h (PPC_OPCODE_POWER6): Define.
1383 Adjust whitespace.
1384
a9e24354
TS		 13852006-06-05 Thiemo Seufer <ths@mips.com>
1386
e4e42b45 1387 * mips.h: Improve description of MT flags.
a9e24354 1388
a596001e
RS		 13892006-05-25 Richard Sandiford <richard@codesourcery.com>
1390
1391 * m68k.h (mcf_mask): Define.
1392
d43b4baf 13932006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1394 David Ung <davidu@mips.com>
d43b4baf
TS		 1395
1396 * mips.h (enum): Add macro M_CACHE_AB.
1397
39a7806d 13982006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1399 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1400 David Ung <davidu@mips.com>
1401
1402 * mips.h: Add INSN_SMARTMIPS define.
1403
9bcd4f99 14042006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1405 David Ung <davidu@mips.com>
9bcd4f99
TS		 1406
1407 * mips.h: Defines udi bits and masks. Add description of
1408 characters which may appear in the args field of udi
1409 instructions.
1410
ef0ee844
TS		 14112006-04-26 Thiemo Seufer <ths@networkno.de>
1412
1413 * mips.h: Improve comments describing the bitfield instruction
1414 fields.
1415
f7675147
L		 14162006-04-26 Julian Brown <julian@codesourcery.com>
1417
1418 * arm.h (FPU_VFP_EXT_V3): Define constant.
1419 (FPU_NEON_EXT_V1): Likewise.
1420 (FPU_VFP_HARD): Update.
1421 (FPU_VFP_V3): Define macro.
1422 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1423
ef0ee844 14242006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1425
1426 * avr.h (AVR_ISA_PWMx): New.
1427
2da12c60
NS		 14282006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1429
1430 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1431 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1432 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1433 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1434 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1435
0715c387
PB		 14362006-03-10 Paul Brook <paul@codesourcery.com>
1437
1438 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1439
34bdd094
DA		 14402006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1441
1442 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1443 first. Correct mask of bb "B" opcode.
1444
331d2d0d
L		 14452006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1446
1447 * i386.h (i386_optab): Support Intel Merom New Instructions.
1448
62b3e311
PB		 14492006-02-24 Paul Brook <paul@codesourcery.com>
1450
1451 * arm.h: Add V7 feature bits.
1452
59cf82fe
L		 14532006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1454
1455 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1456
e74cfd16
PB		 14572006-01-31 Paul Brook <paul@codesourcery.com>
1458 Richard Earnshaw <rearnsha@arm.com>
1459
1460 * arm.h: Use ARM_CPU_FEATURE.
1461 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1462 (arm_feature_set): Change to a structure.
1463 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1464 ARM_FEATURE): New macros.
1465
5b3f8a92
HPN		 14662005-12-07 Hans-Peter Nilsson <hp@axis.com>
1467
1468 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1469 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1470 (ADD_PC_INCR_OPCODE): Don't define.
1471
cb712a9e
L		 14722005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1473
1474 PR gas/1874
1475 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1476
0499d65b
TS		 14772005-11-14 David Ung <davidu@mips.com>
1478
1479 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1480 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1481 save/restore encoding of the args field.
1482
ea5ca089
DB		 14832005-10-28 Dave Brolley <brolley@redhat.com>
1484
1485 Contribute the following changes:
1486 2005-02-16 Dave Brolley <brolley@redhat.com>
1487
1488 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1489 cgen_isa_mask_* to cgen_bitset_*.
1490 * cgen.h: Likewise.
1491
16175d96
DB		 1492 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1493
1494 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1495 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1496 (CGEN_CPU_TABLE): Make isas a ponter.
1497
1498 2003-09-29 Dave Brolley <brolley@redhat.com>
1499
1500 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1501 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1502 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1503
1504 2002-12-13 Dave Brolley <brolley@redhat.com>
1505
1506 * cgen.h (symcat.h): #include it.
1507 (cgen-bitset.h): #include it.
1508 (CGEN_ATTR_VALUE_TYPE): Now a union.
1509 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1510 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1511 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1512 * cgen-bitset.h: New file.
1513
3c9b82ba
NC		 15142005-09-30 Catherine Moore <clm@cm00re.com>
1515
1516 * bfin.h: New file.
1517
6a2375c6
JB		 15182005-10-24 Jan Beulich <jbeulich@novell.com>
1519
1520 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1521 indirect operands.
1522
c06a12f8
DA		 15232005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1524
1525 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1526 Add FLAG_STRICT to pa10 ftest opcode.
1527
4d443107
DA		 15282005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1529
1530 * hppa.h (pa_opcodes): Remove lha entries.
1531
f0a3b40f
DA		 15322005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1533
1534 * hppa.h (FLAG_STRICT): Revise comment.
1535 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1536 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1537 entries for "fdc".
1538
e210c36b
NC		 15392005-09-30 Catherine Moore <clm@cm00re.com>
1540
1541 * bfin.h: New file.
1542
1b7e1362
DA		 15432005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1544
1545 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1546
089b39de
CF		 15472005-09-06 Chao-ying Fu <fu@mips.com>
1548
1549 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1550 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1551 define.
1552 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1553 (INSN_ASE_MASK): Update to include INSN_MT.
1554 (INSN_MT): New define for MT ASE.
1555
93c34b9b
CF		 15562005-08-25 Chao-ying Fu <fu@mips.com>
1557
1558 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1559 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1560 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1561 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1562 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1563 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1564 instructions.
1565 (INSN_DSP): New define for DSP ASE.
1566
848cf006
AM		 15672005-08-18 Alan Modra <amodra@bigpond.net.au>
1568
1569 * a29k.h: Delete.
1570
36ae0db3
DJ		 15712005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1572
1573 * ppc.h (PPC_OPCODE_E300): Define.
1574
8c929562
MS		 15752005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1576
1577 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1578
f7b8cccc
DA		 15792005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1580
1581 PR gas/336
1582 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1583 and pitlb.
1584
8b5328ac
JB		 15852005-07-27 Jan Beulich <jbeulich@novell.com>
1586
1587 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1588 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1589 Add movq-s as 64-bit variants of movd-s.
1590
f417d200
DA		 15912005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1592
18b3bdfc
DA		 1593 * hppa.h: Fix punctuation in comment.
1594
f417d200
DA		 1595 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1596 implicit space-register addressing. Set space-register bits on opcodes
1597 using implicit space-register addressing. Add various missing pa20
1598 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1599 space-register addressing. Use "fE" instead of "fe" in various
1600 fstw opcodes.
1601
9a145ce6
JB		 16022005-07-18 Jan Beulich <jbeulich@novell.com>
1603
1604 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1605
90700ea2
L		 16062007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1607
1608 * i386.h (i386_optab): Support Intel VMX Instructions.
1609
48f130a8
DA		 16102005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1611
1612 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1613
30123838
JB		 16142005-07-05 Jan Beulich <jbeulich@novell.com>
1615
1616 * i386.h (i386_optab): Add new insns.
1617
47b0e7ad
NC		 16182005-07-01 Nick Clifton <nickc@redhat.com>
1619
1620 * sparc.h: Add typedefs to structure declarations.
1621
b300c311
L		 16222005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1623
1624 PR 1013
1625 * i386.h (i386_optab): Update comments for 64bit addressing on
1626 mov. Allow 64bit addressing for mov and movq.
1627
2db495be
DA		 16282005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1629
1630 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1631 respectively, in various floating-point load and store patterns.
1632
caa05036
DA		 16332005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1634
1635 * hppa.h (FLAG_STRICT): Correct comment.
1636 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1637 PA 2.0 mneumonics when equivalent. Entries with cache control
1638 completers now require PA 1.1. Adjust whitespace.
1639
f4411256
AM		 16402005-05-19 Anton Blanchard <anton@samba.org>
1641
1642 * ppc.h (PPC_OPCODE_POWER5): Define.
1643
e172dbf8
NC		 16442005-05-10 Nick Clifton <nickc@redhat.com>
1645
1646 * Update the address and phone number of the FSF organization in
1647 the GPL notices in the following files:
1648 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1649 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1650 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1651 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1652 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1653 tic54x.h, tic80.h, v850.h, vax.h
1654
e44823cf
JB		 16552005-05-09 Jan Beulich <jbeulich@novell.com>
1656
1657 * i386.h (i386_optab): Add ht and hnt.
1658
791fe849
MK		 16592005-04-18 Mark Kettenis <kettenis@gnu.org>
1660
1661 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1662 Add xcrypt-ctr. Provide aliases without hyphens.
1663
faa7ef87
L		 16642005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1665
a63027e5
L		 1666 Moved from ../ChangeLog
1667
faa7ef87
L		 1668 2005-04-12 Paul Brook <paul@codesourcery.com>
1669 * m88k.h: Rename psr macros to avoid conflicts.
1670
1671 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1672 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1673 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1674 and ARM_ARCH_V6ZKT2.
1675
1676 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1677 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1678 Remove redundant instruction types.
1679 (struct argument): X_op - new field.
1680 (struct cst4_entry): Remove.
1681 (no_op_insn): Declare.
1682
1683 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1684 * crx.h (enum argtype): Rename types, remove unused types.
1685
1686 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1687 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1688 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1689 (enum operand_type): Rearrange operands, edit comments.
1690 replace us<N> with ui<N> for unsigned immediate.
1691 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1692 displacements (respectively).
1693 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1694 (instruction type): Add NO_TYPE_INS.
1695 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1696 (operand_entry): New field - 'flags'.
1697 (operand flags): New.
1698
1699 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1700 * crx.h (operand_type): Remove redundant types i3, i4,
1701 i5, i8, i12.
1702 Add new unsigned immediate types us3, us4, us5, us16.
1703
bc4bd9ab
MK		 17042005-04-12 Mark Kettenis <kettenis@gnu.org>
1705
1706 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1707 adjust them accordingly.
1708
373ff435
JB		 17092005-04-01 Jan Beulich <jbeulich@novell.com>
1710
1711 * i386.h (i386_optab): Add rdtscp.
1712
4cc91dba
L		 17132005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1714
1715 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1716 between memory and segment register. Allow movq for moving between
1717 general-purpose register and segment register.
4cc91dba 1718
9ae09ff9
JB		 17192005-02-09 Jan Beulich <jbeulich@novell.com>
1720
1721 PR gas/707
1722 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1723 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1724 fnstsw.
1725
638e7a64
NS		 17262006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1727
1728 * m68k.h (m68008, m68ec030, m68882): Remove.
1729 (m68k_mask): New.
1730 (cpu_m68k, cpu_cf): New.
1731 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1732 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1733
90219bd0
AO		 17342005-01-25 Alexandre Oliva <aoliva@redhat.com>
1735
1736 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1737 * cgen.h (enum cgen_parse_operand_type): Add
1738 CGEN_PARSE_OPERAND_SYMBOLIC.
1739
239cb185
FF		 17402005-01-21 Fred Fish <fnf@specifixinc.com>
1741
1742 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1743 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1744 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1745
dc9a9f39
FF		 17462005-01-19 Fred Fish <fnf@specifixinc.com>
1747
1748 * mips.h (struct mips_opcode): Add new pinfo2 member.
1749 (INSN_ALIAS): New define for opcode table entries that are
1750 specific instances of another entry, such as 'move' for an 'or'
1751 with a zero operand.
1752 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1753 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1754
98e7aba8
ILT		 17552004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1756
1757 * mips.h (CPU_RM9000): Define.
1758 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1759
37edbb65
JB		 17602004-11-25 Jan Beulich <jbeulich@novell.com>
1761
1762 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1763 to/from test registers are illegal in 64-bit mode. Add missing
1764 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1765 (previously one had to explicitly encode a rex64 prefix). Re-enable
1766 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1767 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1768
17692004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 1770
1771 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1772 available only with SSE2. Change the MMX additions introduced by SSE
1773 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1774 instructions by their now designated identifier (since combining i686
1775 and 3DNow! does not really imply 3DNow!A).
1776
f5c7edf4
AM		 17772004-11-19 Alan Modra <amodra@bigpond.net.au>
1778
1779 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1780 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1781
7499d566
NC		 17822004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1783 Vineet Sharma <vineets@noida.hcltech.com>
1784
1785 * maxq.h: New file: Disassembly information for the maxq port.
1786
bcb9eebe
L		 17872004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1788
1789 * i386.h (i386_optab): Put back "movzb".
1790
94bb3d38
HPN		 17912004-11-04 Hans-Peter Nilsson <hp@axis.com>
1792
1793 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1794 comments. Remove member cris_ver_sim. Add members
1795 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1796 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1797 (struct cris_support_reg, struct cris_cond15): New types.
1798 (cris_conds15): Declare.
1799 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1800 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1801 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1802 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1803 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1804 SIZE_FIELD_UNSIGNED.
1805
37edbb65 18062004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 1807
1808 * i386.h (sldx_Suf): Remove.
1809 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1810 (q_FP): Define, implying no REX64.
1811 (x_FP, sl_FP): Imply FloatMF.
1812 (i386_optab): Split reg and mem forms of moving from segment registers
1813 so that the memory forms can ignore the 16-/32-bit operand size
1814 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1815 all non-floating-point instructions. Unite 32- and 64-bit forms of
1816 movsx, movzx, and movd. Adjust floating point operations for the above
1817 changes to the *FP macros. Add DefaultSize to floating point control
1818 insns operating on larger memory ranges. Remove left over comments
1819 hinting at certain insns being Intel-syntax ones where the ones
1820 actually meant are already gone.
1821
48c9f030
NC		 18222004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1823
1824 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1825 instruction type.
1826
0dd132b6
NC		 18272004-09-30 Paul Brook <paul@codesourcery.com>
1828
1829 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1830 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1831
23794b24
MM		 18322004-09-11 Theodore A. Roth <troth@openavr.org>
1833
1834 * avr.h: Add support for
1835 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1836
2a309db0
AM		 18372004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1838
1839 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1840
b18c562e
NC		 18412004-08-24 Dmitry Diky <diwil@spec.ru>
1842
1843 * msp430.h (msp430_opc): Add new instructions.
1844 (msp430_rcodes): Declare new instructions.
1845 (msp430_hcodes): Likewise..
1846
45d313cd
NC		 18472004-08-13 Nick Clifton <nickc@redhat.com>
1848
1849 PR/301
1850 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1851 processors.
1852
30d1c836
ML		 18532004-08-30 Michal Ludvig <mludvig@suse.cz>
1854
1855 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1856
9a45f1c2
L		 18572004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1858
1859 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1860
543613e9
NC		 18612004-07-21 Jan Beulich <jbeulich@novell.com>
1862
1863 * i386.h: Adjust instruction descriptions to better match the
1864 specification.
1865
b781e558
RE		 18662004-07-16 Richard Earnshaw <rearnsha@arm.com>
1867
1868 * arm.h: Remove all old content. Replace with architecture defines
1869 from gas/config/tc-arm.c.
1870
8577e690
AS		 18712004-07-09 Andreas Schwab <schwab@suse.de>
1872
1873 * m68k.h: Fix comment.
1874
1fe1f39c
NC		 18752004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1876
1877 * crx.h: New file.
1878
1d9f512f
AM		 18792004-06-24 Alan Modra <amodra@bigpond.net.au>
1880
1881 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1882
be8c092b
NC		 18832004-05-24 Peter Barada <peter@the-baradas.com>
1884
1885 * m68k.h: Add 'size' to m68k_opcode.
1886
6b6e92f4
NC		 18872004-05-05 Peter Barada <peter@the-baradas.com>
1888
1889 * m68k.h: Switch from ColdFire chip name to core variant.
1890
18912004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 1892
1893 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1894 descriptions for new EMAC cases.
1895 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1896 handle Motorola MAC syntax.
1897 Allow disassembly of ColdFire V4e object files.
1898
fdd12ef3
AM		 18992004-03-16 Alan Modra <amodra@bigpond.net.au>
1900
1901 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1902
3922a64c
L		 19032004-03-12 Jakub Jelinek <jakub@redhat.com>
1904
1905 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1906
1f45d988
ML		 19072004-03-12 Michal Ludvig <mludvig@suse.cz>
1908
1909 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1910
0f10071e
ML		 19112004-03-12 Michal Ludvig <mludvig@suse.cz>
1912
1913 * i386.h (i386_optab): Added xstore/xcrypt insns.
1914
3255318a
NC		 19152004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1916
1917 * h8300.h (32bit ldc/stc): Add relaxing support.
1918
ca9a79a1 19192004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 1920
ca9a79a1
NC		 1921 * h8300.h (BITOP): Pass MEMRELAX flag.
1922
875a0b14
NC		 19232004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1924
1925 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1926 except for the H8S.
252b5132 1927
c9e214e5 1928For older changes see ChangeLog-9103
252b5132 1929\f
752937aa
NC		 1930Copyright (C) 2004-2012 Free Software Foundation, Inc.
1931
1932Copying and distribution of this file, with or without modification,
1933are permitted in any medium without royalty provided the copyright
1934notice and this notice are preserved.
1935
252b5132 1936Local Variables:
c9e214e5
AM		 1937mode: change-log
1938left-margin: 8
1939fill-column: 74
252b5132
RH		 1940version-control: never
1941End:
GDB Binutils - Deliverables
This page took 0.657537 seconds and 4 git commands to generate.