projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| b300c311 L |
1 | 2005-06-20 H.J. Lu <hongjiu.lu@intel.com> |
| 2 | ||
| 3 | PR 1013 | |
| 4 | * i386.h (i386_optab): Update comments for 64bit addressing on | |
| 5 | mov. Allow 64bit addressing for mov and movq. | |
| 6 | ||
| 2db495be DA |
7 | 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 8 | ||
| 9 | * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, | |
| 10 | respectively, in various floating-point load and store patterns. | |
| 11 | ||
| caa05036 DA |
12 | 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 13 | ||
| 14 | * hppa.h (FLAG_STRICT): Correct comment. | |
| 15 | (pa_opcodes): Update load and store entries to allow both PA 1.X and | |
| 16 | PA 2.0 mneumonics when equivalent. Entries with cache control | |
| 17 | completers now require PA 1.1. Adjust whitespace. | |
| 18 | ||
| f4411256 AM |
19 | 2005-05-19 Anton Blanchard <anton@samba.org> |
| 20 | ||
| 21 | * ppc.h (PPC_OPCODE_POWER5): Define. | |
| 22 | ||
| e172dbf8 NC |
23 | 2005-05-10 Nick Clifton <nickc@redhat.com> |
| 24 | ||
| 25 | * Update the address and phone number of the FSF organization in | |
| 26 | the GPL notices in the following files: | |
| 27 | a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, | |
| 28 | crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, | |
| 29 | i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, | |
| 30 | mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, | |
| 31 | pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, | |
| 32 | tic54x.h, tic80.h, v850.h, vax.h | |
| 33 | ||
| e44823cf JB |
34 | 2005-05-09 Jan Beulich <jbeulich@novell.com> |
| 35 | ||
| 36 | * i386.h (i386_optab): Add ht and hnt. | |
| 37 | ||
| 791fe849 MK |
38 | 2005-04-18 Mark Kettenis <kettenis@gnu.org> |
| 39 | ||
| 40 | * i386.h: Insert hyphens into selected VIA PadLock extensions. | |
| 41 | Add xcrypt-ctr. Provide aliases without hyphens. | |
| 42 | ||
| faa7ef87 L |
43 | 2005-04-13 H.J. Lu <hongjiu.lu@intel.com> |
| 44 | ||
| a63027e5 L |
45 | Moved from ../ChangeLog |
| 46 | ||
| faa7ef87 L |
47 | 2005-04-12 Paul Brook <paul@codesourcery.com> |
| 48 | * m88k.h: Rename psr macros to avoid conflicts. | |
| 49 | ||
| 50 | 2005-03-12 Zack Weinberg <zack@codesourcery.com> | |
| 51 | * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. | |
| 52 | Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, | |
| 53 | and ARM_ARCH_V6ZKT2. | |
| 54 | ||
| 55 | 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> | |
| 56 | * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. | |
| 57 | Remove redundant instruction types. | |
| 58 | (struct argument): X_op - new field. | |
| 59 | (struct cst4_entry): Remove. | |
| 60 | (no_op_insn): Declare. | |
| 61 | ||
| 62 | 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> | |
| 63 | * crx.h (enum argtype): Rename types, remove unused types. | |
| 64 | ||
| 65 | 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> | |
| 66 | * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. | |
| 67 | (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. | |
| 68 | (enum operand_type): Rearrange operands, edit comments. | |
| 69 | replace us<N> with ui<N> for unsigned immediate. | |
| 70 | replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped | |
| 71 | displacements (respectively). | |
| 72 | replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. | |
| 73 | (instruction type): Add NO_TYPE_INS. | |
| 74 | (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. | |
| 75 | (operand_entry): New field - 'flags'. | |
| 76 | (operand flags): New. | |
| 77 | ||
| 78 | 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> | |
| 79 | * crx.h (operand_type): Remove redundant types i3, i4, | |
| 80 | i5, i8, i12. | |
| 81 | Add new unsigned immediate types us3, us4, us5, us16. | |
| 82 | ||
| bc4bd9ab MK |
83 | 2005-04-12 Mark Kettenis <kettenis@gnu.org> |
| 84 | ||
| 85 | * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and | |
| 86 | adjust them accordingly. | |
| 87 | ||
| 373ff435 JB |
88 | 2005-04-01 Jan Beulich <jbeulich@novell.com> |
| 89 | ||
| 90 | * i386.h (i386_optab): Add rdtscp. | |
| 91 | ||
| 4cc91dba L |
92 | 2005-03-29 H.J. Lu <hongjiu.lu@intel.com> |
| 93 | ||
| 94 | * i386.h (i386_optab): Don't allow the `l' suffix for moving | |
| 418a8fca AS |
95 | between memory and segment register. Allow movq for moving between |
| 96 | general-purpose register and segment register. | |
| 4cc91dba | 97 | |
| 9ae09ff9 JB |
98 | 2005-02-09 Jan Beulich <jbeulich@novell.com> |
| 99 | ||
| 100 | PR gas/707 | |
| 101 | * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and | |
| 102 | FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and | |
| 103 | fnstsw. | |
| 104 | ||
| 90219bd0 AO |
105 | 2005-01-25 Alexandre Oliva <aoliva@redhat.com> |
| 106 | ||
| 107 | 2004-11-10 Alexandre Oliva <aoliva@redhat.com> | |
| 108 | * cgen.h (enum cgen_parse_operand_type): Add | |
| 109 | CGEN_PARSE_OPERAND_SYMBOLIC. | |
| 110 | ||
| 239cb185 FF |
111 | 2005-01-21 Fred Fish <fnf@specifixinc.com> |
| 112 | ||
| 113 | * mips.h: Change INSN_ALIAS to INSN2_ALIAS. | |
| 114 | Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. | |
| 115 | Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. | |
| 116 | ||
| dc9a9f39 FF |
117 | 2005-01-19 Fred Fish <fnf@specifixinc.com> |
| 118 | ||
| 119 | * mips.h (struct mips_opcode): Add new pinfo2 member. | |
| 120 | (INSN_ALIAS): New define for opcode table entries that are | |
| 121 | specific instances of another entry, such as 'move' for an 'or' | |
| 122 | with a zero operand. | |
| 123 | (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. | |
| 124 | (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. | |
| 125 | ||
| 98e7aba8 ILT |
126 | 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com> |
| 127 | ||
| 128 | * mips.h (CPU_RM9000): Define. | |
| 129 | (OPCODE_IS_MEMBER): Handle CPU_RM9000. | |
| 130 | ||
| 37edbb65 JB |
131 | 2004-11-25 Jan Beulich <jbeulich@novell.com> |
| 132 | ||
| 133 | * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves | |
| 134 | to/from test registers are illegal in 64-bit mode. Add missing | |
| 135 | NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix | |
| 136 | (previously one had to explicitly encode a rex64 prefix). Re-enable | |
| 137 | lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings | |
| 138 | support it there. Add cmpxchg16b as per Intel's 64-bit documentation. | |
| 139 | ||
| 140 | 2004-11-23 Jan Beulich <jbeulich@novell.com> | |
| 5c6af06e JB |
141 | |
| 142 | * i386.h (i386_optab): paddq and psubq, even in their MMX form, are | |
| 143 | available only with SSE2. Change the MMX additions introduced by SSE | |
| 144 | and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A | |
| 145 | instructions by their now designated identifier (since combining i686 | |
| 146 | and 3DNow! does not really imply 3DNow!A). | |
| 147 | ||
| f5c7edf4 AM |
148 | 2004-11-19 Alan Modra <amodra@bigpond.net.au> |
| 149 | ||
| 150 | * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, | |
| 151 | struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. | |
| 152 | ||
| 7499d566 NC |
153 | 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> |
| 154 | Vineet Sharma <vineets@noida.hcltech.com> | |
| 155 | ||
| 156 | * maxq.h: New file: Disassembly information for the maxq port. | |
| 157 | ||
| bcb9eebe L |
158 | 2004-11-05 H.J. Lu <hongjiu.lu@intel.com> |
| 159 | ||
| 160 | * i386.h (i386_optab): Put back "movzb". | |
| 161 | ||
| 94bb3d38 HPN |
162 | 2004-11-04 Hans-Peter Nilsson <hp@axis.com> |
| 163 | ||
| 164 | * cris.h (enum cris_insn_version_usage): Tweak formatting and | |
| 165 | comments. Remove member cris_ver_sim. Add members | |
| 166 | cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, | |
| 167 | cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. | |
| 168 | (struct cris_support_reg, struct cris_cond15): New types. | |
| 169 | (cris_conds15): Declare. | |
| 170 | (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) | |
| 171 | (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) | |
| 172 | (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. | |
| 173 | (NOP_Z_BITS): Define in terms of NOP_OPCODE. | |
| 174 | (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and | |
| 175 | SIZE_FIELD_UNSIGNED. | |
| 176 | ||
| 37edbb65 | 177 | 2004-11-04 Jan Beulich <jbeulich@novell.com> |
| 9306ca4a JB |
178 | |
| 179 | * i386.h (sldx_Suf): Remove. | |
| 180 | (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. | |
| 181 | (q_FP): Define, implying no REX64. | |
| 182 | (x_FP, sl_FP): Imply FloatMF. | |
| 183 | (i386_optab): Split reg and mem forms of moving from segment registers | |
| 184 | so that the memory forms can ignore the 16-/32-bit operand size | |
| 185 | distinction. Adjust a few others for Intel mode. Remove *FP uses from | |
| 186 | all non-floating-point instructions. Unite 32- and 64-bit forms of | |
| 187 | movsx, movzx, and movd. Adjust floating point operations for the above | |
| 188 | changes to the *FP macros. Add DefaultSize to floating point control | |
| 189 | insns operating on larger memory ranges. Remove left over comments | |
| 190 | hinting at certain insns being Intel-syntax ones where the ones | |
| 191 | actually meant are already gone. | |
| 192 | ||
| 48c9f030 NC |
193 | 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com> |
| 194 | ||
| 195 | * crx.h: Add COPS_REG_INS - Coprocessor Special register | |
| 196 | instruction type. | |
| 197 | ||
| 0dd132b6 NC |
198 | 2004-09-30 Paul Brook <paul@codesourcery.com> |
| 199 | ||
| 200 | * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. | |
| 201 | (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. | |
| 202 | ||
| 23794b24 MM |
203 | 2004-09-11 Theodore A. Roth <troth@openavr.org> |
| 204 | ||
| 205 | * avr.h: Add support for | |
| 206 | atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. | |
| 207 | ||
| 2a309db0 AM |
208 | 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org> |
| 209 | ||
| 210 | * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. | |
| 211 | ||
| b18c562e NC |
212 | 2004-08-24 Dmitry Diky <diwil@spec.ru> |
| 213 | ||
| 214 | * msp430.h (msp430_opc): Add new instructions. | |
| 215 | (msp430_rcodes): Declare new instructions. | |
| 216 | (msp430_hcodes): Likewise.. | |
| 217 | ||
| 45d313cd NC |
218 | 2004-08-13 Nick Clifton <nickc@redhat.com> |
| 219 | ||
| 220 | PR/301 | |
| 221 | * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX | |
| 222 | processors. | |
| 223 | ||
| 30d1c836 ML |
224 | 2004-08-30 Michal Ludvig <mludvig@suse.cz> |
| 225 | ||
| 226 | * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. | |
| 227 | ||
| 9a45f1c2 L |
228 | 2004-07-22 H.J. Lu <hongjiu.lu@intel.com> |
| 229 | ||
| 230 | * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. | |
| 231 | ||
| 543613e9 NC |
232 | 2004-07-21 Jan Beulich <jbeulich@novell.com> |
| 233 | ||
| 234 | * i386.h: Adjust instruction descriptions to better match the | |
| 235 | specification. | |
| 236 | ||
| b781e558 RE |
237 | 2004-07-16 Richard Earnshaw <rearnsha@arm.com> |
| 238 | ||
| 239 | * arm.h: Remove all old content. Replace with architecture defines | |
| 240 | from gas/config/tc-arm.c. | |
| 241 | ||
| 8577e690 AS |
242 | 2004-07-09 Andreas Schwab <schwab@suse.de> |
| 243 | ||
| 244 | * m68k.h: Fix comment. | |
| 245 | ||
| 1fe1f39c NC |
246 | 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> |
| 247 | ||
| 248 | * crx.h: New file. | |
| 249 | ||
| 1d9f512f AM |
250 | 2004-06-24 Alan Modra <amodra@bigpond.net.au> |
| 251 | ||
| 252 | * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. | |
| 253 | ||
| be8c092b NC |
254 | 2004-05-24 Peter Barada <peter@the-baradas.com> |
| 255 | ||
| 256 | * m68k.h: Add 'size' to m68k_opcode. | |
| 257 | ||
| 6b6e92f4 NC |
258 | 2004-05-05 Peter Barada <peter@the-baradas.com> |
| 259 | ||
| 260 | * m68k.h: Switch from ColdFire chip name to core variant. | |
| 261 | ||
| 262 | 2004-04-22 Peter Barada <peter@the-baradas.com> | |
| fd99574b NC |
263 | |
| 264 | * m68k.h: Add mcfmac/mcfemac definitions. Update operand | |
| 265 | descriptions for new EMAC cases. | |
| 266 | Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly | |
| 267 | handle Motorola MAC syntax. | |
| 268 | Allow disassembly of ColdFire V4e object files. | |
| 269 | ||
| fdd12ef3 AM |
270 | 2004-03-16 Alan Modra <amodra@bigpond.net.au> |
| 271 | ||
| 272 | * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. | |
| 273 | ||
| 3922a64c L |
274 | 2004-03-12 Jakub Jelinek <jakub@redhat.com> |
| 275 | ||
| 276 | * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. | |
| 277 | ||
| 1f45d988 ML |
278 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
| 279 | ||
| 280 | * i386.h (i386_optab): Added xstore as an alias for xstorerng. | |
| 281 | ||
| 0f10071e ML |
282 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
| 283 | ||
| 284 | * i386.h (i386_optab): Added xstore/xcrypt insns. | |
| 285 | ||
| 3255318a NC |
286 | 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> |
| 287 | ||
| 288 | * h8300.h (32bit ldc/stc): Add relaxing support. | |
| 289 | ||
| ca9a79a1 | 290 | 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> |
| fdd12ef3 | 291 | |
| ca9a79a1 NC |
292 | * h8300.h (BITOP): Pass MEMRELAX flag. |
| 293 | ||
| 875a0b14 NC |
294 | 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> |
| 295 | ||
| 296 | * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 | |
| 297 | except for the H8S. | |
| 252b5132 | 298 | |
| c9e214e5 | 299 | For older changes see ChangeLog-9103 |
| 252b5132 RH |
300 | \f |
| 301 | Local Variables: | |
| c9e214e5 AM |
302 | mode: change-log |
| 303 | left-margin: 8 | |
| 304 | fill-column: 74 | |
| 252b5132 RH |
305 | version-control: never |
| 306 | End: |