projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Automatic date update in version.in
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
250aafa4
MW		 12015-11-20 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64.h (AARCH64_FEATURE_V8_1): New.
4 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
5
56a1b672
MW		 62015-11-19 Matthew Wahab <matthew.wahab@arm.com>
7
8 * arm.h (ARM_EXT2_V8_2A): New.
9 (ARM_ARCH_V8_2A): New.
10
acb787b0
MW		 112015-11-19 Matthew Wahab <matthew.wahab@arm.com>
12
13 * aarch64.h (AARCH64_FEATURE_V8_2): New.
14 (AARCH64_ARCH_V8_2): New.
15
a680de9a
PB		 162015-11-11 Alan Modra <amodra@gmail.com>
17 Peter Bergner <bergner@vnet.ibm.com>
18
19 * ppc.h (PPC_OPCODE_POWER9): New define.
20 (PPC_OPCODE_VSX3): Likewise.
21
854eb72b
NC		 222015-11-02 Nick Clifton <nickc@redhat.com>
23
24 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
25
e292aa7a
NC		 262015-11-02 Nick Clifton <nickc@redhat.com>
27
28 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
29
43cdf5ae
YQ		 302015-10-28 Yao Qi <yao.qi@linaro.org>
31
32 * aarch64.h (aarch64_decode_insn): Update declaration.
33
875880c6
YQ		 342015-10-07 Yao Qi <yao.qi@linaro.org>
35
36 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
37 <name>: New field.
38
d3e12b29
YQ		 392015-10-07 Yao Qi <yao.qi@linaro.org>
40
41 * aarch64.h [__cplusplus]: Wrap in extern "C".
42
886a2506
NC		 432015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
44 Cupertino Miranda <cmiranda@synopsys.com>
45
46 * arc-func.h: New file.
47 * arc.h: Likewise.
48
e141d84e
YQ		 492015-10-02 Yao Qi <yao.qi@linaro.org>
50
51 * aarch64.h (aarch64_zero_register_p): Move the declaration
52 to column one.
53
36f4aab1
YQ		 542015-10-02 Yao Qi <yao.qi@linaro.org>
55
56 * aarch64.h (aarch64_decode_insn): Declare it.
57
7ecc513a
DV		 582015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
59
60 * s390.h (S390_INSTR_FLAG_HTM): New flag.
61 (S390_INSTR_FLAG_VX): New flag.
62 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
63
b6518b38
NC		 642015-09-23 Nick Clifton <nickc@redhat.com>
65
66 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
67 shifting.
68
f04265ec
NC		 692015-09-22 Nick Clifton <nickc@redhat.com>
70
71 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
72
7bdf96ef
NC		 732015-09-09 Daniel Santos <daniel.santos@pobox.com>
74
75 * visium.h (gen_reg_table): Make static.
76 (fp_reg_table): Likewise.
77 (cc_table): Likewise.
78
f33026a9
MW		 792015-07-20 Matthew Wahab <matthew.wahab@arm.com>
80
81 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
82 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
83 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
84 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
85
ef5a96d5
AM		 862015-07-03 Alan Modra <amodra@gmail.com>
87
88 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
89
c8c8175b
SL		 902015-07-01 Sandra Loosemore <sandra@codesourcery.com>
91 Cesar Philippidis <cesar@codesourcery.com>
92
93 * nios2.h (enum iw_format_type): Add R2 formats.
94 (enum overflow_type): Add signed_immed12_overflow and
95 enumeration_overflow for R2.
96 (struct nios2_opcode): Document new argument letters for R2.
97 (REG_3BIT, REG_LDWM, REG_POP): Define.
98 (includes): Include nios2r2.h.
99 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
100 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
101 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
102 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
103 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
104 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
105 Declare.
106 * nios2r2.h: New file.
107
11a0cf2e
PB		 1082015-06-19 Peter Bergner <bergner@vnet.ibm.com>
109
110 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
111 (ppc_optional_operand_value): New inline function.
112
88f0ea34
MW		 1132015-06-04 Matthew Wahab <matthew.wahab@arm.com>
114
115 * aarch64.h (AARCH64_V8_1): New.
116
a5932920
MW		 1172015-06-03 Matthew Wahab <matthew.wahab@arm.com>
118
119 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
120 (ARM_ARCH_V8_1A): New.
121 (ARM_ARCH_V8_1A_FP): New.
122 (ARM_ARCH_V8_1A_SIMD): New.
123 (ARM_ARCH_V8_1A_CRYPTOV1): New.
124 (ARM_FEATURE_CORE): New.
125
ddfded2f
MW		 1262015-06-02 Matthew Wahab <matthew.wahab@arm.com>
127
128 * arm.h (ARM_EXT2_PAN): New.
129 (ARM_FEATURE_CORE_HIGH): New.
130
1af1dd51
MW		 1312015-06-02 Matthew Wahab <matthew.wahab@arm.com>
132
133 * arm.h (ARM_FEATURE_ALL): New.
134
9e1f0fa7
MW		 1352015-06-02 Matthew Wahab <matthew.wahab@arm.com>
136
137 * aarch64.h (AARCH64_FEATURE_RDMA): New.
138
290806fd
MW		 1392015-06-02 Matthew Wahab <matthew.wahab@arm.com>
140
141 * aarch64.h (AARCH64_FEATURE_LOR): New.
142
f21cce2c
MW		 1432015-06-01 Matthew Wahab <matthew.wahab@arm.com>
144
145 * aarch64.h (AARCH64_FEATURE_PAN): New.
146 (aarch64_sys_reg_supported_p): Declare.
147 (aarch64_pstatefield_supported_p): Declare.
148
0952813b
DD		 1492015-04-30 DJ Delorie <dj@redhat.com>
150
151 * rl78.h (RL78_Dis_Isa): New.
152 (rl78_decode_opcode): Add ISA parameter.
153
823d2571
TG		 1542015-03-24 Terry Guo <terry.guo@arm.com>
155
156 * arm.h (arm_feature_set): Extended to provide more available bits.
157 (ARM_ANY): Updated to follow above new definition.
158 (ARM_CPU_HAS_FEATURE): Likewise.
159 (ARM_CPU_IS_ANY): Likewise.
160 (ARM_MERGE_FEATURE_SETS): Likewise.
161 (ARM_CLEAR_FEATURE): Likewise.
162 (ARM_FEATURE): Likewise.
163 (ARM_FEATURE_COPY): New macro.
164 (ARM_FEATURE_EQUAL): Likewise.
165 (ARM_FEATURE_ZERO): Likewise.
166 (ARM_FEATURE_CORE_EQUAL): Likewise.
167 (ARM_FEATURE_LOW): Likewise.
168 (ARM_FEATURE_CORE_LOW): Likewise.
169 (ARM_FEATURE_CORE_COPROC): Likewise.
170
f63c1776
PA		 1712015-02-19 Pedro Alves <palves@redhat.com>
172
173 * cgen.h [__cplusplus]: Wrap in extern "C".
174 * msp430-decode.h [__cplusplus]: Likewise.
175 * nios2.h [__cplusplus]: Likewise.
176 * rl78.h [__cplusplus]: Likewise.
177 * rx.h [__cplusplus]: Likewise.
178 * tilegx.h [__cplusplus]: Likewise.
179
3f8107ab
AM		 1802015-01-28 James Bowman <james.bowman@ftdichip.com>
181
182 * ft32.h: New file.
183
1e2e8c52
AK		 1842015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
185
186 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
187
b90efa5b
AM		 1882015-01-01 Alan Modra <amodra@gmail.com>
189
190 Update year range in copyright notice of all files.
191
bffb6004
AG		 1922014-12-27 Anthony Green <green@moxielogic.com>
193
194 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
195 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
196
1945cfa5
EB		 1972014-12-06 Eric Botcazou <ebotcazou@adacore.com>
198
199 * visium.h: New file.
200
d306ce58
SL		 2012014-11-28 Sandra Loosemore <sandra@codesourcery.com>
202
203 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
204 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
205 (NIOS2_INSN_OPTARG): Renumber.
206
b4714c7c
SL		 2072014-11-06 Sandra Loosemore <sandra@codesourcery.com>
208
209 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
210 declaration. Fix obsolete comment.
211
96ba4233
SL		 2122014-10-23 Sandra Loosemore <sandra@codesourcery.com>
213
214 * nios2.h (enum iw_format_type): New.
215 (struct nios2_opcode): Update comments. Add size and format fields.
216 (NIOS2_INSN_OPTARG): New.
217 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
218 (struct nios2_reg): Add regtype field.
219 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
220 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
221 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
222 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
223 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
224 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
225 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
226 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
227 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
228 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
229 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
230 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
231 (OP_MASK_OP, OP_SH_OP): Delete.
232 (OP_MASK_IOP, OP_SH_IOP): Delete.
233 (OP_MASK_IRD, OP_SH_IRD): Delete.
234 (OP_MASK_IRT, OP_SH_IRT): Delete.
235 (OP_MASK_IRS, OP_SH_IRS): Delete.
236 (OP_MASK_ROP, OP_SH_ROP): Delete.
237 (OP_MASK_RRD, OP_SH_RRD): Delete.
238 (OP_MASK_RRT, OP_SH_RRT): Delete.
239 (OP_MASK_RRS, OP_SH_RRS): Delete.
240 (OP_MASK_JOP, OP_SH_JOP): Delete.
241 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
242 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
243 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
244 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
245 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
246 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
247 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
248 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
249 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
250 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
251 (OP_MASK_<insn>, OP_MASK): Delete.
252 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
253 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
254 Include nios2r1.h to define new instruction opcode constants
255 and accessors.
256 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
257 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
258 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
259 (NUMOPCODES, NUMREGISTERS): Delete.
260 * nios2r1.h: New file.
261
0b6be415
JM		 2622014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
263
264 * sparc.h (HWCAP2_VIS3B): Documentation improved.
265
3d68f91c
JM		 2662014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
267
268 * sparc.h (sparc_opcode): new field `hwcaps2'.
269 (HWCAP2_FJATHPLUS): New define.
270 (HWCAP2_VIS3B): Likewise.
271 (HWCAP2_ADP): Likewise.
272 (HWCAP2_SPARC5): Likewise.
273 (HWCAP2_MWAIT): Likewise.
274 (HWCAP2_XMPMUL): Likewise.
275 (HWCAP2_XMONT): Likewise.
276 (HWCAP2_NSEC): Likewise.
277 (HWCAP2_FJATHHPC): Likewise.
278 (HWCAP2_FJDES): Likewise.
279 (HWCAP2_FJAES): Likewise.
280 Document the new operand kind `{', corresponding to the mcdper
281 ancillary state register.
282 Document the new operand kind }, which represents frsd floating
283 point registers (double precision) which must be the same than
284 frs1 in its containing instruction.
285
40c7a7cb
KLC		 2862014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
287
72f4393d 288 * nds32.h: Add new opcode declaration.
40c7a7cb 289
7361da2c
AB		 2902014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
291 Matthew Fortune <matthew.fortune@imgtec.com>
292
293 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
294 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
295 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
296 +I, +O, +R, +:, +\, +", +;
297 (mips_check_prev_operand): New struct.
298 (INSN2_FORBIDDEN_SLOT): New define.
299 (INSN_ISA32R6): New define.
300 (INSN_ISA64R6): New define.
301 (INSN_UPTO32R6): New define.
302 (INSN_UPTO64R6): New define.
303 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
304 (ISA_MIPS32R6): New define.
305 (ISA_MIPS64R6): New define.
306 (CPU_MIPS32R6): New define.
307 (CPU_MIPS64R6): New define.
308 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
309
ee804238
JW		 3102014-09-03 Jiong Wang <jiong.wang@arm.com>
311
312 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
313 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
314 (aarch64_insn_class): Add lse_atomic.
315 (F_LSE_SZ): New field added.
316 (opcode_has_special_coder): Recognize F_LSE_SZ.
317
5575639b
MR		 3182014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
319
320 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
321 over to `+J'.
322
43885403
MF		 3232014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
324
325 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
326 (INSN_LOAD_COPROC): New define.
327 (INSN_COPROC_MOVE_DELAY): Rename to...
328 (INSN_COPROC_MOVE): New define.
329
f36e8886 3302014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 331 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
332 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
333 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 334
335 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
336 (AVR_ISA_2xxxa): Define ISA without LPM.
337 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
338 Add doc for contraint used in 16 bit lds/sts.
339 Adjust ISA group for icall, ijmp, pop and push.
340 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
341
00b32ff2
NC		 3422014-05-19 Nick Clifton <nickc@redhat.com>
343
344 * msp430.h (struct msp430_operand_s): Add vshift field.
345
ae52f483
AB		 3462014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
347
348 * mips.h (INSN_ISA_MASK): Updated.
349 (INSN_ISA32R3): New define.
350 (INSN_ISA32R5): New define.
351 (INSN_ISA64R3): New define.
352 (INSN_ISA64R5): New define.
353 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
354 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
355 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
356 mips64r5.
357 (INSN_UPTO32R3): New define.
358 (INSN_UPTO32R5): New define.
359 (INSN_UPTO64R3): New define.
360 (INSN_UPTO64R5): New define.
361 (ISA_MIPS32R3): New define.
362 (ISA_MIPS32R5): New define.
363 (ISA_MIPS64R3): New define.
364 (ISA_MIPS64R5): New define.
365 (CPU_MIPS32R3): New define.
366 (CPU_MIPS32R5): New define.
367 (CPU_MIPS64R3): New define.
368 (CPU_MIPS64R5): New define.
369
3efe9ec5
RS		 3702014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
371
372 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
373
73589c9d
CS		 3742014-04-22 Christian Svensson <blue@cmd.nu>
375
376 * or32.h: Delete.
377
4b95cf5c
AM		 3782014-03-05 Alan Modra <amodra@gmail.com>
379
380 Update copyright years.
381
e269fea7
AB		 3822013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
383
384 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
385 microMIPS.
386
35c08157
KLC		 3872013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
388 Wei-Cheng Wang <cole945@gmail.com>
389
390 * nds32.h: New file for Andes NDS32.
391
594d8fa8
MF		 3922013-12-07 Mike Frysinger <vapier@gentoo.org>
393
394 * bfin.h: Remove +x file mode.
395
87b8eed7
YZ		 3962013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
397
398 * aarch64.h (aarch64_pstatefields): Change element type to
399 aarch64_sys_reg.
400
c9fb6e58
YZ		 4012013-11-18 Renlin Li <Renlin.Li@arm.com>
402
403 * arm.h (ARM_AEXT_V7VE): New define.
404 (ARM_ARCH_V7VE): New define.
405 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
406
a203d9b7
YZ		 4072013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
408
409 Revert
410
411 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
412
413 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
414 (aarch64_sys_reg_writeonly_p): Ditto.
415
75468c93
YZ		 4162013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
417
418 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
419 (aarch64_sys_reg_writeonly_p): Ditto.
420
49eec193
YZ		 4212013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
422
423 * aarch64.h (aarch64_sys_reg): New typedef.
424 (aarch64_sys_regs): Change to define with the new type.
425 (aarch64_sys_reg_deprecated_p): Declare.
426
68a64283
YZ		 4272013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
428
429 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
430 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
431
387a82f1
CF		 4322013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
433
434 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
435 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
436 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
437 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
438 For MIPS, update extension character sequences after +.
439 (ASE_MSA): New define.
440 (ASE_MSA64): New define.
441 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
442 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
443 For microMIPS, update extension character sequences after +.
444
9aff4b7a
NC		 4452013-08-23 Yuri Chornoivan <yurchor@ukr.net>
446
447 PR binutils/15834
448 * i960.h: Fix typos.
449
e423441d
RS		 4502013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
451
452 * mips.h: Remove references to "+I" and imm2_expr.
453
5e0dc5ba
RS		 4542013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
455
456 * mips.h (M_DEXT, M_DINS): Delete.
457
0f35dbc4
RS		 4582013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
459
460 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
461 (mips_optional_operand_p): New function.
462
14daeee3
RS		 4632013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
464 Richard Sandiford <rdsandiford@googlemail.com>
465
466 * mips.h: Document new VU0 operand characters.
467 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
468 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
469 (OP_REG_R5900_ACC): New mips_reg_operand_types.
470 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
471 (mips_vu0_channel_mask): Declare.
472
3ccad066
RS		 4732013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
474
475 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
476 (mips_int_operand_min, mips_int_operand_max): New functions.
477 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
478
fc76e730
RS		 4792013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
480
481 * mips.h (mips_decode_reg_operand): New function.
482 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
483 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
484 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
485 New macros.
486 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
487 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
488 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
489 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
490 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
491 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
492 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
493 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
494 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
495 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
496 macros to cover the gaps.
497 (INSN2_MOD_SP): Replace with...
498 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
499 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
500 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
501 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
502 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
503 Delete.
504
26545944
RS		 5052013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
506
507 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
508 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
509 (MIPS16_INSN_COND_BRANCH): Delete.
510
7e8b059b
L		 5112013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
512 Kirill Yukhin <kirill.yukhin@intel.com>
513 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
514
515 * i386.h (BND_PREFIX_OPCODE): New.
516
c3c07478
RS		 5172013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
518
519 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
520 OP_SAVE_RESTORE_LIST.
521 (decode_mips16_operand): Declare.
522
ab902481
RS		 5232013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
524
525 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
526 (mips_operand, mips_int_operand, mips_mapped_int_operand)
527 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
528 (mips_pcrel_operand): New structures.
529 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
530 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
531 (decode_mips_operand, decode_micromips_operand): Declare.
532
cc537e56
RS		 5332013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
534
535 * mips.h: Document MIPS16 "I" opcode.
536
f2ae14a1
RS		 5372013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
538
539 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
540 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
541 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
542 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
543 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
544 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
545 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
546 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
547 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
548 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
549 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
550 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
551 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
552 Rename to...
553 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
554 (M_USD_AB): ...these.
555
5c324c16
RS		 5562013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
557
558 * mips.h: Remove documentation of "[" and "]". Update documentation
559 of "k" and the MDMX formats.
560
23e69e47
RS		 5612013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
562
563 * mips.h: Update documentation of "+s" and "+S".
564
27c5c572
RS		 5652013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
566
567 * mips.h: Document "+i".
568
e76ff5ab
RS		 5692013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
570
571 * mips.h: Remove "mi" documentation. Update "mh" documentation.
572 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
573 Delete.
574 (INSN2_WRITE_GPR_MHI): Rename to...
575 (INSN2_WRITE_GPR_MH): ...this.
576
fa7616a4
RS		 5772013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
578
579 * mips.h: Remove documentation of "+D" and "+T".
580
18870af7
RS		 5812013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
582
583 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
584 Use "source" rather than "destination" for microMIPS "G".
585
833794fc
MR		 5862013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
587
588 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
589 values.
590
c3678916
RS		 5912013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
592
593 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
594
7f3c4072
CM		 5952013-06-17 Catherine Moore <clm@codesourcery.com>
596 Maciej W. Rozycki <macro@codesourcery.com>
597 Chao-Ying Fu <fu@mips.com>
598
599 * mips.h (OP_SH_EVAOFFSET): Define.
600 (OP_MASK_EVAOFFSET): Define.
601 (INSN_ASE_MASK): Delete.
602 (ASE_EVA): Define.
603 (M_CACHEE_AB, M_CACHEE_OB): New.
604 (M_LBE_OB, M_LBE_AB): New.
605 (M_LBUE_OB, M_LBUE_AB): New.
606 (M_LHE_OB, M_LHE_AB): New.
607 (M_LHUE_OB, M_LHUE_AB): New.
608 (M_LLE_AB, M_LLE_OB): New.
609 (M_LWE_OB, M_LWE_AB): New.
610 (M_LWLE_AB, M_LWLE_OB): New.
611 (M_LWRE_AB, M_LWRE_OB): New.
612 (M_PREFE_AB, M_PREFE_OB): New.
613 (M_SCE_AB, M_SCE_OB): New.
614 (M_SBE_OB, M_SBE_AB): New.
615 (M_SHE_OB, M_SHE_AB): New.
616 (M_SWE_OB, M_SWE_AB): New.
617 (M_SWLE_AB, M_SWLE_OB): New.
618 (M_SWRE_AB, M_SWRE_OB): New.
619 (MICROMIPSOP_SH_EVAOFFSET): Define.
620 (MICROMIPSOP_MASK_EVAOFFSET): Define.
621
0c8fe7cf
SL		 6222013-06-12 Sandra Loosemore <sandra@codesourcery.com>
623
624 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
625
c77c0862
RS		 6262013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
627
628 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
629
b015e599
AP		 6302013-05-09 Andrew Pinski <apinski@cavium.com>
631
632 * mips.h (OP_MASK_CODE10): Correct definition.
633 (OP_SH_CODE10): Likewise.
634 Add a comment that "+J" is used now for OP_*CODE10.
635 (INSN_ASE_MASK): Update.
636 (INSN_VIRT): New macro.
637 (INSN_VIRT64): New macro
638
13761a11
NC		 6392013-05-02 Nick Clifton <nickc@redhat.com>
640
641 * msp430.h: Add patterns for MSP430X instructions.
642
0afd1215
DM		 6432013-04-06 David S. Miller <davem@davemloft.net>
644
645 * sparc.h (F_PREFERRED): Define.
646 (F_PREF_ALIAS): Define.
647
41702d50
NC		 6482013-04-03 Nick Clifton <nickc@redhat.com>
649
650 * v850.h (V850_INVERSE_PCREL): Define.
651
e21e1a51
NC		 6522013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
653
654 PR binutils/15068
655 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
656
51dcdd4d
NC		 6572013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
658
659 PR binutils/15068
660 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
661 Add 16-bit opcodes.
662 * tic6xc-opcode-table.h: Add 16-bit insns.
663 * tic6x.h: Add support for 16-bit insns.
664
81f5558e
NC		 6652013-03-21 Michael Schewe <michael.schewe@gmx.net>
666
667 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
668 and mov.b/w/l Rs,@(d:32,ERd).
669
165546ad
NC		 6702013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
671
672 PR gas/15082
673 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
674 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
675 tic6x_operand_xregpair operand coding type.
676 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
677 opcode field, usu ORXREGD1324 for the src2 operand and remove the
678 TIC6X_FLAG_NO_CROSS.
679
795b8e6b
NC		 6802013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
681
682 PR gas/15095
683 * tic6x.h (enum tic6x_coding_method): Add
684 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
685 separately the msb and lsb of a register pair. This is needed to
686 encode the opcodes in the same way as TI assembler does.
687 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
688 and rsqrdp opcodes to use the new field coding types.
689
dd5181d5
KT		 6902013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
691
692 * arm.h (CRC_EXT_ARMV8): New constant.
693 (ARCH_CRC_ARMV8): New macro.
694
e60bb1dd
YZ		 6952013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
696
697 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
698
36591ba1 6992013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 700 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 701
702 Based on patches from Altera Corporation.
703
704 * nios2.h: New file.
705
e30181a5
YZ		 7062013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
707
708 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
709
0c9573f4
NC		 7102013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
711
712 PR gas/15069
713 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
714
981dc7f1
NC		 7152013-01-24 Nick Clifton <nickc@redhat.com>
716
717 * v850.h: Add e3v5 support.
718
f5555712
YZ		 7192013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
720
721 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
722
5817ffd1
PB		 7232013-01-10 Peter Bergner <bergner@vnet.ibm.com>
724
725 * ppc.h (PPC_OPCODE_POWER8): New define.
726 (PPC_OPCODE_HTM): Likewise.
727
a3c62988
NC		 7282013-01-10 Will Newton <will.newton@imgtec.com>
729
730 * metag.h: New file.
731
73335eae
NC		 7322013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
733
734 * cr16.h (make_instruction): Rename to cr16_make_instruction.
735 (match_opcode): Rename to cr16_match_opcode.
736
e407c74b
NC		 7372013-01-04 Juergen Urban <JuergenUrban@gmx.de>
738
739 * mips.h: Add support for r5900 instructions including lq and sq.
740
bab4becb
NC		 7412013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
742
743 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
744 (make_instruction,match_opcode): Added function prototypes.
745 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
746
776fc418
AM		 7472012-11-23 Alan Modra <amodra@gmail.com>
748
749 * ppc.h (ppc_parse_cpu): Update prototype.
750
f05682d4
DA		 7512012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
752
753 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
754 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
755
cfc72779
AK		 7562012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
757
758 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
759
b3e14eda
L		 7602012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
761
762 * ia64.h (ia64_opnd): Add new operand types.
763
2c63854f
DM		 7642012-08-21 David S. Miller <davem@davemloft.net>
765
766 * sparc.h (F3F4): New macro.
767
a06ea964 7682012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 769 Laurent Desnogues <laurent.desnogues@arm.com>
770 Jim MacArthur <jim.macarthur@arm.com>
771 Marcus Shawcroft <marcus.shawcroft@arm.com>
772 Nigel Stephens <nigel.stephens@arm.com>
773 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
774 Richard Earnshaw <rearnsha@arm.com>
775 Sofiane Naci <sofiane.naci@arm.com>
776 Tejas Belagod <tejas.belagod@arm.com>
777 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 778
779 * aarch64.h: New file.
780
35d0a169 7812012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 782 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 783
784 * mips.h (mips_opcode): Add the exclusions field.
785 (OPCODE_IS_MEMBER): Remove macro.
786 (cpu_is_member): New inline function.
787 (opcode_is_member): Likewise.
788
03f66e8a 7892012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 790 Catherine Moore <clm@codesourcery.com>
791 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 792
793 * mips.h: Document microMIPS DSP ASE usage.
794 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
795 microMIPS DSP ASE support.
796 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
797 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
798 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
799 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
800 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
801 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
802 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
803
9d7b4c23
MR		 8042012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
805
806 * mips.h: Fix a typo in description.
807
76e879f8
NC		 8082012-06-07 Georg-Johann Lay <avr@gjlay.de>
809
810 * avr.h: (AVR_ISA_XCH): New define.
811 (AVR_ISA_XMEGA): Use it.
812 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
813
6927f982
NC		 8142012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
815
816 * m68hc11.h: Add XGate definitions.
817 (struct m68hc11_opcode): Add xg_mask field.
818
b9c361e0
JL		 8192012-05-14 Catherine Moore <clm@codesourcery.com>
820 Maciej W. Rozycki <macro@codesourcery.com>
821 Rhonda Wittels <rhonda@codesourcery.com>
822
6927f982 823 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 824 (PPC_OP_SA): New macro.
825 (PPC_OP_SE_VLE): New macro.
826 (PPC_OP): Use a variable shift amount.
827 (powerpc_operand): Update comments.
828 (PPC_OPSHIFT_INV): New macro.
829 (PPC_OPERAND_CR): Replace with...
830 (PPC_OPERAND_CR_BIT): ...this and
831 (PPC_OPERAND_CR_REG): ...this.
832
833
f6c1a2d5
NC		 8342012-05-03 Sean Keys <skeys@ipdatasys.com>
835
836 * xgate.h: Header file for XGATE assembler.
837
ec668d69
DM		 8382012-04-27 David S. Miller <davem@davemloft.net>
839
6cda1326
DM		 840 * sparc.h: Document new arg code' )' for crypto RS3
841 immediates.
842
ec668d69
DM		 843 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
844 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
845 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
846 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
847 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
848 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
849 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
850 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
851 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
852 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
853 HWCAP_CBCOND, HWCAP_CRC32): New defines.
854
aea77599
AM		 8552012-03-10 Edmar Wienskoski <edmar@freescale.com>
856
857 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
858
1f42f8b3
AM		 8592012-02-27 Alan Modra <amodra@gmail.com>
860
861 * crx.h (cst4_map): Update declaration.
862
6f7be959
WL		 8632012-02-25 Walter Lee <walt@tilera.com>
864
865 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
866 TILEGX_OPC_LD_TLS.
867 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
868 TILEPRO_OPC_LW_TLS_SN.
869
42164a71
L		 8702012-02-08 H.J. Lu <hongjiu.lu@intel.com>
871
872 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
873 (XRELEASE_PREFIX_OPCODE): Likewise.
874
432233b3 8752011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 876 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 877
878 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
879 (INSN_OCTEON2): New macro.
880 (CPU_OCTEON2): New macro.
881 (OPCODE_IS_MEMBER): Add Octeon2.
882
dd6a37e7
AP		 8832011-11-29 Andrew Pinski <apinski@cavium.com>
884
885 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
886 (INSN_OCTEONP): New macro.
887 (CPU_OCTEONP): New macro.
888 (OPCODE_IS_MEMBER): Add Octeon+.
889 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
890
99c513f6
DD		 8912011-11-01 DJ Delorie <dj@redhat.com>
892
893 * rl78.h: New file.
894
26f85d7a
MR		 8952011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
896
897 * mips.h: Fix a typo in description.
898
9e8c70f9
DM		 8992011-09-21 David S. Miller <davem@davemloft.net>
900
901 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
902 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
903 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
904 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
905
dec0624d 9062011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 907 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 908
909 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
910 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
911 (INSN_ASE_MASK): Add the MCU bit.
912 (INSN_MCU): New macro.
913 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
914 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
915
2b0c8b40
MR		 9162011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
917
918 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
919 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
920 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
921 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
922 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
923 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
924 (INSN2_READ_GPR_MMN): Likewise.
925 (INSN2_READ_FPR_D): Change the bit used.
926 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
927 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
928 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
929 (INSN2_COND_BRANCH): Likewise.
930 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
931 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
932 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
933 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
934 (INSN2_MOD_GPR_MN): Likewise.
935
ea783ef3
DM		 9362011-08-05 David S. Miller <davem@davemloft.net>
937
938 * sparc.h: Document new format codes '4', '5', and '('.
939 (OPF_LOW4, RS3): New macros.
940
7c176fa8
MR		 9412011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
942
943 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
944 order of flags documented.
945
2309ddf2
MR		 9462011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
947
948 * mips.h: Clarify the description of microMIPS instruction
949 manipulation macros.
950 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
951
df58fc94 9522011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 953 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 954
955 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
956 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
957 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
958 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
959 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
960 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
961 (OP_MASK_RS3, OP_SH_RS3): Likewise.
962 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
963 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
964 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
965 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
966 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
967 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
968 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
969 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
970 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
971 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
972 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
973 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
974 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
975 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
976 (INSN_WRITE_GPR_S): New macro.
977 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
978 (INSN2_READ_FPR_D): Likewise.
979 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
980 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
981 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
982 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
983 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
984 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
985 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
986 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
987 (CPU_MICROMIPS): New macro.
988 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
989 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
990 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
991 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
992 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
993 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
994 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
995 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
996 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
997 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
998 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
999 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1000 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1001 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1002 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1003 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1004 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1005 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1006 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1007 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1008 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1009 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1010 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1011 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1012 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1013 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1014 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1015 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1016 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1017 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1018 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1019 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1020 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1021 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1022 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1023 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1024 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1025 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1026 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1027 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1028 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1029 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1030 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1031 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1032 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1033 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1034 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1035 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1036 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1037 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1038 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1039 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1040 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1041 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1042 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1043 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1044 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1045 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1046 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1047 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1048 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1049 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1050 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1051 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1052 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1053 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1054 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1055 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1056 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1057 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1058 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1059 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1060 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1061 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1062 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1063 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1064 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1065 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1066 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1067 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1068 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1069 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1070 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1071 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1072 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1073 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1074 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1075 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1076 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1077 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1078 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1079 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1080 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1081 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1082 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1083 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1084 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1085 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1086 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1087 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1088 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1089 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1090 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1091 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1092 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1093 (micromips_opcodes): New declaration.
1094 (bfd_micromips_num_opcodes): Likewise.
1095
bcd530a7
RS		 10962011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1097
1098 * mips.h (INSN_TRAP): Rename to...
1099 (INSN_NO_DELAY_SLOT): ... this.
1100 (INSN_SYNC): Remove macro.
1101
2dad5a91
EW		 11022011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1103
1104 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1105 a duplicate of AVR_ISA_SPM.
1106
5d73b1f1
NC		 11072011-07-01 Nick Clifton <nickc@redhat.com>
1108
1109 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1110
ef26d60e
MF		 11112011-06-18 Robin Getz <robin.getz@analog.com>
1112
1113 * bfin.h (is_macmod_signed): New func
1114
8fb8dca7
MF		 11152011-06-18 Mike Frysinger <vapier@gentoo.org>
1116
1117 * bfin.h (is_macmod_pmove): Add missing space before func args.
1118 (is_macmod_hmove): Likewise.
1119
aa137e4d
NC		 11202011-06-13 Walter Lee <walt@tilera.com>
1121
1122 * tilegx.h: New file.
1123 * tilepro.h: New file.
1124
3b2f0793
PB		 11252011-05-31 Paul Brook <paul@codesourcery.com>
1126
aa137e4d
NC		 1127 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1128
11292011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1130
1131 * s390.h: Replace S390_OPERAND_REG_EVEN with
1132 S390_OPERAND_REG_PAIR.
1133
11342011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1135
1136 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1137
ac7f631b
NC		 11382011-04-18 Julian Brown <julian@codesourcery.com>
1139
1140 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1141
84701018
NC		 11422011-04-11 Dan McDonald <dan@wellkeeper.com>
1143
1144 PR gas/12296
1145 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1146
8cc66334
EW		 11472011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1148
1149 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1150 New instruction set flags.
1151 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1152
3eebd5eb
MR		 11532011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1154
1155 * mips.h (M_PREF_AB): New enum value.
1156
26bb3ddd
MF		 11572011-02-12 Mike Frysinger <vapier@gentoo.org>
1158
89c0d58c
MR		 1159 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1160 M_IU): Define.
1161 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1162
dd76fcb8
MF		 11632011-02-11 Mike Frysinger <vapier@gentoo.org>
1164
1165 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1166
98d23bef
BS		 11672011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1168
1169 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1170 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1171
3c853d93
DA		 11722010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1173
1174 PR gas/11395
1175 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1176 "bb" entries.
1177
79676006
DA		 11782010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1179
1180 PR gas/11395
1181 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1182
1bec78e9
RS		 11832010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1184
1185 * mips.h: Update commentary after last commit.
1186
98675402
RS		 11872010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1188
1189 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1190 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1191 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1192
aa137e4d
NC		 11932010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1194
1195 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1196
435b94a4
RS		 11972010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1198
1199 * mips.h: Fix previous commit.
1200
d051516a
NC		 12012010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1202
1203 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1204 (INSN_LOONGSON_3A): Clear bit 31.
1205
251665fc
MGD		 12062010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1207
1208 PR gas/12198
1209 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1210 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1211 (ARM_ARCH_V6M_ONLY): New define.
1212
fd503541
NC		 12132010-11-11 Mingming Sun <mingm.sun@gmail.com>
1214
1215 * mips.h (INSN_LOONGSON_3A): Defined.
1216 (CPU_LOONGSON_3A): Defined.
1217 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1218
4469d2be
AM		 12192010-10-09 Matt Rice <ratmice@gmail.com>
1220
1221 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1222 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1223
90ec0d68
MGD		 12242010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1225
1226 * arm.h (ARM_EXT_VIRT): New define.
1227 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1228 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1229 Extensions.
1230
eea54501 12312010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1232
eea54501
MGD		 1233 * arm.h (ARM_AEXT_ADIV): New define.
1234 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1235
b2a5fbdc
MGD		 12362010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1237
1238 * arm.h (ARM_EXT_OS): New define.
1239 (ARM_AEXT_V6SM): Likewise.
1240 (ARM_ARCH_V6SM): Likewise.
1241
60e5ef9f
MGD		 12422010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1243
1244 * arm.h (ARM_EXT_MP): Add.
1245 (ARM_ARCH_V7A_MP): Likewise.
1246
73a63ccf
MF		 12472010-09-22 Mike Frysinger <vapier@gentoo.org>
1248
1249 * bfin.h: Declare pseudoChr structs/defines.
1250
ee99860a
MF		 12512010-09-21 Mike Frysinger <vapier@gentoo.org>
1252
1253 * bfin.h: Strip trailing whitespace.
1254
f9c7014e
DD		 12552010-07-29 DJ Delorie <dj@redhat.com>
1256
1257 * rx.h (RX_Operand_Type): Add TwoReg.
1258 (RX_Opcode_ID): Remove ediv and ediv2.
1259
93378652
DD		 12602010-07-27 DJ Delorie <dj@redhat.com>
1261
1262 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1263
1cd986c5
NC		 12642010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1265 Ina Pandit <ina.pandit@kpitcummins.com>
1266
1267 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1268 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1269 PROCESSOR_V850E2_ALL.
1270 Remove PROCESSOR_V850EA support.
1271 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1272 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1273 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1274 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1275 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1276 V850_OPERAND_PERCENT.
1277 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1278 V850_NOT_R0.
1279 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1280 and V850E_PUSH_POP
1281
9a2c7088
MR		 12822010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1283
1284 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1285 (MIPS16_INSN_BRANCH): Rename to...
1286 (MIPS16_INSN_COND_BRANCH): ... this.
1287
bdc70b4a
AM		 12882010-07-03 Alan Modra <amodra@gmail.com>
1289
1290 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1291 Renumber other PPC_OPCODE defines.
1292
f2bae120
AM		 12932010-07-03 Alan Modra <amodra@gmail.com>
1294
1295 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1296
360cfc9c
AM		 12972010-06-29 Alan Modra <amodra@gmail.com>
1298
1299 * maxq.h: Delete file.
1300
e01d869a
AM		 13012010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1302
1303 * ppc.h (PPC_OPCODE_E500): Define.
1304
f79e2745
CM		 13052010-05-26 Catherine Moore <clm@codesourcery.com>
1306
1307 * opcode/mips.h (INSN_MIPS16): Remove.
1308
2462afa1
JM		 13092010-04-21 Joseph Myers <joseph@codesourcery.com>
1310
1311 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1312
e4e42b45
NC		 13132010-04-15 Nick Clifton <nickc@redhat.com>
1314
1315 * alpha.h: Update copyright notice to use GPLv3.
1316 * arc.h: Likewise.
1317 * arm.h: Likewise.
1318 * avr.h: Likewise.
1319 * bfin.h: Likewise.
1320 * cgen.h: Likewise.
1321 * convex.h: Likewise.
1322 * cr16.h: Likewise.
1323 * cris.h: Likewise.
1324 * crx.h: Likewise.
1325 * d10v.h: Likewise.
1326 * d30v.h: Likewise.
1327 * dlx.h: Likewise.
1328 * h8300.h: Likewise.
1329 * hppa.h: Likewise.
1330 * i370.h: Likewise.
1331 * i386.h: Likewise.
1332 * i860.h: Likewise.
1333 * i960.h: Likewise.
1334 * ia64.h: Likewise.
1335 * m68hc11.h: Likewise.
1336 * m68k.h: Likewise.
1337 * m88k.h: Likewise.
1338 * maxq.h: Likewise.
1339 * mips.h: Likewise.
1340 * mmix.h: Likewise.
1341 * mn10200.h: Likewise.
1342 * mn10300.h: Likewise.
1343 * msp430.h: Likewise.
1344 * np1.h: Likewise.
1345 * ns32k.h: Likewise.
1346 * or32.h: Likewise.
1347 * pdp11.h: Likewise.
1348 * pj.h: Likewise.
1349 * pn.h: Likewise.
1350 * ppc.h: Likewise.
1351 * pyr.h: Likewise.
1352 * rx.h: Likewise.
1353 * s390.h: Likewise.
1354 * score-datadep.h: Likewise.
1355 * score-inst.h: Likewise.
1356 * sparc.h: Likewise.
1357 * spu-insns.h: Likewise.
1358 * spu.h: Likewise.
1359 * tic30.h: Likewise.
1360 * tic4x.h: Likewise.
1361 * tic54x.h: Likewise.
1362 * tic80.h: Likewise.
1363 * v850.h: Likewise.
1364 * vax.h: Likewise.
1365
40b36596
JM		 13662010-03-25 Joseph Myers <joseph@codesourcery.com>
1367
1368 * tic6x-control-registers.h, tic6x-insn-formats.h,
1369 tic6x-opcode-table.h, tic6x.h: New.
1370
c67a084a
NC		 13712010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1372
1373 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1374
466ef64f
AM		 13752010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1376
1377 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1378
1319d143
L		 13792010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1380
1381 * ia64.h (ia64_find_opcode): Remove argument name.
1382 (ia64_find_next_opcode): Likewise.
1383 (ia64_dis_opcode): Likewise.
1384 (ia64_free_opcode): Likewise.
1385 (ia64_find_dependency): Likewise.
1386
1fbb9298
DE		 13872009-11-22 Doug Evans <dje@sebabeach.org>
1388
1389 * cgen.h: Include bfd_stdint.h.
1390 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1391
ada65aa3
PB		 13922009-11-18 Paul Brook <paul@codesourcery.com>
1393
1394 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1395
9e3c6df6
PB		 13962009-11-17 Paul Brook <paul@codesourcery.com>
1397 Daniel Jacobowitz <dan@codesourcery.com>
1398
1399 * arm.h (ARM_EXT_V6_DSP): Define.
1400 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1401 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1402
0d734b5d
DD		 14032009-11-04 DJ Delorie <dj@redhat.com>
1404
1405 * rx.h (rx_decode_opcode) (mvtipl): Add.
1406 (mvtcp, mvfcp, opecp): Remove.
1407
62f3b8c8
PB		 14082009-11-02 Paul Brook <paul@codesourcery.com>
1409
1410 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1411 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1412 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1413 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1414 FPU_ARCH_NEON_VFP_V4): Define.
1415
ac1e9eca
DE		 14162009-10-23 Doug Evans <dje@sebabeach.org>
1417
1418 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1419 * cgen.h: Update. Improve multi-inclusion macro name.
1420
9fe54b1c
PB		 14212009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1422
1423 * ppc.h (PPC_OPCODE_476): Define.
1424
634b50f2
PB		 14252009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1426
1427 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1428
c7927a3c
NC		 14292009-09-29 DJ Delorie <dj@redhat.com>
1430
1431 * rx.h: New file.
1432
b961e85b
AM		 14332009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1434
1435 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1436
e0d602ec
BE		 14372009-09-21 Ben Elliston <bje@au.ibm.com>
1438
1439 * ppc.h (PPC_OPCODE_PPCA2): New.
1440
96d56e9f
NC		 14412009-09-05 Martin Thuresson <martin@mtme.org>
1442
1443 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1444
d3ce72d0
NC		 14452009-08-29 Martin Thuresson <martin@mtme.org>
1446
1447 * tic30.h (template): Rename type template to
1448 insn_template. Updated code to use new name.
1449 * tic54x.h (template): Rename type template to
1450 insn_template.
1451
824b28db
NH		 14522009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1453
1454 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1455
f865a31d
AG		 14562009-06-11 Anthony Green <green@moxielogic.com>
1457
1458 * moxie.h (MOXIE_F3_PCREL): Define.
1459 (moxie_form3_opc_info): Grow.
1460
0e7c7f11
AG		 14612009-06-06 Anthony Green <green@moxielogic.com>
1462
1463 * moxie.h (MOXIE_F1_M): Define.
1464
20135e4c
NC		 14652009-04-15 Anthony Green <green@moxielogic.com>
1466
1467 * moxie.h: Created.
1468
bcb012d3
DD		 14692009-04-06 DJ Delorie <dj@redhat.com>
1470
1471 * h8300.h: Add relaxation attributes to MOVA opcodes.
1472
69fe9ce5
AM		 14732009-03-10 Alan Modra <amodra@bigpond.net.au>
1474
1475 * ppc.h (ppc_parse_cpu): Declare.
1476
c3b7224a
NC		 14772009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1478
1479 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1480 and _IMM11 for mbitclr and mbitset.
1481 * score-datadep.h: Update dependency information.
1482
066be9f7
PB		 14832009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1484
1485 * ppc.h (PPC_OPCODE_POWER7): New.
1486
fedc618e
DE		 14872009-02-06 Doug Evans <dje@google.com>
1488
1489 * i386.h: Add comment regarding sse* insns and prefixes.
1490
52b6b6b9
JM		 14912009-02-03 Sandip Matte <sandip@rmicorp.com>
1492
1493 * mips.h (INSN_XLR): Define.
1494 (INSN_CHIP_MASK): Update.
1495 (CPU_XLR): Define.
1496 (OPCODE_IS_MEMBER): Update.
1497 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1498
35669430
DE		 14992009-01-28 Doug Evans <dje@google.com>
1500
1501 * opcode/i386.h: Add multiple inclusion protection.
1502 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1503 (EDI_REG_NUM): New macros.
1504 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1505 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1506 (REX_PREFIX_P): New macro.
35669430 1507
1cb0a767
PB		 15082009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1509
1510 * ppc.h (struct powerpc_opcode): New field "deprecated".
1511 (PPC_OPCODE_NOPOWER4): Delete.
1512
3aa3176b
TS		 15132008-11-28 Joshua Kinard <kumba@gentoo.org>
1514
1515 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1516 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1517
8e79c3df
CM		 15182008-11-18 Catherine Moore <clm@codesourcery.com>
1519
1520 * arm.h (FPU_NEON_FP16): New.
1521 (FPU_ARCH_NEON_FP16): New.
1522
de9a3e51
CF		 15232008-11-06 Chao-ying Fu <fu@mips.com>
1524
1525 * mips.h: Doucument '1' for 5-bit sync type.
1526
1ca35711
L		 15272008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1528
1529 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1530 IA64_RS_CR.
1531
9b4e5766
PB		 15322008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1533
1534 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1535
081ba1b3
AM		 15362008-07-30 Michael J. Eager <eager@eagercon.com>
1537
1538 * ppc.h (PPC_OPCODE_405): Define.
1539 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1540
fa452fa6
PB		 15412008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1542
1543 * ppc.h (ppc_cpu_t): New typedef.
1544 (struct powerpc_opcode <flags>): Use it.
1545 (struct powerpc_operand <insert, extract>): Likewise.
1546 (struct powerpc_macro <flags>): Likewise.
1547
bb35fb24
NC		 15482008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1549
1550 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1551 Update comment before MIPS16 field descriptors to mention MIPS16.
1552 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1553 BBIT.
1554 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1555 New bit masks and shift counts for cins and exts.
1556
dd3cbb7e
NC		 1557 * mips.h: Document new field descriptors +Q.
1558 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1559
d0799671
AN		 15602008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1561
9aff4b7a 1562 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1563 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1564
19a6653c
AM		 15652008-04-14 Edmar Wienskoski <edmar@freescale.com>
1566
1567 * ppc.h: (PPC_OPCODE_E500MC): New.
1568
c0f3af97
L		 15692008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1570
1571 * i386.h (MAX_OPERANDS): Set to 5.
1572 (MAX_MNEM_SIZE): Changed to 20.
1573
e210c36b
NC		 15742008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1575
1576 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1577
b1cc4aeb
PB		 15782008-03-09 Paul Brook <paul@codesourcery.com>
1579
1580 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1581
7e806470
PB		 15822008-03-04 Paul Brook <paul@codesourcery.com>
1583
1584 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1585 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1586 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1587
7b2185f9 15882008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1589 Nick Clifton <nickc@redhat.com>
1590
1591 PR 3134
1592 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1593 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1594 set.
af7329f0 1595
796d5313
NC		 15962008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1597
1598 * cr16.h (cr16_num_optab): Declared.
1599
d669d37f
NC		 16002008-02-14 Hakan Ardo <hakan@debian.org>
1601
1602 PR gas/2626
1603 * avr.h (AVR_ISA_2xxe): Define.
1604
e6429699
AN		 16052008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1606
1607 * mips.h: Update copyright.
1608 (INSN_CHIP_MASK): New macro.
1609 (INSN_OCTEON): New macro.
1610 (CPU_OCTEON): New macro.
1611 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1612
e210c36b
NC		 16132008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1614
1615 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1616
16172008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1618
1619 * avr.h (AVR_ISA_USB162): Add new opcode set.
1620 (AVR_ISA_AVR3): Likewise.
1621
350cc38d
MS		 16222007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1623
1624 * mips.h (INSN_LOONGSON_2E): New.
1625 (INSN_LOONGSON_2F): New.
1626 (CPU_LOONGSON_2E): New.
1627 (CPU_LOONGSON_2F): New.
1628 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1629
56950294
MS		 16302007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1631
1632 * mips.h (INSN_ISA*): Redefine certain values as an
1633 enumeration. Update comments.
1634 (mips_isa_table): New.
1635 (ISA_MIPS*): Redefine to match enumeration.
1636 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1637 values.
1638
c3d65c1c
BE		 16392007-08-08 Ben Elliston <bje@au.ibm.com>
1640
1641 * ppc.h (PPC_OPCODE_PPCPS): New.
1642
0fdaa005
L		 16432007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1644
1645 * m68k.h: Document j K & E.
1646
16472007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1648
1649 * cr16.h: New file for CR16 target.
1650
3896c469
AM		 16512007-05-02 Alan Modra <amodra@bigpond.net.au>
1652
1653 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1654
9a2e615a
NS		 16552007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1656
1657 * m68k.h (mcfisa_c): New.
1658 (mcfusp, mcf_mask): Adjust.
1659
b84bf58a
AM		 16602007-04-20 Alan Modra <amodra@bigpond.net.au>
1661
1662 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1663 (num_powerpc_operands): Declare.
1664 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1665 (PPC_OPERAND_PLUS1): Define.
1666
831480e9 16672007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1668
1669 * i386.h (REX_MODE64): Renamed to ...
1670 (REX_W): This.
1671 (REX_EXTX): Renamed to ...
1672 (REX_R): This.
1673 (REX_EXTY): Renamed to ...
1674 (REX_X): This.
1675 (REX_EXTZ): Renamed to ...
1676 (REX_B): This.
1677
0b1cf022
L		 16782007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1679
1680 * i386.h: Add entries from config/tc-i386.h and move tables
1681 to opcodes/i386-opc.h.
1682
d796c0ad
L		 16832007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1684
1685 * i386.h (FloatDR): Removed.
1686 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1687
30ac7323
AM		 16882007-03-01 Alan Modra <amodra@bigpond.net.au>
1689
1690 * spu-insns.h: Add soma double-float insns.
1691
8b082fb1 16922007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1693 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1694
1695 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1696 (INSN_DSPR2): Add flag for DSP R2 instructions.
1697 (M_BALIGN): New macro.
1698
4eed87de
AM		 16992007-02-14 Alan Modra <amodra@bigpond.net.au>
1700
1701 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1702 and Seg3ShortFrom with Shortform.
1703
fda592e8
L		 17042007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1705
1706 PR gas/4027
1707 * i386.h (i386_optab): Put the real "test" before the pseudo
1708 one.
1709
3bdcfdf4
KH		 17102007-01-08 Kazu Hirata <kazu@codesourcery.com>
1711
1712 * m68k.h (m68010up): OR fido_a.
1713
9840d27e
KH		 17142006-12-25 Kazu Hirata <kazu@codesourcery.com>
1715
1716 * m68k.h (fido_a): New.
1717
c629cdac
KH		 17182006-12-24 Kazu Hirata <kazu@codesourcery.com>
1719
1720 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1721 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1722 values.
1723
b7d9ef37
L		 17242006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1725
1726 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1727
b138abaa
NC		 17282006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1729
1730 * score-inst.h (enum score_insn_type): Add Insn_internal.
1731
e9f53129
AM		 17322006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1733 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1734 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1735 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1736 Alan Modra <amodra@bigpond.net.au>
1737
1738 * spu-insns.h: New file.
1739 * spu.h: New file.
1740
ede602d7
AM		 17412006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1742
1743 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1744
7918206c
MM		 17452006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1746
e4e42b45 1747 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1748 in amdfam10 architecture.
1749
ef05d495
L		 17502006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1751
1752 * i386.h: Replace CpuMNI with CpuSSSE3.
1753
2d447fca 17542006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1755 Joseph Myers <joseph@codesourcery.com>
1756 Ian Lance Taylor <ian@wasabisystems.com>
1757 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1758
1759 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1760
1c0d3aa6
NC		 17612006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1762
1763 * score-datadep.h: New file.
1764 * score-inst.h: New file.
1765
c2f0420e
L		 17662006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1767
1768 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1769 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1770 movdq2q and movq2dq.
1771
050dfa73
MM		 17722006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1773 Michael Meissner <michael.meissner@amd.com>
1774
1775 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1776
15965411
L		 17772006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1778
1779 * i386.h (i386_optab): Add "nop" with memory reference.
1780
46e883c5
L		 17812006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1782
1783 * i386.h (i386_optab): Update comment for 64bit NOP.
1784
9622b051
AM		 17852006-06-06 Ben Elliston <bje@au.ibm.com>
1786 Anton Blanchard <anton@samba.org>
1787
1788 * ppc.h (PPC_OPCODE_POWER6): Define.
1789 Adjust whitespace.
1790
a9e24354
TS		 17912006-06-05 Thiemo Seufer <ths@mips.com>
1792
e4e42b45 1793 * mips.h: Improve description of MT flags.
a9e24354 1794
a596001e
RS		 17952006-05-25 Richard Sandiford <richard@codesourcery.com>
1796
1797 * m68k.h (mcf_mask): Define.
1798
d43b4baf 17992006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1800 David Ung <davidu@mips.com>
d43b4baf
TS		 1801
1802 * mips.h (enum): Add macro M_CACHE_AB.
1803
39a7806d 18042006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1805 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1806 David Ung <davidu@mips.com>
1807
1808 * mips.h: Add INSN_SMARTMIPS define.
1809
9bcd4f99 18102006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1811 David Ung <davidu@mips.com>
9bcd4f99
TS		 1812
1813 * mips.h: Defines udi bits and masks. Add description of
1814 characters which may appear in the args field of udi
1815 instructions.
1816
ef0ee844
TS		 18172006-04-26 Thiemo Seufer <ths@networkno.de>
1818
1819 * mips.h: Improve comments describing the bitfield instruction
1820 fields.
1821
f7675147
L		 18222006-04-26 Julian Brown <julian@codesourcery.com>
1823
1824 * arm.h (FPU_VFP_EXT_V3): Define constant.
1825 (FPU_NEON_EXT_V1): Likewise.
1826 (FPU_VFP_HARD): Update.
1827 (FPU_VFP_V3): Define macro.
1828 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1829
ef0ee844 18302006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1831
1832 * avr.h (AVR_ISA_PWMx): New.
1833
2da12c60
NS		 18342006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1835
1836 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1837 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1838 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1839 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1840 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1841
0715c387
PB		 18422006-03-10 Paul Brook <paul@codesourcery.com>
1843
1844 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1845
34bdd094
DA		 18462006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1847
1848 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1849 first. Correct mask of bb "B" opcode.
1850
331d2d0d
L		 18512006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1852
1853 * i386.h (i386_optab): Support Intel Merom New Instructions.
1854
62b3e311
PB		 18552006-02-24 Paul Brook <paul@codesourcery.com>
1856
1857 * arm.h: Add V7 feature bits.
1858
59cf82fe
L		 18592006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1860
1861 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1862
e74cfd16
PB		 18632006-01-31 Paul Brook <paul@codesourcery.com>
1864 Richard Earnshaw <rearnsha@arm.com>
1865
1866 * arm.h: Use ARM_CPU_FEATURE.
1867 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1868 (arm_feature_set): Change to a structure.
1869 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1870 ARM_FEATURE): New macros.
1871
5b3f8a92
HPN		 18722005-12-07 Hans-Peter Nilsson <hp@axis.com>
1873
1874 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1875 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1876 (ADD_PC_INCR_OPCODE): Don't define.
1877
cb712a9e
L		 18782005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1879
1880 PR gas/1874
1881 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1882
0499d65b
TS		 18832005-11-14 David Ung <davidu@mips.com>
1884
1885 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1886 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1887 save/restore encoding of the args field.
1888
ea5ca089
DB		 18892005-10-28 Dave Brolley <brolley@redhat.com>
1890
1891 Contribute the following changes:
1892 2005-02-16 Dave Brolley <brolley@redhat.com>
1893
1894 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1895 cgen_isa_mask_* to cgen_bitset_*.
1896 * cgen.h: Likewise.
1897
16175d96
DB		 1898 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1899
1900 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1901 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1902 (CGEN_CPU_TABLE): Make isas a ponter.
1903
1904 2003-09-29 Dave Brolley <brolley@redhat.com>
1905
1906 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1907 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1908 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1909
1910 2002-12-13 Dave Brolley <brolley@redhat.com>
1911
1912 * cgen.h (symcat.h): #include it.
1913 (cgen-bitset.h): #include it.
1914 (CGEN_ATTR_VALUE_TYPE): Now a union.
1915 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1916 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1917 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1918 * cgen-bitset.h: New file.
1919
3c9b82ba
NC		 19202005-09-30 Catherine Moore <clm@cm00re.com>
1921
1922 * bfin.h: New file.
1923
6a2375c6
JB		 19242005-10-24 Jan Beulich <jbeulich@novell.com>
1925
1926 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1927 indirect operands.
1928
c06a12f8
DA		 19292005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1930
1931 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1932 Add FLAG_STRICT to pa10 ftest opcode.
1933
4d443107
DA		 19342005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1935
1936 * hppa.h (pa_opcodes): Remove lha entries.
1937
f0a3b40f
DA		 19382005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1939
1940 * hppa.h (FLAG_STRICT): Revise comment.
1941 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1942 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1943 entries for "fdc".
1944
e210c36b
NC		 19452005-09-30 Catherine Moore <clm@cm00re.com>
1946
1947 * bfin.h: New file.
1948
1b7e1362
DA		 19492005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1950
1951 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1952
089b39de
CF		 19532005-09-06 Chao-ying Fu <fu@mips.com>
1954
1955 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1956 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1957 define.
1958 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1959 (INSN_ASE_MASK): Update to include INSN_MT.
1960 (INSN_MT): New define for MT ASE.
1961
93c34b9b
CF		 19622005-08-25 Chao-ying Fu <fu@mips.com>
1963
1964 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1965 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1966 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1967 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1968 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1969 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1970 instructions.
1971 (INSN_DSP): New define for DSP ASE.
1972
848cf006
AM		 19732005-08-18 Alan Modra <amodra@bigpond.net.au>
1974
1975 * a29k.h: Delete.
1976
36ae0db3
DJ		 19772005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1978
1979 * ppc.h (PPC_OPCODE_E300): Define.
1980
8c929562
MS		 19812005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1982
1983 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1984
f7b8cccc
DA		 19852005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1986
1987 PR gas/336
1988 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1989 and pitlb.
1990
8b5328ac
JB		 19912005-07-27 Jan Beulich <jbeulich@novell.com>
1992
1993 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1994 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1995 Add movq-s as 64-bit variants of movd-s.
1996
f417d200
DA		 19972005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1998
18b3bdfc
DA		 1999 * hppa.h: Fix punctuation in comment.
2000
f417d200
DA		 2001 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2002 implicit space-register addressing. Set space-register bits on opcodes
2003 using implicit space-register addressing. Add various missing pa20
2004 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2005 space-register addressing. Use "fE" instead of "fe" in various
2006 fstw opcodes.
2007
9a145ce6
JB		 20082005-07-18 Jan Beulich <jbeulich@novell.com>
2009
2010 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2011
90700ea2
L		 20122007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2013
2014 * i386.h (i386_optab): Support Intel VMX Instructions.
2015
48f130a8
DA		 20162005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2017
2018 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2019
30123838
JB		 20202005-07-05 Jan Beulich <jbeulich@novell.com>
2021
2022 * i386.h (i386_optab): Add new insns.
2023
47b0e7ad
NC		 20242005-07-01 Nick Clifton <nickc@redhat.com>
2025
2026 * sparc.h: Add typedefs to structure declarations.
2027
b300c311
L		 20282005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2029
2030 PR 1013
2031 * i386.h (i386_optab): Update comments for 64bit addressing on
2032 mov. Allow 64bit addressing for mov and movq.
2033
2db495be
DA		 20342005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2035
2036 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2037 respectively, in various floating-point load and store patterns.
2038
caa05036
DA		 20392005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2040
2041 * hppa.h (FLAG_STRICT): Correct comment.
2042 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2043 PA 2.0 mneumonics when equivalent. Entries with cache control
2044 completers now require PA 1.1. Adjust whitespace.
2045
f4411256
AM		 20462005-05-19 Anton Blanchard <anton@samba.org>
2047
2048 * ppc.h (PPC_OPCODE_POWER5): Define.
2049
e172dbf8
NC		 20502005-05-10 Nick Clifton <nickc@redhat.com>
2051
2052 * Update the address and phone number of the FSF organization in
2053 the GPL notices in the following files:
2054 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2055 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2056 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2057 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2058 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2059 tic54x.h, tic80.h, v850.h, vax.h
2060
e44823cf
JB		 20612005-05-09 Jan Beulich <jbeulich@novell.com>
2062
2063 * i386.h (i386_optab): Add ht and hnt.
2064
791fe849
MK		 20652005-04-18 Mark Kettenis <kettenis@gnu.org>
2066
2067 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2068 Add xcrypt-ctr. Provide aliases without hyphens.
2069
faa7ef87
L		 20702005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2071
a63027e5
L		 2072 Moved from ../ChangeLog
2073
faa7ef87
L		 2074 2005-04-12 Paul Brook <paul@codesourcery.com>
2075 * m88k.h: Rename psr macros to avoid conflicts.
2076
2077 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2078 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2079 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2080 and ARM_ARCH_V6ZKT2.
2081
2082 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2083 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2084 Remove redundant instruction types.
2085 (struct argument): X_op - new field.
2086 (struct cst4_entry): Remove.
2087 (no_op_insn): Declare.
2088
2089 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2090 * crx.h (enum argtype): Rename types, remove unused types.
2091
2092 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2093 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2094 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2095 (enum operand_type): Rearrange operands, edit comments.
2096 replace us<N> with ui<N> for unsigned immediate.
2097 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2098 displacements (respectively).
2099 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2100 (instruction type): Add NO_TYPE_INS.
2101 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2102 (operand_entry): New field - 'flags'.
2103 (operand flags): New.
2104
2105 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2106 * crx.h (operand_type): Remove redundant types i3, i4,
2107 i5, i8, i12.
2108 Add new unsigned immediate types us3, us4, us5, us16.
2109
bc4bd9ab
MK		 21102005-04-12 Mark Kettenis <kettenis@gnu.org>
2111
2112 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2113 adjust them accordingly.
2114
373ff435
JB		 21152005-04-01 Jan Beulich <jbeulich@novell.com>
2116
2117 * i386.h (i386_optab): Add rdtscp.
2118
4cc91dba
L		 21192005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2120
2121 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2122 between memory and segment register. Allow movq for moving between
2123 general-purpose register and segment register.
4cc91dba 2124
9ae09ff9
JB		 21252005-02-09 Jan Beulich <jbeulich@novell.com>
2126
2127 PR gas/707
2128 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2129 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2130 fnstsw.
2131
638e7a64
NS		 21322006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2133
2134 * m68k.h (m68008, m68ec030, m68882): Remove.
2135 (m68k_mask): New.
2136 (cpu_m68k, cpu_cf): New.
2137 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2138 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2139
90219bd0
AO		 21402005-01-25 Alexandre Oliva <aoliva@redhat.com>
2141
2142 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2143 * cgen.h (enum cgen_parse_operand_type): Add
2144 CGEN_PARSE_OPERAND_SYMBOLIC.
2145
239cb185
FF		 21462005-01-21 Fred Fish <fnf@specifixinc.com>
2147
2148 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2149 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2150 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2151
dc9a9f39
FF		 21522005-01-19 Fred Fish <fnf@specifixinc.com>
2153
2154 * mips.h (struct mips_opcode): Add new pinfo2 member.
2155 (INSN_ALIAS): New define for opcode table entries that are
2156 specific instances of another entry, such as 'move' for an 'or'
2157 with a zero operand.
2158 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2159 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2160
98e7aba8
ILT		 21612004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2162
2163 * mips.h (CPU_RM9000): Define.
2164 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2165
37edbb65
JB		 21662004-11-25 Jan Beulich <jbeulich@novell.com>
2167
2168 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2169 to/from test registers are illegal in 64-bit mode. Add missing
2170 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2171 (previously one had to explicitly encode a rex64 prefix). Re-enable
2172 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2173 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2174
21752004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2176
2177 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2178 available only with SSE2. Change the MMX additions introduced by SSE
2179 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2180 instructions by their now designated identifier (since combining i686
2181 and 3DNow! does not really imply 3DNow!A).
2182
f5c7edf4
AM		 21832004-11-19 Alan Modra <amodra@bigpond.net.au>
2184
2185 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2186 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2187
7499d566
NC		 21882004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2189 Vineet Sharma <vineets@noida.hcltech.com>
2190
2191 * maxq.h: New file: Disassembly information for the maxq port.
2192
bcb9eebe
L		 21932004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2194
2195 * i386.h (i386_optab): Put back "movzb".
2196
94bb3d38
HPN		 21972004-11-04 Hans-Peter Nilsson <hp@axis.com>
2198
2199 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2200 comments. Remove member cris_ver_sim. Add members
2201 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2202 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2203 (struct cris_support_reg, struct cris_cond15): New types.
2204 (cris_conds15): Declare.
2205 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2206 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2207 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2208 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2209 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2210 SIZE_FIELD_UNSIGNED.
2211
37edbb65 22122004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2213
2214 * i386.h (sldx_Suf): Remove.
2215 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2216 (q_FP): Define, implying no REX64.
2217 (x_FP, sl_FP): Imply FloatMF.
2218 (i386_optab): Split reg and mem forms of moving from segment registers
2219 so that the memory forms can ignore the 16-/32-bit operand size
2220 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2221 all non-floating-point instructions. Unite 32- and 64-bit forms of
2222 movsx, movzx, and movd. Adjust floating point operations for the above
2223 changes to the *FP macros. Add DefaultSize to floating point control
2224 insns operating on larger memory ranges. Remove left over comments
2225 hinting at certain insns being Intel-syntax ones where the ones
2226 actually meant are already gone.
2227
48c9f030
NC		 22282004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2229
2230 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2231 instruction type.
2232
0dd132b6
NC		 22332004-09-30 Paul Brook <paul@codesourcery.com>
2234
2235 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2236 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2237
23794b24
MM		 22382004-09-11 Theodore A. Roth <troth@openavr.org>
2239
2240 * avr.h: Add support for
2241 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2242
2a309db0
AM		 22432004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2244
2245 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2246
b18c562e
NC		 22472004-08-24 Dmitry Diky <diwil@spec.ru>
2248
2249 * msp430.h (msp430_opc): Add new instructions.
2250 (msp430_rcodes): Declare new instructions.
2251 (msp430_hcodes): Likewise..
2252
45d313cd
NC		 22532004-08-13 Nick Clifton <nickc@redhat.com>
2254
2255 PR/301
2256 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2257 processors.
2258
30d1c836
ML		 22592004-08-30 Michal Ludvig <mludvig@suse.cz>
2260
2261 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2262
9a45f1c2
L		 22632004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2264
2265 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2266
543613e9
NC		 22672004-07-21 Jan Beulich <jbeulich@novell.com>
2268
2269 * i386.h: Adjust instruction descriptions to better match the
2270 specification.
2271
b781e558
RE		 22722004-07-16 Richard Earnshaw <rearnsha@arm.com>
2273
2274 * arm.h: Remove all old content. Replace with architecture defines
2275 from gas/config/tc-arm.c.
2276
8577e690
AS		 22772004-07-09 Andreas Schwab <schwab@suse.de>
2278
2279 * m68k.h: Fix comment.
2280
1fe1f39c
NC		 22812004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2282
2283 * crx.h: New file.
2284
1d9f512f
AM		 22852004-06-24 Alan Modra <amodra@bigpond.net.au>
2286
2287 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2288
be8c092b
NC		 22892004-05-24 Peter Barada <peter@the-baradas.com>
2290
2291 * m68k.h: Add 'size' to m68k_opcode.
2292
6b6e92f4
NC		 22932004-05-05 Peter Barada <peter@the-baradas.com>
2294
2295 * m68k.h: Switch from ColdFire chip name to core variant.
2296
22972004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2298
2299 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2300 descriptions for new EMAC cases.
2301 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2302 handle Motorola MAC syntax.
2303 Allow disassembly of ColdFire V4e object files.
2304
fdd12ef3
AM		 23052004-03-16 Alan Modra <amodra@bigpond.net.au>
2306
2307 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2308
3922a64c
L		 23092004-03-12 Jakub Jelinek <jakub@redhat.com>
2310
2311 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2312
1f45d988
ML		 23132004-03-12 Michal Ludvig <mludvig@suse.cz>
2314
2315 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2316
0f10071e
ML		 23172004-03-12 Michal Ludvig <mludvig@suse.cz>
2318
2319 * i386.h (i386_optab): Added xstore/xcrypt insns.
2320
3255318a
NC		 23212004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2322
2323 * h8300.h (32bit ldc/stc): Add relaxing support.
2324
ca9a79a1 23252004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2326
ca9a79a1
NC		 2327 * h8300.h (BITOP): Pass MEMRELAX flag.
2328
875a0b14
NC		 23292004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2330
2331 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2332 except for the H8S.
252b5132 2333
c9e214e5 2334For older changes see ChangeLog-9103
252b5132 2335\f
b90efa5b 2336Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2337
2338Copying and distribution of this file, with or without modification,
2339are permitted in any medium without royalty provided the copyright
2340notice and this notice are preserved.
2341
252b5132 2342Local Variables:
c9e214e5
AM		 2343mode: change-log
2344left-margin: 8
2345fill-column: 74
252b5132
RH		 2346version-control: never
2347End:
GDB Binutils - Deliverables
This page took 0.77682 seconds and 4 git commands to generate.