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[ARM] Use frag's thumb_mode information when available
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
a5932920
MW		 12015-06-03 Matthew Wahab <matthew.wahab@arm.com>
2
3 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
4 (ARM_ARCH_V8_1A): New.
5 (ARM_ARCH_V8_1A_FP): New.
6 (ARM_ARCH_V8_1A_SIMD): New.
7 (ARM_ARCH_V8_1A_CRYPTOV1): New.
8 (ARM_FEATURE_CORE): New.
9
ddfded2f
MW		 102015-06-02 Matthew Wahab <matthew.wahab@arm.com>
11
12 * arm.h (ARM_EXT2_PAN): New.
13 (ARM_FEATURE_CORE_HIGH): New.
14
1af1dd51
MW		 152015-06-02 Matthew Wahab <matthew.wahab@arm.com>
16
17 * arm.h (ARM_FEATURE_ALL): New.
18
9e1f0fa7
MW		 192015-06-02 Matthew Wahab <matthew.wahab@arm.com>
20
21 * aarch64.h (AARCH64_FEATURE_RDMA): New.
22
290806fd
MW		 232015-06-02 Matthew Wahab <matthew.wahab@arm.com>
24
25 * aarch64.h (AARCH64_FEATURE_LOR): New.
26
f21cce2c
MW		 272015-06-01 Matthew Wahab <matthew.wahab@arm.com>
28
29 * aarch64.h (AARCH64_FEATURE_PAN): New.
30 (aarch64_sys_reg_supported_p): Declare.
31 (aarch64_pstatefield_supported_p): Declare.
32
0952813b
DD		 332015-04-30 DJ Delorie <dj@redhat.com>
34
35 * rl78.h (RL78_Dis_Isa): New.
36 (rl78_decode_opcode): Add ISA parameter.
37
823d2571
TG		 382015-03-24 Terry Guo <terry.guo@arm.com>
39
40 * arm.h (arm_feature_set): Extended to provide more available bits.
41 (ARM_ANY): Updated to follow above new definition.
42 (ARM_CPU_HAS_FEATURE): Likewise.
43 (ARM_CPU_IS_ANY): Likewise.
44 (ARM_MERGE_FEATURE_SETS): Likewise.
45 (ARM_CLEAR_FEATURE): Likewise.
46 (ARM_FEATURE): Likewise.
47 (ARM_FEATURE_COPY): New macro.
48 (ARM_FEATURE_EQUAL): Likewise.
49 (ARM_FEATURE_ZERO): Likewise.
50 (ARM_FEATURE_CORE_EQUAL): Likewise.
51 (ARM_FEATURE_LOW): Likewise.
52 (ARM_FEATURE_CORE_LOW): Likewise.
53 (ARM_FEATURE_CORE_COPROC): Likewise.
54
f63c1776
PA		 552015-02-19 Pedro Alves <palves@redhat.com>
56
57 * cgen.h [__cplusplus]: Wrap in extern "C".
58 * msp430-decode.h [__cplusplus]: Likewise.
59 * nios2.h [__cplusplus]: Likewise.
60 * rl78.h [__cplusplus]: Likewise.
61 * rx.h [__cplusplus]: Likewise.
62 * tilegx.h [__cplusplus]: Likewise.
63
3f8107ab
AM		 642015-01-28 James Bowman <james.bowman@ftdichip.com>
65
66 * ft32.h: New file.
67
1e2e8c52
AK		 682015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
69
70 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
71
b90efa5b
AM		 722015-01-01 Alan Modra <amodra@gmail.com>
73
74 Update year range in copyright notice of all files.
75
bffb6004
AG		 762014-12-27 Anthony Green <green@moxielogic.com>
77
78 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
79 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
80
1945cfa5
EB		 812014-12-06 Eric Botcazou <ebotcazou@adacore.com>
82
83 * visium.h: New file.
84
d306ce58
SL		 852014-11-28 Sandra Loosemore <sandra@codesourcery.com>
86
87 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
88 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
89 (NIOS2_INSN_OPTARG): Renumber.
90
b4714c7c
SL		 912014-11-06 Sandra Loosemore <sandra@codesourcery.com>
92
93 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
94 declaration. Fix obsolete comment.
95
96ba4233
SL		 962014-10-23 Sandra Loosemore <sandra@codesourcery.com>
97
98 * nios2.h (enum iw_format_type): New.
99 (struct nios2_opcode): Update comments. Add size and format fields.
100 (NIOS2_INSN_OPTARG): New.
101 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
102 (struct nios2_reg): Add regtype field.
103 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
104 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
105 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
106 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
107 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
108 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
109 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
110 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
111 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
112 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
113 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
114 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
115 (OP_MASK_OP, OP_SH_OP): Delete.
116 (OP_MASK_IOP, OP_SH_IOP): Delete.
117 (OP_MASK_IRD, OP_SH_IRD): Delete.
118 (OP_MASK_IRT, OP_SH_IRT): Delete.
119 (OP_MASK_IRS, OP_SH_IRS): Delete.
120 (OP_MASK_ROP, OP_SH_ROP): Delete.
121 (OP_MASK_RRD, OP_SH_RRD): Delete.
122 (OP_MASK_RRT, OP_SH_RRT): Delete.
123 (OP_MASK_RRS, OP_SH_RRS): Delete.
124 (OP_MASK_JOP, OP_SH_JOP): Delete.
125 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
126 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
127 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
128 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
129 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
130 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
131 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
132 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
133 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
134 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
135 (OP_MASK_<insn>, OP_MASK): Delete.
136 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
137 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
138 Include nios2r1.h to define new instruction opcode constants
139 and accessors.
140 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
141 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
142 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
143 (NUMOPCODES, NUMREGISTERS): Delete.
144 * nios2r1.h: New file.
145
0b6be415
JM		 1462014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
147
148 * sparc.h (HWCAP2_VIS3B): Documentation improved.
149
3d68f91c
JM		 1502014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
151
152 * sparc.h (sparc_opcode): new field `hwcaps2'.
153 (HWCAP2_FJATHPLUS): New define.
154 (HWCAP2_VIS3B): Likewise.
155 (HWCAP2_ADP): Likewise.
156 (HWCAP2_SPARC5): Likewise.
157 (HWCAP2_MWAIT): Likewise.
158 (HWCAP2_XMPMUL): Likewise.
159 (HWCAP2_XMONT): Likewise.
160 (HWCAP2_NSEC): Likewise.
161 (HWCAP2_FJATHHPC): Likewise.
162 (HWCAP2_FJDES): Likewise.
163 (HWCAP2_FJAES): Likewise.
164 Document the new operand kind `{', corresponding to the mcdper
165 ancillary state register.
166 Document the new operand kind }, which represents frsd floating
167 point registers (double precision) which must be the same than
168 frs1 in its containing instruction.
169
40c7a7cb
KLC		 1702014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
171
172 * nds32.h: Add new opcode declaration.
173
7361da2c
AB		 1742014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
175 Matthew Fortune <matthew.fortune@imgtec.com>
176
177 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
178 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
179 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
180 +I, +O, +R, +:, +\, +", +;
181 (mips_check_prev_operand): New struct.
182 (INSN2_FORBIDDEN_SLOT): New define.
183 (INSN_ISA32R6): New define.
184 (INSN_ISA64R6): New define.
185 (INSN_UPTO32R6): New define.
186 (INSN_UPTO64R6): New define.
187 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
188 (ISA_MIPS32R6): New define.
189 (ISA_MIPS64R6): New define.
190 (CPU_MIPS32R6): New define.
191 (CPU_MIPS64R6): New define.
192 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
193
ee804238
JW		 1942014-09-03 Jiong Wang <jiong.wang@arm.com>
195
196 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
197 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
198 (aarch64_insn_class): Add lse_atomic.
199 (F_LSE_SZ): New field added.
200 (opcode_has_special_coder): Recognize F_LSE_SZ.
201
5575639b
MR		 2022014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
203
204 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
205 over to `+J'.
206
43885403
MF		 2072014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
208
209 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
210 (INSN_LOAD_COPROC): New define.
211 (INSN_COPROC_MOVE_DELAY): Rename to...
212 (INSN_COPROC_MOVE): New define.
213
f36e8886
BS		 2142014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
215 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
216 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
217 Soundararajan <Sounderarajan.D@atmel.com>
218
219 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
220 (AVR_ISA_2xxxa): Define ISA without LPM.
221 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
222 Add doc for contraint used in 16 bit lds/sts.
223 Adjust ISA group for icall, ijmp, pop and push.
224 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
225
00b32ff2
NC		 2262014-05-19 Nick Clifton <nickc@redhat.com>
227
228 * msp430.h (struct msp430_operand_s): Add vshift field.
229
ae52f483
AB		 2302014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
231
232 * mips.h (INSN_ISA_MASK): Updated.
233 (INSN_ISA32R3): New define.
234 (INSN_ISA32R5): New define.
235 (INSN_ISA64R3): New define.
236 (INSN_ISA64R5): New define.
237 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
238 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
239 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
240 mips64r5.
241 (INSN_UPTO32R3): New define.
242 (INSN_UPTO32R5): New define.
243 (INSN_UPTO64R3): New define.
244 (INSN_UPTO64R5): New define.
245 (ISA_MIPS32R3): New define.
246 (ISA_MIPS32R5): New define.
247 (ISA_MIPS64R3): New define.
248 (ISA_MIPS64R5): New define.
249 (CPU_MIPS32R3): New define.
250 (CPU_MIPS32R5): New define.
251 (CPU_MIPS64R3): New define.
252 (CPU_MIPS64R5): New define.
253
3efe9ec5
RS		 2542014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
255
256 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
257
73589c9d
CS		 2582014-04-22 Christian Svensson <blue@cmd.nu>
259
260 * or32.h: Delete.
261
4b95cf5c
AM		 2622014-03-05 Alan Modra <amodra@gmail.com>
263
264 Update copyright years.
265
e269fea7
AB		 2662013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
267
268 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
269 microMIPS.
270
35c08157
KLC		 2712013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
272 Wei-Cheng Wang <cole945@gmail.com>
273
274 * nds32.h: New file for Andes NDS32.
275
594d8fa8
MF		 2762013-12-07 Mike Frysinger <vapier@gentoo.org>
277
278 * bfin.h: Remove +x file mode.
279
87b8eed7
YZ		 2802013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
281
282 * aarch64.h (aarch64_pstatefields): Change element type to
283 aarch64_sys_reg.
284
c9fb6e58
YZ		 2852013-11-18 Renlin Li <Renlin.Li@arm.com>
286
287 * arm.h (ARM_AEXT_V7VE): New define.
288 (ARM_ARCH_V7VE): New define.
289 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
290
a203d9b7
YZ		 2912013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
292
293 Revert
294
295 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
296
297 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
298 (aarch64_sys_reg_writeonly_p): Ditto.
299
75468c93
YZ		 3002013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
301
302 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
303 (aarch64_sys_reg_writeonly_p): Ditto.
304
49eec193
YZ		 3052013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
306
307 * aarch64.h (aarch64_sys_reg): New typedef.
308 (aarch64_sys_regs): Change to define with the new type.
309 (aarch64_sys_reg_deprecated_p): Declare.
310
68a64283
YZ		 3112013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
312
313 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
314 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
315
387a82f1
CF		 3162013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
317
318 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
319 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
320 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
321 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
322 For MIPS, update extension character sequences after +.
323 (ASE_MSA): New define.
324 (ASE_MSA64): New define.
325 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
326 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
327 For microMIPS, update extension character sequences after +.
328
9aff4b7a
NC		 3292013-08-23 Yuri Chornoivan <yurchor@ukr.net>
330
331 PR binutils/15834
332 * i960.h: Fix typos.
333
e423441d
RS		 3342013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
335
336 * mips.h: Remove references to "+I" and imm2_expr.
337
5e0dc5ba
RS		 3382013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
339
340 * mips.h (M_DEXT, M_DINS): Delete.
341
0f35dbc4
RS		 3422013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
343
344 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
345 (mips_optional_operand_p): New function.
346
14daeee3
RS		 3472013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
348 Richard Sandiford <rdsandiford@googlemail.com>
349
350 * mips.h: Document new VU0 operand characters.
351 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
352 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
353 (OP_REG_R5900_ACC): New mips_reg_operand_types.
354 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
355 (mips_vu0_channel_mask): Declare.
356
3ccad066
RS		 3572013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
358
359 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
360 (mips_int_operand_min, mips_int_operand_max): New functions.
361 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
362
fc76e730
RS		 3632013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
364
365 * mips.h (mips_decode_reg_operand): New function.
366 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
367 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
368 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
369 New macros.
370 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
371 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
372 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
373 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
374 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
375 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
376 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
377 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
378 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
379 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
380 macros to cover the gaps.
381 (INSN2_MOD_SP): Replace with...
382 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
383 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
384 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
385 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
386 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
387 Delete.
388
26545944
RS		 3892013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
390
391 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
392 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
393 (MIPS16_INSN_COND_BRANCH): Delete.
394
7e8b059b
L		 3952013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
396 Kirill Yukhin <kirill.yukhin@intel.com>
397 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
398
399 * i386.h (BND_PREFIX_OPCODE): New.
400
c3c07478
RS		 4012013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
402
403 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
404 OP_SAVE_RESTORE_LIST.
405 (decode_mips16_operand): Declare.
406
ab902481
RS		 4072013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
408
409 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
410 (mips_operand, mips_int_operand, mips_mapped_int_operand)
411 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
412 (mips_pcrel_operand): New structures.
413 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
414 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
415 (decode_mips_operand, decode_micromips_operand): Declare.
416
cc537e56
RS		 4172013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
418
419 * mips.h: Document MIPS16 "I" opcode.
420
f2ae14a1
RS		 4212013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
422
423 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
424 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
425 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
426 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
427 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
428 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
429 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
430 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
431 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
432 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
433 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
434 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
435 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
436 Rename to...
437 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
438 (M_USD_AB): ...these.
439
5c324c16
RS		 4402013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
441
442 * mips.h: Remove documentation of "[" and "]". Update documentation
443 of "k" and the MDMX formats.
444
23e69e47
RS		 4452013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
446
447 * mips.h: Update documentation of "+s" and "+S".
448
27c5c572
RS		 4492013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
450
451 * mips.h: Document "+i".
452
e76ff5ab
RS		 4532013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
454
455 * mips.h: Remove "mi" documentation. Update "mh" documentation.
456 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
457 Delete.
458 (INSN2_WRITE_GPR_MHI): Rename to...
459 (INSN2_WRITE_GPR_MH): ...this.
460
fa7616a4
RS		 4612013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
462
463 * mips.h: Remove documentation of "+D" and "+T".
464
18870af7
RS		 4652013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
466
467 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
468 Use "source" rather than "destination" for microMIPS "G".
469
833794fc
MR		 4702013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
471
472 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
473 values.
474
c3678916
RS		 4752013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
476
477 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
478
7f3c4072
CM		 4792013-06-17 Catherine Moore <clm@codesourcery.com>
480 Maciej W. Rozycki <macro@codesourcery.com>
481 Chao-Ying Fu <fu@mips.com>
482
483 * mips.h (OP_SH_EVAOFFSET): Define.
484 (OP_MASK_EVAOFFSET): Define.
485 (INSN_ASE_MASK): Delete.
486 (ASE_EVA): Define.
487 (M_CACHEE_AB, M_CACHEE_OB): New.
488 (M_LBE_OB, M_LBE_AB): New.
489 (M_LBUE_OB, M_LBUE_AB): New.
490 (M_LHE_OB, M_LHE_AB): New.
491 (M_LHUE_OB, M_LHUE_AB): New.
492 (M_LLE_AB, M_LLE_OB): New.
493 (M_LWE_OB, M_LWE_AB): New.
494 (M_LWLE_AB, M_LWLE_OB): New.
495 (M_LWRE_AB, M_LWRE_OB): New.
496 (M_PREFE_AB, M_PREFE_OB): New.
497 (M_SCE_AB, M_SCE_OB): New.
498 (M_SBE_OB, M_SBE_AB): New.
499 (M_SHE_OB, M_SHE_AB): New.
500 (M_SWE_OB, M_SWE_AB): New.
501 (M_SWLE_AB, M_SWLE_OB): New.
502 (M_SWRE_AB, M_SWRE_OB): New.
503 (MICROMIPSOP_SH_EVAOFFSET): Define.
504 (MICROMIPSOP_MASK_EVAOFFSET): Define.
505
0c8fe7cf
SL		 5062013-06-12 Sandra Loosemore <sandra@codesourcery.com>
507
508 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
509
c77c0862
RS		 5102013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
511
512 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
513
b015e599
AP		 5142013-05-09 Andrew Pinski <apinski@cavium.com>
515
516 * mips.h (OP_MASK_CODE10): Correct definition.
517 (OP_SH_CODE10): Likewise.
518 Add a comment that "+J" is used now for OP_*CODE10.
519 (INSN_ASE_MASK): Update.
520 (INSN_VIRT): New macro.
521 (INSN_VIRT64): New macro
522
13761a11
NC		 5232013-05-02 Nick Clifton <nickc@redhat.com>
524
525 * msp430.h: Add patterns for MSP430X instructions.
526
0afd1215
DM		 5272013-04-06 David S. Miller <davem@davemloft.net>
528
529 * sparc.h (F_PREFERRED): Define.
530 (F_PREF_ALIAS): Define.
531
41702d50
NC		 5322013-04-03 Nick Clifton <nickc@redhat.com>
533
534 * v850.h (V850_INVERSE_PCREL): Define.
535
e21e1a51
NC		 5362013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
537
538 PR binutils/15068
539 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
540
51dcdd4d
NC		 5412013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
542
543 PR binutils/15068
544 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
545 Add 16-bit opcodes.
546 * tic6xc-opcode-table.h: Add 16-bit insns.
547 * tic6x.h: Add support for 16-bit insns.
548
81f5558e
NC		 5492013-03-21 Michael Schewe <michael.schewe@gmx.net>
550
551 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
552 and mov.b/w/l Rs,@(d:32,ERd).
553
165546ad
NC		 5542013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
555
556 PR gas/15082
557 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
558 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
559 tic6x_operand_xregpair operand coding type.
560 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
561 opcode field, usu ORXREGD1324 for the src2 operand and remove the
562 TIC6X_FLAG_NO_CROSS.
563
795b8e6b
NC		 5642013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
565
566 PR gas/15095
567 * tic6x.h (enum tic6x_coding_method): Add
568 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
569 separately the msb and lsb of a register pair. This is needed to
570 encode the opcodes in the same way as TI assembler does.
571 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
572 and rsqrdp opcodes to use the new field coding types.
573
dd5181d5
KT		 5742013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
575
576 * arm.h (CRC_EXT_ARMV8): New constant.
577 (ARCH_CRC_ARMV8): New macro.
578
e60bb1dd
YZ		 5792013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
580
581 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
582
36591ba1
SL		 5832013-02-06 Sandra Loosemore <sandra@codesourcery.com>
584 Andrew Jenner <andrew@codesourcery.com>
585
586 Based on patches from Altera Corporation.
587
588 * nios2.h: New file.
589
e30181a5
YZ		 5902013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
591
592 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
593
0c9573f4
NC		 5942013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
595
596 PR gas/15069
597 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
598
981dc7f1
NC		 5992013-01-24 Nick Clifton <nickc@redhat.com>
600
601 * v850.h: Add e3v5 support.
602
f5555712
YZ		 6032013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
604
605 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
606
5817ffd1
PB		 6072013-01-10 Peter Bergner <bergner@vnet.ibm.com>
608
609 * ppc.h (PPC_OPCODE_POWER8): New define.
610 (PPC_OPCODE_HTM): Likewise.
611
a3c62988
NC		 6122013-01-10 Will Newton <will.newton@imgtec.com>
613
614 * metag.h: New file.
615
73335eae
NC		 6162013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
617
618 * cr16.h (make_instruction): Rename to cr16_make_instruction.
619 (match_opcode): Rename to cr16_match_opcode.
620
e407c74b
NC		 6212013-01-04 Juergen Urban <JuergenUrban@gmx.de>
622
623 * mips.h: Add support for r5900 instructions including lq and sq.
624
bab4becb
NC		 6252013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
626
627 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
628 (make_instruction,match_opcode): Added function prototypes.
629 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
630
776fc418
AM		 6312012-11-23 Alan Modra <amodra@gmail.com>
632
633 * ppc.h (ppc_parse_cpu): Update prototype.
634
f05682d4
DA		 6352012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
636
637 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
638 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
639
cfc72779
AK		 6402012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
641
642 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
643
b3e14eda
L		 6442012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
645
646 * ia64.h (ia64_opnd): Add new operand types.
647
2c63854f
DM		 6482012-08-21 David S. Miller <davem@davemloft.net>
649
650 * sparc.h (F3F4): New macro.
651
a06ea964 6522012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 653 Laurent Desnogues <laurent.desnogues@arm.com>
654 Jim MacArthur <jim.macarthur@arm.com>
655 Marcus Shawcroft <marcus.shawcroft@arm.com>
656 Nigel Stephens <nigel.stephens@arm.com>
657 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
658 Richard Earnshaw <rearnsha@arm.com>
659 Sofiane Naci <sofiane.naci@arm.com>
660 Tejas Belagod <tejas.belagod@arm.com>
661 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 662
663 * aarch64.h: New file.
664
35d0a169 6652012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 666 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 667
668 * mips.h (mips_opcode): Add the exclusions field.
669 (OPCODE_IS_MEMBER): Remove macro.
670 (cpu_is_member): New inline function.
671 (opcode_is_member): Likewise.
672
03f66e8a 6732012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 674 Catherine Moore <clm@codesourcery.com>
675 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 676
677 * mips.h: Document microMIPS DSP ASE usage.
678 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
679 microMIPS DSP ASE support.
680 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
681 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
682 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
683 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
684 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
685 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
686 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
687
9d7b4c23
MR		 6882012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
689
690 * mips.h: Fix a typo in description.
691
76e879f8
NC		 6922012-06-07 Georg-Johann Lay <avr@gjlay.de>
693
694 * avr.h: (AVR_ISA_XCH): New define.
695 (AVR_ISA_XMEGA): Use it.
696 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
697
6927f982
NC		 6982012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
699
700 * m68hc11.h: Add XGate definitions.
701 (struct m68hc11_opcode): Add xg_mask field.
702
b9c361e0
JL		 7032012-05-14 Catherine Moore <clm@codesourcery.com>
704 Maciej W. Rozycki <macro@codesourcery.com>
705 Rhonda Wittels <rhonda@codesourcery.com>
706
6927f982 707 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 708 (PPC_OP_SA): New macro.
709 (PPC_OP_SE_VLE): New macro.
710 (PPC_OP): Use a variable shift amount.
711 (powerpc_operand): Update comments.
712 (PPC_OPSHIFT_INV): New macro.
713 (PPC_OPERAND_CR): Replace with...
714 (PPC_OPERAND_CR_BIT): ...this and
715 (PPC_OPERAND_CR_REG): ...this.
716
717
f6c1a2d5
NC		 7182012-05-03 Sean Keys <skeys@ipdatasys.com>
719
720 * xgate.h: Header file for XGATE assembler.
721
ec668d69
DM		 7222012-04-27 David S. Miller <davem@davemloft.net>
723
6cda1326
DM		 724 * sparc.h: Document new arg code' )' for crypto RS3
725 immediates.
726
ec668d69
DM		 727 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
728 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
729 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
730 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
731 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
732 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
733 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
734 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
735 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
736 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
737 HWCAP_CBCOND, HWCAP_CRC32): New defines.
738
aea77599
AM		 7392012-03-10 Edmar Wienskoski <edmar@freescale.com>
740
741 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
742
1f42f8b3
AM		 7432012-02-27 Alan Modra <amodra@gmail.com>
744
745 * crx.h (cst4_map): Update declaration.
746
6f7be959
WL		 7472012-02-25 Walter Lee <walt@tilera.com>
748
749 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
750 TILEGX_OPC_LD_TLS.
751 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
752 TILEPRO_OPC_LW_TLS_SN.
753
42164a71
L		 7542012-02-08 H.J. Lu <hongjiu.lu@intel.com>
755
756 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
757 (XRELEASE_PREFIX_OPCODE): Likewise.
758
432233b3 7592011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 760 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 761
762 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
763 (INSN_OCTEON2): New macro.
764 (CPU_OCTEON2): New macro.
765 (OPCODE_IS_MEMBER): Add Octeon2.
766
dd6a37e7
AP		 7672011-11-29 Andrew Pinski <apinski@cavium.com>
768
769 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
770 (INSN_OCTEONP): New macro.
771 (CPU_OCTEONP): New macro.
772 (OPCODE_IS_MEMBER): Add Octeon+.
773 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
774
99c513f6
DD		 7752011-11-01 DJ Delorie <dj@redhat.com>
776
777 * rl78.h: New file.
778
26f85d7a
MR		 7792011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
780
781 * mips.h: Fix a typo in description.
782
9e8c70f9
DM		 7832011-09-21 David S. Miller <davem@davemloft.net>
784
785 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
786 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
787 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
788 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
789
dec0624d 7902011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 791 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 792
793 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
794 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
795 (INSN_ASE_MASK): Add the MCU bit.
796 (INSN_MCU): New macro.
797 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
798 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
799
2b0c8b40
MR		 8002011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
801
802 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
803 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
804 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
805 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
806 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
807 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
808 (INSN2_READ_GPR_MMN): Likewise.
809 (INSN2_READ_FPR_D): Change the bit used.
810 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
811 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
812 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
813 (INSN2_COND_BRANCH): Likewise.
814 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
815 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
816 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
817 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
818 (INSN2_MOD_GPR_MN): Likewise.
819
ea783ef3
DM		 8202011-08-05 David S. Miller <davem@davemloft.net>
821
822 * sparc.h: Document new format codes '4', '5', and '('.
823 (OPF_LOW4, RS3): New macros.
824
7c176fa8
MR		 8252011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
826
827 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
828 order of flags documented.
829
2309ddf2
MR		 8302011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
831
832 * mips.h: Clarify the description of microMIPS instruction
833 manipulation macros.
834 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
835
df58fc94 8362011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 837 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 838
839 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
840 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
841 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
842 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
843 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
844 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
845 (OP_MASK_RS3, OP_SH_RS3): Likewise.
846 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
847 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
848 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
849 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
850 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
851 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
852 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
853 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
854 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
855 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
856 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
857 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
858 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
859 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
860 (INSN_WRITE_GPR_S): New macro.
861 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
862 (INSN2_READ_FPR_D): Likewise.
863 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
864 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
865 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
866 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
867 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
868 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
869 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
870 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
871 (CPU_MICROMIPS): New macro.
872 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
873 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
874 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
875 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
876 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
877 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
878 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
879 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
880 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
881 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
882 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
883 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
884 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
885 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
886 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
887 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
888 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
889 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
890 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
891 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
892 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
893 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
894 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
895 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
896 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
897 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
898 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
899 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
900 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
901 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
902 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
903 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
904 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
905 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
906 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
907 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
908 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
909 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
910 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
911 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
912 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
913 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
914 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
915 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
916 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
917 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
918 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
919 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
920 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
921 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
922 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
923 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
924 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
925 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
926 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
927 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
928 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
929 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
930 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
931 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
932 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
933 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
934 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
935 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
936 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
937 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
938 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
939 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
940 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
941 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
942 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
943 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
944 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
945 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
946 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
947 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
948 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
949 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
950 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
951 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
952 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
953 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
954 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
955 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
956 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
957 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
958 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
959 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
960 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
961 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
962 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
963 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
964 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
965 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
966 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
967 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
968 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
969 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
970 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
971 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
972 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
973 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
974 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
975 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
976 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
977 (micromips_opcodes): New declaration.
978 (bfd_micromips_num_opcodes): Likewise.
979
bcd530a7
RS		 9802011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
981
982 * mips.h (INSN_TRAP): Rename to...
983 (INSN_NO_DELAY_SLOT): ... this.
984 (INSN_SYNC): Remove macro.
985
2dad5a91
EW		 9862011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
987
988 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
989 a duplicate of AVR_ISA_SPM.
990
5d73b1f1
NC		 9912011-07-01 Nick Clifton <nickc@redhat.com>
992
993 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
994
ef26d60e
MF		 9952011-06-18 Robin Getz <robin.getz@analog.com>
996
997 * bfin.h (is_macmod_signed): New func
998
8fb8dca7
MF		 9992011-06-18 Mike Frysinger <vapier@gentoo.org>
1000
1001 * bfin.h (is_macmod_pmove): Add missing space before func args.
1002 (is_macmod_hmove): Likewise.
1003
aa137e4d
NC		 10042011-06-13 Walter Lee <walt@tilera.com>
1005
1006 * tilegx.h: New file.
1007 * tilepro.h: New file.
1008
3b2f0793
PB		 10092011-05-31 Paul Brook <paul@codesourcery.com>
1010
aa137e4d
NC		 1011 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1012
10132011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1014
1015 * s390.h: Replace S390_OPERAND_REG_EVEN with
1016 S390_OPERAND_REG_PAIR.
1017
10182011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1019
1020 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1021
ac7f631b
NC		 10222011-04-18 Julian Brown <julian@codesourcery.com>
1023
1024 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1025
84701018
NC		 10262011-04-11 Dan McDonald <dan@wellkeeper.com>
1027
1028 PR gas/12296
1029 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1030
8cc66334
EW		 10312011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1032
1033 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1034 New instruction set flags.
1035 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1036
3eebd5eb
MR		 10372011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1038
1039 * mips.h (M_PREF_AB): New enum value.
1040
26bb3ddd
MF		 10412011-02-12 Mike Frysinger <vapier@gentoo.org>
1042
89c0d58c
MR		 1043 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1044 M_IU): Define.
1045 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1046
dd76fcb8
MF		 10472011-02-11 Mike Frysinger <vapier@gentoo.org>
1048
1049 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1050
98d23bef
BS		 10512011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1052
1053 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1054 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1055
3c853d93
DA		 10562010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1057
1058 PR gas/11395
1059 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1060 "bb" entries.
1061
79676006
DA		 10622010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1063
1064 PR gas/11395
1065 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1066
1bec78e9
RS		 10672010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1068
1069 * mips.h: Update commentary after last commit.
1070
98675402
RS		 10712010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1072
1073 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1074 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1075 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1076
aa137e4d
NC		 10772010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1078
1079 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1080
435b94a4
RS		 10812010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1082
1083 * mips.h: Fix previous commit.
1084
d051516a
NC		 10852010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1086
1087 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1088 (INSN_LOONGSON_3A): Clear bit 31.
1089
251665fc
MGD		 10902010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1091
1092 PR gas/12198
1093 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1094 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1095 (ARM_ARCH_V6M_ONLY): New define.
1096
fd503541
NC		 10972010-11-11 Mingming Sun <mingm.sun@gmail.com>
1098
1099 * mips.h (INSN_LOONGSON_3A): Defined.
1100 (CPU_LOONGSON_3A): Defined.
1101 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1102
4469d2be
AM		 11032010-10-09 Matt Rice <ratmice@gmail.com>
1104
1105 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1106 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1107
90ec0d68
MGD		 11082010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1109
1110 * arm.h (ARM_EXT_VIRT): New define.
1111 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1112 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1113 Extensions.
1114
eea54501 11152010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1116
eea54501
MGD		 1117 * arm.h (ARM_AEXT_ADIV): New define.
1118 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1119
b2a5fbdc
MGD		 11202010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1121
1122 * arm.h (ARM_EXT_OS): New define.
1123 (ARM_AEXT_V6SM): Likewise.
1124 (ARM_ARCH_V6SM): Likewise.
1125
60e5ef9f
MGD		 11262010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1127
1128 * arm.h (ARM_EXT_MP): Add.
1129 (ARM_ARCH_V7A_MP): Likewise.
1130
73a63ccf
MF		 11312010-09-22 Mike Frysinger <vapier@gentoo.org>
1132
1133 * bfin.h: Declare pseudoChr structs/defines.
1134
ee99860a
MF		 11352010-09-21 Mike Frysinger <vapier@gentoo.org>
1136
1137 * bfin.h: Strip trailing whitespace.
1138
f9c7014e
DD		 11392010-07-29 DJ Delorie <dj@redhat.com>
1140
1141 * rx.h (RX_Operand_Type): Add TwoReg.
1142 (RX_Opcode_ID): Remove ediv and ediv2.
1143
93378652
DD		 11442010-07-27 DJ Delorie <dj@redhat.com>
1145
1146 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1147
1cd986c5
NC		 11482010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1149 Ina Pandit <ina.pandit@kpitcummins.com>
1150
1151 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1152 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1153 PROCESSOR_V850E2_ALL.
1154 Remove PROCESSOR_V850EA support.
1155 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1156 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1157 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1158 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1159 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1160 V850_OPERAND_PERCENT.
1161 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1162 V850_NOT_R0.
1163 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1164 and V850E_PUSH_POP
1165
9a2c7088
MR		 11662010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1167
1168 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1169 (MIPS16_INSN_BRANCH): Rename to...
1170 (MIPS16_INSN_COND_BRANCH): ... this.
1171
bdc70b4a
AM		 11722010-07-03 Alan Modra <amodra@gmail.com>
1173
1174 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1175 Renumber other PPC_OPCODE defines.
1176
f2bae120
AM		 11772010-07-03 Alan Modra <amodra@gmail.com>
1178
1179 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1180
360cfc9c
AM		 11812010-06-29 Alan Modra <amodra@gmail.com>
1182
1183 * maxq.h: Delete file.
1184
e01d869a
AM		 11852010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1186
1187 * ppc.h (PPC_OPCODE_E500): Define.
1188
f79e2745
CM		 11892010-05-26 Catherine Moore <clm@codesourcery.com>
1190
1191 * opcode/mips.h (INSN_MIPS16): Remove.
1192
2462afa1
JM		 11932010-04-21 Joseph Myers <joseph@codesourcery.com>
1194
1195 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1196
e4e42b45
NC		 11972010-04-15 Nick Clifton <nickc@redhat.com>
1198
1199 * alpha.h: Update copyright notice to use GPLv3.
1200 * arc.h: Likewise.
1201 * arm.h: Likewise.
1202 * avr.h: Likewise.
1203 * bfin.h: Likewise.
1204 * cgen.h: Likewise.
1205 * convex.h: Likewise.
1206 * cr16.h: Likewise.
1207 * cris.h: Likewise.
1208 * crx.h: Likewise.
1209 * d10v.h: Likewise.
1210 * d30v.h: Likewise.
1211 * dlx.h: Likewise.
1212 * h8300.h: Likewise.
1213 * hppa.h: Likewise.
1214 * i370.h: Likewise.
1215 * i386.h: Likewise.
1216 * i860.h: Likewise.
1217 * i960.h: Likewise.
1218 * ia64.h: Likewise.
1219 * m68hc11.h: Likewise.
1220 * m68k.h: Likewise.
1221 * m88k.h: Likewise.
1222 * maxq.h: Likewise.
1223 * mips.h: Likewise.
1224 * mmix.h: Likewise.
1225 * mn10200.h: Likewise.
1226 * mn10300.h: Likewise.
1227 * msp430.h: Likewise.
1228 * np1.h: Likewise.
1229 * ns32k.h: Likewise.
1230 * or32.h: Likewise.
1231 * pdp11.h: Likewise.
1232 * pj.h: Likewise.
1233 * pn.h: Likewise.
1234 * ppc.h: Likewise.
1235 * pyr.h: Likewise.
1236 * rx.h: Likewise.
1237 * s390.h: Likewise.
1238 * score-datadep.h: Likewise.
1239 * score-inst.h: Likewise.
1240 * sparc.h: Likewise.
1241 * spu-insns.h: Likewise.
1242 * spu.h: Likewise.
1243 * tic30.h: Likewise.
1244 * tic4x.h: Likewise.
1245 * tic54x.h: Likewise.
1246 * tic80.h: Likewise.
1247 * v850.h: Likewise.
1248 * vax.h: Likewise.
1249
40b36596
JM		 12502010-03-25 Joseph Myers <joseph@codesourcery.com>
1251
1252 * tic6x-control-registers.h, tic6x-insn-formats.h,
1253 tic6x-opcode-table.h, tic6x.h: New.
1254
c67a084a
NC		 12552010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1256
1257 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1258
466ef64f
AM		 12592010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1260
1261 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1262
1319d143
L		 12632010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1264
1265 * ia64.h (ia64_find_opcode): Remove argument name.
1266 (ia64_find_next_opcode): Likewise.
1267 (ia64_dis_opcode): Likewise.
1268 (ia64_free_opcode): Likewise.
1269 (ia64_find_dependency): Likewise.
1270
1fbb9298
DE		 12712009-11-22 Doug Evans <dje@sebabeach.org>
1272
1273 * cgen.h: Include bfd_stdint.h.
1274 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1275
ada65aa3
PB		 12762009-11-18 Paul Brook <paul@codesourcery.com>
1277
1278 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1279
9e3c6df6
PB		 12802009-11-17 Paul Brook <paul@codesourcery.com>
1281 Daniel Jacobowitz <dan@codesourcery.com>
1282
1283 * arm.h (ARM_EXT_V6_DSP): Define.
1284 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1285 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1286
0d734b5d
DD		 12872009-11-04 DJ Delorie <dj@redhat.com>
1288
1289 * rx.h (rx_decode_opcode) (mvtipl): Add.
1290 (mvtcp, mvfcp, opecp): Remove.
1291
62f3b8c8
PB		 12922009-11-02 Paul Brook <paul@codesourcery.com>
1293
1294 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1295 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1296 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1297 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1298 FPU_ARCH_NEON_VFP_V4): Define.
1299
ac1e9eca
DE		 13002009-10-23 Doug Evans <dje@sebabeach.org>
1301
1302 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1303 * cgen.h: Update. Improve multi-inclusion macro name.
1304
9fe54b1c
PB		 13052009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1306
1307 * ppc.h (PPC_OPCODE_476): Define.
1308
634b50f2
PB		 13092009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1310
1311 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1312
c7927a3c
NC		 13132009-09-29 DJ Delorie <dj@redhat.com>
1314
1315 * rx.h: New file.
1316
b961e85b
AM		 13172009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1318
1319 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1320
e0d602ec
BE		 13212009-09-21 Ben Elliston <bje@au.ibm.com>
1322
1323 * ppc.h (PPC_OPCODE_PPCA2): New.
1324
96d56e9f
NC		 13252009-09-05 Martin Thuresson <martin@mtme.org>
1326
1327 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1328
d3ce72d0
NC		 13292009-08-29 Martin Thuresson <martin@mtme.org>
1330
1331 * tic30.h (template): Rename type template to
1332 insn_template. Updated code to use new name.
1333 * tic54x.h (template): Rename type template to
1334 insn_template.
1335
824b28db
NH		 13362009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1337
1338 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1339
f865a31d
AG		 13402009-06-11 Anthony Green <green@moxielogic.com>
1341
1342 * moxie.h (MOXIE_F3_PCREL): Define.
1343 (moxie_form3_opc_info): Grow.
1344
0e7c7f11
AG		 13452009-06-06 Anthony Green <green@moxielogic.com>
1346
1347 * moxie.h (MOXIE_F1_M): Define.
1348
20135e4c
NC		 13492009-04-15 Anthony Green <green@moxielogic.com>
1350
1351 * moxie.h: Created.
1352
bcb012d3
DD		 13532009-04-06 DJ Delorie <dj@redhat.com>
1354
1355 * h8300.h: Add relaxation attributes to MOVA opcodes.
1356
69fe9ce5
AM		 13572009-03-10 Alan Modra <amodra@bigpond.net.au>
1358
1359 * ppc.h (ppc_parse_cpu): Declare.
1360
c3b7224a
NC		 13612009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1362
1363 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1364 and _IMM11 for mbitclr and mbitset.
1365 * score-datadep.h: Update dependency information.
1366
066be9f7
PB		 13672009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1368
1369 * ppc.h (PPC_OPCODE_POWER7): New.
1370
fedc618e
DE		 13712009-02-06 Doug Evans <dje@google.com>
1372
1373 * i386.h: Add comment regarding sse* insns and prefixes.
1374
52b6b6b9
JM		 13752009-02-03 Sandip Matte <sandip@rmicorp.com>
1376
1377 * mips.h (INSN_XLR): Define.
1378 (INSN_CHIP_MASK): Update.
1379 (CPU_XLR): Define.
1380 (OPCODE_IS_MEMBER): Update.
1381 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1382
35669430
DE		 13832009-01-28 Doug Evans <dje@google.com>
1384
1385 * opcode/i386.h: Add multiple inclusion protection.
1386 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1387 (EDI_REG_NUM): New macros.
1388 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1389 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1390 (REX_PREFIX_P): New macro.
35669430 1391
1cb0a767
PB		 13922009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1393
1394 * ppc.h (struct powerpc_opcode): New field "deprecated".
1395 (PPC_OPCODE_NOPOWER4): Delete.
1396
3aa3176b
TS		 13972008-11-28 Joshua Kinard <kumba@gentoo.org>
1398
1399 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1400 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1401
8e79c3df
CM		 14022008-11-18 Catherine Moore <clm@codesourcery.com>
1403
1404 * arm.h (FPU_NEON_FP16): New.
1405 (FPU_ARCH_NEON_FP16): New.
1406
de9a3e51
CF		 14072008-11-06 Chao-ying Fu <fu@mips.com>
1408
1409 * mips.h: Doucument '1' for 5-bit sync type.
1410
1ca35711
L		 14112008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1412
1413 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1414 IA64_RS_CR.
1415
9b4e5766
PB		 14162008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1417
1418 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1419
081ba1b3
AM		 14202008-07-30 Michael J. Eager <eager@eagercon.com>
1421
1422 * ppc.h (PPC_OPCODE_405): Define.
1423 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1424
fa452fa6
PB		 14252008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1426
1427 * ppc.h (ppc_cpu_t): New typedef.
1428 (struct powerpc_opcode <flags>): Use it.
1429 (struct powerpc_operand <insert, extract>): Likewise.
1430 (struct powerpc_macro <flags>): Likewise.
1431
bb35fb24
NC		 14322008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1433
1434 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1435 Update comment before MIPS16 field descriptors to mention MIPS16.
1436 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1437 BBIT.
1438 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1439 New bit masks and shift counts for cins and exts.
1440
dd3cbb7e
NC		 1441 * mips.h: Document new field descriptors +Q.
1442 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1443
d0799671
AN		 14442008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1445
9aff4b7a 1446 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1447 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1448
19a6653c
AM		 14492008-04-14 Edmar Wienskoski <edmar@freescale.com>
1450
1451 * ppc.h: (PPC_OPCODE_E500MC): New.
1452
c0f3af97
L		 14532008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1454
1455 * i386.h (MAX_OPERANDS): Set to 5.
1456 (MAX_MNEM_SIZE): Changed to 20.
1457
e210c36b
NC		 14582008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1459
1460 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1461
b1cc4aeb
PB		 14622008-03-09 Paul Brook <paul@codesourcery.com>
1463
1464 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1465
7e806470
PB		 14662008-03-04 Paul Brook <paul@codesourcery.com>
1467
1468 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1469 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1470 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1471
7b2185f9 14722008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1473 Nick Clifton <nickc@redhat.com>
1474
1475 PR 3134
1476 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1477 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1478 set.
af7329f0 1479
796d5313
NC		 14802008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1481
1482 * cr16.h (cr16_num_optab): Declared.
1483
d669d37f
NC		 14842008-02-14 Hakan Ardo <hakan@debian.org>
1485
1486 PR gas/2626
1487 * avr.h (AVR_ISA_2xxe): Define.
1488
e6429699
AN		 14892008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1490
1491 * mips.h: Update copyright.
1492 (INSN_CHIP_MASK): New macro.
1493 (INSN_OCTEON): New macro.
1494 (CPU_OCTEON): New macro.
1495 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1496
e210c36b
NC		 14972008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1498
1499 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1500
15012008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1502
1503 * avr.h (AVR_ISA_USB162): Add new opcode set.
1504 (AVR_ISA_AVR3): Likewise.
1505
350cc38d
MS		 15062007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1507
1508 * mips.h (INSN_LOONGSON_2E): New.
1509 (INSN_LOONGSON_2F): New.
1510 (CPU_LOONGSON_2E): New.
1511 (CPU_LOONGSON_2F): New.
1512 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1513
56950294
MS		 15142007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1515
1516 * mips.h (INSN_ISA*): Redefine certain values as an
1517 enumeration. Update comments.
1518 (mips_isa_table): New.
1519 (ISA_MIPS*): Redefine to match enumeration.
1520 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1521 values.
1522
c3d65c1c
BE		 15232007-08-08 Ben Elliston <bje@au.ibm.com>
1524
1525 * ppc.h (PPC_OPCODE_PPCPS): New.
1526
0fdaa005
L		 15272007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1528
1529 * m68k.h: Document j K & E.
1530
15312007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1532
1533 * cr16.h: New file for CR16 target.
1534
3896c469
AM		 15352007-05-02 Alan Modra <amodra@bigpond.net.au>
1536
1537 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1538
9a2e615a
NS		 15392007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1540
1541 * m68k.h (mcfisa_c): New.
1542 (mcfusp, mcf_mask): Adjust.
1543
b84bf58a
AM		 15442007-04-20 Alan Modra <amodra@bigpond.net.au>
1545
1546 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1547 (num_powerpc_operands): Declare.
1548 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1549 (PPC_OPERAND_PLUS1): Define.
1550
831480e9 15512007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1552
1553 * i386.h (REX_MODE64): Renamed to ...
1554 (REX_W): This.
1555 (REX_EXTX): Renamed to ...
1556 (REX_R): This.
1557 (REX_EXTY): Renamed to ...
1558 (REX_X): This.
1559 (REX_EXTZ): Renamed to ...
1560 (REX_B): This.
1561
0b1cf022
L		 15622007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1563
1564 * i386.h: Add entries from config/tc-i386.h and move tables
1565 to opcodes/i386-opc.h.
1566
d796c0ad
L		 15672007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1568
1569 * i386.h (FloatDR): Removed.
1570 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1571
30ac7323
AM		 15722007-03-01 Alan Modra <amodra@bigpond.net.au>
1573
1574 * spu-insns.h: Add soma double-float insns.
1575
8b082fb1 15762007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1577 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1578
1579 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1580 (INSN_DSPR2): Add flag for DSP R2 instructions.
1581 (M_BALIGN): New macro.
1582
4eed87de
AM		 15832007-02-14 Alan Modra <amodra@bigpond.net.au>
1584
1585 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1586 and Seg3ShortFrom with Shortform.
1587
fda592e8
L		 15882007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1589
1590 PR gas/4027
1591 * i386.h (i386_optab): Put the real "test" before the pseudo
1592 one.
1593
3bdcfdf4
KH		 15942007-01-08 Kazu Hirata <kazu@codesourcery.com>
1595
1596 * m68k.h (m68010up): OR fido_a.
1597
9840d27e
KH		 15982006-12-25 Kazu Hirata <kazu@codesourcery.com>
1599
1600 * m68k.h (fido_a): New.
1601
c629cdac
KH		 16022006-12-24 Kazu Hirata <kazu@codesourcery.com>
1603
1604 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1605 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1606 values.
1607
b7d9ef37
L		 16082006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1609
1610 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1611
b138abaa
NC		 16122006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1613
1614 * score-inst.h (enum score_insn_type): Add Insn_internal.
1615
e9f53129
AM		 16162006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1617 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1618 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1619 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1620 Alan Modra <amodra@bigpond.net.au>
1621
1622 * spu-insns.h: New file.
1623 * spu.h: New file.
1624
ede602d7
AM		 16252006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1626
1627 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1628
7918206c
MM		 16292006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1630
e4e42b45 1631 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1632 in amdfam10 architecture.
1633
ef05d495
L		 16342006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1635
1636 * i386.h: Replace CpuMNI with CpuSSSE3.
1637
2d447fca 16382006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1639 Joseph Myers <joseph@codesourcery.com>
1640 Ian Lance Taylor <ian@wasabisystems.com>
1641 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1642
1643 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1644
1c0d3aa6
NC		 16452006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1646
1647 * score-datadep.h: New file.
1648 * score-inst.h: New file.
1649
c2f0420e
L		 16502006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1651
1652 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1653 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1654 movdq2q and movq2dq.
1655
050dfa73
MM		 16562006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1657 Michael Meissner <michael.meissner@amd.com>
1658
1659 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1660
15965411
L		 16612006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1662
1663 * i386.h (i386_optab): Add "nop" with memory reference.
1664
46e883c5
L		 16652006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1666
1667 * i386.h (i386_optab): Update comment for 64bit NOP.
1668
9622b051
AM		 16692006-06-06 Ben Elliston <bje@au.ibm.com>
1670 Anton Blanchard <anton@samba.org>
1671
1672 * ppc.h (PPC_OPCODE_POWER6): Define.
1673 Adjust whitespace.
1674
a9e24354
TS		 16752006-06-05 Thiemo Seufer <ths@mips.com>
1676
e4e42b45 1677 * mips.h: Improve description of MT flags.
a9e24354 1678
a596001e
RS		 16792006-05-25 Richard Sandiford <richard@codesourcery.com>
1680
1681 * m68k.h (mcf_mask): Define.
1682
d43b4baf 16832006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1684 David Ung <davidu@mips.com>
d43b4baf
TS		 1685
1686 * mips.h (enum): Add macro M_CACHE_AB.
1687
39a7806d 16882006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1689 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1690 David Ung <davidu@mips.com>
1691
1692 * mips.h: Add INSN_SMARTMIPS define.
1693
9bcd4f99 16942006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1695 David Ung <davidu@mips.com>
9bcd4f99
TS		 1696
1697 * mips.h: Defines udi bits and masks. Add description of
1698 characters which may appear in the args field of udi
1699 instructions.
1700
ef0ee844
TS		 17012006-04-26 Thiemo Seufer <ths@networkno.de>
1702
1703 * mips.h: Improve comments describing the bitfield instruction
1704 fields.
1705
f7675147
L		 17062006-04-26 Julian Brown <julian@codesourcery.com>
1707
1708 * arm.h (FPU_VFP_EXT_V3): Define constant.
1709 (FPU_NEON_EXT_V1): Likewise.
1710 (FPU_VFP_HARD): Update.
1711 (FPU_VFP_V3): Define macro.
1712 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1713
ef0ee844 17142006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1715
1716 * avr.h (AVR_ISA_PWMx): New.
1717
2da12c60
NS		 17182006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1719
1720 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1721 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1722 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1723 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1724 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1725
0715c387
PB		 17262006-03-10 Paul Brook <paul@codesourcery.com>
1727
1728 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1729
34bdd094
DA		 17302006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1731
1732 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1733 first. Correct mask of bb "B" opcode.
1734
331d2d0d
L		 17352006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1736
1737 * i386.h (i386_optab): Support Intel Merom New Instructions.
1738
62b3e311
PB		 17392006-02-24 Paul Brook <paul@codesourcery.com>
1740
1741 * arm.h: Add V7 feature bits.
1742
59cf82fe
L		 17432006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1744
1745 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1746
e74cfd16
PB		 17472006-01-31 Paul Brook <paul@codesourcery.com>
1748 Richard Earnshaw <rearnsha@arm.com>
1749
1750 * arm.h: Use ARM_CPU_FEATURE.
1751 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1752 (arm_feature_set): Change to a structure.
1753 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1754 ARM_FEATURE): New macros.
1755
5b3f8a92
HPN		 17562005-12-07 Hans-Peter Nilsson <hp@axis.com>
1757
1758 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1759 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1760 (ADD_PC_INCR_OPCODE): Don't define.
1761
cb712a9e
L		 17622005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1763
1764 PR gas/1874
1765 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1766
0499d65b
TS		 17672005-11-14 David Ung <davidu@mips.com>
1768
1769 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1770 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1771 save/restore encoding of the args field.
1772
ea5ca089
DB		 17732005-10-28 Dave Brolley <brolley@redhat.com>
1774
1775 Contribute the following changes:
1776 2005-02-16 Dave Brolley <brolley@redhat.com>
1777
1778 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1779 cgen_isa_mask_* to cgen_bitset_*.
1780 * cgen.h: Likewise.
1781
16175d96
DB		 1782 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1783
1784 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1785 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1786 (CGEN_CPU_TABLE): Make isas a ponter.
1787
1788 2003-09-29 Dave Brolley <brolley@redhat.com>
1789
1790 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1791 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1792 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1793
1794 2002-12-13 Dave Brolley <brolley@redhat.com>
1795
1796 * cgen.h (symcat.h): #include it.
1797 (cgen-bitset.h): #include it.
1798 (CGEN_ATTR_VALUE_TYPE): Now a union.
1799 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1800 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1801 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1802 * cgen-bitset.h: New file.
1803
3c9b82ba
NC		 18042005-09-30 Catherine Moore <clm@cm00re.com>
1805
1806 * bfin.h: New file.
1807
6a2375c6
JB		 18082005-10-24 Jan Beulich <jbeulich@novell.com>
1809
1810 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1811 indirect operands.
1812
c06a12f8
DA		 18132005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1814
1815 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1816 Add FLAG_STRICT to pa10 ftest opcode.
1817
4d443107
DA		 18182005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1819
1820 * hppa.h (pa_opcodes): Remove lha entries.
1821
f0a3b40f
DA		 18222005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1823
1824 * hppa.h (FLAG_STRICT): Revise comment.
1825 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1826 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1827 entries for "fdc".
1828
e210c36b
NC		 18292005-09-30 Catherine Moore <clm@cm00re.com>
1830
1831 * bfin.h: New file.
1832
1b7e1362
DA		 18332005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1834
1835 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1836
089b39de
CF		 18372005-09-06 Chao-ying Fu <fu@mips.com>
1838
1839 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1840 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1841 define.
1842 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1843 (INSN_ASE_MASK): Update to include INSN_MT.
1844 (INSN_MT): New define for MT ASE.
1845
93c34b9b
CF		 18462005-08-25 Chao-ying Fu <fu@mips.com>
1847
1848 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1849 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1850 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1851 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1852 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1853 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1854 instructions.
1855 (INSN_DSP): New define for DSP ASE.
1856
848cf006
AM		 18572005-08-18 Alan Modra <amodra@bigpond.net.au>
1858
1859 * a29k.h: Delete.
1860
36ae0db3
DJ		 18612005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1862
1863 * ppc.h (PPC_OPCODE_E300): Define.
1864
8c929562
MS		 18652005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1866
1867 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1868
f7b8cccc
DA		 18692005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1870
1871 PR gas/336
1872 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1873 and pitlb.
1874
8b5328ac
JB		 18752005-07-27 Jan Beulich <jbeulich@novell.com>
1876
1877 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1878 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1879 Add movq-s as 64-bit variants of movd-s.
1880
f417d200
DA		 18812005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1882
18b3bdfc
DA		 1883 * hppa.h: Fix punctuation in comment.
1884
f417d200
DA		 1885 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1886 implicit space-register addressing. Set space-register bits on opcodes
1887 using implicit space-register addressing. Add various missing pa20
1888 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1889 space-register addressing. Use "fE" instead of "fe" in various
1890 fstw opcodes.
1891
9a145ce6
JB		 18922005-07-18 Jan Beulich <jbeulich@novell.com>
1893
1894 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1895
90700ea2
L		 18962007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1897
1898 * i386.h (i386_optab): Support Intel VMX Instructions.
1899
48f130a8
DA		 19002005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1901
1902 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1903
30123838
JB		 19042005-07-05 Jan Beulich <jbeulich@novell.com>
1905
1906 * i386.h (i386_optab): Add new insns.
1907
47b0e7ad
NC		 19082005-07-01 Nick Clifton <nickc@redhat.com>
1909
1910 * sparc.h: Add typedefs to structure declarations.
1911
b300c311
L		 19122005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1913
1914 PR 1013
1915 * i386.h (i386_optab): Update comments for 64bit addressing on
1916 mov. Allow 64bit addressing for mov and movq.
1917
2db495be
DA		 19182005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1919
1920 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1921 respectively, in various floating-point load and store patterns.
1922
caa05036
DA		 19232005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1924
1925 * hppa.h (FLAG_STRICT): Correct comment.
1926 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1927 PA 2.0 mneumonics when equivalent. Entries with cache control
1928 completers now require PA 1.1. Adjust whitespace.
1929
f4411256
AM		 19302005-05-19 Anton Blanchard <anton@samba.org>
1931
1932 * ppc.h (PPC_OPCODE_POWER5): Define.
1933
e172dbf8
NC		 19342005-05-10 Nick Clifton <nickc@redhat.com>
1935
1936 * Update the address and phone number of the FSF organization in
1937 the GPL notices in the following files:
1938 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1939 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1940 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1941 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1942 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1943 tic54x.h, tic80.h, v850.h, vax.h
1944
e44823cf
JB		 19452005-05-09 Jan Beulich <jbeulich@novell.com>
1946
1947 * i386.h (i386_optab): Add ht and hnt.
1948
791fe849
MK		 19492005-04-18 Mark Kettenis <kettenis@gnu.org>
1950
1951 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1952 Add xcrypt-ctr. Provide aliases without hyphens.
1953
faa7ef87
L		 19542005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1955
a63027e5
L		 1956 Moved from ../ChangeLog
1957
faa7ef87
L		 1958 2005-04-12 Paul Brook <paul@codesourcery.com>
1959 * m88k.h: Rename psr macros to avoid conflicts.
1960
1961 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1962 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1963 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1964 and ARM_ARCH_V6ZKT2.
1965
1966 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1967 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1968 Remove redundant instruction types.
1969 (struct argument): X_op - new field.
1970 (struct cst4_entry): Remove.
1971 (no_op_insn): Declare.
1972
1973 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1974 * crx.h (enum argtype): Rename types, remove unused types.
1975
1976 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1977 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1978 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1979 (enum operand_type): Rearrange operands, edit comments.
1980 replace us<N> with ui<N> for unsigned immediate.
1981 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1982 displacements (respectively).
1983 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1984 (instruction type): Add NO_TYPE_INS.
1985 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1986 (operand_entry): New field - 'flags'.
1987 (operand flags): New.
1988
1989 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1990 * crx.h (operand_type): Remove redundant types i3, i4,
1991 i5, i8, i12.
1992 Add new unsigned immediate types us3, us4, us5, us16.
1993
bc4bd9ab
MK		 19942005-04-12 Mark Kettenis <kettenis@gnu.org>
1995
1996 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1997 adjust them accordingly.
1998
373ff435
JB		 19992005-04-01 Jan Beulich <jbeulich@novell.com>
2000
2001 * i386.h (i386_optab): Add rdtscp.
2002
4cc91dba
L		 20032005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2004
2005 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2006 between memory and segment register. Allow movq for moving between
2007 general-purpose register and segment register.
4cc91dba 2008
9ae09ff9
JB		 20092005-02-09 Jan Beulich <jbeulich@novell.com>
2010
2011 PR gas/707
2012 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2013 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2014 fnstsw.
2015
638e7a64
NS		 20162006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2017
2018 * m68k.h (m68008, m68ec030, m68882): Remove.
2019 (m68k_mask): New.
2020 (cpu_m68k, cpu_cf): New.
2021 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2022 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2023
90219bd0
AO		 20242005-01-25 Alexandre Oliva <aoliva@redhat.com>
2025
2026 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2027 * cgen.h (enum cgen_parse_operand_type): Add
2028 CGEN_PARSE_OPERAND_SYMBOLIC.
2029
239cb185
FF		 20302005-01-21 Fred Fish <fnf@specifixinc.com>
2031
2032 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2033 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2034 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2035
dc9a9f39
FF		 20362005-01-19 Fred Fish <fnf@specifixinc.com>
2037
2038 * mips.h (struct mips_opcode): Add new pinfo2 member.
2039 (INSN_ALIAS): New define for opcode table entries that are
2040 specific instances of another entry, such as 'move' for an 'or'
2041 with a zero operand.
2042 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2043 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2044
98e7aba8
ILT		 20452004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2046
2047 * mips.h (CPU_RM9000): Define.
2048 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2049
37edbb65
JB		 20502004-11-25 Jan Beulich <jbeulich@novell.com>
2051
2052 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2053 to/from test registers are illegal in 64-bit mode. Add missing
2054 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2055 (previously one had to explicitly encode a rex64 prefix). Re-enable
2056 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2057 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2058
20592004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2060
2061 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2062 available only with SSE2. Change the MMX additions introduced by SSE
2063 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2064 instructions by their now designated identifier (since combining i686
2065 and 3DNow! does not really imply 3DNow!A).
2066
f5c7edf4
AM		 20672004-11-19 Alan Modra <amodra@bigpond.net.au>
2068
2069 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2070 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2071
7499d566
NC		 20722004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2073 Vineet Sharma <vineets@noida.hcltech.com>
2074
2075 * maxq.h: New file: Disassembly information for the maxq port.
2076
bcb9eebe
L		 20772004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2078
2079 * i386.h (i386_optab): Put back "movzb".
2080
94bb3d38
HPN		 20812004-11-04 Hans-Peter Nilsson <hp@axis.com>
2082
2083 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2084 comments. Remove member cris_ver_sim. Add members
2085 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2086 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2087 (struct cris_support_reg, struct cris_cond15): New types.
2088 (cris_conds15): Declare.
2089 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2090 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2091 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2092 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2093 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2094 SIZE_FIELD_UNSIGNED.
2095
37edbb65 20962004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2097
2098 * i386.h (sldx_Suf): Remove.
2099 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2100 (q_FP): Define, implying no REX64.
2101 (x_FP, sl_FP): Imply FloatMF.
2102 (i386_optab): Split reg and mem forms of moving from segment registers
2103 so that the memory forms can ignore the 16-/32-bit operand size
2104 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2105 all non-floating-point instructions. Unite 32- and 64-bit forms of
2106 movsx, movzx, and movd. Adjust floating point operations for the above
2107 changes to the *FP macros. Add DefaultSize to floating point control
2108 insns operating on larger memory ranges. Remove left over comments
2109 hinting at certain insns being Intel-syntax ones where the ones
2110 actually meant are already gone.
2111
48c9f030
NC		 21122004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2113
2114 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2115 instruction type.
2116
0dd132b6
NC		 21172004-09-30 Paul Brook <paul@codesourcery.com>
2118
2119 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2120 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2121
23794b24
MM		 21222004-09-11 Theodore A. Roth <troth@openavr.org>
2123
2124 * avr.h: Add support for
2125 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2126
2a309db0
AM		 21272004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2128
2129 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2130
b18c562e
NC		 21312004-08-24 Dmitry Diky <diwil@spec.ru>
2132
2133 * msp430.h (msp430_opc): Add new instructions.
2134 (msp430_rcodes): Declare new instructions.
2135 (msp430_hcodes): Likewise..
2136
45d313cd
NC		 21372004-08-13 Nick Clifton <nickc@redhat.com>
2138
2139 PR/301
2140 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2141 processors.
2142
30d1c836
ML		 21432004-08-30 Michal Ludvig <mludvig@suse.cz>
2144
2145 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2146
9a45f1c2
L		 21472004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2148
2149 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2150
543613e9
NC		 21512004-07-21 Jan Beulich <jbeulich@novell.com>
2152
2153 * i386.h: Adjust instruction descriptions to better match the
2154 specification.
2155
b781e558
RE		 21562004-07-16 Richard Earnshaw <rearnsha@arm.com>
2157
2158 * arm.h: Remove all old content. Replace with architecture defines
2159 from gas/config/tc-arm.c.
2160
8577e690
AS		 21612004-07-09 Andreas Schwab <schwab@suse.de>
2162
2163 * m68k.h: Fix comment.
2164
1fe1f39c
NC		 21652004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2166
2167 * crx.h: New file.
2168
1d9f512f
AM		 21692004-06-24 Alan Modra <amodra@bigpond.net.au>
2170
2171 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2172
be8c092b
NC		 21732004-05-24 Peter Barada <peter@the-baradas.com>
2174
2175 * m68k.h: Add 'size' to m68k_opcode.
2176
6b6e92f4
NC		 21772004-05-05 Peter Barada <peter@the-baradas.com>
2178
2179 * m68k.h: Switch from ColdFire chip name to core variant.
2180
21812004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2182
2183 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2184 descriptions for new EMAC cases.
2185 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2186 handle Motorola MAC syntax.
2187 Allow disassembly of ColdFire V4e object files.
2188
fdd12ef3
AM		 21892004-03-16 Alan Modra <amodra@bigpond.net.au>
2190
2191 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2192
3922a64c
L		 21932004-03-12 Jakub Jelinek <jakub@redhat.com>
2194
2195 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2196
1f45d988
ML		 21972004-03-12 Michal Ludvig <mludvig@suse.cz>
2198
2199 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2200
0f10071e
ML		 22012004-03-12 Michal Ludvig <mludvig@suse.cz>
2202
2203 * i386.h (i386_optab): Added xstore/xcrypt insns.
2204
3255318a
NC		 22052004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2206
2207 * h8300.h (32bit ldc/stc): Add relaxing support.
2208
ca9a79a1 22092004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2210
ca9a79a1
NC		 2211 * h8300.h (BITOP): Pass MEMRELAX flag.
2212
875a0b14
NC		 22132004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2214
2215 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2216 except for the H8S.
252b5132 2217
c9e214e5 2218For older changes see ChangeLog-9103
252b5132 2219\f
b90efa5b 2220Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2221
2222Copying and distribution of this file, with or without modification,
2223are permitted in any medium without royalty provided the copyright
2224notice and this notice are preserved.
2225
252b5132 2226Local Variables:
c9e214e5
AM		 2227mode: change-log
2228left-margin: 8
2229fill-column: 74
252b5132
RH		 2230version-control: never
2231End:
GDB Binutils - Deliverables
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