projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
stap-probe: Remove unnecessary cast
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
7bdf96ef
NC		 12015-09-09 Daniel Santos <daniel.santos@pobox.com>
2
3 * visium.h (gen_reg_table): Make static.
4 (fp_reg_table): Likewise.
5 (cc_table): Likewise.
6
f33026a9
MW		 72015-07-20 Matthew Wahab <matthew.wahab@arm.com>
8
9 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
10 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
11 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
12 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
13
ef5a96d5
AM		 142015-07-03 Alan Modra <amodra@gmail.com>
15
16 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
17
c8c8175b
SL		 182015-07-01 Sandra Loosemore <sandra@codesourcery.com>
19 Cesar Philippidis <cesar@codesourcery.com>
20
21 * nios2.h (enum iw_format_type): Add R2 formats.
22 (enum overflow_type): Add signed_immed12_overflow and
23 enumeration_overflow for R2.
24 (struct nios2_opcode): Document new argument letters for R2.
25 (REG_3BIT, REG_LDWM, REG_POP): Define.
26 (includes): Include nios2r2.h.
27 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
28 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
29 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
30 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
31 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
32 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
33 Declare.
34 * nios2r2.h: New file.
35
11a0cf2e
PB		 362015-06-19 Peter Bergner <bergner@vnet.ibm.com>
37
38 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
39 (ppc_optional_operand_value): New inline function.
40
88f0ea34
MW		 412015-06-04 Matthew Wahab <matthew.wahab@arm.com>
42
43 * aarch64.h (AARCH64_V8_1): New.
44
a5932920
MW		 452015-06-03 Matthew Wahab <matthew.wahab@arm.com>
46
47 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
48 (ARM_ARCH_V8_1A): New.
49 (ARM_ARCH_V8_1A_FP): New.
50 (ARM_ARCH_V8_1A_SIMD): New.
51 (ARM_ARCH_V8_1A_CRYPTOV1): New.
52 (ARM_FEATURE_CORE): New.
53
ddfded2f
MW		 542015-06-02 Matthew Wahab <matthew.wahab@arm.com>
55
56 * arm.h (ARM_EXT2_PAN): New.
57 (ARM_FEATURE_CORE_HIGH): New.
58
1af1dd51
MW		 592015-06-02 Matthew Wahab <matthew.wahab@arm.com>
60
61 * arm.h (ARM_FEATURE_ALL): New.
62
9e1f0fa7
MW		 632015-06-02 Matthew Wahab <matthew.wahab@arm.com>
64
65 * aarch64.h (AARCH64_FEATURE_RDMA): New.
66
290806fd
MW		 672015-06-02 Matthew Wahab <matthew.wahab@arm.com>
68
69 * aarch64.h (AARCH64_FEATURE_LOR): New.
70
f21cce2c
MW		 712015-06-01 Matthew Wahab <matthew.wahab@arm.com>
72
73 * aarch64.h (AARCH64_FEATURE_PAN): New.
74 (aarch64_sys_reg_supported_p): Declare.
75 (aarch64_pstatefield_supported_p): Declare.
76
0952813b
DD		 772015-04-30 DJ Delorie <dj@redhat.com>
78
79 * rl78.h (RL78_Dis_Isa): New.
80 (rl78_decode_opcode): Add ISA parameter.
81
823d2571
TG		 822015-03-24 Terry Guo <terry.guo@arm.com>
83
84 * arm.h (arm_feature_set): Extended to provide more available bits.
85 (ARM_ANY): Updated to follow above new definition.
86 (ARM_CPU_HAS_FEATURE): Likewise.
87 (ARM_CPU_IS_ANY): Likewise.
88 (ARM_MERGE_FEATURE_SETS): Likewise.
89 (ARM_CLEAR_FEATURE): Likewise.
90 (ARM_FEATURE): Likewise.
91 (ARM_FEATURE_COPY): New macro.
92 (ARM_FEATURE_EQUAL): Likewise.
93 (ARM_FEATURE_ZERO): Likewise.
94 (ARM_FEATURE_CORE_EQUAL): Likewise.
95 (ARM_FEATURE_LOW): Likewise.
96 (ARM_FEATURE_CORE_LOW): Likewise.
97 (ARM_FEATURE_CORE_COPROC): Likewise.
98
f63c1776
PA		 992015-02-19 Pedro Alves <palves@redhat.com>
100
101 * cgen.h [__cplusplus]: Wrap in extern "C".
102 * msp430-decode.h [__cplusplus]: Likewise.
103 * nios2.h [__cplusplus]: Likewise.
104 * rl78.h [__cplusplus]: Likewise.
105 * rx.h [__cplusplus]: Likewise.
106 * tilegx.h [__cplusplus]: Likewise.
107
3f8107ab
AM		 1082015-01-28 James Bowman <james.bowman@ftdichip.com>
109
110 * ft32.h: New file.
111
1e2e8c52
AK		 1122015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
113
114 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
115
b90efa5b
AM		 1162015-01-01 Alan Modra <amodra@gmail.com>
117
118 Update year range in copyright notice of all files.
119
bffb6004
AG		 1202014-12-27 Anthony Green <green@moxielogic.com>
121
122 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
123 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
124
1945cfa5
EB		 1252014-12-06 Eric Botcazou <ebotcazou@adacore.com>
126
127 * visium.h: New file.
128
d306ce58
SL		 1292014-11-28 Sandra Loosemore <sandra@codesourcery.com>
130
131 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
132 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
133 (NIOS2_INSN_OPTARG): Renumber.
134
b4714c7c
SL		 1352014-11-06 Sandra Loosemore <sandra@codesourcery.com>
136
137 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
138 declaration. Fix obsolete comment.
139
96ba4233
SL		 1402014-10-23 Sandra Loosemore <sandra@codesourcery.com>
141
142 * nios2.h (enum iw_format_type): New.
143 (struct nios2_opcode): Update comments. Add size and format fields.
144 (NIOS2_INSN_OPTARG): New.
145 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
146 (struct nios2_reg): Add regtype field.
147 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
148 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
149 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
150 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
151 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
152 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
153 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
154 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
155 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
156 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
157 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
158 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
159 (OP_MASK_OP, OP_SH_OP): Delete.
160 (OP_MASK_IOP, OP_SH_IOP): Delete.
161 (OP_MASK_IRD, OP_SH_IRD): Delete.
162 (OP_MASK_IRT, OP_SH_IRT): Delete.
163 (OP_MASK_IRS, OP_SH_IRS): Delete.
164 (OP_MASK_ROP, OP_SH_ROP): Delete.
165 (OP_MASK_RRD, OP_SH_RRD): Delete.
166 (OP_MASK_RRT, OP_SH_RRT): Delete.
167 (OP_MASK_RRS, OP_SH_RRS): Delete.
168 (OP_MASK_JOP, OP_SH_JOP): Delete.
169 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
170 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
171 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
172 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
173 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
174 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
175 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
176 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
177 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
178 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
179 (OP_MASK_<insn>, OP_MASK): Delete.
180 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
181 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
182 Include nios2r1.h to define new instruction opcode constants
183 and accessors.
184 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
185 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
186 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
187 (NUMOPCODES, NUMREGISTERS): Delete.
188 * nios2r1.h: New file.
189
0b6be415
JM		 1902014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
191
192 * sparc.h (HWCAP2_VIS3B): Documentation improved.
193
3d68f91c
JM		 1942014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
195
196 * sparc.h (sparc_opcode): new field `hwcaps2'.
197 (HWCAP2_FJATHPLUS): New define.
198 (HWCAP2_VIS3B): Likewise.
199 (HWCAP2_ADP): Likewise.
200 (HWCAP2_SPARC5): Likewise.
201 (HWCAP2_MWAIT): Likewise.
202 (HWCAP2_XMPMUL): Likewise.
203 (HWCAP2_XMONT): Likewise.
204 (HWCAP2_NSEC): Likewise.
205 (HWCAP2_FJATHHPC): Likewise.
206 (HWCAP2_FJDES): Likewise.
207 (HWCAP2_FJAES): Likewise.
208 Document the new operand kind `{', corresponding to the mcdper
209 ancillary state register.
210 Document the new operand kind }, which represents frsd floating
211 point registers (double precision) which must be the same than
212 frs1 in its containing instruction.
213
40c7a7cb
KLC		 2142014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
215
72f4393d 216 * nds32.h: Add new opcode declaration.
40c7a7cb 217
7361da2c
AB		 2182014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
219 Matthew Fortune <matthew.fortune@imgtec.com>
220
221 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
222 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
223 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
224 +I, +O, +R, +:, +\, +", +;
225 (mips_check_prev_operand): New struct.
226 (INSN2_FORBIDDEN_SLOT): New define.
227 (INSN_ISA32R6): New define.
228 (INSN_ISA64R6): New define.
229 (INSN_UPTO32R6): New define.
230 (INSN_UPTO64R6): New define.
231 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
232 (ISA_MIPS32R6): New define.
233 (ISA_MIPS64R6): New define.
234 (CPU_MIPS32R6): New define.
235 (CPU_MIPS64R6): New define.
236 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
237
ee804238
JW		 2382014-09-03 Jiong Wang <jiong.wang@arm.com>
239
240 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
241 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
242 (aarch64_insn_class): Add lse_atomic.
243 (F_LSE_SZ): New field added.
244 (opcode_has_special_coder): Recognize F_LSE_SZ.
245
5575639b
MR		 2462014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
247
248 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
249 over to `+J'.
250
43885403
MF		 2512014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
252
253 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
254 (INSN_LOAD_COPROC): New define.
255 (INSN_COPROC_MOVE_DELAY): Rename to...
256 (INSN_COPROC_MOVE): New define.
257
f36e8886 2582014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 259 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
260 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
261 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 262
263 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
264 (AVR_ISA_2xxxa): Define ISA without LPM.
265 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
266 Add doc for contraint used in 16 bit lds/sts.
267 Adjust ISA group for icall, ijmp, pop and push.
268 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
269
00b32ff2
NC		 2702014-05-19 Nick Clifton <nickc@redhat.com>
271
272 * msp430.h (struct msp430_operand_s): Add vshift field.
273
ae52f483
AB		 2742014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
275
276 * mips.h (INSN_ISA_MASK): Updated.
277 (INSN_ISA32R3): New define.
278 (INSN_ISA32R5): New define.
279 (INSN_ISA64R3): New define.
280 (INSN_ISA64R5): New define.
281 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
282 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
283 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
284 mips64r5.
285 (INSN_UPTO32R3): New define.
286 (INSN_UPTO32R5): New define.
287 (INSN_UPTO64R3): New define.
288 (INSN_UPTO64R5): New define.
289 (ISA_MIPS32R3): New define.
290 (ISA_MIPS32R5): New define.
291 (ISA_MIPS64R3): New define.
292 (ISA_MIPS64R5): New define.
293 (CPU_MIPS32R3): New define.
294 (CPU_MIPS32R5): New define.
295 (CPU_MIPS64R3): New define.
296 (CPU_MIPS64R5): New define.
297
3efe9ec5
RS		 2982014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
299
300 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
301
73589c9d
CS		 3022014-04-22 Christian Svensson <blue@cmd.nu>
303
304 * or32.h: Delete.
305
4b95cf5c
AM		 3062014-03-05 Alan Modra <amodra@gmail.com>
307
308 Update copyright years.
309
e269fea7
AB		 3102013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
311
312 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
313 microMIPS.
314
35c08157
KLC		 3152013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
316 Wei-Cheng Wang <cole945@gmail.com>
317
318 * nds32.h: New file for Andes NDS32.
319
594d8fa8
MF		 3202013-12-07 Mike Frysinger <vapier@gentoo.org>
321
322 * bfin.h: Remove +x file mode.
323
87b8eed7
YZ		 3242013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
325
326 * aarch64.h (aarch64_pstatefields): Change element type to
327 aarch64_sys_reg.
328
c9fb6e58
YZ		 3292013-11-18 Renlin Li <Renlin.Li@arm.com>
330
331 * arm.h (ARM_AEXT_V7VE): New define.
332 (ARM_ARCH_V7VE): New define.
333 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
334
a203d9b7
YZ		 3352013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
336
337 Revert
338
339 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
340
341 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
342 (aarch64_sys_reg_writeonly_p): Ditto.
343
75468c93
YZ		 3442013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
345
346 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
347 (aarch64_sys_reg_writeonly_p): Ditto.
348
49eec193
YZ		 3492013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
350
351 * aarch64.h (aarch64_sys_reg): New typedef.
352 (aarch64_sys_regs): Change to define with the new type.
353 (aarch64_sys_reg_deprecated_p): Declare.
354
68a64283
YZ		 3552013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
356
357 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
358 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
359
387a82f1
CF		 3602013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
361
362 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
363 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
364 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
365 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
366 For MIPS, update extension character sequences after +.
367 (ASE_MSA): New define.
368 (ASE_MSA64): New define.
369 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
370 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
371 For microMIPS, update extension character sequences after +.
372
9aff4b7a
NC		 3732013-08-23 Yuri Chornoivan <yurchor@ukr.net>
374
375 PR binutils/15834
376 * i960.h: Fix typos.
377
e423441d
RS		 3782013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
379
380 * mips.h: Remove references to "+I" and imm2_expr.
381
5e0dc5ba
RS		 3822013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
383
384 * mips.h (M_DEXT, M_DINS): Delete.
385
0f35dbc4
RS		 3862013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
387
388 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
389 (mips_optional_operand_p): New function.
390
14daeee3
RS		 3912013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
392 Richard Sandiford <rdsandiford@googlemail.com>
393
394 * mips.h: Document new VU0 operand characters.
395 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
396 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
397 (OP_REG_R5900_ACC): New mips_reg_operand_types.
398 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
399 (mips_vu0_channel_mask): Declare.
400
3ccad066
RS		 4012013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
402
403 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
404 (mips_int_operand_min, mips_int_operand_max): New functions.
405 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
406
fc76e730
RS		 4072013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
408
409 * mips.h (mips_decode_reg_operand): New function.
410 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
411 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
412 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
413 New macros.
414 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
415 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
416 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
417 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
418 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
419 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
420 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
421 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
422 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
423 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
424 macros to cover the gaps.
425 (INSN2_MOD_SP): Replace with...
426 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
427 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
428 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
429 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
430 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
431 Delete.
432
26545944
RS		 4332013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
434
435 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
436 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
437 (MIPS16_INSN_COND_BRANCH): Delete.
438
7e8b059b
L		 4392013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
440 Kirill Yukhin <kirill.yukhin@intel.com>
441 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
442
443 * i386.h (BND_PREFIX_OPCODE): New.
444
c3c07478
RS		 4452013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
446
447 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
448 OP_SAVE_RESTORE_LIST.
449 (decode_mips16_operand): Declare.
450
ab902481
RS		 4512013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
452
453 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
454 (mips_operand, mips_int_operand, mips_mapped_int_operand)
455 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
456 (mips_pcrel_operand): New structures.
457 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
458 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
459 (decode_mips_operand, decode_micromips_operand): Declare.
460
cc537e56
RS		 4612013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
462
463 * mips.h: Document MIPS16 "I" opcode.
464
f2ae14a1
RS		 4652013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
466
467 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
468 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
469 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
470 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
471 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
472 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
473 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
474 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
475 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
476 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
477 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
478 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
479 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
480 Rename to...
481 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
482 (M_USD_AB): ...these.
483
5c324c16
RS		 4842013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
485
486 * mips.h: Remove documentation of "[" and "]". Update documentation
487 of "k" and the MDMX formats.
488
23e69e47
RS		 4892013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
490
491 * mips.h: Update documentation of "+s" and "+S".
492
27c5c572
RS		 4932013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
494
495 * mips.h: Document "+i".
496
e76ff5ab
RS		 4972013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
498
499 * mips.h: Remove "mi" documentation. Update "mh" documentation.
500 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
501 Delete.
502 (INSN2_WRITE_GPR_MHI): Rename to...
503 (INSN2_WRITE_GPR_MH): ...this.
504
fa7616a4
RS		 5052013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
506
507 * mips.h: Remove documentation of "+D" and "+T".
508
18870af7
RS		 5092013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
510
511 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
512 Use "source" rather than "destination" for microMIPS "G".
513
833794fc
MR		 5142013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
515
516 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
517 values.
518
c3678916
RS		 5192013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
520
521 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
522
7f3c4072
CM		 5232013-06-17 Catherine Moore <clm@codesourcery.com>
524 Maciej W. Rozycki <macro@codesourcery.com>
525 Chao-Ying Fu <fu@mips.com>
526
527 * mips.h (OP_SH_EVAOFFSET): Define.
528 (OP_MASK_EVAOFFSET): Define.
529 (INSN_ASE_MASK): Delete.
530 (ASE_EVA): Define.
531 (M_CACHEE_AB, M_CACHEE_OB): New.
532 (M_LBE_OB, M_LBE_AB): New.
533 (M_LBUE_OB, M_LBUE_AB): New.
534 (M_LHE_OB, M_LHE_AB): New.
535 (M_LHUE_OB, M_LHUE_AB): New.
536 (M_LLE_AB, M_LLE_OB): New.
537 (M_LWE_OB, M_LWE_AB): New.
538 (M_LWLE_AB, M_LWLE_OB): New.
539 (M_LWRE_AB, M_LWRE_OB): New.
540 (M_PREFE_AB, M_PREFE_OB): New.
541 (M_SCE_AB, M_SCE_OB): New.
542 (M_SBE_OB, M_SBE_AB): New.
543 (M_SHE_OB, M_SHE_AB): New.
544 (M_SWE_OB, M_SWE_AB): New.
545 (M_SWLE_AB, M_SWLE_OB): New.
546 (M_SWRE_AB, M_SWRE_OB): New.
547 (MICROMIPSOP_SH_EVAOFFSET): Define.
548 (MICROMIPSOP_MASK_EVAOFFSET): Define.
549
0c8fe7cf
SL		 5502013-06-12 Sandra Loosemore <sandra@codesourcery.com>
551
552 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
553
c77c0862
RS		 5542013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
555
556 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
557
b015e599
AP		 5582013-05-09 Andrew Pinski <apinski@cavium.com>
559
560 * mips.h (OP_MASK_CODE10): Correct definition.
561 (OP_SH_CODE10): Likewise.
562 Add a comment that "+J" is used now for OP_*CODE10.
563 (INSN_ASE_MASK): Update.
564 (INSN_VIRT): New macro.
565 (INSN_VIRT64): New macro
566
13761a11
NC		 5672013-05-02 Nick Clifton <nickc@redhat.com>
568
569 * msp430.h: Add patterns for MSP430X instructions.
570
0afd1215
DM		 5712013-04-06 David S. Miller <davem@davemloft.net>
572
573 * sparc.h (F_PREFERRED): Define.
574 (F_PREF_ALIAS): Define.
575
41702d50
NC		 5762013-04-03 Nick Clifton <nickc@redhat.com>
577
578 * v850.h (V850_INVERSE_PCREL): Define.
579
e21e1a51
NC		 5802013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
581
582 PR binutils/15068
583 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
584
51dcdd4d
NC		 5852013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
586
587 PR binutils/15068
588 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
589 Add 16-bit opcodes.
590 * tic6xc-opcode-table.h: Add 16-bit insns.
591 * tic6x.h: Add support for 16-bit insns.
592
81f5558e
NC		 5932013-03-21 Michael Schewe <michael.schewe@gmx.net>
594
595 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
596 and mov.b/w/l Rs,@(d:32,ERd).
597
165546ad
NC		 5982013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
599
600 PR gas/15082
601 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
602 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
603 tic6x_operand_xregpair operand coding type.
604 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
605 opcode field, usu ORXREGD1324 for the src2 operand and remove the
606 TIC6X_FLAG_NO_CROSS.
607
795b8e6b
NC		 6082013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
609
610 PR gas/15095
611 * tic6x.h (enum tic6x_coding_method): Add
612 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
613 separately the msb and lsb of a register pair. This is needed to
614 encode the opcodes in the same way as TI assembler does.
615 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
616 and rsqrdp opcodes to use the new field coding types.
617
dd5181d5
KT		 6182013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
619
620 * arm.h (CRC_EXT_ARMV8): New constant.
621 (ARCH_CRC_ARMV8): New macro.
622
e60bb1dd
YZ		 6232013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
624
625 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
626
36591ba1 6272013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 628 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 629
630 Based on patches from Altera Corporation.
631
632 * nios2.h: New file.
633
e30181a5
YZ		 6342013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
635
636 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
637
0c9573f4
NC		 6382013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
639
640 PR gas/15069
641 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
642
981dc7f1
NC		 6432013-01-24 Nick Clifton <nickc@redhat.com>
644
645 * v850.h: Add e3v5 support.
646
f5555712
YZ		 6472013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
648
649 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
650
5817ffd1
PB		 6512013-01-10 Peter Bergner <bergner@vnet.ibm.com>
652
653 * ppc.h (PPC_OPCODE_POWER8): New define.
654 (PPC_OPCODE_HTM): Likewise.
655
a3c62988
NC		 6562013-01-10 Will Newton <will.newton@imgtec.com>
657
658 * metag.h: New file.
659
73335eae
NC		 6602013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
661
662 * cr16.h (make_instruction): Rename to cr16_make_instruction.
663 (match_opcode): Rename to cr16_match_opcode.
664
e407c74b
NC		 6652013-01-04 Juergen Urban <JuergenUrban@gmx.de>
666
667 * mips.h: Add support for r5900 instructions including lq and sq.
668
bab4becb
NC		 6692013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
670
671 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
672 (make_instruction,match_opcode): Added function prototypes.
673 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
674
776fc418
AM		 6752012-11-23 Alan Modra <amodra@gmail.com>
676
677 * ppc.h (ppc_parse_cpu): Update prototype.
678
f05682d4
DA		 6792012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
680
681 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
682 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
683
cfc72779
AK		 6842012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
685
686 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
687
b3e14eda
L		 6882012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
689
690 * ia64.h (ia64_opnd): Add new operand types.
691
2c63854f
DM		 6922012-08-21 David S. Miller <davem@davemloft.net>
693
694 * sparc.h (F3F4): New macro.
695
a06ea964 6962012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 697 Laurent Desnogues <laurent.desnogues@arm.com>
698 Jim MacArthur <jim.macarthur@arm.com>
699 Marcus Shawcroft <marcus.shawcroft@arm.com>
700 Nigel Stephens <nigel.stephens@arm.com>
701 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
702 Richard Earnshaw <rearnsha@arm.com>
703 Sofiane Naci <sofiane.naci@arm.com>
704 Tejas Belagod <tejas.belagod@arm.com>
705 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 706
707 * aarch64.h: New file.
708
35d0a169 7092012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 710 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 711
712 * mips.h (mips_opcode): Add the exclusions field.
713 (OPCODE_IS_MEMBER): Remove macro.
714 (cpu_is_member): New inline function.
715 (opcode_is_member): Likewise.
716
03f66e8a 7172012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 718 Catherine Moore <clm@codesourcery.com>
719 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 720
721 * mips.h: Document microMIPS DSP ASE usage.
722 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
723 microMIPS DSP ASE support.
724 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
725 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
726 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
727 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
728 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
729 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
730 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
731
9d7b4c23
MR		 7322012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
733
734 * mips.h: Fix a typo in description.
735
76e879f8
NC		 7362012-06-07 Georg-Johann Lay <avr@gjlay.de>
737
738 * avr.h: (AVR_ISA_XCH): New define.
739 (AVR_ISA_XMEGA): Use it.
740 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
741
6927f982
NC		 7422012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
743
744 * m68hc11.h: Add XGate definitions.
745 (struct m68hc11_opcode): Add xg_mask field.
746
b9c361e0
JL		 7472012-05-14 Catherine Moore <clm@codesourcery.com>
748 Maciej W. Rozycki <macro@codesourcery.com>
749 Rhonda Wittels <rhonda@codesourcery.com>
750
6927f982 751 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 752 (PPC_OP_SA): New macro.
753 (PPC_OP_SE_VLE): New macro.
754 (PPC_OP): Use a variable shift amount.
755 (powerpc_operand): Update comments.
756 (PPC_OPSHIFT_INV): New macro.
757 (PPC_OPERAND_CR): Replace with...
758 (PPC_OPERAND_CR_BIT): ...this and
759 (PPC_OPERAND_CR_REG): ...this.
760
761
f6c1a2d5
NC		 7622012-05-03 Sean Keys <skeys@ipdatasys.com>
763
764 * xgate.h: Header file for XGATE assembler.
765
ec668d69
DM		 7662012-04-27 David S. Miller <davem@davemloft.net>
767
6cda1326
DM		 768 * sparc.h: Document new arg code' )' for crypto RS3
769 immediates.
770
ec668d69
DM		 771 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
772 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
773 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
774 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
775 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
776 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
777 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
778 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
779 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
780 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
781 HWCAP_CBCOND, HWCAP_CRC32): New defines.
782
aea77599
AM		 7832012-03-10 Edmar Wienskoski <edmar@freescale.com>
784
785 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
786
1f42f8b3
AM		 7872012-02-27 Alan Modra <amodra@gmail.com>
788
789 * crx.h (cst4_map): Update declaration.
790
6f7be959
WL		 7912012-02-25 Walter Lee <walt@tilera.com>
792
793 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
794 TILEGX_OPC_LD_TLS.
795 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
796 TILEPRO_OPC_LW_TLS_SN.
797
42164a71
L		 7982012-02-08 H.J. Lu <hongjiu.lu@intel.com>
799
800 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
801 (XRELEASE_PREFIX_OPCODE): Likewise.
802
432233b3 8032011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 804 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 805
806 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
807 (INSN_OCTEON2): New macro.
808 (CPU_OCTEON2): New macro.
809 (OPCODE_IS_MEMBER): Add Octeon2.
810
dd6a37e7
AP		 8112011-11-29 Andrew Pinski <apinski@cavium.com>
812
813 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
814 (INSN_OCTEONP): New macro.
815 (CPU_OCTEONP): New macro.
816 (OPCODE_IS_MEMBER): Add Octeon+.
817 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
818
99c513f6
DD		 8192011-11-01 DJ Delorie <dj@redhat.com>
820
821 * rl78.h: New file.
822
26f85d7a
MR		 8232011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
824
825 * mips.h: Fix a typo in description.
826
9e8c70f9
DM		 8272011-09-21 David S. Miller <davem@davemloft.net>
828
829 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
830 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
831 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
832 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
833
dec0624d 8342011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 835 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 836
837 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
838 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
839 (INSN_ASE_MASK): Add the MCU bit.
840 (INSN_MCU): New macro.
841 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
842 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
843
2b0c8b40
MR		 8442011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
845
846 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
847 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
848 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
849 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
850 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
851 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
852 (INSN2_READ_GPR_MMN): Likewise.
853 (INSN2_READ_FPR_D): Change the bit used.
854 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
855 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
856 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
857 (INSN2_COND_BRANCH): Likewise.
858 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
859 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
860 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
861 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
862 (INSN2_MOD_GPR_MN): Likewise.
863
ea783ef3
DM		 8642011-08-05 David S. Miller <davem@davemloft.net>
865
866 * sparc.h: Document new format codes '4', '5', and '('.
867 (OPF_LOW4, RS3): New macros.
868
7c176fa8
MR		 8692011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
870
871 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
872 order of flags documented.
873
2309ddf2
MR		 8742011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
875
876 * mips.h: Clarify the description of microMIPS instruction
877 manipulation macros.
878 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
879
df58fc94 8802011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 881 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 882
883 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
884 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
885 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
886 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
887 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
888 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
889 (OP_MASK_RS3, OP_SH_RS3): Likewise.
890 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
891 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
892 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
893 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
894 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
895 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
896 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
897 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
898 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
899 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
900 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
901 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
902 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
903 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
904 (INSN_WRITE_GPR_S): New macro.
905 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
906 (INSN2_READ_FPR_D): Likewise.
907 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
908 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
909 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
910 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
911 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
912 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
913 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
914 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
915 (CPU_MICROMIPS): New macro.
916 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
917 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
918 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
919 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
920 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
921 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
922 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
923 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
924 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
925 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
926 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
927 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
928 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
929 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
930 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
931 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
932 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
933 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
934 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
935 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
936 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
937 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
938 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
939 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
940 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
941 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
942 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
943 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
944 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
945 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
946 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
947 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
948 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
949 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
950 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
951 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
952 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
953 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
954 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
955 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
956 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
957 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
958 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
959 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
960 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
961 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
962 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
963 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
964 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
965 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
966 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
967 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
968 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
969 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
970 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
971 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
972 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
973 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
974 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
975 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
976 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
977 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
978 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
979 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
980 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
981 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
982 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
983 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
984 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
985 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
986 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
987 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
988 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
989 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
990 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
991 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
992 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
993 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
994 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
995 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
996 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
997 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
998 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
999 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1000 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1001 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1002 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1003 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1004 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1005 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1006 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1007 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1008 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1009 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1010 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1011 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1012 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1013 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1014 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1015 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1016 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1017 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1018 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1019 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1020 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1021 (micromips_opcodes): New declaration.
1022 (bfd_micromips_num_opcodes): Likewise.
1023
bcd530a7
RS		 10242011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1025
1026 * mips.h (INSN_TRAP): Rename to...
1027 (INSN_NO_DELAY_SLOT): ... this.
1028 (INSN_SYNC): Remove macro.
1029
2dad5a91
EW		 10302011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1031
1032 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1033 a duplicate of AVR_ISA_SPM.
1034
5d73b1f1
NC		 10352011-07-01 Nick Clifton <nickc@redhat.com>
1036
1037 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1038
ef26d60e
MF		 10392011-06-18 Robin Getz <robin.getz@analog.com>
1040
1041 * bfin.h (is_macmod_signed): New func
1042
8fb8dca7
MF		 10432011-06-18 Mike Frysinger <vapier@gentoo.org>
1044
1045 * bfin.h (is_macmod_pmove): Add missing space before func args.
1046 (is_macmod_hmove): Likewise.
1047
aa137e4d
NC		 10482011-06-13 Walter Lee <walt@tilera.com>
1049
1050 * tilegx.h: New file.
1051 * tilepro.h: New file.
1052
3b2f0793
PB		 10532011-05-31 Paul Brook <paul@codesourcery.com>
1054
aa137e4d
NC		 1055 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1056
10572011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1058
1059 * s390.h: Replace S390_OPERAND_REG_EVEN with
1060 S390_OPERAND_REG_PAIR.
1061
10622011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1063
1064 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1065
ac7f631b
NC		 10662011-04-18 Julian Brown <julian@codesourcery.com>
1067
1068 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1069
84701018
NC		 10702011-04-11 Dan McDonald <dan@wellkeeper.com>
1071
1072 PR gas/12296
1073 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1074
8cc66334
EW		 10752011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1076
1077 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1078 New instruction set flags.
1079 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1080
3eebd5eb
MR		 10812011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1082
1083 * mips.h (M_PREF_AB): New enum value.
1084
26bb3ddd
MF		 10852011-02-12 Mike Frysinger <vapier@gentoo.org>
1086
89c0d58c
MR		 1087 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1088 M_IU): Define.
1089 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1090
dd76fcb8
MF		 10912011-02-11 Mike Frysinger <vapier@gentoo.org>
1092
1093 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1094
98d23bef
BS		 10952011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1096
1097 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1098 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1099
3c853d93
DA		 11002010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1101
1102 PR gas/11395
1103 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1104 "bb" entries.
1105
79676006
DA		 11062010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1107
1108 PR gas/11395
1109 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1110
1bec78e9
RS		 11112010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1112
1113 * mips.h: Update commentary after last commit.
1114
98675402
RS		 11152010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1116
1117 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1118 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1119 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1120
aa137e4d
NC		 11212010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1122
1123 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1124
435b94a4
RS		 11252010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1126
1127 * mips.h: Fix previous commit.
1128
d051516a
NC		 11292010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1130
1131 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1132 (INSN_LOONGSON_3A): Clear bit 31.
1133
251665fc
MGD		 11342010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1135
1136 PR gas/12198
1137 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1138 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1139 (ARM_ARCH_V6M_ONLY): New define.
1140
fd503541
NC		 11412010-11-11 Mingming Sun <mingm.sun@gmail.com>
1142
1143 * mips.h (INSN_LOONGSON_3A): Defined.
1144 (CPU_LOONGSON_3A): Defined.
1145 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1146
4469d2be
AM		 11472010-10-09 Matt Rice <ratmice@gmail.com>
1148
1149 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1150 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1151
90ec0d68
MGD		 11522010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1153
1154 * arm.h (ARM_EXT_VIRT): New define.
1155 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1156 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1157 Extensions.
1158
eea54501 11592010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1160
eea54501
MGD		 1161 * arm.h (ARM_AEXT_ADIV): New define.
1162 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1163
b2a5fbdc
MGD		 11642010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1165
1166 * arm.h (ARM_EXT_OS): New define.
1167 (ARM_AEXT_V6SM): Likewise.
1168 (ARM_ARCH_V6SM): Likewise.
1169
60e5ef9f
MGD		 11702010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1171
1172 * arm.h (ARM_EXT_MP): Add.
1173 (ARM_ARCH_V7A_MP): Likewise.
1174
73a63ccf
MF		 11752010-09-22 Mike Frysinger <vapier@gentoo.org>
1176
1177 * bfin.h: Declare pseudoChr structs/defines.
1178
ee99860a
MF		 11792010-09-21 Mike Frysinger <vapier@gentoo.org>
1180
1181 * bfin.h: Strip trailing whitespace.
1182
f9c7014e
DD		 11832010-07-29 DJ Delorie <dj@redhat.com>
1184
1185 * rx.h (RX_Operand_Type): Add TwoReg.
1186 (RX_Opcode_ID): Remove ediv and ediv2.
1187
93378652
DD		 11882010-07-27 DJ Delorie <dj@redhat.com>
1189
1190 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1191
1cd986c5
NC		 11922010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1193 Ina Pandit <ina.pandit@kpitcummins.com>
1194
1195 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1196 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1197 PROCESSOR_V850E2_ALL.
1198 Remove PROCESSOR_V850EA support.
1199 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1200 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1201 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1202 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1203 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1204 V850_OPERAND_PERCENT.
1205 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1206 V850_NOT_R0.
1207 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1208 and V850E_PUSH_POP
1209
9a2c7088
MR		 12102010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1211
1212 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1213 (MIPS16_INSN_BRANCH): Rename to...
1214 (MIPS16_INSN_COND_BRANCH): ... this.
1215
bdc70b4a
AM		 12162010-07-03 Alan Modra <amodra@gmail.com>
1217
1218 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1219 Renumber other PPC_OPCODE defines.
1220
f2bae120
AM		 12212010-07-03 Alan Modra <amodra@gmail.com>
1222
1223 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1224
360cfc9c
AM		 12252010-06-29 Alan Modra <amodra@gmail.com>
1226
1227 * maxq.h: Delete file.
1228
e01d869a
AM		 12292010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1230
1231 * ppc.h (PPC_OPCODE_E500): Define.
1232
f79e2745
CM		 12332010-05-26 Catherine Moore <clm@codesourcery.com>
1234
1235 * opcode/mips.h (INSN_MIPS16): Remove.
1236
2462afa1
JM		 12372010-04-21 Joseph Myers <joseph@codesourcery.com>
1238
1239 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1240
e4e42b45
NC		 12412010-04-15 Nick Clifton <nickc@redhat.com>
1242
1243 * alpha.h: Update copyright notice to use GPLv3.
1244 * arc.h: Likewise.
1245 * arm.h: Likewise.
1246 * avr.h: Likewise.
1247 * bfin.h: Likewise.
1248 * cgen.h: Likewise.
1249 * convex.h: Likewise.
1250 * cr16.h: Likewise.
1251 * cris.h: Likewise.
1252 * crx.h: Likewise.
1253 * d10v.h: Likewise.
1254 * d30v.h: Likewise.
1255 * dlx.h: Likewise.
1256 * h8300.h: Likewise.
1257 * hppa.h: Likewise.
1258 * i370.h: Likewise.
1259 * i386.h: Likewise.
1260 * i860.h: Likewise.
1261 * i960.h: Likewise.
1262 * ia64.h: Likewise.
1263 * m68hc11.h: Likewise.
1264 * m68k.h: Likewise.
1265 * m88k.h: Likewise.
1266 * maxq.h: Likewise.
1267 * mips.h: Likewise.
1268 * mmix.h: Likewise.
1269 * mn10200.h: Likewise.
1270 * mn10300.h: Likewise.
1271 * msp430.h: Likewise.
1272 * np1.h: Likewise.
1273 * ns32k.h: Likewise.
1274 * or32.h: Likewise.
1275 * pdp11.h: Likewise.
1276 * pj.h: Likewise.
1277 * pn.h: Likewise.
1278 * ppc.h: Likewise.
1279 * pyr.h: Likewise.
1280 * rx.h: Likewise.
1281 * s390.h: Likewise.
1282 * score-datadep.h: Likewise.
1283 * score-inst.h: Likewise.
1284 * sparc.h: Likewise.
1285 * spu-insns.h: Likewise.
1286 * spu.h: Likewise.
1287 * tic30.h: Likewise.
1288 * tic4x.h: Likewise.
1289 * tic54x.h: Likewise.
1290 * tic80.h: Likewise.
1291 * v850.h: Likewise.
1292 * vax.h: Likewise.
1293
40b36596
JM		 12942010-03-25 Joseph Myers <joseph@codesourcery.com>
1295
1296 * tic6x-control-registers.h, tic6x-insn-formats.h,
1297 tic6x-opcode-table.h, tic6x.h: New.
1298
c67a084a
NC		 12992010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1300
1301 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1302
466ef64f
AM		 13032010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1304
1305 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1306
1319d143
L		 13072010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1308
1309 * ia64.h (ia64_find_opcode): Remove argument name.
1310 (ia64_find_next_opcode): Likewise.
1311 (ia64_dis_opcode): Likewise.
1312 (ia64_free_opcode): Likewise.
1313 (ia64_find_dependency): Likewise.
1314
1fbb9298
DE		 13152009-11-22 Doug Evans <dje@sebabeach.org>
1316
1317 * cgen.h: Include bfd_stdint.h.
1318 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1319
ada65aa3
PB		 13202009-11-18 Paul Brook <paul@codesourcery.com>
1321
1322 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1323
9e3c6df6
PB		 13242009-11-17 Paul Brook <paul@codesourcery.com>
1325 Daniel Jacobowitz <dan@codesourcery.com>
1326
1327 * arm.h (ARM_EXT_V6_DSP): Define.
1328 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1329 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1330
0d734b5d
DD		 13312009-11-04 DJ Delorie <dj@redhat.com>
1332
1333 * rx.h (rx_decode_opcode) (mvtipl): Add.
1334 (mvtcp, mvfcp, opecp): Remove.
1335
62f3b8c8
PB		 13362009-11-02 Paul Brook <paul@codesourcery.com>
1337
1338 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1339 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1340 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1341 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1342 FPU_ARCH_NEON_VFP_V4): Define.
1343
ac1e9eca
DE		 13442009-10-23 Doug Evans <dje@sebabeach.org>
1345
1346 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1347 * cgen.h: Update. Improve multi-inclusion macro name.
1348
9fe54b1c
PB		 13492009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1350
1351 * ppc.h (PPC_OPCODE_476): Define.
1352
634b50f2
PB		 13532009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1354
1355 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1356
c7927a3c
NC		 13572009-09-29 DJ Delorie <dj@redhat.com>
1358
1359 * rx.h: New file.
1360
b961e85b
AM		 13612009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1362
1363 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1364
e0d602ec
BE		 13652009-09-21 Ben Elliston <bje@au.ibm.com>
1366
1367 * ppc.h (PPC_OPCODE_PPCA2): New.
1368
96d56e9f
NC		 13692009-09-05 Martin Thuresson <martin@mtme.org>
1370
1371 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1372
d3ce72d0
NC		 13732009-08-29 Martin Thuresson <martin@mtme.org>
1374
1375 * tic30.h (template): Rename type template to
1376 insn_template. Updated code to use new name.
1377 * tic54x.h (template): Rename type template to
1378 insn_template.
1379
824b28db
NH		 13802009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1381
1382 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1383
f865a31d
AG		 13842009-06-11 Anthony Green <green@moxielogic.com>
1385
1386 * moxie.h (MOXIE_F3_PCREL): Define.
1387 (moxie_form3_opc_info): Grow.
1388
0e7c7f11
AG		 13892009-06-06 Anthony Green <green@moxielogic.com>
1390
1391 * moxie.h (MOXIE_F1_M): Define.
1392
20135e4c
NC		 13932009-04-15 Anthony Green <green@moxielogic.com>
1394
1395 * moxie.h: Created.
1396
bcb012d3
DD		 13972009-04-06 DJ Delorie <dj@redhat.com>
1398
1399 * h8300.h: Add relaxation attributes to MOVA opcodes.
1400
69fe9ce5
AM		 14012009-03-10 Alan Modra <amodra@bigpond.net.au>
1402
1403 * ppc.h (ppc_parse_cpu): Declare.
1404
c3b7224a
NC		 14052009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1406
1407 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1408 and _IMM11 for mbitclr and mbitset.
1409 * score-datadep.h: Update dependency information.
1410
066be9f7
PB		 14112009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1412
1413 * ppc.h (PPC_OPCODE_POWER7): New.
1414
fedc618e
DE		 14152009-02-06 Doug Evans <dje@google.com>
1416
1417 * i386.h: Add comment regarding sse* insns and prefixes.
1418
52b6b6b9
JM		 14192009-02-03 Sandip Matte <sandip@rmicorp.com>
1420
1421 * mips.h (INSN_XLR): Define.
1422 (INSN_CHIP_MASK): Update.
1423 (CPU_XLR): Define.
1424 (OPCODE_IS_MEMBER): Update.
1425 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1426
35669430
DE		 14272009-01-28 Doug Evans <dje@google.com>
1428
1429 * opcode/i386.h: Add multiple inclusion protection.
1430 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1431 (EDI_REG_NUM): New macros.
1432 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1433 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1434 (REX_PREFIX_P): New macro.
35669430 1435
1cb0a767
PB		 14362009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1437
1438 * ppc.h (struct powerpc_opcode): New field "deprecated".
1439 (PPC_OPCODE_NOPOWER4): Delete.
1440
3aa3176b
TS		 14412008-11-28 Joshua Kinard <kumba@gentoo.org>
1442
1443 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1444 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1445
8e79c3df
CM		 14462008-11-18 Catherine Moore <clm@codesourcery.com>
1447
1448 * arm.h (FPU_NEON_FP16): New.
1449 (FPU_ARCH_NEON_FP16): New.
1450
de9a3e51
CF		 14512008-11-06 Chao-ying Fu <fu@mips.com>
1452
1453 * mips.h: Doucument '1' for 5-bit sync type.
1454
1ca35711
L		 14552008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1456
1457 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1458 IA64_RS_CR.
1459
9b4e5766
PB		 14602008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1461
1462 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1463
081ba1b3
AM		 14642008-07-30 Michael J. Eager <eager@eagercon.com>
1465
1466 * ppc.h (PPC_OPCODE_405): Define.
1467 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1468
fa452fa6
PB		 14692008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1470
1471 * ppc.h (ppc_cpu_t): New typedef.
1472 (struct powerpc_opcode <flags>): Use it.
1473 (struct powerpc_operand <insert, extract>): Likewise.
1474 (struct powerpc_macro <flags>): Likewise.
1475
bb35fb24
NC		 14762008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1477
1478 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1479 Update comment before MIPS16 field descriptors to mention MIPS16.
1480 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1481 BBIT.
1482 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1483 New bit masks and shift counts for cins and exts.
1484
dd3cbb7e
NC		 1485 * mips.h: Document new field descriptors +Q.
1486 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1487
d0799671
AN		 14882008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1489
9aff4b7a 1490 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1491 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1492
19a6653c
AM		 14932008-04-14 Edmar Wienskoski <edmar@freescale.com>
1494
1495 * ppc.h: (PPC_OPCODE_E500MC): New.
1496
c0f3af97
L		 14972008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1498
1499 * i386.h (MAX_OPERANDS): Set to 5.
1500 (MAX_MNEM_SIZE): Changed to 20.
1501
e210c36b
NC		 15022008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1503
1504 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1505
b1cc4aeb
PB		 15062008-03-09 Paul Brook <paul@codesourcery.com>
1507
1508 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1509
7e806470
PB		 15102008-03-04 Paul Brook <paul@codesourcery.com>
1511
1512 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1513 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1514 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1515
7b2185f9 15162008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1517 Nick Clifton <nickc@redhat.com>
1518
1519 PR 3134
1520 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1521 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1522 set.
af7329f0 1523
796d5313
NC		 15242008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1525
1526 * cr16.h (cr16_num_optab): Declared.
1527
d669d37f
NC		 15282008-02-14 Hakan Ardo <hakan@debian.org>
1529
1530 PR gas/2626
1531 * avr.h (AVR_ISA_2xxe): Define.
1532
e6429699
AN		 15332008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1534
1535 * mips.h: Update copyright.
1536 (INSN_CHIP_MASK): New macro.
1537 (INSN_OCTEON): New macro.
1538 (CPU_OCTEON): New macro.
1539 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1540
e210c36b
NC		 15412008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1542
1543 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1544
15452008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1546
1547 * avr.h (AVR_ISA_USB162): Add new opcode set.
1548 (AVR_ISA_AVR3): Likewise.
1549
350cc38d
MS		 15502007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1551
1552 * mips.h (INSN_LOONGSON_2E): New.
1553 (INSN_LOONGSON_2F): New.
1554 (CPU_LOONGSON_2E): New.
1555 (CPU_LOONGSON_2F): New.
1556 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1557
56950294
MS		 15582007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1559
1560 * mips.h (INSN_ISA*): Redefine certain values as an
1561 enumeration. Update comments.
1562 (mips_isa_table): New.
1563 (ISA_MIPS*): Redefine to match enumeration.
1564 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1565 values.
1566
c3d65c1c
BE		 15672007-08-08 Ben Elliston <bje@au.ibm.com>
1568
1569 * ppc.h (PPC_OPCODE_PPCPS): New.
1570
0fdaa005
L		 15712007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1572
1573 * m68k.h: Document j K & E.
1574
15752007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1576
1577 * cr16.h: New file for CR16 target.
1578
3896c469
AM		 15792007-05-02 Alan Modra <amodra@bigpond.net.au>
1580
1581 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1582
9a2e615a
NS		 15832007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1584
1585 * m68k.h (mcfisa_c): New.
1586 (mcfusp, mcf_mask): Adjust.
1587
b84bf58a
AM		 15882007-04-20 Alan Modra <amodra@bigpond.net.au>
1589
1590 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1591 (num_powerpc_operands): Declare.
1592 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1593 (PPC_OPERAND_PLUS1): Define.
1594
831480e9 15952007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1596
1597 * i386.h (REX_MODE64): Renamed to ...
1598 (REX_W): This.
1599 (REX_EXTX): Renamed to ...
1600 (REX_R): This.
1601 (REX_EXTY): Renamed to ...
1602 (REX_X): This.
1603 (REX_EXTZ): Renamed to ...
1604 (REX_B): This.
1605
0b1cf022
L		 16062007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1607
1608 * i386.h: Add entries from config/tc-i386.h and move tables
1609 to opcodes/i386-opc.h.
1610
d796c0ad
L		 16112007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1612
1613 * i386.h (FloatDR): Removed.
1614 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1615
30ac7323
AM		 16162007-03-01 Alan Modra <amodra@bigpond.net.au>
1617
1618 * spu-insns.h: Add soma double-float insns.
1619
8b082fb1 16202007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1621 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1622
1623 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1624 (INSN_DSPR2): Add flag for DSP R2 instructions.
1625 (M_BALIGN): New macro.
1626
4eed87de
AM		 16272007-02-14 Alan Modra <amodra@bigpond.net.au>
1628
1629 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1630 and Seg3ShortFrom with Shortform.
1631
fda592e8
L		 16322007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1633
1634 PR gas/4027
1635 * i386.h (i386_optab): Put the real "test" before the pseudo
1636 one.
1637
3bdcfdf4
KH		 16382007-01-08 Kazu Hirata <kazu@codesourcery.com>
1639
1640 * m68k.h (m68010up): OR fido_a.
1641
9840d27e
KH		 16422006-12-25 Kazu Hirata <kazu@codesourcery.com>
1643
1644 * m68k.h (fido_a): New.
1645
c629cdac
KH		 16462006-12-24 Kazu Hirata <kazu@codesourcery.com>
1647
1648 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1649 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1650 values.
1651
b7d9ef37
L		 16522006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1653
1654 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1655
b138abaa
NC		 16562006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1657
1658 * score-inst.h (enum score_insn_type): Add Insn_internal.
1659
e9f53129
AM		 16602006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1661 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1662 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1663 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1664 Alan Modra <amodra@bigpond.net.au>
1665
1666 * spu-insns.h: New file.
1667 * spu.h: New file.
1668
ede602d7
AM		 16692006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1670
1671 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1672
7918206c
MM		 16732006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1674
e4e42b45 1675 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1676 in amdfam10 architecture.
1677
ef05d495
L		 16782006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1679
1680 * i386.h: Replace CpuMNI with CpuSSSE3.
1681
2d447fca 16822006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1683 Joseph Myers <joseph@codesourcery.com>
1684 Ian Lance Taylor <ian@wasabisystems.com>
1685 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1686
1687 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1688
1c0d3aa6
NC		 16892006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1690
1691 * score-datadep.h: New file.
1692 * score-inst.h: New file.
1693
c2f0420e
L		 16942006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1695
1696 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1697 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1698 movdq2q and movq2dq.
1699
050dfa73
MM		 17002006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1701 Michael Meissner <michael.meissner@amd.com>
1702
1703 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1704
15965411
L		 17052006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1706
1707 * i386.h (i386_optab): Add "nop" with memory reference.
1708
46e883c5
L		 17092006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1710
1711 * i386.h (i386_optab): Update comment for 64bit NOP.
1712
9622b051
AM		 17132006-06-06 Ben Elliston <bje@au.ibm.com>
1714 Anton Blanchard <anton@samba.org>
1715
1716 * ppc.h (PPC_OPCODE_POWER6): Define.
1717 Adjust whitespace.
1718
a9e24354
TS		 17192006-06-05 Thiemo Seufer <ths@mips.com>
1720
e4e42b45 1721 * mips.h: Improve description of MT flags.
a9e24354 1722
a596001e
RS		 17232006-05-25 Richard Sandiford <richard@codesourcery.com>
1724
1725 * m68k.h (mcf_mask): Define.
1726
d43b4baf 17272006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1728 David Ung <davidu@mips.com>
d43b4baf
TS		 1729
1730 * mips.h (enum): Add macro M_CACHE_AB.
1731
39a7806d 17322006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1733 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1734 David Ung <davidu@mips.com>
1735
1736 * mips.h: Add INSN_SMARTMIPS define.
1737
9bcd4f99 17382006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1739 David Ung <davidu@mips.com>
9bcd4f99
TS		 1740
1741 * mips.h: Defines udi bits and masks. Add description of
1742 characters which may appear in the args field of udi
1743 instructions.
1744
ef0ee844
TS		 17452006-04-26 Thiemo Seufer <ths@networkno.de>
1746
1747 * mips.h: Improve comments describing the bitfield instruction
1748 fields.
1749
f7675147
L		 17502006-04-26 Julian Brown <julian@codesourcery.com>
1751
1752 * arm.h (FPU_VFP_EXT_V3): Define constant.
1753 (FPU_NEON_EXT_V1): Likewise.
1754 (FPU_VFP_HARD): Update.
1755 (FPU_VFP_V3): Define macro.
1756 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1757
ef0ee844 17582006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1759
1760 * avr.h (AVR_ISA_PWMx): New.
1761
2da12c60
NS		 17622006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1763
1764 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1765 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1766 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1767 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1768 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1769
0715c387
PB		 17702006-03-10 Paul Brook <paul@codesourcery.com>
1771
1772 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1773
34bdd094
DA		 17742006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1775
1776 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1777 first. Correct mask of bb "B" opcode.
1778
331d2d0d
L		 17792006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1780
1781 * i386.h (i386_optab): Support Intel Merom New Instructions.
1782
62b3e311
PB		 17832006-02-24 Paul Brook <paul@codesourcery.com>
1784
1785 * arm.h: Add V7 feature bits.
1786
59cf82fe
L		 17872006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1788
1789 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1790
e74cfd16
PB		 17912006-01-31 Paul Brook <paul@codesourcery.com>
1792 Richard Earnshaw <rearnsha@arm.com>
1793
1794 * arm.h: Use ARM_CPU_FEATURE.
1795 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1796 (arm_feature_set): Change to a structure.
1797 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1798 ARM_FEATURE): New macros.
1799
5b3f8a92
HPN		 18002005-12-07 Hans-Peter Nilsson <hp@axis.com>
1801
1802 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1803 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1804 (ADD_PC_INCR_OPCODE): Don't define.
1805
cb712a9e
L		 18062005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1807
1808 PR gas/1874
1809 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1810
0499d65b
TS		 18112005-11-14 David Ung <davidu@mips.com>
1812
1813 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1814 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1815 save/restore encoding of the args field.
1816
ea5ca089
DB		 18172005-10-28 Dave Brolley <brolley@redhat.com>
1818
1819 Contribute the following changes:
1820 2005-02-16 Dave Brolley <brolley@redhat.com>
1821
1822 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1823 cgen_isa_mask_* to cgen_bitset_*.
1824 * cgen.h: Likewise.
1825
16175d96
DB		 1826 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1827
1828 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1829 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1830 (CGEN_CPU_TABLE): Make isas a ponter.
1831
1832 2003-09-29 Dave Brolley <brolley@redhat.com>
1833
1834 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1835 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1836 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1837
1838 2002-12-13 Dave Brolley <brolley@redhat.com>
1839
1840 * cgen.h (symcat.h): #include it.
1841 (cgen-bitset.h): #include it.
1842 (CGEN_ATTR_VALUE_TYPE): Now a union.
1843 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1844 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1845 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1846 * cgen-bitset.h: New file.
1847
3c9b82ba
NC		 18482005-09-30 Catherine Moore <clm@cm00re.com>
1849
1850 * bfin.h: New file.
1851
6a2375c6
JB		 18522005-10-24 Jan Beulich <jbeulich@novell.com>
1853
1854 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1855 indirect operands.
1856
c06a12f8
DA		 18572005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1858
1859 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1860 Add FLAG_STRICT to pa10 ftest opcode.
1861
4d443107
DA		 18622005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1863
1864 * hppa.h (pa_opcodes): Remove lha entries.
1865
f0a3b40f
DA		 18662005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1867
1868 * hppa.h (FLAG_STRICT): Revise comment.
1869 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1870 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1871 entries for "fdc".
1872
e210c36b
NC		 18732005-09-30 Catherine Moore <clm@cm00re.com>
1874
1875 * bfin.h: New file.
1876
1b7e1362
DA		 18772005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1878
1879 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1880
089b39de
CF		 18812005-09-06 Chao-ying Fu <fu@mips.com>
1882
1883 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1884 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1885 define.
1886 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1887 (INSN_ASE_MASK): Update to include INSN_MT.
1888 (INSN_MT): New define for MT ASE.
1889
93c34b9b
CF		 18902005-08-25 Chao-ying Fu <fu@mips.com>
1891
1892 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1893 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1894 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1895 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1896 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1897 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1898 instructions.
1899 (INSN_DSP): New define for DSP ASE.
1900
848cf006
AM		 19012005-08-18 Alan Modra <amodra@bigpond.net.au>
1902
1903 * a29k.h: Delete.
1904
36ae0db3
DJ		 19052005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1906
1907 * ppc.h (PPC_OPCODE_E300): Define.
1908
8c929562
MS		 19092005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1910
1911 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1912
f7b8cccc
DA		 19132005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1914
1915 PR gas/336
1916 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1917 and pitlb.
1918
8b5328ac
JB		 19192005-07-27 Jan Beulich <jbeulich@novell.com>
1920
1921 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1922 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1923 Add movq-s as 64-bit variants of movd-s.
1924
f417d200
DA		 19252005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1926
18b3bdfc
DA		 1927 * hppa.h: Fix punctuation in comment.
1928
f417d200
DA		 1929 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1930 implicit space-register addressing. Set space-register bits on opcodes
1931 using implicit space-register addressing. Add various missing pa20
1932 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1933 space-register addressing. Use "fE" instead of "fe" in various
1934 fstw opcodes.
1935
9a145ce6
JB		 19362005-07-18 Jan Beulich <jbeulich@novell.com>
1937
1938 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1939
90700ea2
L		 19402007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1941
1942 * i386.h (i386_optab): Support Intel VMX Instructions.
1943
48f130a8
DA		 19442005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1945
1946 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1947
30123838
JB		 19482005-07-05 Jan Beulich <jbeulich@novell.com>
1949
1950 * i386.h (i386_optab): Add new insns.
1951
47b0e7ad
NC		 19522005-07-01 Nick Clifton <nickc@redhat.com>
1953
1954 * sparc.h: Add typedefs to structure declarations.
1955
b300c311
L		 19562005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1957
1958 PR 1013
1959 * i386.h (i386_optab): Update comments for 64bit addressing on
1960 mov. Allow 64bit addressing for mov and movq.
1961
2db495be
DA		 19622005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1963
1964 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1965 respectively, in various floating-point load and store patterns.
1966
caa05036
DA		 19672005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1968
1969 * hppa.h (FLAG_STRICT): Correct comment.
1970 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1971 PA 2.0 mneumonics when equivalent. Entries with cache control
1972 completers now require PA 1.1. Adjust whitespace.
1973
f4411256
AM		 19742005-05-19 Anton Blanchard <anton@samba.org>
1975
1976 * ppc.h (PPC_OPCODE_POWER5): Define.
1977
e172dbf8
NC		 19782005-05-10 Nick Clifton <nickc@redhat.com>
1979
1980 * Update the address and phone number of the FSF organization in
1981 the GPL notices in the following files:
1982 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1983 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1984 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1985 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1986 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1987 tic54x.h, tic80.h, v850.h, vax.h
1988
e44823cf
JB		 19892005-05-09 Jan Beulich <jbeulich@novell.com>
1990
1991 * i386.h (i386_optab): Add ht and hnt.
1992
791fe849
MK		 19932005-04-18 Mark Kettenis <kettenis@gnu.org>
1994
1995 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1996 Add xcrypt-ctr. Provide aliases without hyphens.
1997
faa7ef87
L		 19982005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1999
a63027e5
L		 2000 Moved from ../ChangeLog
2001
faa7ef87
L		 2002 2005-04-12 Paul Brook <paul@codesourcery.com>
2003 * m88k.h: Rename psr macros to avoid conflicts.
2004
2005 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2006 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2007 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2008 and ARM_ARCH_V6ZKT2.
2009
2010 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2011 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2012 Remove redundant instruction types.
2013 (struct argument): X_op - new field.
2014 (struct cst4_entry): Remove.
2015 (no_op_insn): Declare.
2016
2017 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2018 * crx.h (enum argtype): Rename types, remove unused types.
2019
2020 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2021 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2022 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2023 (enum operand_type): Rearrange operands, edit comments.
2024 replace us<N> with ui<N> for unsigned immediate.
2025 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2026 displacements (respectively).
2027 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2028 (instruction type): Add NO_TYPE_INS.
2029 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2030 (operand_entry): New field - 'flags'.
2031 (operand flags): New.
2032
2033 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2034 * crx.h (operand_type): Remove redundant types i3, i4,
2035 i5, i8, i12.
2036 Add new unsigned immediate types us3, us4, us5, us16.
2037
bc4bd9ab
MK		 20382005-04-12 Mark Kettenis <kettenis@gnu.org>
2039
2040 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2041 adjust them accordingly.
2042
373ff435
JB		 20432005-04-01 Jan Beulich <jbeulich@novell.com>
2044
2045 * i386.h (i386_optab): Add rdtscp.
2046
4cc91dba
L		 20472005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2048
2049 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2050 between memory and segment register. Allow movq for moving between
2051 general-purpose register and segment register.
4cc91dba 2052
9ae09ff9
JB		 20532005-02-09 Jan Beulich <jbeulich@novell.com>
2054
2055 PR gas/707
2056 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2057 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2058 fnstsw.
2059
638e7a64
NS		 20602006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2061
2062 * m68k.h (m68008, m68ec030, m68882): Remove.
2063 (m68k_mask): New.
2064 (cpu_m68k, cpu_cf): New.
2065 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2066 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2067
90219bd0
AO		 20682005-01-25 Alexandre Oliva <aoliva@redhat.com>
2069
2070 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2071 * cgen.h (enum cgen_parse_operand_type): Add
2072 CGEN_PARSE_OPERAND_SYMBOLIC.
2073
239cb185
FF		 20742005-01-21 Fred Fish <fnf@specifixinc.com>
2075
2076 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2077 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2078 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2079
dc9a9f39
FF		 20802005-01-19 Fred Fish <fnf@specifixinc.com>
2081
2082 * mips.h (struct mips_opcode): Add new pinfo2 member.
2083 (INSN_ALIAS): New define for opcode table entries that are
2084 specific instances of another entry, such as 'move' for an 'or'
2085 with a zero operand.
2086 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2087 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2088
98e7aba8
ILT		 20892004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2090
2091 * mips.h (CPU_RM9000): Define.
2092 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2093
37edbb65
JB		 20942004-11-25 Jan Beulich <jbeulich@novell.com>
2095
2096 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2097 to/from test registers are illegal in 64-bit mode. Add missing
2098 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2099 (previously one had to explicitly encode a rex64 prefix). Re-enable
2100 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2101 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2102
21032004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2104
2105 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2106 available only with SSE2. Change the MMX additions introduced by SSE
2107 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2108 instructions by their now designated identifier (since combining i686
2109 and 3DNow! does not really imply 3DNow!A).
2110
f5c7edf4
AM		 21112004-11-19 Alan Modra <amodra@bigpond.net.au>
2112
2113 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2114 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2115
7499d566
NC		 21162004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2117 Vineet Sharma <vineets@noida.hcltech.com>
2118
2119 * maxq.h: New file: Disassembly information for the maxq port.
2120
bcb9eebe
L		 21212004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2122
2123 * i386.h (i386_optab): Put back "movzb".
2124
94bb3d38
HPN		 21252004-11-04 Hans-Peter Nilsson <hp@axis.com>
2126
2127 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2128 comments. Remove member cris_ver_sim. Add members
2129 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2130 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2131 (struct cris_support_reg, struct cris_cond15): New types.
2132 (cris_conds15): Declare.
2133 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2134 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2135 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2136 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2137 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2138 SIZE_FIELD_UNSIGNED.
2139
37edbb65 21402004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2141
2142 * i386.h (sldx_Suf): Remove.
2143 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2144 (q_FP): Define, implying no REX64.
2145 (x_FP, sl_FP): Imply FloatMF.
2146 (i386_optab): Split reg and mem forms of moving from segment registers
2147 so that the memory forms can ignore the 16-/32-bit operand size
2148 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2149 all non-floating-point instructions. Unite 32- and 64-bit forms of
2150 movsx, movzx, and movd. Adjust floating point operations for the above
2151 changes to the *FP macros. Add DefaultSize to floating point control
2152 insns operating on larger memory ranges. Remove left over comments
2153 hinting at certain insns being Intel-syntax ones where the ones
2154 actually meant are already gone.
2155
48c9f030
NC		 21562004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2157
2158 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2159 instruction type.
2160
0dd132b6
NC		 21612004-09-30 Paul Brook <paul@codesourcery.com>
2162
2163 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2164 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2165
23794b24
MM		 21662004-09-11 Theodore A. Roth <troth@openavr.org>
2167
2168 * avr.h: Add support for
2169 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2170
2a309db0
AM		 21712004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2172
2173 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2174
b18c562e
NC		 21752004-08-24 Dmitry Diky <diwil@spec.ru>
2176
2177 * msp430.h (msp430_opc): Add new instructions.
2178 (msp430_rcodes): Declare new instructions.
2179 (msp430_hcodes): Likewise..
2180
45d313cd
NC		 21812004-08-13 Nick Clifton <nickc@redhat.com>
2182
2183 PR/301
2184 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2185 processors.
2186
30d1c836
ML		 21872004-08-30 Michal Ludvig <mludvig@suse.cz>
2188
2189 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2190
9a45f1c2
L		 21912004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2192
2193 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2194
543613e9
NC		 21952004-07-21 Jan Beulich <jbeulich@novell.com>
2196
2197 * i386.h: Adjust instruction descriptions to better match the
2198 specification.
2199
b781e558
RE		 22002004-07-16 Richard Earnshaw <rearnsha@arm.com>
2201
2202 * arm.h: Remove all old content. Replace with architecture defines
2203 from gas/config/tc-arm.c.
2204
8577e690
AS		 22052004-07-09 Andreas Schwab <schwab@suse.de>
2206
2207 * m68k.h: Fix comment.
2208
1fe1f39c
NC		 22092004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2210
2211 * crx.h: New file.
2212
1d9f512f
AM		 22132004-06-24 Alan Modra <amodra@bigpond.net.au>
2214
2215 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2216
be8c092b
NC		 22172004-05-24 Peter Barada <peter@the-baradas.com>
2218
2219 * m68k.h: Add 'size' to m68k_opcode.
2220
6b6e92f4
NC		 22212004-05-05 Peter Barada <peter@the-baradas.com>
2222
2223 * m68k.h: Switch from ColdFire chip name to core variant.
2224
22252004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2226
2227 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2228 descriptions for new EMAC cases.
2229 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2230 handle Motorola MAC syntax.
2231 Allow disassembly of ColdFire V4e object files.
2232
fdd12ef3
AM		 22332004-03-16 Alan Modra <amodra@bigpond.net.au>
2234
2235 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2236
3922a64c
L		 22372004-03-12 Jakub Jelinek <jakub@redhat.com>
2238
2239 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2240
1f45d988
ML		 22412004-03-12 Michal Ludvig <mludvig@suse.cz>
2242
2243 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2244
0f10071e
ML		 22452004-03-12 Michal Ludvig <mludvig@suse.cz>
2246
2247 * i386.h (i386_optab): Added xstore/xcrypt insns.
2248
3255318a
NC		 22492004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2250
2251 * h8300.h (32bit ldc/stc): Add relaxing support.
2252
ca9a79a1 22532004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2254
ca9a79a1
NC		 2255 * h8300.h (BITOP): Pass MEMRELAX flag.
2256
875a0b14
NC		 22572004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2258
2259 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2260 except for the H8S.
252b5132 2261
c9e214e5 2262For older changes see ChangeLog-9103
252b5132 2263\f
b90efa5b 2264Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2265
2266Copying and distribution of this file, with or without modification,
2267are permitted in any medium without royalty provided the copyright
2268notice and this notice are preserved.
2269
252b5132 2270Local Variables:
c9e214e5
AM		 2271mode: change-log
2272left-margin: 8
2273fill-column: 74
252b5132
RH		 2274version-control: never
2275End:
GDB Binutils - Deliverables
This page took 0.801011 seconds and 4 git commands to generate.