[deliverable/binutils-gdb.git] / include / opcode / ChangeLog

2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>

	* s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.

2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	PR gas/336
 	* hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
	and pitlb.

2005-07-27  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add comment to movd. Use LongMem for all
	movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
	Add movq-s as 64-bit variants of movd-s.

2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h: Fix punctuation in comment.

	* hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
	implicit space-register addressing.  Set space-register bits on opcodes
	using implicit space-register addressing.  Add various missing pa20
	long-immediate opcodes.  Remove various opcodes using implicit 3-bit
	space-register addressing.  Use "fE" instead of "fe" in various
	fstw opcodes.

2005-07-18  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Operands of aam and aad are unsigned.

2007-07-15  H.J. Lu <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Support Intel VMX Instructions.

2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.

2005-07-05  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add new insns.

2005-07-01  Nick Clifton  <nickc@redhat.com>

	* sparc.h: Add typedefs to structure declarations.

2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>

	PR 1013
	* i386.h (i386_optab): Update comments for 64bit addressing on
	mov. Allow 64bit addressing for mov and movq.

2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
	respectively, in various floating-point load and store patterns.

2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* hppa.h (FLAG_STRICT): Correct comment.
	(pa_opcodes): Update load and store entries to allow both PA 1.X and
	PA 2.0 mneumonics when equivalent.  Entries with cache control
	completers now require PA 1.1.  Adjust whitespace.

2005-05-19  Anton Blanchard  <anton@samba.org>

	* ppc.h (PPC_OPCODE_POWER5): Define.

2005-05-10  Nick Clifton  <nickc@redhat.com>

	* Update the address and phone number of the FSF organization in
	the GPL notices in the following files:
	a29k.h,	alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
	crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
	i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
	mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
	pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
	tic54x.h, tic80.h, v850.h, vax.h

2005-05-09  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add ht and hnt.

2005-04-18  Mark Kettenis  <kettenis@gnu.org>

	* i386.h: Insert hyphens into selected VIA PadLock extensions.
	Add xcrypt-ctr.  Provide aliases without hyphens.

2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>

	Moved from ../ChangeLog

	2005-04-12  Paul Brook  <paul@codesourcery.com>
	* m88k.h: Rename psr macros to avoid conflicts.

	2005-03-12  Zack Weinberg  <zack@codesourcery.com>
	* arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
	Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
	and ARM_ARCH_V6ZKT2.

	2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
	Remove redundant instruction types.
	(struct argument): X_op - new field.
	(struct cst4_entry): Remove.
	(no_op_insn): Declare.

	2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum argtype): Rename types, remove unused types.

	2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
	(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
	(enum operand_type): Rearrange operands, edit comments.
	replace us<N> with ui<N> for unsigned immediate.
	replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
	displacements (respectively).
	replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
	(instruction type): Add NO_TYPE_INS.
	(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
	(operand_entry): New field - 'flags'.
	(operand flags): New.

	2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
	* crx.h (operand_type): Remove redundant types i3, i4,
	i5, i8, i12.
	Add new unsigned immediate types us3, us4, us5, us16.

2005-04-12  Mark Kettenis  <kettenis@gnu.org>

	* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
	adjust them accordingly.

2005-04-01  Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): Add rdtscp.

2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Don't allow the `l' suffix for moving
	between memory and segment register. Allow movq for moving between
	general-purpose register and segment register.

2005-02-09  Jan Beulich  <jbeulich@novell.com>

	PR gas/707
	* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
	FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
	fnstsw.

2005-01-25  Alexandre Oliva  <aoliva@redhat.com>

	2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
	* cgen.h (enum cgen_parse_operand_type): Add
	CGEN_PARSE_OPERAND_SYMBOLIC.

2005-01-21  Fred Fish  <fnf@specifixinc.com>

	* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
	Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
	Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.

2005-01-19  Fred Fish  <fnf@specifixinc.com>

	* mips.h (struct mips_opcode): Add new pinfo2 member.
	(INSN_ALIAS): New define for opcode table entries that are
	specific instances of another entry, such as 'move' for an 'or'
	with a zero operand.
	(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
	(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.

2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>

	* mips.h (CPU_RM9000): Define.
	(OPCODE_IS_MEMBER): Handle CPU_RM9000.

2004-11-25 Jan Beulich  <jbeulich@novell.com>

	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
	to/from test registers are illegal in 64-bit mode. Add missing
	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
	(previously one had to explicitly encode a rex64 prefix). Re-enable
	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.

2004-11-23 Jan Beulich  <jbeulich@novell.com>

	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
	available only with SSE2. Change the MMX additions introduced by SSE
	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
	instructions by their now designated identifier (since combining i686
	and 3DNow! does not really imply 3DNow!A).

2004-11-19  Alan Modra  <amodra@bigpond.net.au>

	* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
	struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.

2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
	    Vineet Sharma      <vineets@noida.hcltech.com>

	* maxq.h: New file: Disassembly information for the maxq port.

2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Put back "movzb".

2004-11-04  Hans-Peter Nilsson  <hp@axis.com>

	* cris.h (enum cris_insn_version_usage): Tweak formatting and
	comments.  Remove member cris_ver_sim.  Add members
	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
	(struct cris_support_reg, struct cris_cond15): New types.
	(cris_conds15): Declare.
	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
	SIZE_FIELD_UNSIGNED.

2004-11-04 Jan Beulich  <jbeulich@novell.com>

	* i386.h (sldx_Suf): Remove.
	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	(q_FP): Define, implying no REX64.
	(x_FP, sl_FP): Imply FloatMF.
	(i386_optab): Split reg and mem forms of moving from segment registers
	so that the memory forms can ignore the 16-/32-bit operand size
	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	all non-floating-point instructions. Unite 32- and 64-bit forms of
	movsx, movzx, and movd. Adjust floating point operations for the above
	changes to the *FP macros. Add DefaultSize to floating point control
	insns operating on larger memory ranges. Remove left over comments
	hinting at certain insns being Intel-syntax ones where the ones
	actually meant are already gone.

2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>

	* crx.h: Add COPS_REG_INS - Coprocessor Special register
	instruction type.

2004-09-30  Paul Brook  <paul@codesourcery.com>

	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.

2004-09-11  Theodore A. Roth  <troth@openavr.org>

	* avr.h: Add support for
	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.

2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>

	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.

2004-08-24  Dmitry Diky  <diwil@spec.ru>

	* msp430.h (msp430_opc): Add new instructions.
	(msp430_rcodes): Declare new instructions.
	(msp430_hcodes): Likewise..

2004-08-13  Nick Clifton  <nickc@redhat.com>

	PR/301
	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
	processors.

2004-08-30  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.

2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.

2004-07-21  Jan Beulich  <jbeulich@novell.com>

	* i386.h: Adjust instruction descriptions to better match the
	specification.

2004-07-16  Richard Earnshaw  <rearnsha@arm.com>

	* arm.h: Remove all old content.  Replace with architecture defines
	from gas/config/tc-arm.c.

2004-07-09  Andreas Schwab  <schwab@suse.de>

	* m68k.h: Fix comment.

2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>

	* crx.h: New file.

2004-06-24  Alan Modra  <amodra@bigpond.net.au>

	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.

2004-05-24  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Add 'size' to m68k_opcode.

2004-05-05  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Switch from ColdFire chip name to core variant.

2004-04-22  Peter Barada  <peter@the-baradas.com>

	* m68k.h: Add mcfmac/mcfemac definitions.  Update operand
	descriptions for new EMAC cases.
	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
	handle Motorola MAC syntax.
	Allow disassembly of ColdFire V4e object files.

2004-03-16  Alan Modra  <amodra@bigpond.net.au>

	* ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.

2004-03-12  Jakub Jelinek  <jakub@redhat.com>

	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.

2004-03-12  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added xstore as an alias for xstorerng.

2004-03-12  Michal Ludvig  <mludvig@suse.cz>

	* i386.h (i386_optab): Added xstore/xcrypt insns.

2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (32bit ldc/stc): Add relaxing support.

2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (BITOP): Pass MEMRELAX flag.

2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>

	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
	except for the H8S.

For older changes see ChangeLog-9103
\f
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Commit	Line	Data
8c929562 MS	1	2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
	2
	3	* s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
	4
f7b8cccc DA	5	2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	6
	7	PR gas/336
	8	* hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
	9	and pitlb.
	10
8b5328ac JB	11	2005-07-27 Jan Beulich <jbeulich@novell.com>
	12
	13	* i386.h (i386_optab): Add comment to movd. Use LongMem for all
	14	movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
	15	Add movq-s as 64-bit variants of movd-s.
	16
f417d200 DA	17	2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
f417d200 DA	18
18b3bdfc DA	19	* hppa.h: Fix punctuation in comment.
18b3bdfc DA	20
f417d200 DA	21	* hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
	22	implicit space-register addressing. Set space-register bits on opcodes
	23	using implicit space-register addressing. Add various missing pa20
	24	long-immediate opcodes. Remove various opcodes using implicit 3-bit
	25	space-register addressing. Use "fE" instead of "fe" in various
	26	fstw opcodes.
	27
9a145ce6 JB	28	2005-07-18 Jan Beulich <jbeulich@novell.com>
	29
	30	* i386.h (i386_optab): Operands of aam and aad are unsigned.
	31
90700ea2 L	32	2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
	33
	34	* i386.h (i386_optab): Support Intel VMX Instructions.
	35
48f130a8 DA	36	2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	37
	38	* hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
	39
30123838 JB	40	2005-07-05 Jan Beulich <jbeulich@novell.com>
	41
	42	* i386.h (i386_optab): Add new insns.
	43
47b0e7ad NC	44	2005-07-01 Nick Clifton <nickc@redhat.com>
	45
	46	* sparc.h: Add typedefs to structure declarations.
	47
b300c311 L	48	2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
	49
	50	PR 1013
	51	* i386.h (i386_optab): Update comments for 64bit addressing on
	52	mov. Allow 64bit addressing for mov and movq.
	53
2db495be DA	54	2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	55
	56	* hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
	57	respectively, in various floating-point load and store patterns.
	58
caa05036 DA	59	2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
	60
	61	* hppa.h (FLAG_STRICT): Correct comment.
	62	(pa_opcodes): Update load and store entries to allow both PA 1.X and
	63	PA 2.0 mneumonics when equivalent. Entries with cache control
	64	completers now require PA 1.1. Adjust whitespace.
	65
f4411256 AM	66	2005-05-19 Anton Blanchard <anton@samba.org>
	67
	68	* ppc.h (PPC_OPCODE_POWER5): Define.
	69
e172dbf8 NC	70	2005-05-10 Nick Clifton <nickc@redhat.com>
	71
	72	* Update the address and phone number of the FSF organization in
	73	the GPL notices in the following files:
	74	a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
	75	crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
	76	i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
	77	mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
	78	pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
	79	tic54x.h, tic80.h, v850.h, vax.h
	80
e44823cf JB	81	2005-05-09 Jan Beulich <jbeulich@novell.com>
	82
	83	* i386.h (i386_optab): Add ht and hnt.
	84
791fe849 MK	85	2005-04-18 Mark Kettenis <kettenis@gnu.org>
	86
	87	* i386.h: Insert hyphens into selected VIA PadLock extensions.
	88	Add xcrypt-ctr. Provide aliases without hyphens.
	89
faa7ef87 L	90	2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
faa7ef87 L	91
a63027e5 L	92	Moved from ../ChangeLog
a63027e5 L	93
faa7ef87 L	94	2005-04-12 Paul Brook <paul@codesourcery.com>
	95	* m88k.h: Rename psr macros to avoid conflicts.
	96
	97	2005-03-12 Zack Weinberg <zack@codesourcery.com>
	98	* arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
	99	Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
	100	and ARM_ARCH_V6ZKT2.
	101
	102	2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
	103	* crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
	104	Remove redundant instruction types.
	105	(struct argument): X_op - new field.
	106	(struct cst4_entry): Remove.
	107	(no_op_insn): Declare.
	108
	109	2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
	110	* crx.h (enum argtype): Rename types, remove unused types.
	111
	112	2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
	113	* crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
	114	(enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
	115	(enum operand_type): Rearrange operands, edit comments.
	116	replace us<N> with ui<N> for unsigned immediate.
	117	replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
	118	displacements (respectively).
	119	replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
	120	(instruction type): Add NO_TYPE_INS.
	121	(instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
	122	(operand_entry): New field - 'flags'.
	123	(operand flags): New.
	124
	125	2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
	126	* crx.h (operand_type): Remove redundant types i3, i4,
	127	i5, i8, i12.
	128	Add new unsigned immediate types us3, us4, us5, us16.
	129
bc4bd9ab MK	130	2005-04-12 Mark Kettenis <kettenis@gnu.org>
	131
	132	* i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
	133	adjust them accordingly.
	134
373ff435 JB	135	2005-04-01 Jan Beulich <jbeulich@novell.com>
	136
	137	* i386.h (i386_optab): Add rdtscp.
	138
4cc91dba L	139	2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
	140
	141	* i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca AS	142	between memory and segment register. Allow movq for moving between
418a8fca AS	143	general-purpose register and segment register.
4cc91dba	144
9ae09ff9 JB	145	2005-02-09 Jan Beulich <jbeulich@novell.com>
	146
	147	PR gas/707
	148	* i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
	149	FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
	150	fnstsw.
	151
90219bd0 AO	152	2005-01-25 Alexandre Oliva <aoliva@redhat.com>
	153
	154	2004-11-10 Alexandre Oliva <aoliva@redhat.com>
	155	* cgen.h (enum cgen_parse_operand_type): Add
	156	CGEN_PARSE_OPERAND_SYMBOLIC.
	157
239cb185 FF	158	2005-01-21 Fred Fish <fnf@specifixinc.com>
	159
	160	* mips.h: Change INSN_ALIAS to INSN2_ALIAS.
	161	Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
	162	Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
	163
dc9a9f39 FF	164	2005-01-19 Fred Fish <fnf@specifixinc.com>
	165
	166	* mips.h (struct mips_opcode): Add new pinfo2 member.
	167	(INSN_ALIAS): New define for opcode table entries that are
	168	specific instances of another entry, such as 'move' for an 'or'
	169	with a zero operand.
	170	(INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
	171	(INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
	172
98e7aba8 ILT	173	2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
	174
	175	* mips.h (CPU_RM9000): Define.
	176	(OPCODE_IS_MEMBER): Handle CPU_RM9000.
	177
37edbb65 JB	178	2004-11-25 Jan Beulich <jbeulich@novell.com>
	179
	180	* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
	181	to/from test registers are illegal in 64-bit mode. Add missing
	182	NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
	183	(previously one had to explicitly encode a rex64 prefix). Re-enable
	184	lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
	185	support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
	186
	187	2004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e JB	188
	189	* i386.h (i386_optab): paddq and psubq, even in their MMX form, are
	190	available only with SSE2. Change the MMX additions introduced by SSE
	191	and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
	192	instructions by their now designated identifier (since combining i686
	193	and 3DNow! does not really imply 3DNow!A).
	194
f5c7edf4 AM	195	2004-11-19 Alan Modra <amodra@bigpond.net.au>
	196
	197	* msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
	198	struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
	199
7499d566 NC	200	2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
	201	Vineet Sharma <vineets@noida.hcltech.com>
	202
	203	* maxq.h: New file: Disassembly information for the maxq port.
	204
bcb9eebe L	205	2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
	206
	207	* i386.h (i386_optab): Put back "movzb".
	208
94bb3d38 HPN	209	2004-11-04 Hans-Peter Nilsson <hp@axis.com>
	210
	211	* cris.h (enum cris_insn_version_usage): Tweak formatting and
	212	comments. Remove member cris_ver_sim. Add members
	213	cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
	214	cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
	215	(struct cris_support_reg, struct cris_cond15): New types.
	216	(cris_conds15): Declare.
	217	(JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
	218	(NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
	219	(NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
	220	(NOP_Z_BITS): Define in terms of NOP_OPCODE.
	221	(cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
	222	SIZE_FIELD_UNSIGNED.
	223
37edbb65	224	2004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a JB	225
	226	* i386.h (sldx_Suf): Remove.
	227	(FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
	228	(q_FP): Define, implying no REX64.
	229	(x_FP, sl_FP): Imply FloatMF.
	230	(i386_optab): Split reg and mem forms of moving from segment registers
	231	so that the memory forms can ignore the 16-/32-bit operand size
	232	distinction. Adjust a few others for Intel mode. Remove *FP uses from
	233	all non-floating-point instructions. Unite 32- and 64-bit forms of
	234	movsx, movzx, and movd. Adjust floating point operations for the above
	235	changes to the *FP macros. Add DefaultSize to floating point control
	236	insns operating on larger memory ranges. Remove left over comments
	237	hinting at certain insns being Intel-syntax ones where the ones
	238	actually meant are already gone.
	239
48c9f030 NC	240	2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
	241
	242	* crx.h: Add COPS_REG_INS - Coprocessor Special register
	243	instruction type.
	244
0dd132b6 NC	245	2004-09-30 Paul Brook <paul@codesourcery.com>
	246
	247	* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
	248	(ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
	249
23794b24 MM	250	2004-09-11 Theodore A. Roth <troth@openavr.org>
	251
	252	* avr.h: Add support for
	253	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
	254
2a309db0 AM	255	2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
	256
	257	* ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
	258
b18c562e NC	259	2004-08-24 Dmitry Diky <diwil@spec.ru>
	260
	261	* msp430.h (msp430_opc): Add new instructions.
	262	(msp430_rcodes): Declare new instructions.
	263	(msp430_hcodes): Likewise..
	264
45d313cd NC	265	2004-08-13 Nick Clifton <nickc@redhat.com>
	266
	267	PR/301
	268	* h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
	269	processors.
	270
30d1c836 ML	271	2004-08-30 Michal Ludvig <mludvig@suse.cz>
	272
	273	* i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
	274
9a45f1c2 L	275	2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
	276
	277	* i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
	278
543613e9 NC	279	2004-07-21 Jan Beulich <jbeulich@novell.com>
	280
	281	* i386.h: Adjust instruction descriptions to better match the
	282	specification.
	283
b781e558 RE	284	2004-07-16 Richard Earnshaw <rearnsha@arm.com>
	285
	286	* arm.h: Remove all old content. Replace with architecture defines
	287	from gas/config/tc-arm.c.
	288
8577e690 AS	289	2004-07-09 Andreas Schwab <schwab@suse.de>
	290
	291	* m68k.h: Fix comment.
	292
1fe1f39c NC	293	2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
	294
	295	* crx.h: New file.
	296
1d9f512f AM	297	2004-06-24 Alan Modra <amodra@bigpond.net.au>
	298
	299	* i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
	300
be8c092b NC	301	2004-05-24 Peter Barada <peter@the-baradas.com>
	302
	303	* m68k.h: Add 'size' to m68k_opcode.
	304
6b6e92f4 NC	305	2004-05-05 Peter Barada <peter@the-baradas.com>
	306
	307	* m68k.h: Switch from ColdFire chip name to core variant.
	308
	309	2004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b NC	310
	311	* m68k.h: Add mcfmac/mcfemac definitions. Update operand
	312	descriptions for new EMAC cases.
	313	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
	314	handle Motorola MAC syntax.
	315	Allow disassembly of ColdFire V4e object files.
	316
fdd12ef3 AM	317	2004-03-16 Alan Modra <amodra@bigpond.net.au>
	318
	319	* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
	320
3922a64c L	321	2004-03-12 Jakub Jelinek <jakub@redhat.com>
	322
	323	* i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
	324
1f45d988 ML	325	2004-03-12 Michal Ludvig <mludvig@suse.cz>
	326
	327	* i386.h (i386_optab): Added xstore as an alias for xstorerng.
	328
0f10071e ML	329	2004-03-12 Michal Ludvig <mludvig@suse.cz>
	330
	331	* i386.h (i386_optab): Added xstore/xcrypt insns.
	332
3255318a NC	333	2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
	334
	335	* h8300.h (32bit ldc/stc): Add relaxing support.
	336
ca9a79a1	337	2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3	338
ca9a79a1 NC	339	* h8300.h (BITOP): Pass MEMRELAX flag.
ca9a79a1 NC	340
875a0b14 NC	341	2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
	342
	343	* h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
	344	except for the H8S.
252b5132	345
c9e214e5	346	For older changes see ChangeLog-9103
252b5132 RH	347	\f
252b5132 RH	348	Local Variables:
c9e214e5 AM	349	mode: change-log
	350	left-margin: 8
	351	fill-column: 74
252b5132 RH	352	version-control: never
252b5132 RH	353	End: