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[ARM] Add support for ARMv8.1 PAN extension
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
ddfded2f
MW		 12015-06-02 Matthew Wahab <matthew.wahab@arm.com>
2
3 * arm.h (ARM_EXT2_PAN): New.
4 (ARM_FEATURE_CORE_HIGH): New.
5
1af1dd51
MW		 62015-06-02 Matthew Wahab <matthew.wahab@arm.com>
7
8 * arm.h (ARM_FEATURE_ALL): New.
9
9e1f0fa7
MW		 102015-06-02 Matthew Wahab <matthew.wahab@arm.com>
11
12 * aarch64.h (AARCH64_FEATURE_RDMA): New.
13
290806fd
MW		 142015-06-02 Matthew Wahab <matthew.wahab@arm.com>
15
16 * aarch64.h (AARCH64_FEATURE_LOR): New.
17
f21cce2c
MW		 182015-06-01 Matthew Wahab <matthew.wahab@arm.com>
19
20 * aarch64.h (AARCH64_FEATURE_PAN): New.
21 (aarch64_sys_reg_supported_p): Declare.
22 (aarch64_pstatefield_supported_p): Declare.
23
0952813b
DD		 242015-04-30 DJ Delorie <dj@redhat.com>
25
26 * rl78.h (RL78_Dis_Isa): New.
27 (rl78_decode_opcode): Add ISA parameter.
28
823d2571
TG		 292015-03-24 Terry Guo <terry.guo@arm.com>
30
31 * arm.h (arm_feature_set): Extended to provide more available bits.
32 (ARM_ANY): Updated to follow above new definition.
33 (ARM_CPU_HAS_FEATURE): Likewise.
34 (ARM_CPU_IS_ANY): Likewise.
35 (ARM_MERGE_FEATURE_SETS): Likewise.
36 (ARM_CLEAR_FEATURE): Likewise.
37 (ARM_FEATURE): Likewise.
38 (ARM_FEATURE_COPY): New macro.
39 (ARM_FEATURE_EQUAL): Likewise.
40 (ARM_FEATURE_ZERO): Likewise.
41 (ARM_FEATURE_CORE_EQUAL): Likewise.
42 (ARM_FEATURE_LOW): Likewise.
43 (ARM_FEATURE_CORE_LOW): Likewise.
44 (ARM_FEATURE_CORE_COPROC): Likewise.
45
f63c1776
PA		 462015-02-19 Pedro Alves <palves@redhat.com>
47
48 * cgen.h [__cplusplus]: Wrap in extern "C".
49 * msp430-decode.h [__cplusplus]: Likewise.
50 * nios2.h [__cplusplus]: Likewise.
51 * rl78.h [__cplusplus]: Likewise.
52 * rx.h [__cplusplus]: Likewise.
53 * tilegx.h [__cplusplus]: Likewise.
54
3f8107ab
AM		 552015-01-28 James Bowman <james.bowman@ftdichip.com>
56
57 * ft32.h: New file.
58
1e2e8c52
AK		 592015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
60
61 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
62
b90efa5b
AM		 632015-01-01 Alan Modra <amodra@gmail.com>
64
65 Update year range in copyright notice of all files.
66
bffb6004
AG		 672014-12-27 Anthony Green <green@moxielogic.com>
68
69 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
70 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
71
1945cfa5
EB		 722014-12-06 Eric Botcazou <ebotcazou@adacore.com>
73
74 * visium.h: New file.
75
d306ce58
SL		 762014-11-28 Sandra Loosemore <sandra@codesourcery.com>
77
78 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
79 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
80 (NIOS2_INSN_OPTARG): Renumber.
81
b4714c7c
SL		 822014-11-06 Sandra Loosemore <sandra@codesourcery.com>
83
84 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
85 declaration. Fix obsolete comment.
86
96ba4233
SL		 872014-10-23 Sandra Loosemore <sandra@codesourcery.com>
88
89 * nios2.h (enum iw_format_type): New.
90 (struct nios2_opcode): Update comments. Add size and format fields.
91 (NIOS2_INSN_OPTARG): New.
92 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
93 (struct nios2_reg): Add regtype field.
94 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
95 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
96 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
97 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
98 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
99 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
100 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
101 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
102 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
103 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
104 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
105 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
106 (OP_MASK_OP, OP_SH_OP): Delete.
107 (OP_MASK_IOP, OP_SH_IOP): Delete.
108 (OP_MASK_IRD, OP_SH_IRD): Delete.
109 (OP_MASK_IRT, OP_SH_IRT): Delete.
110 (OP_MASK_IRS, OP_SH_IRS): Delete.
111 (OP_MASK_ROP, OP_SH_ROP): Delete.
112 (OP_MASK_RRD, OP_SH_RRD): Delete.
113 (OP_MASK_RRT, OP_SH_RRT): Delete.
114 (OP_MASK_RRS, OP_SH_RRS): Delete.
115 (OP_MASK_JOP, OP_SH_JOP): Delete.
116 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
117 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
118 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
119 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
120 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
121 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
122 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
123 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
124 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
125 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
126 (OP_MASK_<insn>, OP_MASK): Delete.
127 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
128 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
129 Include nios2r1.h to define new instruction opcode constants
130 and accessors.
131 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
132 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
133 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
134 (NUMOPCODES, NUMREGISTERS): Delete.
135 * nios2r1.h: New file.
136
0b6be415
JM		 1372014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
138
139 * sparc.h (HWCAP2_VIS3B): Documentation improved.
140
3d68f91c
JM		 1412014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
142
143 * sparc.h (sparc_opcode): new field `hwcaps2'.
144 (HWCAP2_FJATHPLUS): New define.
145 (HWCAP2_VIS3B): Likewise.
146 (HWCAP2_ADP): Likewise.
147 (HWCAP2_SPARC5): Likewise.
148 (HWCAP2_MWAIT): Likewise.
149 (HWCAP2_XMPMUL): Likewise.
150 (HWCAP2_XMONT): Likewise.
151 (HWCAP2_NSEC): Likewise.
152 (HWCAP2_FJATHHPC): Likewise.
153 (HWCAP2_FJDES): Likewise.
154 (HWCAP2_FJAES): Likewise.
155 Document the new operand kind `{', corresponding to the mcdper
156 ancillary state register.
157 Document the new operand kind }, which represents frsd floating
158 point registers (double precision) which must be the same than
159 frs1 in its containing instruction.
160
40c7a7cb
KLC		 1612014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
162
163 * nds32.h: Add new opcode declaration.
164
7361da2c
AB		 1652014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
166 Matthew Fortune <matthew.fortune@imgtec.com>
167
168 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
169 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
170 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
171 +I, +O, +R, +:, +\, +", +;
172 (mips_check_prev_operand): New struct.
173 (INSN2_FORBIDDEN_SLOT): New define.
174 (INSN_ISA32R6): New define.
175 (INSN_ISA64R6): New define.
176 (INSN_UPTO32R6): New define.
177 (INSN_UPTO64R6): New define.
178 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
179 (ISA_MIPS32R6): New define.
180 (ISA_MIPS64R6): New define.
181 (CPU_MIPS32R6): New define.
182 (CPU_MIPS64R6): New define.
183 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
184
ee804238
JW		 1852014-09-03 Jiong Wang <jiong.wang@arm.com>
186
187 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
188 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
189 (aarch64_insn_class): Add lse_atomic.
190 (F_LSE_SZ): New field added.
191 (opcode_has_special_coder): Recognize F_LSE_SZ.
192
5575639b
MR		 1932014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
194
195 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
196 over to `+J'.
197
43885403
MF		 1982014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
199
200 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
201 (INSN_LOAD_COPROC): New define.
202 (INSN_COPROC_MOVE_DELAY): Rename to...
203 (INSN_COPROC_MOVE): New define.
204
f36e8886
BS		 2052014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
206 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
207 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
208 Soundararajan <Sounderarajan.D@atmel.com>
209
210 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
211 (AVR_ISA_2xxxa): Define ISA without LPM.
212 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
213 Add doc for contraint used in 16 bit lds/sts.
214 Adjust ISA group for icall, ijmp, pop and push.
215 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
216
00b32ff2
NC		 2172014-05-19 Nick Clifton <nickc@redhat.com>
218
219 * msp430.h (struct msp430_operand_s): Add vshift field.
220
ae52f483
AB		 2212014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
222
223 * mips.h (INSN_ISA_MASK): Updated.
224 (INSN_ISA32R3): New define.
225 (INSN_ISA32R5): New define.
226 (INSN_ISA64R3): New define.
227 (INSN_ISA64R5): New define.
228 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
229 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
230 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
231 mips64r5.
232 (INSN_UPTO32R3): New define.
233 (INSN_UPTO32R5): New define.
234 (INSN_UPTO64R3): New define.
235 (INSN_UPTO64R5): New define.
236 (ISA_MIPS32R3): New define.
237 (ISA_MIPS32R5): New define.
238 (ISA_MIPS64R3): New define.
239 (ISA_MIPS64R5): New define.
240 (CPU_MIPS32R3): New define.
241 (CPU_MIPS32R5): New define.
242 (CPU_MIPS64R3): New define.
243 (CPU_MIPS64R5): New define.
244
3efe9ec5
RS		 2452014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
246
247 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
248
73589c9d
CS		 2492014-04-22 Christian Svensson <blue@cmd.nu>
250
251 * or32.h: Delete.
252
4b95cf5c
AM		 2532014-03-05 Alan Modra <amodra@gmail.com>
254
255 Update copyright years.
256
e269fea7
AB		 2572013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
258
259 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
260 microMIPS.
261
35c08157
KLC		 2622013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
263 Wei-Cheng Wang <cole945@gmail.com>
264
265 * nds32.h: New file for Andes NDS32.
266
594d8fa8
MF		 2672013-12-07 Mike Frysinger <vapier@gentoo.org>
268
269 * bfin.h: Remove +x file mode.
270
87b8eed7
YZ		 2712013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
272
273 * aarch64.h (aarch64_pstatefields): Change element type to
274 aarch64_sys_reg.
275
c9fb6e58
YZ		 2762013-11-18 Renlin Li <Renlin.Li@arm.com>
277
278 * arm.h (ARM_AEXT_V7VE): New define.
279 (ARM_ARCH_V7VE): New define.
280 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
281
a203d9b7
YZ		 2822013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
283
284 Revert
285
286 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
287
288 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
289 (aarch64_sys_reg_writeonly_p): Ditto.
290
75468c93
YZ		 2912013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
292
293 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
294 (aarch64_sys_reg_writeonly_p): Ditto.
295
49eec193
YZ		 2962013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
297
298 * aarch64.h (aarch64_sys_reg): New typedef.
299 (aarch64_sys_regs): Change to define with the new type.
300 (aarch64_sys_reg_deprecated_p): Declare.
301
68a64283
YZ		 3022013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
303
304 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
305 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
306
387a82f1
CF		 3072013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
308
309 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
310 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
311 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
312 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
313 For MIPS, update extension character sequences after +.
314 (ASE_MSA): New define.
315 (ASE_MSA64): New define.
316 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
317 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
318 For microMIPS, update extension character sequences after +.
319
9aff4b7a
NC		 3202013-08-23 Yuri Chornoivan <yurchor@ukr.net>
321
322 PR binutils/15834
323 * i960.h: Fix typos.
324
e423441d
RS		 3252013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
326
327 * mips.h: Remove references to "+I" and imm2_expr.
328
5e0dc5ba
RS		 3292013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
330
331 * mips.h (M_DEXT, M_DINS): Delete.
332
0f35dbc4
RS		 3332013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
334
335 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
336 (mips_optional_operand_p): New function.
337
14daeee3
RS		 3382013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
339 Richard Sandiford <rdsandiford@googlemail.com>
340
341 * mips.h: Document new VU0 operand characters.
342 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
343 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
344 (OP_REG_R5900_ACC): New mips_reg_operand_types.
345 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
346 (mips_vu0_channel_mask): Declare.
347
3ccad066
RS		 3482013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
349
350 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
351 (mips_int_operand_min, mips_int_operand_max): New functions.
352 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
353
fc76e730
RS		 3542013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
355
356 * mips.h (mips_decode_reg_operand): New function.
357 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
358 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
359 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
360 New macros.
361 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
362 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
363 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
364 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
365 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
366 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
367 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
368 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
369 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
370 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
371 macros to cover the gaps.
372 (INSN2_MOD_SP): Replace with...
373 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
374 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
375 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
376 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
377 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
378 Delete.
379
26545944
RS		 3802013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
381
382 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
383 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
384 (MIPS16_INSN_COND_BRANCH): Delete.
385
7e8b059b
L		 3862013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
387 Kirill Yukhin <kirill.yukhin@intel.com>
388 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
389
390 * i386.h (BND_PREFIX_OPCODE): New.
391
c3c07478
RS		 3922013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
393
394 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
395 OP_SAVE_RESTORE_LIST.
396 (decode_mips16_operand): Declare.
397
ab902481
RS		 3982013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
399
400 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
401 (mips_operand, mips_int_operand, mips_mapped_int_operand)
402 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
403 (mips_pcrel_operand): New structures.
404 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
405 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
406 (decode_mips_operand, decode_micromips_operand): Declare.
407
cc537e56
RS		 4082013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
409
410 * mips.h: Document MIPS16 "I" opcode.
411
f2ae14a1
RS		 4122013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
413
414 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
415 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
416 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
417 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
418 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
419 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
420 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
421 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
422 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
423 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
424 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
425 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
426 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
427 Rename to...
428 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
429 (M_USD_AB): ...these.
430
5c324c16
RS		 4312013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
432
433 * mips.h: Remove documentation of "[" and "]". Update documentation
434 of "k" and the MDMX formats.
435
23e69e47
RS		 4362013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
437
438 * mips.h: Update documentation of "+s" and "+S".
439
27c5c572
RS		 4402013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
441
442 * mips.h: Document "+i".
443
e76ff5ab
RS		 4442013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
445
446 * mips.h: Remove "mi" documentation. Update "mh" documentation.
447 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
448 Delete.
449 (INSN2_WRITE_GPR_MHI): Rename to...
450 (INSN2_WRITE_GPR_MH): ...this.
451
fa7616a4
RS		 4522013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
453
454 * mips.h: Remove documentation of "+D" and "+T".
455
18870af7
RS		 4562013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
457
458 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
459 Use "source" rather than "destination" for microMIPS "G".
460
833794fc
MR		 4612013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
462
463 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
464 values.
465
c3678916
RS		 4662013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
467
468 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
469
7f3c4072
CM		 4702013-06-17 Catherine Moore <clm@codesourcery.com>
471 Maciej W. Rozycki <macro@codesourcery.com>
472 Chao-Ying Fu <fu@mips.com>
473
474 * mips.h (OP_SH_EVAOFFSET): Define.
475 (OP_MASK_EVAOFFSET): Define.
476 (INSN_ASE_MASK): Delete.
477 (ASE_EVA): Define.
478 (M_CACHEE_AB, M_CACHEE_OB): New.
479 (M_LBE_OB, M_LBE_AB): New.
480 (M_LBUE_OB, M_LBUE_AB): New.
481 (M_LHE_OB, M_LHE_AB): New.
482 (M_LHUE_OB, M_LHUE_AB): New.
483 (M_LLE_AB, M_LLE_OB): New.
484 (M_LWE_OB, M_LWE_AB): New.
485 (M_LWLE_AB, M_LWLE_OB): New.
486 (M_LWRE_AB, M_LWRE_OB): New.
487 (M_PREFE_AB, M_PREFE_OB): New.
488 (M_SCE_AB, M_SCE_OB): New.
489 (M_SBE_OB, M_SBE_AB): New.
490 (M_SHE_OB, M_SHE_AB): New.
491 (M_SWE_OB, M_SWE_AB): New.
492 (M_SWLE_AB, M_SWLE_OB): New.
493 (M_SWRE_AB, M_SWRE_OB): New.
494 (MICROMIPSOP_SH_EVAOFFSET): Define.
495 (MICROMIPSOP_MASK_EVAOFFSET): Define.
496
0c8fe7cf
SL		 4972013-06-12 Sandra Loosemore <sandra@codesourcery.com>
498
499 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
500
c77c0862
RS		 5012013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
502
503 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
504
b015e599
AP		 5052013-05-09 Andrew Pinski <apinski@cavium.com>
506
507 * mips.h (OP_MASK_CODE10): Correct definition.
508 (OP_SH_CODE10): Likewise.
509 Add a comment that "+J" is used now for OP_*CODE10.
510 (INSN_ASE_MASK): Update.
511 (INSN_VIRT): New macro.
512 (INSN_VIRT64): New macro
513
13761a11
NC		 5142013-05-02 Nick Clifton <nickc@redhat.com>
515
516 * msp430.h: Add patterns for MSP430X instructions.
517
0afd1215
DM		 5182013-04-06 David S. Miller <davem@davemloft.net>
519
520 * sparc.h (F_PREFERRED): Define.
521 (F_PREF_ALIAS): Define.
522
41702d50
NC		 5232013-04-03 Nick Clifton <nickc@redhat.com>
524
525 * v850.h (V850_INVERSE_PCREL): Define.
526
e21e1a51
NC		 5272013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
528
529 PR binutils/15068
530 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
531
51dcdd4d
NC		 5322013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
533
534 PR binutils/15068
535 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
536 Add 16-bit opcodes.
537 * tic6xc-opcode-table.h: Add 16-bit insns.
538 * tic6x.h: Add support for 16-bit insns.
539
81f5558e
NC		 5402013-03-21 Michael Schewe <michael.schewe@gmx.net>
541
542 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
543 and mov.b/w/l Rs,@(d:32,ERd).
544
165546ad
NC		 5452013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
546
547 PR gas/15082
548 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
549 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
550 tic6x_operand_xregpair operand coding type.
551 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
552 opcode field, usu ORXREGD1324 for the src2 operand and remove the
553 TIC6X_FLAG_NO_CROSS.
554
795b8e6b
NC		 5552013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
556
557 PR gas/15095
558 * tic6x.h (enum tic6x_coding_method): Add
559 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
560 separately the msb and lsb of a register pair. This is needed to
561 encode the opcodes in the same way as TI assembler does.
562 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
563 and rsqrdp opcodes to use the new field coding types.
564
dd5181d5
KT		 5652013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
566
567 * arm.h (CRC_EXT_ARMV8): New constant.
568 (ARCH_CRC_ARMV8): New macro.
569
e60bb1dd
YZ		 5702013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
571
572 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
573
36591ba1
SL		 5742013-02-06 Sandra Loosemore <sandra@codesourcery.com>
575 Andrew Jenner <andrew@codesourcery.com>
576
577 Based on patches from Altera Corporation.
578
579 * nios2.h: New file.
580
e30181a5
YZ		 5812013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
582
583 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
584
0c9573f4
NC		 5852013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
586
587 PR gas/15069
588 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
589
981dc7f1
NC		 5902013-01-24 Nick Clifton <nickc@redhat.com>
591
592 * v850.h: Add e3v5 support.
593
f5555712
YZ		 5942013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
595
596 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
597
5817ffd1
PB		 5982013-01-10 Peter Bergner <bergner@vnet.ibm.com>
599
600 * ppc.h (PPC_OPCODE_POWER8): New define.
601 (PPC_OPCODE_HTM): Likewise.
602
a3c62988
NC		 6032013-01-10 Will Newton <will.newton@imgtec.com>
604
605 * metag.h: New file.
606
73335eae
NC		 6072013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
608
609 * cr16.h (make_instruction): Rename to cr16_make_instruction.
610 (match_opcode): Rename to cr16_match_opcode.
611
e407c74b
NC		 6122013-01-04 Juergen Urban <JuergenUrban@gmx.de>
613
614 * mips.h: Add support for r5900 instructions including lq and sq.
615
bab4becb
NC		 6162013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
617
618 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
619 (make_instruction,match_opcode): Added function prototypes.
620 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
621
776fc418
AM		 6222012-11-23 Alan Modra <amodra@gmail.com>
623
624 * ppc.h (ppc_parse_cpu): Update prototype.
625
f05682d4
DA		 6262012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
627
628 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
629 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
630
cfc72779
AK		 6312012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
632
633 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
634
b3e14eda
L		 6352012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
636
637 * ia64.h (ia64_opnd): Add new operand types.
638
2c63854f
DM		 6392012-08-21 David S. Miller <davem@davemloft.net>
640
641 * sparc.h (F3F4): New macro.
642
a06ea964 6432012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 644 Laurent Desnogues <laurent.desnogues@arm.com>
645 Jim MacArthur <jim.macarthur@arm.com>
646 Marcus Shawcroft <marcus.shawcroft@arm.com>
647 Nigel Stephens <nigel.stephens@arm.com>
648 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
649 Richard Earnshaw <rearnsha@arm.com>
650 Sofiane Naci <sofiane.naci@arm.com>
651 Tejas Belagod <tejas.belagod@arm.com>
652 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 653
654 * aarch64.h: New file.
655
35d0a169 6562012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 657 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 658
659 * mips.h (mips_opcode): Add the exclusions field.
660 (OPCODE_IS_MEMBER): Remove macro.
661 (cpu_is_member): New inline function.
662 (opcode_is_member): Likewise.
663
03f66e8a 6642012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 665 Catherine Moore <clm@codesourcery.com>
666 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 667
668 * mips.h: Document microMIPS DSP ASE usage.
669 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
670 microMIPS DSP ASE support.
671 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
672 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
673 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
674 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
675 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
676 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
677 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
678
9d7b4c23
MR		 6792012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
680
681 * mips.h: Fix a typo in description.
682
76e879f8
NC		 6832012-06-07 Georg-Johann Lay <avr@gjlay.de>
684
685 * avr.h: (AVR_ISA_XCH): New define.
686 (AVR_ISA_XMEGA): Use it.
687 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
688
6927f982
NC		 6892012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
690
691 * m68hc11.h: Add XGate definitions.
692 (struct m68hc11_opcode): Add xg_mask field.
693
b9c361e0
JL		 6942012-05-14 Catherine Moore <clm@codesourcery.com>
695 Maciej W. Rozycki <macro@codesourcery.com>
696 Rhonda Wittels <rhonda@codesourcery.com>
697
6927f982 698 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 699 (PPC_OP_SA): New macro.
700 (PPC_OP_SE_VLE): New macro.
701 (PPC_OP): Use a variable shift amount.
702 (powerpc_operand): Update comments.
703 (PPC_OPSHIFT_INV): New macro.
704 (PPC_OPERAND_CR): Replace with...
705 (PPC_OPERAND_CR_BIT): ...this and
706 (PPC_OPERAND_CR_REG): ...this.
707
708
f6c1a2d5
NC		 7092012-05-03 Sean Keys <skeys@ipdatasys.com>
710
711 * xgate.h: Header file for XGATE assembler.
712
ec668d69
DM		 7132012-04-27 David S. Miller <davem@davemloft.net>
714
6cda1326
DM		 715 * sparc.h: Document new arg code' )' for crypto RS3
716 immediates.
717
ec668d69
DM		 718 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
719 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
720 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
721 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
722 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
723 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
724 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
725 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
726 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
727 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
728 HWCAP_CBCOND, HWCAP_CRC32): New defines.
729
aea77599
AM		 7302012-03-10 Edmar Wienskoski <edmar@freescale.com>
731
732 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
733
1f42f8b3
AM		 7342012-02-27 Alan Modra <amodra@gmail.com>
735
736 * crx.h (cst4_map): Update declaration.
737
6f7be959
WL		 7382012-02-25 Walter Lee <walt@tilera.com>
739
740 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
741 TILEGX_OPC_LD_TLS.
742 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
743 TILEPRO_OPC_LW_TLS_SN.
744
42164a71
L		 7452012-02-08 H.J. Lu <hongjiu.lu@intel.com>
746
747 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
748 (XRELEASE_PREFIX_OPCODE): Likewise.
749
432233b3 7502011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 751 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 752
753 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
754 (INSN_OCTEON2): New macro.
755 (CPU_OCTEON2): New macro.
756 (OPCODE_IS_MEMBER): Add Octeon2.
757
dd6a37e7
AP		 7582011-11-29 Andrew Pinski <apinski@cavium.com>
759
760 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
761 (INSN_OCTEONP): New macro.
762 (CPU_OCTEONP): New macro.
763 (OPCODE_IS_MEMBER): Add Octeon+.
764 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
765
99c513f6
DD		 7662011-11-01 DJ Delorie <dj@redhat.com>
767
768 * rl78.h: New file.
769
26f85d7a
MR		 7702011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
771
772 * mips.h: Fix a typo in description.
773
9e8c70f9
DM		 7742011-09-21 David S. Miller <davem@davemloft.net>
775
776 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
777 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
778 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
779 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
780
dec0624d 7812011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 782 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 783
784 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
785 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
786 (INSN_ASE_MASK): Add the MCU bit.
787 (INSN_MCU): New macro.
788 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
789 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
790
2b0c8b40
MR		 7912011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
792
793 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
794 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
795 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
796 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
797 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
798 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
799 (INSN2_READ_GPR_MMN): Likewise.
800 (INSN2_READ_FPR_D): Change the bit used.
801 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
802 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
803 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
804 (INSN2_COND_BRANCH): Likewise.
805 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
806 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
807 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
808 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
809 (INSN2_MOD_GPR_MN): Likewise.
810
ea783ef3
DM		 8112011-08-05 David S. Miller <davem@davemloft.net>
812
813 * sparc.h: Document new format codes '4', '5', and '('.
814 (OPF_LOW4, RS3): New macros.
815
7c176fa8
MR		 8162011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
817
818 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
819 order of flags documented.
820
2309ddf2
MR		 8212011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
822
823 * mips.h: Clarify the description of microMIPS instruction
824 manipulation macros.
825 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
826
df58fc94 8272011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 828 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 829
830 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
831 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
832 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
833 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
834 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
835 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
836 (OP_MASK_RS3, OP_SH_RS3): Likewise.
837 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
838 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
839 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
840 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
841 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
842 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
843 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
844 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
845 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
846 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
847 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
848 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
849 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
850 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
851 (INSN_WRITE_GPR_S): New macro.
852 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
853 (INSN2_READ_FPR_D): Likewise.
854 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
855 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
856 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
857 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
858 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
859 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
860 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
861 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
862 (CPU_MICROMIPS): New macro.
863 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
864 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
865 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
866 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
867 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
868 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
869 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
870 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
871 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
872 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
873 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
874 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
875 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
876 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
877 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
878 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
879 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
880 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
881 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
882 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
883 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
884 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
885 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
886 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
887 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
888 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
889 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
890 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
891 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
892 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
893 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
894 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
895 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
896 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
897 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
898 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
899 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
900 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
901 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
902 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
903 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
904 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
905 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
906 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
907 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
908 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
909 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
910 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
911 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
912 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
913 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
914 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
915 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
916 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
917 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
918 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
919 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
920 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
921 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
922 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
923 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
924 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
925 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
926 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
927 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
928 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
929 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
930 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
931 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
932 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
933 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
934 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
935 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
936 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
937 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
938 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
939 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
940 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
941 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
942 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
943 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
944 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
945 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
946 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
947 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
948 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
949 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
950 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
951 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
952 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
953 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
954 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
955 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
956 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
957 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
958 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
959 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
960 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
961 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
962 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
963 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
964 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
965 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
966 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
967 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
968 (micromips_opcodes): New declaration.
969 (bfd_micromips_num_opcodes): Likewise.
970
bcd530a7
RS		 9712011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
972
973 * mips.h (INSN_TRAP): Rename to...
974 (INSN_NO_DELAY_SLOT): ... this.
975 (INSN_SYNC): Remove macro.
976
2dad5a91
EW		 9772011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
978
979 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
980 a duplicate of AVR_ISA_SPM.
981
5d73b1f1
NC		 9822011-07-01 Nick Clifton <nickc@redhat.com>
983
984 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
985
ef26d60e
MF		 9862011-06-18 Robin Getz <robin.getz@analog.com>
987
988 * bfin.h (is_macmod_signed): New func
989
8fb8dca7
MF		 9902011-06-18 Mike Frysinger <vapier@gentoo.org>
991
992 * bfin.h (is_macmod_pmove): Add missing space before func args.
993 (is_macmod_hmove): Likewise.
994
aa137e4d
NC		 9952011-06-13 Walter Lee <walt@tilera.com>
996
997 * tilegx.h: New file.
998 * tilepro.h: New file.
999
3b2f0793
PB		 10002011-05-31 Paul Brook <paul@codesourcery.com>
1001
aa137e4d
NC		 1002 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1003
10042011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1005
1006 * s390.h: Replace S390_OPERAND_REG_EVEN with
1007 S390_OPERAND_REG_PAIR.
1008
10092011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1010
1011 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1012
ac7f631b
NC		 10132011-04-18 Julian Brown <julian@codesourcery.com>
1014
1015 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1016
84701018
NC		 10172011-04-11 Dan McDonald <dan@wellkeeper.com>
1018
1019 PR gas/12296
1020 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1021
8cc66334
EW		 10222011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1023
1024 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1025 New instruction set flags.
1026 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1027
3eebd5eb
MR		 10282011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1029
1030 * mips.h (M_PREF_AB): New enum value.
1031
26bb3ddd
MF		 10322011-02-12 Mike Frysinger <vapier@gentoo.org>
1033
89c0d58c
MR		 1034 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1035 M_IU): Define.
1036 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1037
dd76fcb8
MF		 10382011-02-11 Mike Frysinger <vapier@gentoo.org>
1039
1040 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1041
98d23bef
BS		 10422011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1043
1044 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1045 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1046
3c853d93
DA		 10472010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1048
1049 PR gas/11395
1050 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1051 "bb" entries.
1052
79676006
DA		 10532010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1054
1055 PR gas/11395
1056 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1057
1bec78e9
RS		 10582010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1059
1060 * mips.h: Update commentary after last commit.
1061
98675402
RS		 10622010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1063
1064 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1065 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1066 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1067
aa137e4d
NC		 10682010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1069
1070 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1071
435b94a4
RS		 10722010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1073
1074 * mips.h: Fix previous commit.
1075
d051516a
NC		 10762010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1077
1078 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1079 (INSN_LOONGSON_3A): Clear bit 31.
1080
251665fc
MGD		 10812010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1082
1083 PR gas/12198
1084 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1085 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1086 (ARM_ARCH_V6M_ONLY): New define.
1087
fd503541
NC		 10882010-11-11 Mingming Sun <mingm.sun@gmail.com>
1089
1090 * mips.h (INSN_LOONGSON_3A): Defined.
1091 (CPU_LOONGSON_3A): Defined.
1092 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1093
4469d2be
AM		 10942010-10-09 Matt Rice <ratmice@gmail.com>
1095
1096 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1097 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1098
90ec0d68
MGD		 10992010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1100
1101 * arm.h (ARM_EXT_VIRT): New define.
1102 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1103 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1104 Extensions.
1105
eea54501 11062010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1107
eea54501
MGD		 1108 * arm.h (ARM_AEXT_ADIV): New define.
1109 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1110
b2a5fbdc
MGD		 11112010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1112
1113 * arm.h (ARM_EXT_OS): New define.
1114 (ARM_AEXT_V6SM): Likewise.
1115 (ARM_ARCH_V6SM): Likewise.
1116
60e5ef9f
MGD		 11172010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1118
1119 * arm.h (ARM_EXT_MP): Add.
1120 (ARM_ARCH_V7A_MP): Likewise.
1121
73a63ccf
MF		 11222010-09-22 Mike Frysinger <vapier@gentoo.org>
1123
1124 * bfin.h: Declare pseudoChr structs/defines.
1125
ee99860a
MF		 11262010-09-21 Mike Frysinger <vapier@gentoo.org>
1127
1128 * bfin.h: Strip trailing whitespace.
1129
f9c7014e
DD		 11302010-07-29 DJ Delorie <dj@redhat.com>
1131
1132 * rx.h (RX_Operand_Type): Add TwoReg.
1133 (RX_Opcode_ID): Remove ediv and ediv2.
1134
93378652
DD		 11352010-07-27 DJ Delorie <dj@redhat.com>
1136
1137 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1138
1cd986c5
NC		 11392010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1140 Ina Pandit <ina.pandit@kpitcummins.com>
1141
1142 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1143 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1144 PROCESSOR_V850E2_ALL.
1145 Remove PROCESSOR_V850EA support.
1146 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1147 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1148 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1149 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1150 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1151 V850_OPERAND_PERCENT.
1152 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1153 V850_NOT_R0.
1154 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1155 and V850E_PUSH_POP
1156
9a2c7088
MR		 11572010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1158
1159 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1160 (MIPS16_INSN_BRANCH): Rename to...
1161 (MIPS16_INSN_COND_BRANCH): ... this.
1162
bdc70b4a
AM		 11632010-07-03 Alan Modra <amodra@gmail.com>
1164
1165 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1166 Renumber other PPC_OPCODE defines.
1167
f2bae120
AM		 11682010-07-03 Alan Modra <amodra@gmail.com>
1169
1170 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1171
360cfc9c
AM		 11722010-06-29 Alan Modra <amodra@gmail.com>
1173
1174 * maxq.h: Delete file.
1175
e01d869a
AM		 11762010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1177
1178 * ppc.h (PPC_OPCODE_E500): Define.
1179
f79e2745
CM		 11802010-05-26 Catherine Moore <clm@codesourcery.com>
1181
1182 * opcode/mips.h (INSN_MIPS16): Remove.
1183
2462afa1
JM		 11842010-04-21 Joseph Myers <joseph@codesourcery.com>
1185
1186 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1187
e4e42b45
NC		 11882010-04-15 Nick Clifton <nickc@redhat.com>
1189
1190 * alpha.h: Update copyright notice to use GPLv3.
1191 * arc.h: Likewise.
1192 * arm.h: Likewise.
1193 * avr.h: Likewise.
1194 * bfin.h: Likewise.
1195 * cgen.h: Likewise.
1196 * convex.h: Likewise.
1197 * cr16.h: Likewise.
1198 * cris.h: Likewise.
1199 * crx.h: Likewise.
1200 * d10v.h: Likewise.
1201 * d30v.h: Likewise.
1202 * dlx.h: Likewise.
1203 * h8300.h: Likewise.
1204 * hppa.h: Likewise.
1205 * i370.h: Likewise.
1206 * i386.h: Likewise.
1207 * i860.h: Likewise.
1208 * i960.h: Likewise.
1209 * ia64.h: Likewise.
1210 * m68hc11.h: Likewise.
1211 * m68k.h: Likewise.
1212 * m88k.h: Likewise.
1213 * maxq.h: Likewise.
1214 * mips.h: Likewise.
1215 * mmix.h: Likewise.
1216 * mn10200.h: Likewise.
1217 * mn10300.h: Likewise.
1218 * msp430.h: Likewise.
1219 * np1.h: Likewise.
1220 * ns32k.h: Likewise.
1221 * or32.h: Likewise.
1222 * pdp11.h: Likewise.
1223 * pj.h: Likewise.
1224 * pn.h: Likewise.
1225 * ppc.h: Likewise.
1226 * pyr.h: Likewise.
1227 * rx.h: Likewise.
1228 * s390.h: Likewise.
1229 * score-datadep.h: Likewise.
1230 * score-inst.h: Likewise.
1231 * sparc.h: Likewise.
1232 * spu-insns.h: Likewise.
1233 * spu.h: Likewise.
1234 * tic30.h: Likewise.
1235 * tic4x.h: Likewise.
1236 * tic54x.h: Likewise.
1237 * tic80.h: Likewise.
1238 * v850.h: Likewise.
1239 * vax.h: Likewise.
1240
40b36596
JM		 12412010-03-25 Joseph Myers <joseph@codesourcery.com>
1242
1243 * tic6x-control-registers.h, tic6x-insn-formats.h,
1244 tic6x-opcode-table.h, tic6x.h: New.
1245
c67a084a
NC		 12462010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1247
1248 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1249
466ef64f
AM		 12502010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1251
1252 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1253
1319d143
L		 12542010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1255
1256 * ia64.h (ia64_find_opcode): Remove argument name.
1257 (ia64_find_next_opcode): Likewise.
1258 (ia64_dis_opcode): Likewise.
1259 (ia64_free_opcode): Likewise.
1260 (ia64_find_dependency): Likewise.
1261
1fbb9298
DE		 12622009-11-22 Doug Evans <dje@sebabeach.org>
1263
1264 * cgen.h: Include bfd_stdint.h.
1265 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1266
ada65aa3
PB		 12672009-11-18 Paul Brook <paul@codesourcery.com>
1268
1269 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1270
9e3c6df6
PB		 12712009-11-17 Paul Brook <paul@codesourcery.com>
1272 Daniel Jacobowitz <dan@codesourcery.com>
1273
1274 * arm.h (ARM_EXT_V6_DSP): Define.
1275 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1276 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1277
0d734b5d
DD		 12782009-11-04 DJ Delorie <dj@redhat.com>
1279
1280 * rx.h (rx_decode_opcode) (mvtipl): Add.
1281 (mvtcp, mvfcp, opecp): Remove.
1282
62f3b8c8
PB		 12832009-11-02 Paul Brook <paul@codesourcery.com>
1284
1285 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1286 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1287 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1288 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1289 FPU_ARCH_NEON_VFP_V4): Define.
1290
ac1e9eca
DE		 12912009-10-23 Doug Evans <dje@sebabeach.org>
1292
1293 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1294 * cgen.h: Update. Improve multi-inclusion macro name.
1295
9fe54b1c
PB		 12962009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1297
1298 * ppc.h (PPC_OPCODE_476): Define.
1299
634b50f2
PB		 13002009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1301
1302 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1303
c7927a3c
NC		 13042009-09-29 DJ Delorie <dj@redhat.com>
1305
1306 * rx.h: New file.
1307
b961e85b
AM		 13082009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1309
1310 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1311
e0d602ec
BE		 13122009-09-21 Ben Elliston <bje@au.ibm.com>
1313
1314 * ppc.h (PPC_OPCODE_PPCA2): New.
1315
96d56e9f
NC		 13162009-09-05 Martin Thuresson <martin@mtme.org>
1317
1318 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1319
d3ce72d0
NC		 13202009-08-29 Martin Thuresson <martin@mtme.org>
1321
1322 * tic30.h (template): Rename type template to
1323 insn_template. Updated code to use new name.
1324 * tic54x.h (template): Rename type template to
1325 insn_template.
1326
824b28db
NH		 13272009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1328
1329 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1330
f865a31d
AG		 13312009-06-11 Anthony Green <green@moxielogic.com>
1332
1333 * moxie.h (MOXIE_F3_PCREL): Define.
1334 (moxie_form3_opc_info): Grow.
1335
0e7c7f11
AG		 13362009-06-06 Anthony Green <green@moxielogic.com>
1337
1338 * moxie.h (MOXIE_F1_M): Define.
1339
20135e4c
NC		 13402009-04-15 Anthony Green <green@moxielogic.com>
1341
1342 * moxie.h: Created.
1343
bcb012d3
DD		 13442009-04-06 DJ Delorie <dj@redhat.com>
1345
1346 * h8300.h: Add relaxation attributes to MOVA opcodes.
1347
69fe9ce5
AM		 13482009-03-10 Alan Modra <amodra@bigpond.net.au>
1349
1350 * ppc.h (ppc_parse_cpu): Declare.
1351
c3b7224a
NC		 13522009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1353
1354 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1355 and _IMM11 for mbitclr and mbitset.
1356 * score-datadep.h: Update dependency information.
1357
066be9f7
PB		 13582009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1359
1360 * ppc.h (PPC_OPCODE_POWER7): New.
1361
fedc618e
DE		 13622009-02-06 Doug Evans <dje@google.com>
1363
1364 * i386.h: Add comment regarding sse* insns and prefixes.
1365
52b6b6b9
JM		 13662009-02-03 Sandip Matte <sandip@rmicorp.com>
1367
1368 * mips.h (INSN_XLR): Define.
1369 (INSN_CHIP_MASK): Update.
1370 (CPU_XLR): Define.
1371 (OPCODE_IS_MEMBER): Update.
1372 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1373
35669430
DE		 13742009-01-28 Doug Evans <dje@google.com>
1375
1376 * opcode/i386.h: Add multiple inclusion protection.
1377 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1378 (EDI_REG_NUM): New macros.
1379 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1380 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1381 (REX_PREFIX_P): New macro.
35669430 1382
1cb0a767
PB		 13832009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1384
1385 * ppc.h (struct powerpc_opcode): New field "deprecated".
1386 (PPC_OPCODE_NOPOWER4): Delete.
1387
3aa3176b
TS		 13882008-11-28 Joshua Kinard <kumba@gentoo.org>
1389
1390 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1391 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1392
8e79c3df
CM		 13932008-11-18 Catherine Moore <clm@codesourcery.com>
1394
1395 * arm.h (FPU_NEON_FP16): New.
1396 (FPU_ARCH_NEON_FP16): New.
1397
de9a3e51
CF		 13982008-11-06 Chao-ying Fu <fu@mips.com>
1399
1400 * mips.h: Doucument '1' for 5-bit sync type.
1401
1ca35711
L		 14022008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1403
1404 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1405 IA64_RS_CR.
1406
9b4e5766
PB		 14072008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1408
1409 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1410
081ba1b3
AM		 14112008-07-30 Michael J. Eager <eager@eagercon.com>
1412
1413 * ppc.h (PPC_OPCODE_405): Define.
1414 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1415
fa452fa6
PB		 14162008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1417
1418 * ppc.h (ppc_cpu_t): New typedef.
1419 (struct powerpc_opcode <flags>): Use it.
1420 (struct powerpc_operand <insert, extract>): Likewise.
1421 (struct powerpc_macro <flags>): Likewise.
1422
bb35fb24
NC		 14232008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1424
1425 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1426 Update comment before MIPS16 field descriptors to mention MIPS16.
1427 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1428 BBIT.
1429 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1430 New bit masks and shift counts for cins and exts.
1431
dd3cbb7e
NC		 1432 * mips.h: Document new field descriptors +Q.
1433 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1434
d0799671
AN		 14352008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1436
9aff4b7a 1437 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1438 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1439
19a6653c
AM		 14402008-04-14 Edmar Wienskoski <edmar@freescale.com>
1441
1442 * ppc.h: (PPC_OPCODE_E500MC): New.
1443
c0f3af97
L		 14442008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1445
1446 * i386.h (MAX_OPERANDS): Set to 5.
1447 (MAX_MNEM_SIZE): Changed to 20.
1448
e210c36b
NC		 14492008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1450
1451 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1452
b1cc4aeb
PB		 14532008-03-09 Paul Brook <paul@codesourcery.com>
1454
1455 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1456
7e806470
PB		 14572008-03-04 Paul Brook <paul@codesourcery.com>
1458
1459 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1460 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1461 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1462
7b2185f9 14632008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1464 Nick Clifton <nickc@redhat.com>
1465
1466 PR 3134
1467 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1468 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1469 set.
af7329f0 1470
796d5313
NC		 14712008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1472
1473 * cr16.h (cr16_num_optab): Declared.
1474
d669d37f
NC		 14752008-02-14 Hakan Ardo <hakan@debian.org>
1476
1477 PR gas/2626
1478 * avr.h (AVR_ISA_2xxe): Define.
1479
e6429699
AN		 14802008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1481
1482 * mips.h: Update copyright.
1483 (INSN_CHIP_MASK): New macro.
1484 (INSN_OCTEON): New macro.
1485 (CPU_OCTEON): New macro.
1486 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1487
e210c36b
NC		 14882008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1489
1490 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1491
14922008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1493
1494 * avr.h (AVR_ISA_USB162): Add new opcode set.
1495 (AVR_ISA_AVR3): Likewise.
1496
350cc38d
MS		 14972007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1498
1499 * mips.h (INSN_LOONGSON_2E): New.
1500 (INSN_LOONGSON_2F): New.
1501 (CPU_LOONGSON_2E): New.
1502 (CPU_LOONGSON_2F): New.
1503 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1504
56950294
MS		 15052007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1506
1507 * mips.h (INSN_ISA*): Redefine certain values as an
1508 enumeration. Update comments.
1509 (mips_isa_table): New.
1510 (ISA_MIPS*): Redefine to match enumeration.
1511 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1512 values.
1513
c3d65c1c
BE		 15142007-08-08 Ben Elliston <bje@au.ibm.com>
1515
1516 * ppc.h (PPC_OPCODE_PPCPS): New.
1517
0fdaa005
L		 15182007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1519
1520 * m68k.h: Document j K & E.
1521
15222007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1523
1524 * cr16.h: New file for CR16 target.
1525
3896c469
AM		 15262007-05-02 Alan Modra <amodra@bigpond.net.au>
1527
1528 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1529
9a2e615a
NS		 15302007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1531
1532 * m68k.h (mcfisa_c): New.
1533 (mcfusp, mcf_mask): Adjust.
1534
b84bf58a
AM		 15352007-04-20 Alan Modra <amodra@bigpond.net.au>
1536
1537 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1538 (num_powerpc_operands): Declare.
1539 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1540 (PPC_OPERAND_PLUS1): Define.
1541
831480e9 15422007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1543
1544 * i386.h (REX_MODE64): Renamed to ...
1545 (REX_W): This.
1546 (REX_EXTX): Renamed to ...
1547 (REX_R): This.
1548 (REX_EXTY): Renamed to ...
1549 (REX_X): This.
1550 (REX_EXTZ): Renamed to ...
1551 (REX_B): This.
1552
0b1cf022
L		 15532007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1554
1555 * i386.h: Add entries from config/tc-i386.h and move tables
1556 to opcodes/i386-opc.h.
1557
d796c0ad
L		 15582007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1559
1560 * i386.h (FloatDR): Removed.
1561 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1562
30ac7323
AM		 15632007-03-01 Alan Modra <amodra@bigpond.net.au>
1564
1565 * spu-insns.h: Add soma double-float insns.
1566
8b082fb1 15672007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1568 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1569
1570 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1571 (INSN_DSPR2): Add flag for DSP R2 instructions.
1572 (M_BALIGN): New macro.
1573
4eed87de
AM		 15742007-02-14 Alan Modra <amodra@bigpond.net.au>
1575
1576 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1577 and Seg3ShortFrom with Shortform.
1578
fda592e8
L		 15792007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1580
1581 PR gas/4027
1582 * i386.h (i386_optab): Put the real "test" before the pseudo
1583 one.
1584
3bdcfdf4
KH		 15852007-01-08 Kazu Hirata <kazu@codesourcery.com>
1586
1587 * m68k.h (m68010up): OR fido_a.
1588
9840d27e
KH		 15892006-12-25 Kazu Hirata <kazu@codesourcery.com>
1590
1591 * m68k.h (fido_a): New.
1592
c629cdac
KH		 15932006-12-24 Kazu Hirata <kazu@codesourcery.com>
1594
1595 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1596 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1597 values.
1598
b7d9ef37
L		 15992006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1600
1601 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1602
b138abaa
NC		 16032006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1604
1605 * score-inst.h (enum score_insn_type): Add Insn_internal.
1606
e9f53129
AM		 16072006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1608 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1609 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1610 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1611 Alan Modra <amodra@bigpond.net.au>
1612
1613 * spu-insns.h: New file.
1614 * spu.h: New file.
1615
ede602d7
AM		 16162006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1617
1618 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1619
7918206c
MM		 16202006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1621
e4e42b45 1622 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1623 in amdfam10 architecture.
1624
ef05d495
L		 16252006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1626
1627 * i386.h: Replace CpuMNI with CpuSSSE3.
1628
2d447fca 16292006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1630 Joseph Myers <joseph@codesourcery.com>
1631 Ian Lance Taylor <ian@wasabisystems.com>
1632 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1633
1634 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1635
1c0d3aa6
NC		 16362006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1637
1638 * score-datadep.h: New file.
1639 * score-inst.h: New file.
1640
c2f0420e
L		 16412006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1642
1643 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1644 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1645 movdq2q and movq2dq.
1646
050dfa73
MM		 16472006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1648 Michael Meissner <michael.meissner@amd.com>
1649
1650 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1651
15965411
L		 16522006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1653
1654 * i386.h (i386_optab): Add "nop" with memory reference.
1655
46e883c5
L		 16562006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1657
1658 * i386.h (i386_optab): Update comment for 64bit NOP.
1659
9622b051
AM		 16602006-06-06 Ben Elliston <bje@au.ibm.com>
1661 Anton Blanchard <anton@samba.org>
1662
1663 * ppc.h (PPC_OPCODE_POWER6): Define.
1664 Adjust whitespace.
1665
a9e24354
TS		 16662006-06-05 Thiemo Seufer <ths@mips.com>
1667
e4e42b45 1668 * mips.h: Improve description of MT flags.
a9e24354 1669
a596001e
RS		 16702006-05-25 Richard Sandiford <richard@codesourcery.com>
1671
1672 * m68k.h (mcf_mask): Define.
1673
d43b4baf 16742006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1675 David Ung <davidu@mips.com>
d43b4baf
TS		 1676
1677 * mips.h (enum): Add macro M_CACHE_AB.
1678
39a7806d 16792006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1680 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1681 David Ung <davidu@mips.com>
1682
1683 * mips.h: Add INSN_SMARTMIPS define.
1684
9bcd4f99 16852006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1686 David Ung <davidu@mips.com>
9bcd4f99
TS		 1687
1688 * mips.h: Defines udi bits and masks. Add description of
1689 characters which may appear in the args field of udi
1690 instructions.
1691
ef0ee844
TS		 16922006-04-26 Thiemo Seufer <ths@networkno.de>
1693
1694 * mips.h: Improve comments describing the bitfield instruction
1695 fields.
1696
f7675147
L		 16972006-04-26 Julian Brown <julian@codesourcery.com>
1698
1699 * arm.h (FPU_VFP_EXT_V3): Define constant.
1700 (FPU_NEON_EXT_V1): Likewise.
1701 (FPU_VFP_HARD): Update.
1702 (FPU_VFP_V3): Define macro.
1703 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1704
ef0ee844 17052006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1706
1707 * avr.h (AVR_ISA_PWMx): New.
1708
2da12c60
NS		 17092006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1710
1711 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1712 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1713 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1714 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1715 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1716
0715c387
PB		 17172006-03-10 Paul Brook <paul@codesourcery.com>
1718
1719 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1720
34bdd094
DA		 17212006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1722
1723 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1724 first. Correct mask of bb "B" opcode.
1725
331d2d0d
L		 17262006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1727
1728 * i386.h (i386_optab): Support Intel Merom New Instructions.
1729
62b3e311
PB		 17302006-02-24 Paul Brook <paul@codesourcery.com>
1731
1732 * arm.h: Add V7 feature bits.
1733
59cf82fe
L		 17342006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1735
1736 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1737
e74cfd16
PB		 17382006-01-31 Paul Brook <paul@codesourcery.com>
1739 Richard Earnshaw <rearnsha@arm.com>
1740
1741 * arm.h: Use ARM_CPU_FEATURE.
1742 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1743 (arm_feature_set): Change to a structure.
1744 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1745 ARM_FEATURE): New macros.
1746
5b3f8a92
HPN		 17472005-12-07 Hans-Peter Nilsson <hp@axis.com>
1748
1749 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1750 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1751 (ADD_PC_INCR_OPCODE): Don't define.
1752
cb712a9e
L		 17532005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1754
1755 PR gas/1874
1756 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1757
0499d65b
TS		 17582005-11-14 David Ung <davidu@mips.com>
1759
1760 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1761 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1762 save/restore encoding of the args field.
1763
ea5ca089
DB		 17642005-10-28 Dave Brolley <brolley@redhat.com>
1765
1766 Contribute the following changes:
1767 2005-02-16 Dave Brolley <brolley@redhat.com>
1768
1769 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1770 cgen_isa_mask_* to cgen_bitset_*.
1771 * cgen.h: Likewise.
1772
16175d96
DB		 1773 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1774
1775 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1776 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1777 (CGEN_CPU_TABLE): Make isas a ponter.
1778
1779 2003-09-29 Dave Brolley <brolley@redhat.com>
1780
1781 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1782 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1783 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1784
1785 2002-12-13 Dave Brolley <brolley@redhat.com>
1786
1787 * cgen.h (symcat.h): #include it.
1788 (cgen-bitset.h): #include it.
1789 (CGEN_ATTR_VALUE_TYPE): Now a union.
1790 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1791 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1792 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1793 * cgen-bitset.h: New file.
1794
3c9b82ba
NC		 17952005-09-30 Catherine Moore <clm@cm00re.com>
1796
1797 * bfin.h: New file.
1798
6a2375c6
JB		 17992005-10-24 Jan Beulich <jbeulich@novell.com>
1800
1801 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1802 indirect operands.
1803
c06a12f8
DA		 18042005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1805
1806 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1807 Add FLAG_STRICT to pa10 ftest opcode.
1808
4d443107
DA		 18092005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1810
1811 * hppa.h (pa_opcodes): Remove lha entries.
1812
f0a3b40f
DA		 18132005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1814
1815 * hppa.h (FLAG_STRICT): Revise comment.
1816 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1817 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1818 entries for "fdc".
1819
e210c36b
NC		 18202005-09-30 Catherine Moore <clm@cm00re.com>
1821
1822 * bfin.h: New file.
1823
1b7e1362
DA		 18242005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1825
1826 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1827
089b39de
CF		 18282005-09-06 Chao-ying Fu <fu@mips.com>
1829
1830 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1831 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1832 define.
1833 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1834 (INSN_ASE_MASK): Update to include INSN_MT.
1835 (INSN_MT): New define for MT ASE.
1836
93c34b9b
CF		 18372005-08-25 Chao-ying Fu <fu@mips.com>
1838
1839 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1840 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1841 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1842 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1843 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1844 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1845 instructions.
1846 (INSN_DSP): New define for DSP ASE.
1847
848cf006
AM		 18482005-08-18 Alan Modra <amodra@bigpond.net.au>
1849
1850 * a29k.h: Delete.
1851
36ae0db3
DJ		 18522005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1853
1854 * ppc.h (PPC_OPCODE_E300): Define.
1855
8c929562
MS		 18562005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1857
1858 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1859
f7b8cccc
DA		 18602005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1861
1862 PR gas/336
1863 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1864 and pitlb.
1865
8b5328ac
JB		 18662005-07-27 Jan Beulich <jbeulich@novell.com>
1867
1868 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1869 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1870 Add movq-s as 64-bit variants of movd-s.
1871
f417d200
DA		 18722005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1873
18b3bdfc
DA		 1874 * hppa.h: Fix punctuation in comment.
1875
f417d200
DA		 1876 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1877 implicit space-register addressing. Set space-register bits on opcodes
1878 using implicit space-register addressing. Add various missing pa20
1879 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1880 space-register addressing. Use "fE" instead of "fe" in various
1881 fstw opcodes.
1882
9a145ce6
JB		 18832005-07-18 Jan Beulich <jbeulich@novell.com>
1884
1885 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1886
90700ea2
L		 18872007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1888
1889 * i386.h (i386_optab): Support Intel VMX Instructions.
1890
48f130a8
DA		 18912005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1892
1893 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1894
30123838
JB		 18952005-07-05 Jan Beulich <jbeulich@novell.com>
1896
1897 * i386.h (i386_optab): Add new insns.
1898
47b0e7ad
NC		 18992005-07-01 Nick Clifton <nickc@redhat.com>
1900
1901 * sparc.h: Add typedefs to structure declarations.
1902
b300c311
L		 19032005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1904
1905 PR 1013
1906 * i386.h (i386_optab): Update comments for 64bit addressing on
1907 mov. Allow 64bit addressing for mov and movq.
1908
2db495be
DA		 19092005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1910
1911 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1912 respectively, in various floating-point load and store patterns.
1913
caa05036
DA		 19142005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1915
1916 * hppa.h (FLAG_STRICT): Correct comment.
1917 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1918 PA 2.0 mneumonics when equivalent. Entries with cache control
1919 completers now require PA 1.1. Adjust whitespace.
1920
f4411256
AM		 19212005-05-19 Anton Blanchard <anton@samba.org>
1922
1923 * ppc.h (PPC_OPCODE_POWER5): Define.
1924
e172dbf8
NC		 19252005-05-10 Nick Clifton <nickc@redhat.com>
1926
1927 * Update the address and phone number of the FSF organization in
1928 the GPL notices in the following files:
1929 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1930 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1931 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1932 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1933 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1934 tic54x.h, tic80.h, v850.h, vax.h
1935
e44823cf
JB		 19362005-05-09 Jan Beulich <jbeulich@novell.com>
1937
1938 * i386.h (i386_optab): Add ht and hnt.
1939
791fe849
MK		 19402005-04-18 Mark Kettenis <kettenis@gnu.org>
1941
1942 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1943 Add xcrypt-ctr. Provide aliases without hyphens.
1944
faa7ef87
L		 19452005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1946
a63027e5
L		 1947 Moved from ../ChangeLog
1948
faa7ef87
L		 1949 2005-04-12 Paul Brook <paul@codesourcery.com>
1950 * m88k.h: Rename psr macros to avoid conflicts.
1951
1952 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1953 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1954 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1955 and ARM_ARCH_V6ZKT2.
1956
1957 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1958 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1959 Remove redundant instruction types.
1960 (struct argument): X_op - new field.
1961 (struct cst4_entry): Remove.
1962 (no_op_insn): Declare.
1963
1964 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1965 * crx.h (enum argtype): Rename types, remove unused types.
1966
1967 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1968 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1969 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1970 (enum operand_type): Rearrange operands, edit comments.
1971 replace us<N> with ui<N> for unsigned immediate.
1972 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1973 displacements (respectively).
1974 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1975 (instruction type): Add NO_TYPE_INS.
1976 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1977 (operand_entry): New field - 'flags'.
1978 (operand flags): New.
1979
1980 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1981 * crx.h (operand_type): Remove redundant types i3, i4,
1982 i5, i8, i12.
1983 Add new unsigned immediate types us3, us4, us5, us16.
1984
bc4bd9ab
MK		 19852005-04-12 Mark Kettenis <kettenis@gnu.org>
1986
1987 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1988 adjust them accordingly.
1989
373ff435
JB		 19902005-04-01 Jan Beulich <jbeulich@novell.com>
1991
1992 * i386.h (i386_optab): Add rdtscp.
1993
4cc91dba
L		 19942005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1995
1996 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1997 between memory and segment register. Allow movq for moving between
1998 general-purpose register and segment register.
4cc91dba 1999
9ae09ff9
JB		 20002005-02-09 Jan Beulich <jbeulich@novell.com>
2001
2002 PR gas/707
2003 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2004 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2005 fnstsw.
2006
638e7a64
NS		 20072006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2008
2009 * m68k.h (m68008, m68ec030, m68882): Remove.
2010 (m68k_mask): New.
2011 (cpu_m68k, cpu_cf): New.
2012 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2013 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2014
90219bd0
AO		 20152005-01-25 Alexandre Oliva <aoliva@redhat.com>
2016
2017 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2018 * cgen.h (enum cgen_parse_operand_type): Add
2019 CGEN_PARSE_OPERAND_SYMBOLIC.
2020
239cb185
FF		 20212005-01-21 Fred Fish <fnf@specifixinc.com>
2022
2023 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2024 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2025 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2026
dc9a9f39
FF		 20272005-01-19 Fred Fish <fnf@specifixinc.com>
2028
2029 * mips.h (struct mips_opcode): Add new pinfo2 member.
2030 (INSN_ALIAS): New define for opcode table entries that are
2031 specific instances of another entry, such as 'move' for an 'or'
2032 with a zero operand.
2033 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2034 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2035
98e7aba8
ILT		 20362004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2037
2038 * mips.h (CPU_RM9000): Define.
2039 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2040
37edbb65
JB		 20412004-11-25 Jan Beulich <jbeulich@novell.com>
2042
2043 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2044 to/from test registers are illegal in 64-bit mode. Add missing
2045 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2046 (previously one had to explicitly encode a rex64 prefix). Re-enable
2047 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2048 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2049
20502004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2051
2052 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2053 available only with SSE2. Change the MMX additions introduced by SSE
2054 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2055 instructions by their now designated identifier (since combining i686
2056 and 3DNow! does not really imply 3DNow!A).
2057
f5c7edf4
AM		 20582004-11-19 Alan Modra <amodra@bigpond.net.au>
2059
2060 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2061 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2062
7499d566
NC		 20632004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2064 Vineet Sharma <vineets@noida.hcltech.com>
2065
2066 * maxq.h: New file: Disassembly information for the maxq port.
2067
bcb9eebe
L		 20682004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2069
2070 * i386.h (i386_optab): Put back "movzb".
2071
94bb3d38
HPN		 20722004-11-04 Hans-Peter Nilsson <hp@axis.com>
2073
2074 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2075 comments. Remove member cris_ver_sim. Add members
2076 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2077 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2078 (struct cris_support_reg, struct cris_cond15): New types.
2079 (cris_conds15): Declare.
2080 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2081 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2082 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2083 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2084 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2085 SIZE_FIELD_UNSIGNED.
2086
37edbb65 20872004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2088
2089 * i386.h (sldx_Suf): Remove.
2090 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2091 (q_FP): Define, implying no REX64.
2092 (x_FP, sl_FP): Imply FloatMF.
2093 (i386_optab): Split reg and mem forms of moving from segment registers
2094 so that the memory forms can ignore the 16-/32-bit operand size
2095 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2096 all non-floating-point instructions. Unite 32- and 64-bit forms of
2097 movsx, movzx, and movd. Adjust floating point operations for the above
2098 changes to the *FP macros. Add DefaultSize to floating point control
2099 insns operating on larger memory ranges. Remove left over comments
2100 hinting at certain insns being Intel-syntax ones where the ones
2101 actually meant are already gone.
2102
48c9f030
NC		 21032004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2104
2105 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2106 instruction type.
2107
0dd132b6
NC		 21082004-09-30 Paul Brook <paul@codesourcery.com>
2109
2110 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2111 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2112
23794b24
MM		 21132004-09-11 Theodore A. Roth <troth@openavr.org>
2114
2115 * avr.h: Add support for
2116 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2117
2a309db0
AM		 21182004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2119
2120 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2121
b18c562e
NC		 21222004-08-24 Dmitry Diky <diwil@spec.ru>
2123
2124 * msp430.h (msp430_opc): Add new instructions.
2125 (msp430_rcodes): Declare new instructions.
2126 (msp430_hcodes): Likewise..
2127
45d313cd
NC		 21282004-08-13 Nick Clifton <nickc@redhat.com>
2129
2130 PR/301
2131 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2132 processors.
2133
30d1c836
ML		 21342004-08-30 Michal Ludvig <mludvig@suse.cz>
2135
2136 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2137
9a45f1c2
L		 21382004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2139
2140 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2141
543613e9
NC		 21422004-07-21 Jan Beulich <jbeulich@novell.com>
2143
2144 * i386.h: Adjust instruction descriptions to better match the
2145 specification.
2146
b781e558
RE		 21472004-07-16 Richard Earnshaw <rearnsha@arm.com>
2148
2149 * arm.h: Remove all old content. Replace with architecture defines
2150 from gas/config/tc-arm.c.
2151
8577e690
AS		 21522004-07-09 Andreas Schwab <schwab@suse.de>
2153
2154 * m68k.h: Fix comment.
2155
1fe1f39c
NC		 21562004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2157
2158 * crx.h: New file.
2159
1d9f512f
AM		 21602004-06-24 Alan Modra <amodra@bigpond.net.au>
2161
2162 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2163
be8c092b
NC		 21642004-05-24 Peter Barada <peter@the-baradas.com>
2165
2166 * m68k.h: Add 'size' to m68k_opcode.
2167
6b6e92f4
NC		 21682004-05-05 Peter Barada <peter@the-baradas.com>
2169
2170 * m68k.h: Switch from ColdFire chip name to core variant.
2171
21722004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2173
2174 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2175 descriptions for new EMAC cases.
2176 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2177 handle Motorola MAC syntax.
2178 Allow disassembly of ColdFire V4e object files.
2179
fdd12ef3
AM		 21802004-03-16 Alan Modra <amodra@bigpond.net.au>
2181
2182 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2183
3922a64c
L		 21842004-03-12 Jakub Jelinek <jakub@redhat.com>
2185
2186 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2187
1f45d988
ML		 21882004-03-12 Michal Ludvig <mludvig@suse.cz>
2189
2190 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2191
0f10071e
ML		 21922004-03-12 Michal Ludvig <mludvig@suse.cz>
2193
2194 * i386.h (i386_optab): Added xstore/xcrypt insns.
2195
3255318a
NC		 21962004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2197
2198 * h8300.h (32bit ldc/stc): Add relaxing support.
2199
ca9a79a1 22002004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2201
ca9a79a1
NC		 2202 * h8300.h (BITOP): Pass MEMRELAX flag.
2203
875a0b14
NC		 22042004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2205
2206 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2207 except for the H8S.
252b5132 2208
c9e214e5 2209For older changes see ChangeLog-9103
252b5132 2210\f
b90efa5b 2211Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2212
2213Copying and distribution of this file, with or without modification,
2214are permitted in any medium without royalty provided the copyright
2215notice and this notice are preserved.
2216
252b5132 2217Local Variables:
c9e214e5
AM		 2218mode: change-log
2219left-margin: 8
2220fill-column: 74
252b5132
RH		 2221version-control: never
2222End:
GDB Binutils - Deliverables
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