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remote.c: Add missing cast
[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
87018195
MW		 12015-11-27 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64.h (AARCH64_FEATURE_F16): New.
4 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
5 features.
6
250aafa4
MW		 72015-11-20 Matthew Wahab <matthew.wahab@arm.com>
8
9 * aarch64.h (AARCH64_FEATURE_V8_1): New.
10 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
11
56a1b672
MW		 122015-11-19 Matthew Wahab <matthew.wahab@arm.com>
13
14 * arm.h (ARM_EXT2_V8_2A): New.
15 (ARM_ARCH_V8_2A): New.
16
acb787b0
MW		 172015-11-19 Matthew Wahab <matthew.wahab@arm.com>
18
19 * aarch64.h (AARCH64_FEATURE_V8_2): New.
20 (AARCH64_ARCH_V8_2): New.
21
a680de9a
PB		 222015-11-11 Alan Modra <amodra@gmail.com>
23 Peter Bergner <bergner@vnet.ibm.com>
24
25 * ppc.h (PPC_OPCODE_POWER9): New define.
26 (PPC_OPCODE_VSX3): Likewise.
27
854eb72b
NC		 282015-11-02 Nick Clifton <nickc@redhat.com>
29
30 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
31
e292aa7a
NC		 322015-11-02 Nick Clifton <nickc@redhat.com>
33
34 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
35
43cdf5ae
YQ		 362015-10-28 Yao Qi <yao.qi@linaro.org>
37
38 * aarch64.h (aarch64_decode_insn): Update declaration.
39
875880c6
YQ		 402015-10-07 Yao Qi <yao.qi@linaro.org>
41
42 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
43 <name>: New field.
44
d3e12b29
YQ		 452015-10-07 Yao Qi <yao.qi@linaro.org>
46
47 * aarch64.h [__cplusplus]: Wrap in extern "C".
48
886a2506
NC		 492015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
50 Cupertino Miranda <cmiranda@synopsys.com>
51
52 * arc-func.h: New file.
53 * arc.h: Likewise.
54
e141d84e
YQ		 552015-10-02 Yao Qi <yao.qi@linaro.org>
56
57 * aarch64.h (aarch64_zero_register_p): Move the declaration
58 to column one.
59
36f4aab1
YQ		 602015-10-02 Yao Qi <yao.qi@linaro.org>
61
62 * aarch64.h (aarch64_decode_insn): Declare it.
63
7ecc513a
DV		 642015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
65
66 * s390.h (S390_INSTR_FLAG_HTM): New flag.
67 (S390_INSTR_FLAG_VX): New flag.
68 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
69
b6518b38
NC		 702015-09-23 Nick Clifton <nickc@redhat.com>
71
72 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
73 shifting.
74
f04265ec
NC		 752015-09-22 Nick Clifton <nickc@redhat.com>
76
77 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
78
7bdf96ef
NC		 792015-09-09 Daniel Santos <daniel.santos@pobox.com>
80
81 * visium.h (gen_reg_table): Make static.
82 (fp_reg_table): Likewise.
83 (cc_table): Likewise.
84
f33026a9
MW		 852015-07-20 Matthew Wahab <matthew.wahab@arm.com>
86
87 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
88 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
89 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
90 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
91
ef5a96d5
AM		 922015-07-03 Alan Modra <amodra@gmail.com>
93
94 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
95
c8c8175b
SL		 962015-07-01 Sandra Loosemore <sandra@codesourcery.com>
97 Cesar Philippidis <cesar@codesourcery.com>
98
99 * nios2.h (enum iw_format_type): Add R2 formats.
100 (enum overflow_type): Add signed_immed12_overflow and
101 enumeration_overflow for R2.
102 (struct nios2_opcode): Document new argument letters for R2.
103 (REG_3BIT, REG_LDWM, REG_POP): Define.
104 (includes): Include nios2r2.h.
105 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
106 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
107 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
108 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
109 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
110 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
111 Declare.
112 * nios2r2.h: New file.
113
11a0cf2e
PB		 1142015-06-19 Peter Bergner <bergner@vnet.ibm.com>
115
116 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
117 (ppc_optional_operand_value): New inline function.
118
88f0ea34
MW		 1192015-06-04 Matthew Wahab <matthew.wahab@arm.com>
120
121 * aarch64.h (AARCH64_V8_1): New.
122
a5932920
MW		 1232015-06-03 Matthew Wahab <matthew.wahab@arm.com>
124
125 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
126 (ARM_ARCH_V8_1A): New.
127 (ARM_ARCH_V8_1A_FP): New.
128 (ARM_ARCH_V8_1A_SIMD): New.
129 (ARM_ARCH_V8_1A_CRYPTOV1): New.
130 (ARM_FEATURE_CORE): New.
131
ddfded2f
MW		 1322015-06-02 Matthew Wahab <matthew.wahab@arm.com>
133
134 * arm.h (ARM_EXT2_PAN): New.
135 (ARM_FEATURE_CORE_HIGH): New.
136
1af1dd51
MW		 1372015-06-02 Matthew Wahab <matthew.wahab@arm.com>
138
139 * arm.h (ARM_FEATURE_ALL): New.
140
9e1f0fa7
MW		 1412015-06-02 Matthew Wahab <matthew.wahab@arm.com>
142
143 * aarch64.h (AARCH64_FEATURE_RDMA): New.
144
290806fd
MW		 1452015-06-02 Matthew Wahab <matthew.wahab@arm.com>
146
147 * aarch64.h (AARCH64_FEATURE_LOR): New.
148
f21cce2c
MW		 1492015-06-01 Matthew Wahab <matthew.wahab@arm.com>
150
151 * aarch64.h (AARCH64_FEATURE_PAN): New.
152 (aarch64_sys_reg_supported_p): Declare.
153 (aarch64_pstatefield_supported_p): Declare.
154
0952813b
DD		 1552015-04-30 DJ Delorie <dj@redhat.com>
156
157 * rl78.h (RL78_Dis_Isa): New.
158 (rl78_decode_opcode): Add ISA parameter.
159
823d2571
TG		 1602015-03-24 Terry Guo <terry.guo@arm.com>
161
162 * arm.h (arm_feature_set): Extended to provide more available bits.
163 (ARM_ANY): Updated to follow above new definition.
164 (ARM_CPU_HAS_FEATURE): Likewise.
165 (ARM_CPU_IS_ANY): Likewise.
166 (ARM_MERGE_FEATURE_SETS): Likewise.
167 (ARM_CLEAR_FEATURE): Likewise.
168 (ARM_FEATURE): Likewise.
169 (ARM_FEATURE_COPY): New macro.
170 (ARM_FEATURE_EQUAL): Likewise.
171 (ARM_FEATURE_ZERO): Likewise.
172 (ARM_FEATURE_CORE_EQUAL): Likewise.
173 (ARM_FEATURE_LOW): Likewise.
174 (ARM_FEATURE_CORE_LOW): Likewise.
175 (ARM_FEATURE_CORE_COPROC): Likewise.
176
f63c1776
PA		 1772015-02-19 Pedro Alves <palves@redhat.com>
178
179 * cgen.h [__cplusplus]: Wrap in extern "C".
180 * msp430-decode.h [__cplusplus]: Likewise.
181 * nios2.h [__cplusplus]: Likewise.
182 * rl78.h [__cplusplus]: Likewise.
183 * rx.h [__cplusplus]: Likewise.
184 * tilegx.h [__cplusplus]: Likewise.
185
3f8107ab
AM		 1862015-01-28 James Bowman <james.bowman@ftdichip.com>
187
188 * ft32.h: New file.
189
1e2e8c52
AK		 1902015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
191
192 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
193
b90efa5b
AM		 1942015-01-01 Alan Modra <amodra@gmail.com>
195
196 Update year range in copyright notice of all files.
197
bffb6004
AG		 1982014-12-27 Anthony Green <green@moxielogic.com>
199
200 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
201 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
202
1945cfa5
EB		 2032014-12-06 Eric Botcazou <ebotcazou@adacore.com>
204
205 * visium.h: New file.
206
d306ce58
SL		 2072014-11-28 Sandra Loosemore <sandra@codesourcery.com>
208
209 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
210 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
211 (NIOS2_INSN_OPTARG): Renumber.
212
b4714c7c
SL		 2132014-11-06 Sandra Loosemore <sandra@codesourcery.com>
214
215 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
216 declaration. Fix obsolete comment.
217
96ba4233
SL		 2182014-10-23 Sandra Loosemore <sandra@codesourcery.com>
219
220 * nios2.h (enum iw_format_type): New.
221 (struct nios2_opcode): Update comments. Add size and format fields.
222 (NIOS2_INSN_OPTARG): New.
223 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
224 (struct nios2_reg): Add regtype field.
225 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
226 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
227 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
228 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
229 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
230 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
231 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
232 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
233 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
234 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
235 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
236 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
237 (OP_MASK_OP, OP_SH_OP): Delete.
238 (OP_MASK_IOP, OP_SH_IOP): Delete.
239 (OP_MASK_IRD, OP_SH_IRD): Delete.
240 (OP_MASK_IRT, OP_SH_IRT): Delete.
241 (OP_MASK_IRS, OP_SH_IRS): Delete.
242 (OP_MASK_ROP, OP_SH_ROP): Delete.
243 (OP_MASK_RRD, OP_SH_RRD): Delete.
244 (OP_MASK_RRT, OP_SH_RRT): Delete.
245 (OP_MASK_RRS, OP_SH_RRS): Delete.
246 (OP_MASK_JOP, OP_SH_JOP): Delete.
247 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
248 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
249 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
250 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
251 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
252 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
253 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
254 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
255 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
256 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
257 (OP_MASK_<insn>, OP_MASK): Delete.
258 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
259 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
260 Include nios2r1.h to define new instruction opcode constants
261 and accessors.
262 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
263 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
264 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
265 (NUMOPCODES, NUMREGISTERS): Delete.
266 * nios2r1.h: New file.
267
0b6be415
JM		 2682014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
269
270 * sparc.h (HWCAP2_VIS3B): Documentation improved.
271
3d68f91c
JM		 2722014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
273
274 * sparc.h (sparc_opcode): new field `hwcaps2'.
275 (HWCAP2_FJATHPLUS): New define.
276 (HWCAP2_VIS3B): Likewise.
277 (HWCAP2_ADP): Likewise.
278 (HWCAP2_SPARC5): Likewise.
279 (HWCAP2_MWAIT): Likewise.
280 (HWCAP2_XMPMUL): Likewise.
281 (HWCAP2_XMONT): Likewise.
282 (HWCAP2_NSEC): Likewise.
283 (HWCAP2_FJATHHPC): Likewise.
284 (HWCAP2_FJDES): Likewise.
285 (HWCAP2_FJAES): Likewise.
286 Document the new operand kind `{', corresponding to the mcdper
287 ancillary state register.
288 Document the new operand kind }, which represents frsd floating
289 point registers (double precision) which must be the same than
290 frs1 in its containing instruction.
291
40c7a7cb
KLC		 2922014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
293
72f4393d 294 * nds32.h: Add new opcode declaration.
40c7a7cb 295
7361da2c
AB		 2962014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
297 Matthew Fortune <matthew.fortune@imgtec.com>
298
299 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
300 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
301 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
302 +I, +O, +R, +:, +\, +", +;
303 (mips_check_prev_operand): New struct.
304 (INSN2_FORBIDDEN_SLOT): New define.
305 (INSN_ISA32R6): New define.
306 (INSN_ISA64R6): New define.
307 (INSN_UPTO32R6): New define.
308 (INSN_UPTO64R6): New define.
309 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
310 (ISA_MIPS32R6): New define.
311 (ISA_MIPS64R6): New define.
312 (CPU_MIPS32R6): New define.
313 (CPU_MIPS64R6): New define.
314 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
315
ee804238
JW		 3162014-09-03 Jiong Wang <jiong.wang@arm.com>
317
318 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
319 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
320 (aarch64_insn_class): Add lse_atomic.
321 (F_LSE_SZ): New field added.
322 (opcode_has_special_coder): Recognize F_LSE_SZ.
323
5575639b
MR		 3242014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
325
326 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
327 over to `+J'.
328
43885403
MF		 3292014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
330
331 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
332 (INSN_LOAD_COPROC): New define.
333 (INSN_COPROC_MOVE_DELAY): Rename to...
334 (INSN_COPROC_MOVE): New define.
335
f36e8886 3362014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
72f4393d
L		 337 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
338 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
339 Soundararajan <Sounderarajan.D@atmel.com>
f36e8886
BS		 340
341 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
342 (AVR_ISA_2xxxa): Define ISA without LPM.
343 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
344 Add doc for contraint used in 16 bit lds/sts.
345 Adjust ISA group for icall, ijmp, pop and push.
346 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
347
00b32ff2
NC		 3482014-05-19 Nick Clifton <nickc@redhat.com>
349
350 * msp430.h (struct msp430_operand_s): Add vshift field.
351
ae52f483
AB		 3522014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
353
354 * mips.h (INSN_ISA_MASK): Updated.
355 (INSN_ISA32R3): New define.
356 (INSN_ISA32R5): New define.
357 (INSN_ISA64R3): New define.
358 (INSN_ISA64R5): New define.
359 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
360 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
361 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
362 mips64r5.
363 (INSN_UPTO32R3): New define.
364 (INSN_UPTO32R5): New define.
365 (INSN_UPTO64R3): New define.
366 (INSN_UPTO64R5): New define.
367 (ISA_MIPS32R3): New define.
368 (ISA_MIPS32R5): New define.
369 (ISA_MIPS64R3): New define.
370 (ISA_MIPS64R5): New define.
371 (CPU_MIPS32R3): New define.
372 (CPU_MIPS32R5): New define.
373 (CPU_MIPS64R3): New define.
374 (CPU_MIPS64R5): New define.
375
3efe9ec5
RS		 3762014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
377
378 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
379
73589c9d
CS		 3802014-04-22 Christian Svensson <blue@cmd.nu>
381
382 * or32.h: Delete.
383
4b95cf5c
AM		 3842014-03-05 Alan Modra <amodra@gmail.com>
385
386 Update copyright years.
387
e269fea7
AB		 3882013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
389
390 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
391 microMIPS.
392
35c08157
KLC		 3932013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
394 Wei-Cheng Wang <cole945@gmail.com>
395
396 * nds32.h: New file for Andes NDS32.
397
594d8fa8
MF		 3982013-12-07 Mike Frysinger <vapier@gentoo.org>
399
400 * bfin.h: Remove +x file mode.
401
87b8eed7
YZ		 4022013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
403
404 * aarch64.h (aarch64_pstatefields): Change element type to
405 aarch64_sys_reg.
406
c9fb6e58
YZ		 4072013-11-18 Renlin Li <Renlin.Li@arm.com>
408
409 * arm.h (ARM_AEXT_V7VE): New define.
410 (ARM_ARCH_V7VE): New define.
411 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
412
a203d9b7
YZ		 4132013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
414
415 Revert
416
417 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
418
419 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
420 (aarch64_sys_reg_writeonly_p): Ditto.
421
75468c93
YZ		 4222013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
423
424 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
425 (aarch64_sys_reg_writeonly_p): Ditto.
426
49eec193
YZ		 4272013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
428
429 * aarch64.h (aarch64_sys_reg): New typedef.
430 (aarch64_sys_regs): Change to define with the new type.
431 (aarch64_sys_reg_deprecated_p): Declare.
432
68a64283
YZ		 4332013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
434
435 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
436 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
437
387a82f1
CF		 4382013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
439
440 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
441 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
442 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
443 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
444 For MIPS, update extension character sequences after +.
445 (ASE_MSA): New define.
446 (ASE_MSA64): New define.
447 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
448 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
449 For microMIPS, update extension character sequences after +.
450
9aff4b7a
NC		 4512013-08-23 Yuri Chornoivan <yurchor@ukr.net>
452
453 PR binutils/15834
454 * i960.h: Fix typos.
455
e423441d
RS		 4562013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
457
458 * mips.h: Remove references to "+I" and imm2_expr.
459
5e0dc5ba
RS		 4602013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
461
462 * mips.h (M_DEXT, M_DINS): Delete.
463
0f35dbc4
RS		 4642013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
465
466 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
467 (mips_optional_operand_p): New function.
468
14daeee3
RS		 4692013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
470 Richard Sandiford <rdsandiford@googlemail.com>
471
472 * mips.h: Document new VU0 operand characters.
473 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
474 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
475 (OP_REG_R5900_ACC): New mips_reg_operand_types.
476 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
477 (mips_vu0_channel_mask): Declare.
478
3ccad066
RS		 4792013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
480
481 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
482 (mips_int_operand_min, mips_int_operand_max): New functions.
483 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
484
fc76e730
RS		 4852013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
486
487 * mips.h (mips_decode_reg_operand): New function.
488 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
489 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
490 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
491 New macros.
492 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
493 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
494 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
495 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
496 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
497 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
498 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
499 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
500 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
501 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
502 macros to cover the gaps.
503 (INSN2_MOD_SP): Replace with...
504 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
505 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
506 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
507 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
508 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
509 Delete.
510
26545944
RS		 5112013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
512
513 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
514 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
515 (MIPS16_INSN_COND_BRANCH): Delete.
516
7e8b059b
L		 5172013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
518 Kirill Yukhin <kirill.yukhin@intel.com>
519 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
520
521 * i386.h (BND_PREFIX_OPCODE): New.
522
c3c07478
RS		 5232013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
524
525 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
526 OP_SAVE_RESTORE_LIST.
527 (decode_mips16_operand): Declare.
528
ab902481
RS		 5292013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
530
531 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
532 (mips_operand, mips_int_operand, mips_mapped_int_operand)
533 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
534 (mips_pcrel_operand): New structures.
535 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
536 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
537 (decode_mips_operand, decode_micromips_operand): Declare.
538
cc537e56
RS		 5392013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
540
541 * mips.h: Document MIPS16 "I" opcode.
542
f2ae14a1
RS		 5432013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
544
545 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
546 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
547 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
548 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
549 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
550 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
551 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
552 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
553 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
554 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
555 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
556 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
557 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
558 Rename to...
559 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
560 (M_USD_AB): ...these.
561
5c324c16
RS		 5622013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
563
564 * mips.h: Remove documentation of "[" and "]". Update documentation
565 of "k" and the MDMX formats.
566
23e69e47
RS		 5672013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
568
569 * mips.h: Update documentation of "+s" and "+S".
570
27c5c572
RS		 5712013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
572
573 * mips.h: Document "+i".
574
e76ff5ab
RS		 5752013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
576
577 * mips.h: Remove "mi" documentation. Update "mh" documentation.
578 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
579 Delete.
580 (INSN2_WRITE_GPR_MHI): Rename to...
581 (INSN2_WRITE_GPR_MH): ...this.
582
fa7616a4
RS		 5832013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
584
585 * mips.h: Remove documentation of "+D" and "+T".
586
18870af7
RS		 5872013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
588
589 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
590 Use "source" rather than "destination" for microMIPS "G".
591
833794fc
MR		 5922013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
593
594 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
595 values.
596
c3678916
RS		 5972013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
598
599 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
600
7f3c4072
CM		 6012013-06-17 Catherine Moore <clm@codesourcery.com>
602 Maciej W. Rozycki <macro@codesourcery.com>
603 Chao-Ying Fu <fu@mips.com>
604
605 * mips.h (OP_SH_EVAOFFSET): Define.
606 (OP_MASK_EVAOFFSET): Define.
607 (INSN_ASE_MASK): Delete.
608 (ASE_EVA): Define.
609 (M_CACHEE_AB, M_CACHEE_OB): New.
610 (M_LBE_OB, M_LBE_AB): New.
611 (M_LBUE_OB, M_LBUE_AB): New.
612 (M_LHE_OB, M_LHE_AB): New.
613 (M_LHUE_OB, M_LHUE_AB): New.
614 (M_LLE_AB, M_LLE_OB): New.
615 (M_LWE_OB, M_LWE_AB): New.
616 (M_LWLE_AB, M_LWLE_OB): New.
617 (M_LWRE_AB, M_LWRE_OB): New.
618 (M_PREFE_AB, M_PREFE_OB): New.
619 (M_SCE_AB, M_SCE_OB): New.
620 (M_SBE_OB, M_SBE_AB): New.
621 (M_SHE_OB, M_SHE_AB): New.
622 (M_SWE_OB, M_SWE_AB): New.
623 (M_SWLE_AB, M_SWLE_OB): New.
624 (M_SWRE_AB, M_SWRE_OB): New.
625 (MICROMIPSOP_SH_EVAOFFSET): Define.
626 (MICROMIPSOP_MASK_EVAOFFSET): Define.
627
0c8fe7cf
SL		 6282013-06-12 Sandra Loosemore <sandra@codesourcery.com>
629
630 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
631
c77c0862
RS		 6322013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
633
634 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
635
b015e599
AP		 6362013-05-09 Andrew Pinski <apinski@cavium.com>
637
638 * mips.h (OP_MASK_CODE10): Correct definition.
639 (OP_SH_CODE10): Likewise.
640 Add a comment that "+J" is used now for OP_*CODE10.
641 (INSN_ASE_MASK): Update.
642 (INSN_VIRT): New macro.
643 (INSN_VIRT64): New macro
644
13761a11
NC		 6452013-05-02 Nick Clifton <nickc@redhat.com>
646
647 * msp430.h: Add patterns for MSP430X instructions.
648
0afd1215
DM		 6492013-04-06 David S. Miller <davem@davemloft.net>
650
651 * sparc.h (F_PREFERRED): Define.
652 (F_PREF_ALIAS): Define.
653
41702d50
NC		 6542013-04-03 Nick Clifton <nickc@redhat.com>
655
656 * v850.h (V850_INVERSE_PCREL): Define.
657
e21e1a51
NC		 6582013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
659
660 PR binutils/15068
661 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
662
51dcdd4d
NC		 6632013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
664
665 PR binutils/15068
666 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
667 Add 16-bit opcodes.
668 * tic6xc-opcode-table.h: Add 16-bit insns.
669 * tic6x.h: Add support for 16-bit insns.
670
81f5558e
NC		 6712013-03-21 Michael Schewe <michael.schewe@gmx.net>
672
673 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
674 and mov.b/w/l Rs,@(d:32,ERd).
675
165546ad
NC		 6762013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
677
678 PR gas/15082
679 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
680 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
681 tic6x_operand_xregpair operand coding type.
682 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
683 opcode field, usu ORXREGD1324 for the src2 operand and remove the
684 TIC6X_FLAG_NO_CROSS.
685
795b8e6b
NC		 6862013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
687
688 PR gas/15095
689 * tic6x.h (enum tic6x_coding_method): Add
690 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
691 separately the msb and lsb of a register pair. This is needed to
692 encode the opcodes in the same way as TI assembler does.
693 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
694 and rsqrdp opcodes to use the new field coding types.
695
dd5181d5
KT		 6962013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
697
698 * arm.h (CRC_EXT_ARMV8): New constant.
699 (ARCH_CRC_ARMV8): New macro.
700
e60bb1dd
YZ		 7012013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
702
703 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
704
36591ba1 7052013-02-06 Sandra Loosemore <sandra@codesourcery.com>
72f4393d 706 Andrew Jenner <andrew@codesourcery.com>
36591ba1
SL		 707
708 Based on patches from Altera Corporation.
709
710 * nios2.h: New file.
711
e30181a5
YZ		 7122013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
713
714 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
715
0c9573f4
NC		 7162013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
717
718 PR gas/15069
719 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
720
981dc7f1
NC		 7212013-01-24 Nick Clifton <nickc@redhat.com>
722
723 * v850.h: Add e3v5 support.
724
f5555712
YZ		 7252013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
726
727 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
728
5817ffd1
PB		 7292013-01-10 Peter Bergner <bergner@vnet.ibm.com>
730
731 * ppc.h (PPC_OPCODE_POWER8): New define.
732 (PPC_OPCODE_HTM): Likewise.
733
a3c62988
NC		 7342013-01-10 Will Newton <will.newton@imgtec.com>
735
736 * metag.h: New file.
737
73335eae
NC		 7382013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
739
740 * cr16.h (make_instruction): Rename to cr16_make_instruction.
741 (match_opcode): Rename to cr16_match_opcode.
742
e407c74b
NC		 7432013-01-04 Juergen Urban <JuergenUrban@gmx.de>
744
745 * mips.h: Add support for r5900 instructions including lq and sq.
746
bab4becb
NC		 7472013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
748
749 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
750 (make_instruction,match_opcode): Added function prototypes.
751 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
752
776fc418
AM		 7532012-11-23 Alan Modra <amodra@gmail.com>
754
755 * ppc.h (ppc_parse_cpu): Update prototype.
756
f05682d4
DA		 7572012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
758
759 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
760 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
761
cfc72779
AK		 7622012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
763
764 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
765
b3e14eda
L		 7662012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
767
768 * ia64.h (ia64_opnd): Add new operand types.
769
2c63854f
DM		 7702012-08-21 David S. Miller <davem@davemloft.net>
771
772 * sparc.h (F3F4): New macro.
773
a06ea964 7742012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 775 Laurent Desnogues <laurent.desnogues@arm.com>
776 Jim MacArthur <jim.macarthur@arm.com>
777 Marcus Shawcroft <marcus.shawcroft@arm.com>
778 Nigel Stephens <nigel.stephens@arm.com>
779 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
780 Richard Earnshaw <rearnsha@arm.com>
781 Sofiane Naci <sofiane.naci@arm.com>
782 Tejas Belagod <tejas.belagod@arm.com>
783 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 784
785 * aarch64.h: New file.
786
35d0a169 7872012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 788 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 789
790 * mips.h (mips_opcode): Add the exclusions field.
791 (OPCODE_IS_MEMBER): Remove macro.
792 (cpu_is_member): New inline function.
793 (opcode_is_member): Likewise.
794
03f66e8a 7952012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 796 Catherine Moore <clm@codesourcery.com>
797 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 798
799 * mips.h: Document microMIPS DSP ASE usage.
800 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
801 microMIPS DSP ASE support.
802 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
803 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
804 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
805 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
806 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
807 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
808 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
809
9d7b4c23
MR		 8102012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
811
812 * mips.h: Fix a typo in description.
813
76e879f8
NC		 8142012-06-07 Georg-Johann Lay <avr@gjlay.de>
815
816 * avr.h: (AVR_ISA_XCH): New define.
817 (AVR_ISA_XMEGA): Use it.
818 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
819
6927f982
NC		 8202012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
821
822 * m68hc11.h: Add XGate definitions.
823 (struct m68hc11_opcode): Add xg_mask field.
824
b9c361e0
JL		 8252012-05-14 Catherine Moore <clm@codesourcery.com>
826 Maciej W. Rozycki <macro@codesourcery.com>
827 Rhonda Wittels <rhonda@codesourcery.com>
828
6927f982 829 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 830 (PPC_OP_SA): New macro.
831 (PPC_OP_SE_VLE): New macro.
832 (PPC_OP): Use a variable shift amount.
833 (powerpc_operand): Update comments.
834 (PPC_OPSHIFT_INV): New macro.
835 (PPC_OPERAND_CR): Replace with...
836 (PPC_OPERAND_CR_BIT): ...this and
837 (PPC_OPERAND_CR_REG): ...this.
838
839
f6c1a2d5
NC		 8402012-05-03 Sean Keys <skeys@ipdatasys.com>
841
842 * xgate.h: Header file for XGATE assembler.
843
ec668d69
DM		 8442012-04-27 David S. Miller <davem@davemloft.net>
845
6cda1326
DM		 846 * sparc.h: Document new arg code' )' for crypto RS3
847 immediates.
848
ec668d69
DM		 849 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
850 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
851 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
852 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
853 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
854 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
855 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
856 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
857 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
858 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
859 HWCAP_CBCOND, HWCAP_CRC32): New defines.
860
aea77599
AM		 8612012-03-10 Edmar Wienskoski <edmar@freescale.com>
862
863 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
864
1f42f8b3
AM		 8652012-02-27 Alan Modra <amodra@gmail.com>
866
867 * crx.h (cst4_map): Update declaration.
868
6f7be959
WL		 8692012-02-25 Walter Lee <walt@tilera.com>
870
871 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
872 TILEGX_OPC_LD_TLS.
873 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
874 TILEPRO_OPC_LW_TLS_SN.
875
42164a71
L		 8762012-02-08 H.J. Lu <hongjiu.lu@intel.com>
877
878 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
879 (XRELEASE_PREFIX_OPCODE): Likewise.
880
432233b3 8812011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 882 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 883
884 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
885 (INSN_OCTEON2): New macro.
886 (CPU_OCTEON2): New macro.
887 (OPCODE_IS_MEMBER): Add Octeon2.
888
dd6a37e7
AP		 8892011-11-29 Andrew Pinski <apinski@cavium.com>
890
891 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
892 (INSN_OCTEONP): New macro.
893 (CPU_OCTEONP): New macro.
894 (OPCODE_IS_MEMBER): Add Octeon+.
895 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
896
99c513f6
DD		 8972011-11-01 DJ Delorie <dj@redhat.com>
898
899 * rl78.h: New file.
900
26f85d7a
MR		 9012011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
902
903 * mips.h: Fix a typo in description.
904
9e8c70f9
DM		 9052011-09-21 David S. Miller <davem@davemloft.net>
906
907 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
908 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
909 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
910 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
911
dec0624d 9122011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 913 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 914
915 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
916 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
917 (INSN_ASE_MASK): Add the MCU bit.
918 (INSN_MCU): New macro.
919 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
920 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
921
2b0c8b40
MR		 9222011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
923
924 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
925 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
926 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
927 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
928 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
929 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
930 (INSN2_READ_GPR_MMN): Likewise.
931 (INSN2_READ_FPR_D): Change the bit used.
932 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
933 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
934 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
935 (INSN2_COND_BRANCH): Likewise.
936 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
937 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
938 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
939 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
940 (INSN2_MOD_GPR_MN): Likewise.
941
ea783ef3
DM		 9422011-08-05 David S. Miller <davem@davemloft.net>
943
944 * sparc.h: Document new format codes '4', '5', and '('.
945 (OPF_LOW4, RS3): New macros.
946
7c176fa8
MR		 9472011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
948
949 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
950 order of flags documented.
951
2309ddf2
MR		 9522011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
953
954 * mips.h: Clarify the description of microMIPS instruction
955 manipulation macros.
956 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
957
df58fc94 9582011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 959 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 960
961 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
962 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
963 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
964 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
965 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
966 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
967 (OP_MASK_RS3, OP_SH_RS3): Likewise.
968 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
969 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
970 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
971 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
972 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
973 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
974 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
975 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
976 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
977 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
978 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
979 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
980 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
981 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
982 (INSN_WRITE_GPR_S): New macro.
983 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
984 (INSN2_READ_FPR_D): Likewise.
985 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
986 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
987 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
988 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
989 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
990 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
991 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
992 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
993 (CPU_MICROMIPS): New macro.
994 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
995 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
996 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
997 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
998 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
999 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1000 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1001 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1002 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1003 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1004 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1005 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1006 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1007 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1008 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1009 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1010 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1011 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1012 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1013 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1014 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1015 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1016 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1017 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1018 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1019 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1020 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1021 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1022 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1023 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1024 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1025 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1026 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1027 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1028 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1029 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1030 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1031 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1032 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1033 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1034 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1035 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1036 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1037 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1038 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1039 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1040 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1041 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1042 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1043 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1044 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1045 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1046 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1047 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1048 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1049 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1050 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1051 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1052 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1053 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1054 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1055 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1056 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1057 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1058 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1059 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1060 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1061 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1062 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1063 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1064 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1065 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1066 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1067 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1068 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1069 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1070 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1071 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1072 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1073 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1074 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1075 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1076 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1077 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1078 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1079 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1080 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1081 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1082 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1083 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1084 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1085 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1086 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1087 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1088 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1089 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1090 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1091 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1092 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1093 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1094 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1095 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1096 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1097 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1098 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1099 (micromips_opcodes): New declaration.
1100 (bfd_micromips_num_opcodes): Likewise.
1101
bcd530a7
RS		 11022011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1103
1104 * mips.h (INSN_TRAP): Rename to...
1105 (INSN_NO_DELAY_SLOT): ... this.
1106 (INSN_SYNC): Remove macro.
1107
2dad5a91
EW		 11082011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1109
1110 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1111 a duplicate of AVR_ISA_SPM.
1112
5d73b1f1
NC		 11132011-07-01 Nick Clifton <nickc@redhat.com>
1114
1115 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1116
ef26d60e
MF		 11172011-06-18 Robin Getz <robin.getz@analog.com>
1118
1119 * bfin.h (is_macmod_signed): New func
1120
8fb8dca7
MF		 11212011-06-18 Mike Frysinger <vapier@gentoo.org>
1122
1123 * bfin.h (is_macmod_pmove): Add missing space before func args.
1124 (is_macmod_hmove): Likewise.
1125
aa137e4d
NC		 11262011-06-13 Walter Lee <walt@tilera.com>
1127
1128 * tilegx.h: New file.
1129 * tilepro.h: New file.
1130
3b2f0793
PB		 11312011-05-31 Paul Brook <paul@codesourcery.com>
1132
aa137e4d
NC		 1133 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1134
11352011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1136
1137 * s390.h: Replace S390_OPERAND_REG_EVEN with
1138 S390_OPERAND_REG_PAIR.
1139
11402011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1141
1142 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 1143
ac7f631b
NC		 11442011-04-18 Julian Brown <julian@codesourcery.com>
1145
1146 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1147
84701018
NC		 11482011-04-11 Dan McDonald <dan@wellkeeper.com>
1149
1150 PR gas/12296
1151 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1152
8cc66334
EW		 11532011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1154
1155 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1156 New instruction set flags.
1157 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1158
3eebd5eb
MR		 11592011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1160
1161 * mips.h (M_PREF_AB): New enum value.
1162
26bb3ddd
MF		 11632011-02-12 Mike Frysinger <vapier@gentoo.org>
1164
89c0d58c
MR		 1165 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1166 M_IU): Define.
1167 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 1168
dd76fcb8
MF		 11692011-02-11 Mike Frysinger <vapier@gentoo.org>
1170
1171 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1172
98d23bef
BS		 11732011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1174
1175 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1176 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1177
3c853d93
DA		 11782010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1179
1180 PR gas/11395
1181 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1182 "bb" entries.
1183
79676006
DA		 11842010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1185
1186 PR gas/11395
1187 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1188
1bec78e9
RS		 11892010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1190
1191 * mips.h: Update commentary after last commit.
1192
98675402
RS		 11932010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1194
1195 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1196 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1197 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1198
aa137e4d
NC		 11992010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1200
1201 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1202
435b94a4
RS		 12032010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1204
1205 * mips.h: Fix previous commit.
1206
d051516a
NC		 12072010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1208
1209 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1210 (INSN_LOONGSON_3A): Clear bit 31.
1211
251665fc
MGD		 12122010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1213
1214 PR gas/12198
1215 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1216 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1217 (ARM_ARCH_V6M_ONLY): New define.
1218
fd503541
NC		 12192010-11-11 Mingming Sun <mingm.sun@gmail.com>
1220
1221 * mips.h (INSN_LOONGSON_3A): Defined.
1222 (CPU_LOONGSON_3A): Defined.
1223 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1224
4469d2be
AM		 12252010-10-09 Matt Rice <ratmice@gmail.com>
1226
1227 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1228 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1229
90ec0d68
MGD		 12302010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1231
1232 * arm.h (ARM_EXT_VIRT): New define.
1233 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1234 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1235 Extensions.
1236
eea54501 12372010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 1238
eea54501
MGD		 1239 * arm.h (ARM_AEXT_ADIV): New define.
1240 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1241
b2a5fbdc
MGD		 12422010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1243
1244 * arm.h (ARM_EXT_OS): New define.
1245 (ARM_AEXT_V6SM): Likewise.
1246 (ARM_ARCH_V6SM): Likewise.
1247
60e5ef9f
MGD		 12482010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1249
1250 * arm.h (ARM_EXT_MP): Add.
1251 (ARM_ARCH_V7A_MP): Likewise.
1252
73a63ccf
MF		 12532010-09-22 Mike Frysinger <vapier@gentoo.org>
1254
1255 * bfin.h: Declare pseudoChr structs/defines.
1256
ee99860a
MF		 12572010-09-21 Mike Frysinger <vapier@gentoo.org>
1258
1259 * bfin.h: Strip trailing whitespace.
1260
f9c7014e
DD		 12612010-07-29 DJ Delorie <dj@redhat.com>
1262
1263 * rx.h (RX_Operand_Type): Add TwoReg.
1264 (RX_Opcode_ID): Remove ediv and ediv2.
1265
93378652
DD		 12662010-07-27 DJ Delorie <dj@redhat.com>
1267
1268 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1269
1cd986c5
NC		 12702010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1271 Ina Pandit <ina.pandit@kpitcummins.com>
1272
1273 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1274 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1275 PROCESSOR_V850E2_ALL.
1276 Remove PROCESSOR_V850EA support.
1277 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1278 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1279 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1280 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1281 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1282 V850_OPERAND_PERCENT.
1283 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1284 V850_NOT_R0.
1285 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1286 and V850E_PUSH_POP
1287
9a2c7088
MR		 12882010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1289
1290 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1291 (MIPS16_INSN_BRANCH): Rename to...
1292 (MIPS16_INSN_COND_BRANCH): ... this.
1293
bdc70b4a
AM		 12942010-07-03 Alan Modra <amodra@gmail.com>
1295
1296 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1297 Renumber other PPC_OPCODE defines.
1298
f2bae120
AM		 12992010-07-03 Alan Modra <amodra@gmail.com>
1300
1301 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1302
360cfc9c
AM		 13032010-06-29 Alan Modra <amodra@gmail.com>
1304
1305 * maxq.h: Delete file.
1306
e01d869a
AM		 13072010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1308
1309 * ppc.h (PPC_OPCODE_E500): Define.
1310
f79e2745
CM		 13112010-05-26 Catherine Moore <clm@codesourcery.com>
1312
1313 * opcode/mips.h (INSN_MIPS16): Remove.
1314
2462afa1
JM		 13152010-04-21 Joseph Myers <joseph@codesourcery.com>
1316
1317 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1318
e4e42b45
NC		 13192010-04-15 Nick Clifton <nickc@redhat.com>
1320
1321 * alpha.h: Update copyright notice to use GPLv3.
1322 * arc.h: Likewise.
1323 * arm.h: Likewise.
1324 * avr.h: Likewise.
1325 * bfin.h: Likewise.
1326 * cgen.h: Likewise.
1327 * convex.h: Likewise.
1328 * cr16.h: Likewise.
1329 * cris.h: Likewise.
1330 * crx.h: Likewise.
1331 * d10v.h: Likewise.
1332 * d30v.h: Likewise.
1333 * dlx.h: Likewise.
1334 * h8300.h: Likewise.
1335 * hppa.h: Likewise.
1336 * i370.h: Likewise.
1337 * i386.h: Likewise.
1338 * i860.h: Likewise.
1339 * i960.h: Likewise.
1340 * ia64.h: Likewise.
1341 * m68hc11.h: Likewise.
1342 * m68k.h: Likewise.
1343 * m88k.h: Likewise.
1344 * maxq.h: Likewise.
1345 * mips.h: Likewise.
1346 * mmix.h: Likewise.
1347 * mn10200.h: Likewise.
1348 * mn10300.h: Likewise.
1349 * msp430.h: Likewise.
1350 * np1.h: Likewise.
1351 * ns32k.h: Likewise.
1352 * or32.h: Likewise.
1353 * pdp11.h: Likewise.
1354 * pj.h: Likewise.
1355 * pn.h: Likewise.
1356 * ppc.h: Likewise.
1357 * pyr.h: Likewise.
1358 * rx.h: Likewise.
1359 * s390.h: Likewise.
1360 * score-datadep.h: Likewise.
1361 * score-inst.h: Likewise.
1362 * sparc.h: Likewise.
1363 * spu-insns.h: Likewise.
1364 * spu.h: Likewise.
1365 * tic30.h: Likewise.
1366 * tic4x.h: Likewise.
1367 * tic54x.h: Likewise.
1368 * tic80.h: Likewise.
1369 * v850.h: Likewise.
1370 * vax.h: Likewise.
1371
40b36596
JM		 13722010-03-25 Joseph Myers <joseph@codesourcery.com>
1373
1374 * tic6x-control-registers.h, tic6x-insn-formats.h,
1375 tic6x-opcode-table.h, tic6x.h: New.
1376
c67a084a
NC		 13772010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1378
1379 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1380
466ef64f
AM		 13812010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1382
1383 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1384
1319d143
L		 13852010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1386
1387 * ia64.h (ia64_find_opcode): Remove argument name.
1388 (ia64_find_next_opcode): Likewise.
1389 (ia64_dis_opcode): Likewise.
1390 (ia64_free_opcode): Likewise.
1391 (ia64_find_dependency): Likewise.
1392
1fbb9298
DE		 13932009-11-22 Doug Evans <dje@sebabeach.org>
1394
1395 * cgen.h: Include bfd_stdint.h.
1396 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1397
ada65aa3
PB		 13982009-11-18 Paul Brook <paul@codesourcery.com>
1399
1400 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1401
9e3c6df6
PB		 14022009-11-17 Paul Brook <paul@codesourcery.com>
1403 Daniel Jacobowitz <dan@codesourcery.com>
1404
1405 * arm.h (ARM_EXT_V6_DSP): Define.
1406 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1407 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1408
0d734b5d
DD		 14092009-11-04 DJ Delorie <dj@redhat.com>
1410
1411 * rx.h (rx_decode_opcode) (mvtipl): Add.
1412 (mvtcp, mvfcp, opecp): Remove.
1413
62f3b8c8
PB		 14142009-11-02 Paul Brook <paul@codesourcery.com>
1415
1416 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1417 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1418 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1419 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1420 FPU_ARCH_NEON_VFP_V4): Define.
1421
ac1e9eca
DE		 14222009-10-23 Doug Evans <dje@sebabeach.org>
1423
1424 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1425 * cgen.h: Update. Improve multi-inclusion macro name.
1426
9fe54b1c
PB		 14272009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1428
1429 * ppc.h (PPC_OPCODE_476): Define.
1430
634b50f2
PB		 14312009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1432
1433 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1434
c7927a3c
NC		 14352009-09-29 DJ Delorie <dj@redhat.com>
1436
1437 * rx.h: New file.
1438
b961e85b
AM		 14392009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1440
1441 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1442
e0d602ec
BE		 14432009-09-21 Ben Elliston <bje@au.ibm.com>
1444
1445 * ppc.h (PPC_OPCODE_PPCA2): New.
1446
96d56e9f
NC		 14472009-09-05 Martin Thuresson <martin@mtme.org>
1448
1449 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1450
d3ce72d0
NC		 14512009-08-29 Martin Thuresson <martin@mtme.org>
1452
1453 * tic30.h (template): Rename type template to
1454 insn_template. Updated code to use new name.
1455 * tic54x.h (template): Rename type template to
1456 insn_template.
1457
824b28db
NH		 14582009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1459
1460 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1461
f865a31d
AG		 14622009-06-11 Anthony Green <green@moxielogic.com>
1463
1464 * moxie.h (MOXIE_F3_PCREL): Define.
1465 (moxie_form3_opc_info): Grow.
1466
0e7c7f11
AG		 14672009-06-06 Anthony Green <green@moxielogic.com>
1468
1469 * moxie.h (MOXIE_F1_M): Define.
1470
20135e4c
NC		 14712009-04-15 Anthony Green <green@moxielogic.com>
1472
1473 * moxie.h: Created.
1474
bcb012d3
DD		 14752009-04-06 DJ Delorie <dj@redhat.com>
1476
1477 * h8300.h: Add relaxation attributes to MOVA opcodes.
1478
69fe9ce5
AM		 14792009-03-10 Alan Modra <amodra@bigpond.net.au>
1480
1481 * ppc.h (ppc_parse_cpu): Declare.
1482
c3b7224a
NC		 14832009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1484
1485 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1486 and _IMM11 for mbitclr and mbitset.
1487 * score-datadep.h: Update dependency information.
1488
066be9f7
PB		 14892009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1490
1491 * ppc.h (PPC_OPCODE_POWER7): New.
1492
fedc618e
DE		 14932009-02-06 Doug Evans <dje@google.com>
1494
1495 * i386.h: Add comment regarding sse* insns and prefixes.
1496
52b6b6b9
JM		 14972009-02-03 Sandip Matte <sandip@rmicorp.com>
1498
1499 * mips.h (INSN_XLR): Define.
1500 (INSN_CHIP_MASK): Update.
1501 (CPU_XLR): Define.
1502 (OPCODE_IS_MEMBER): Update.
1503 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1504
35669430
DE		 15052009-01-28 Doug Evans <dje@google.com>
1506
1507 * opcode/i386.h: Add multiple inclusion protection.
1508 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1509 (EDI_REG_NUM): New macros.
1510 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1511 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1512 (REX_PREFIX_P): New macro.
35669430 1513
1cb0a767
PB		 15142009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1515
1516 * ppc.h (struct powerpc_opcode): New field "deprecated".
1517 (PPC_OPCODE_NOPOWER4): Delete.
1518
3aa3176b
TS		 15192008-11-28 Joshua Kinard <kumba@gentoo.org>
1520
1521 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1522 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1523
8e79c3df
CM		 15242008-11-18 Catherine Moore <clm@codesourcery.com>
1525
1526 * arm.h (FPU_NEON_FP16): New.
1527 (FPU_ARCH_NEON_FP16): New.
1528
de9a3e51
CF		 15292008-11-06 Chao-ying Fu <fu@mips.com>
1530
1531 * mips.h: Doucument '1' for 5-bit sync type.
1532
1ca35711
L		 15332008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1534
1535 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1536 IA64_RS_CR.
1537
9b4e5766
PB		 15382008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1539
1540 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1541
081ba1b3
AM		 15422008-07-30 Michael J. Eager <eager@eagercon.com>
1543
1544 * ppc.h (PPC_OPCODE_405): Define.
1545 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1546
fa452fa6
PB		 15472008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1548
1549 * ppc.h (ppc_cpu_t): New typedef.
1550 (struct powerpc_opcode <flags>): Use it.
1551 (struct powerpc_operand <insert, extract>): Likewise.
1552 (struct powerpc_macro <flags>): Likewise.
1553
bb35fb24
NC		 15542008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1555
1556 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1557 Update comment before MIPS16 field descriptors to mention MIPS16.
1558 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1559 BBIT.
1560 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1561 New bit masks and shift counts for cins and exts.
1562
dd3cbb7e
NC		 1563 * mips.h: Document new field descriptors +Q.
1564 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1565
d0799671
AN		 15662008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1567
9aff4b7a 1568 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
d0799671
AN		 1569 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1570
19a6653c
AM		 15712008-04-14 Edmar Wienskoski <edmar@freescale.com>
1572
1573 * ppc.h: (PPC_OPCODE_E500MC): New.
1574
c0f3af97
L		 15752008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1576
1577 * i386.h (MAX_OPERANDS): Set to 5.
1578 (MAX_MNEM_SIZE): Changed to 20.
1579
e210c36b
NC		 15802008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1581
1582 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1583
b1cc4aeb
PB		 15842008-03-09 Paul Brook <paul@codesourcery.com>
1585
1586 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1587
7e806470
PB		 15882008-03-04 Paul Brook <paul@codesourcery.com>
1589
1590 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1591 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1592 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1593
7b2185f9 15942008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1595 Nick Clifton <nickc@redhat.com>
1596
1597 PR 3134
1598 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1599 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1600 set.
af7329f0 1601
796d5313
NC		 16022008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1603
1604 * cr16.h (cr16_num_optab): Declared.
1605
d669d37f
NC		 16062008-02-14 Hakan Ardo <hakan@debian.org>
1607
1608 PR gas/2626
1609 * avr.h (AVR_ISA_2xxe): Define.
1610
e6429699
AN		 16112008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1612
1613 * mips.h: Update copyright.
1614 (INSN_CHIP_MASK): New macro.
1615 (INSN_OCTEON): New macro.
1616 (CPU_OCTEON): New macro.
1617 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1618
e210c36b
NC		 16192008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1620
1621 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1622
16232008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1624
1625 * avr.h (AVR_ISA_USB162): Add new opcode set.
1626 (AVR_ISA_AVR3): Likewise.
1627
350cc38d
MS		 16282007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1629
1630 * mips.h (INSN_LOONGSON_2E): New.
1631 (INSN_LOONGSON_2F): New.
1632 (CPU_LOONGSON_2E): New.
1633 (CPU_LOONGSON_2F): New.
1634 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1635
56950294
MS		 16362007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1637
1638 * mips.h (INSN_ISA*): Redefine certain values as an
1639 enumeration. Update comments.
1640 (mips_isa_table): New.
1641 (ISA_MIPS*): Redefine to match enumeration.
1642 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1643 values.
1644
c3d65c1c
BE		 16452007-08-08 Ben Elliston <bje@au.ibm.com>
1646
1647 * ppc.h (PPC_OPCODE_PPCPS): New.
1648
0fdaa005
L		 16492007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1650
1651 * m68k.h: Document j K & E.
1652
16532007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1654
1655 * cr16.h: New file for CR16 target.
1656
3896c469
AM		 16572007-05-02 Alan Modra <amodra@bigpond.net.au>
1658
1659 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1660
9a2e615a
NS		 16612007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1662
1663 * m68k.h (mcfisa_c): New.
1664 (mcfusp, mcf_mask): Adjust.
1665
b84bf58a
AM		 16662007-04-20 Alan Modra <amodra@bigpond.net.au>
1667
1668 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1669 (num_powerpc_operands): Declare.
1670 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1671 (PPC_OPERAND_PLUS1): Define.
1672
831480e9 16732007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1674
1675 * i386.h (REX_MODE64): Renamed to ...
1676 (REX_W): This.
1677 (REX_EXTX): Renamed to ...
1678 (REX_R): This.
1679 (REX_EXTY): Renamed to ...
1680 (REX_X): This.
1681 (REX_EXTZ): Renamed to ...
1682 (REX_B): This.
1683
0b1cf022
L		 16842007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1685
1686 * i386.h: Add entries from config/tc-i386.h and move tables
1687 to opcodes/i386-opc.h.
1688
d796c0ad
L		 16892007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1690
1691 * i386.h (FloatDR): Removed.
1692 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1693
30ac7323
AM		 16942007-03-01 Alan Modra <amodra@bigpond.net.au>
1695
1696 * spu-insns.h: Add soma double-float insns.
1697
8b082fb1 16982007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1699 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1700
1701 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1702 (INSN_DSPR2): Add flag for DSP R2 instructions.
1703 (M_BALIGN): New macro.
1704
4eed87de
AM		 17052007-02-14 Alan Modra <amodra@bigpond.net.au>
1706
1707 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1708 and Seg3ShortFrom with Shortform.
1709
fda592e8
L		 17102007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1711
1712 PR gas/4027
1713 * i386.h (i386_optab): Put the real "test" before the pseudo
1714 one.
1715
3bdcfdf4
KH		 17162007-01-08 Kazu Hirata <kazu@codesourcery.com>
1717
1718 * m68k.h (m68010up): OR fido_a.
1719
9840d27e
KH		 17202006-12-25 Kazu Hirata <kazu@codesourcery.com>
1721
1722 * m68k.h (fido_a): New.
1723
c629cdac
KH		 17242006-12-24 Kazu Hirata <kazu@codesourcery.com>
1725
1726 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1727 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1728 values.
1729
b7d9ef37
L		 17302006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1731
1732 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1733
b138abaa
NC		 17342006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1735
1736 * score-inst.h (enum score_insn_type): Add Insn_internal.
1737
e9f53129
AM		 17382006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1739 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1740 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1741 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1742 Alan Modra <amodra@bigpond.net.au>
1743
1744 * spu-insns.h: New file.
1745 * spu.h: New file.
1746
ede602d7
AM		 17472006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1748
1749 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1750
7918206c
MM		 17512006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1752
e4e42b45 1753 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1754 in amdfam10 architecture.
1755
ef05d495
L		 17562006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1757
1758 * i386.h: Replace CpuMNI with CpuSSSE3.
1759
2d447fca 17602006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1761 Joseph Myers <joseph@codesourcery.com>
1762 Ian Lance Taylor <ian@wasabisystems.com>
1763 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1764
1765 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1766
1c0d3aa6
NC		 17672006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1768
1769 * score-datadep.h: New file.
1770 * score-inst.h: New file.
1771
c2f0420e
L		 17722006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1773
1774 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1775 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1776 movdq2q and movq2dq.
1777
050dfa73
MM		 17782006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1779 Michael Meissner <michael.meissner@amd.com>
1780
1781 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1782
15965411
L		 17832006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1784
1785 * i386.h (i386_optab): Add "nop" with memory reference.
1786
46e883c5
L		 17872006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1788
1789 * i386.h (i386_optab): Update comment for 64bit NOP.
1790
9622b051
AM		 17912006-06-06 Ben Elliston <bje@au.ibm.com>
1792 Anton Blanchard <anton@samba.org>
1793
1794 * ppc.h (PPC_OPCODE_POWER6): Define.
1795 Adjust whitespace.
1796
a9e24354
TS		 17972006-06-05 Thiemo Seufer <ths@mips.com>
1798
e4e42b45 1799 * mips.h: Improve description of MT flags.
a9e24354 1800
a596001e
RS		 18012006-05-25 Richard Sandiford <richard@codesourcery.com>
1802
1803 * m68k.h (mcf_mask): Define.
1804
d43b4baf 18052006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1806 David Ung <davidu@mips.com>
d43b4baf
TS		 1807
1808 * mips.h (enum): Add macro M_CACHE_AB.
1809
39a7806d 18102006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1811 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1812 David Ung <davidu@mips.com>
1813
1814 * mips.h: Add INSN_SMARTMIPS define.
1815
9bcd4f99 18162006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1817 David Ung <davidu@mips.com>
9bcd4f99
TS		 1818
1819 * mips.h: Defines udi bits and masks. Add description of
1820 characters which may appear in the args field of udi
1821 instructions.
1822
ef0ee844
TS		 18232006-04-26 Thiemo Seufer <ths@networkno.de>
1824
1825 * mips.h: Improve comments describing the bitfield instruction
1826 fields.
1827
f7675147
L		 18282006-04-26 Julian Brown <julian@codesourcery.com>
1829
1830 * arm.h (FPU_VFP_EXT_V3): Define constant.
1831 (FPU_NEON_EXT_V1): Likewise.
1832 (FPU_VFP_HARD): Update.
1833 (FPU_VFP_V3): Define macro.
1834 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1835
ef0ee844 18362006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1837
1838 * avr.h (AVR_ISA_PWMx): New.
1839
2da12c60
NS		 18402006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1841
1842 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1843 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1844 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1845 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1846 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1847
0715c387
PB		 18482006-03-10 Paul Brook <paul@codesourcery.com>
1849
1850 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1851
34bdd094
DA		 18522006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1853
1854 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1855 first. Correct mask of bb "B" opcode.
1856
331d2d0d
L		 18572006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1858
1859 * i386.h (i386_optab): Support Intel Merom New Instructions.
1860
62b3e311
PB		 18612006-02-24 Paul Brook <paul@codesourcery.com>
1862
1863 * arm.h: Add V7 feature bits.
1864
59cf82fe
L		 18652006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1866
1867 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1868
e74cfd16
PB		 18692006-01-31 Paul Brook <paul@codesourcery.com>
1870 Richard Earnshaw <rearnsha@arm.com>
1871
1872 * arm.h: Use ARM_CPU_FEATURE.
1873 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1874 (arm_feature_set): Change to a structure.
1875 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1876 ARM_FEATURE): New macros.
1877
5b3f8a92
HPN		 18782005-12-07 Hans-Peter Nilsson <hp@axis.com>
1879
1880 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1881 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1882 (ADD_PC_INCR_OPCODE): Don't define.
1883
cb712a9e
L		 18842005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1885
1886 PR gas/1874
1887 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1888
0499d65b
TS		 18892005-11-14 David Ung <davidu@mips.com>
1890
1891 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1892 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1893 save/restore encoding of the args field.
1894
ea5ca089
DB		 18952005-10-28 Dave Brolley <brolley@redhat.com>
1896
1897 Contribute the following changes:
1898 2005-02-16 Dave Brolley <brolley@redhat.com>
1899
1900 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1901 cgen_isa_mask_* to cgen_bitset_*.
1902 * cgen.h: Likewise.
1903
16175d96
DB		 1904 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1905
1906 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1907 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1908 (CGEN_CPU_TABLE): Make isas a ponter.
1909
1910 2003-09-29 Dave Brolley <brolley@redhat.com>
1911
1912 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1913 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1914 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1915
1916 2002-12-13 Dave Brolley <brolley@redhat.com>
1917
1918 * cgen.h (symcat.h): #include it.
1919 (cgen-bitset.h): #include it.
1920 (CGEN_ATTR_VALUE_TYPE): Now a union.
1921 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1922 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1923 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1924 * cgen-bitset.h: New file.
1925
3c9b82ba
NC		 19262005-09-30 Catherine Moore <clm@cm00re.com>
1927
1928 * bfin.h: New file.
1929
6a2375c6
JB		 19302005-10-24 Jan Beulich <jbeulich@novell.com>
1931
1932 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1933 indirect operands.
1934
c06a12f8
DA		 19352005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1936
1937 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1938 Add FLAG_STRICT to pa10 ftest opcode.
1939
4d443107
DA		 19402005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1941
1942 * hppa.h (pa_opcodes): Remove lha entries.
1943
f0a3b40f
DA		 19442005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1945
1946 * hppa.h (FLAG_STRICT): Revise comment.
1947 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1948 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1949 entries for "fdc".
1950
e210c36b
NC		 19512005-09-30 Catherine Moore <clm@cm00re.com>
1952
1953 * bfin.h: New file.
1954
1b7e1362
DA		 19552005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1956
1957 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1958
089b39de
CF		 19592005-09-06 Chao-ying Fu <fu@mips.com>
1960
1961 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1962 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1963 define.
1964 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1965 (INSN_ASE_MASK): Update to include INSN_MT.
1966 (INSN_MT): New define for MT ASE.
1967
93c34b9b
CF		 19682005-08-25 Chao-ying Fu <fu@mips.com>
1969
1970 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1971 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1972 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1973 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1974 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1975 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1976 instructions.
1977 (INSN_DSP): New define for DSP ASE.
1978
848cf006
AM		 19792005-08-18 Alan Modra <amodra@bigpond.net.au>
1980
1981 * a29k.h: Delete.
1982
36ae0db3
DJ		 19832005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1984
1985 * ppc.h (PPC_OPCODE_E300): Define.
1986
8c929562
MS		 19872005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1988
1989 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1990
f7b8cccc
DA		 19912005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1992
1993 PR gas/336
1994 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1995 and pitlb.
1996
8b5328ac
JB		 19972005-07-27 Jan Beulich <jbeulich@novell.com>
1998
1999 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2000 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2001 Add movq-s as 64-bit variants of movd-s.
2002
f417d200
DA		 20032005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2004
18b3bdfc
DA		 2005 * hppa.h: Fix punctuation in comment.
2006
f417d200
DA		 2007 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2008 implicit space-register addressing. Set space-register bits on opcodes
2009 using implicit space-register addressing. Add various missing pa20
2010 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2011 space-register addressing. Use "fE" instead of "fe" in various
2012 fstw opcodes.
2013
9a145ce6
JB		 20142005-07-18 Jan Beulich <jbeulich@novell.com>
2015
2016 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2017
90700ea2
L		 20182007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2019
2020 * i386.h (i386_optab): Support Intel VMX Instructions.
2021
48f130a8
DA		 20222005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2023
2024 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2025
30123838
JB		 20262005-07-05 Jan Beulich <jbeulich@novell.com>
2027
2028 * i386.h (i386_optab): Add new insns.
2029
47b0e7ad
NC		 20302005-07-01 Nick Clifton <nickc@redhat.com>
2031
2032 * sparc.h: Add typedefs to structure declarations.
2033
b300c311
L		 20342005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2035
2036 PR 1013
2037 * i386.h (i386_optab): Update comments for 64bit addressing on
2038 mov. Allow 64bit addressing for mov and movq.
2039
2db495be
DA		 20402005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2041
2042 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2043 respectively, in various floating-point load and store patterns.
2044
caa05036
DA		 20452005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2046
2047 * hppa.h (FLAG_STRICT): Correct comment.
2048 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2049 PA 2.0 mneumonics when equivalent. Entries with cache control
2050 completers now require PA 1.1. Adjust whitespace.
2051
f4411256
AM		 20522005-05-19 Anton Blanchard <anton@samba.org>
2053
2054 * ppc.h (PPC_OPCODE_POWER5): Define.
2055
e172dbf8
NC		 20562005-05-10 Nick Clifton <nickc@redhat.com>
2057
2058 * Update the address and phone number of the FSF organization in
2059 the GPL notices in the following files:
2060 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2061 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2062 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2063 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2064 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2065 tic54x.h, tic80.h, v850.h, vax.h
2066
e44823cf
JB		 20672005-05-09 Jan Beulich <jbeulich@novell.com>
2068
2069 * i386.h (i386_optab): Add ht and hnt.
2070
791fe849
MK		 20712005-04-18 Mark Kettenis <kettenis@gnu.org>
2072
2073 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2074 Add xcrypt-ctr. Provide aliases without hyphens.
2075
faa7ef87
L		 20762005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2077
a63027e5
L		 2078 Moved from ../ChangeLog
2079
faa7ef87
L		 2080 2005-04-12 Paul Brook <paul@codesourcery.com>
2081 * m88k.h: Rename psr macros to avoid conflicts.
2082
2083 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2084 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2085 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2086 and ARM_ARCH_V6ZKT2.
2087
2088 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2089 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2090 Remove redundant instruction types.
2091 (struct argument): X_op - new field.
2092 (struct cst4_entry): Remove.
2093 (no_op_insn): Declare.
2094
2095 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2096 * crx.h (enum argtype): Rename types, remove unused types.
2097
2098 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2099 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2100 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2101 (enum operand_type): Rearrange operands, edit comments.
2102 replace us<N> with ui<N> for unsigned immediate.
2103 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2104 displacements (respectively).
2105 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2106 (instruction type): Add NO_TYPE_INS.
2107 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2108 (operand_entry): New field - 'flags'.
2109 (operand flags): New.
2110
2111 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2112 * crx.h (operand_type): Remove redundant types i3, i4,
2113 i5, i8, i12.
2114 Add new unsigned immediate types us3, us4, us5, us16.
2115
bc4bd9ab
MK		 21162005-04-12 Mark Kettenis <kettenis@gnu.org>
2117
2118 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2119 adjust them accordingly.
2120
373ff435
JB		 21212005-04-01 Jan Beulich <jbeulich@novell.com>
2122
2123 * i386.h (i386_optab): Add rdtscp.
2124
4cc91dba
L		 21252005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2126
2127 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 2128 between memory and segment register. Allow movq for moving between
2129 general-purpose register and segment register.
4cc91dba 2130
9ae09ff9
JB		 21312005-02-09 Jan Beulich <jbeulich@novell.com>
2132
2133 PR gas/707
2134 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2135 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2136 fnstsw.
2137
638e7a64
NS		 21382006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2139
2140 * m68k.h (m68008, m68ec030, m68882): Remove.
2141 (m68k_mask): New.
2142 (cpu_m68k, cpu_cf): New.
2143 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2144 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2145
90219bd0
AO		 21462005-01-25 Alexandre Oliva <aoliva@redhat.com>
2147
2148 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2149 * cgen.h (enum cgen_parse_operand_type): Add
2150 CGEN_PARSE_OPERAND_SYMBOLIC.
2151
239cb185
FF		 21522005-01-21 Fred Fish <fnf@specifixinc.com>
2153
2154 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2155 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2156 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2157
dc9a9f39
FF		 21582005-01-19 Fred Fish <fnf@specifixinc.com>
2159
2160 * mips.h (struct mips_opcode): Add new pinfo2 member.
2161 (INSN_ALIAS): New define for opcode table entries that are
2162 specific instances of another entry, such as 'move' for an 'or'
2163 with a zero operand.
2164 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2165 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2166
98e7aba8
ILT		 21672004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2168
2169 * mips.h (CPU_RM9000): Define.
2170 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2171
37edbb65
JB		 21722004-11-25 Jan Beulich <jbeulich@novell.com>
2173
2174 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2175 to/from test registers are illegal in 64-bit mode. Add missing
2176 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2177 (previously one had to explicitly encode a rex64 prefix). Re-enable
2178 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2179 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2180
21812004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 2182
2183 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2184 available only with SSE2. Change the MMX additions introduced by SSE
2185 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2186 instructions by their now designated identifier (since combining i686
2187 and 3DNow! does not really imply 3DNow!A).
2188
f5c7edf4
AM		 21892004-11-19 Alan Modra <amodra@bigpond.net.au>
2190
2191 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2192 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2193
7499d566
NC		 21942004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2195 Vineet Sharma <vineets@noida.hcltech.com>
2196
2197 * maxq.h: New file: Disassembly information for the maxq port.
2198
bcb9eebe
L		 21992004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2200
2201 * i386.h (i386_optab): Put back "movzb".
2202
94bb3d38
HPN		 22032004-11-04 Hans-Peter Nilsson <hp@axis.com>
2204
2205 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2206 comments. Remove member cris_ver_sim. Add members
2207 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2208 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2209 (struct cris_support_reg, struct cris_cond15): New types.
2210 (cris_conds15): Declare.
2211 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2212 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2213 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2214 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2215 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2216 SIZE_FIELD_UNSIGNED.
2217
37edbb65 22182004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 2219
2220 * i386.h (sldx_Suf): Remove.
2221 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2222 (q_FP): Define, implying no REX64.
2223 (x_FP, sl_FP): Imply FloatMF.
2224 (i386_optab): Split reg and mem forms of moving from segment registers
2225 so that the memory forms can ignore the 16-/32-bit operand size
2226 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2227 all non-floating-point instructions. Unite 32- and 64-bit forms of
2228 movsx, movzx, and movd. Adjust floating point operations for the above
2229 changes to the *FP macros. Add DefaultSize to floating point control
2230 insns operating on larger memory ranges. Remove left over comments
2231 hinting at certain insns being Intel-syntax ones where the ones
2232 actually meant are already gone.
2233
48c9f030
NC		 22342004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2235
2236 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2237 instruction type.
2238
0dd132b6
NC		 22392004-09-30 Paul Brook <paul@codesourcery.com>
2240
2241 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2242 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2243
23794b24
MM		 22442004-09-11 Theodore A. Roth <troth@openavr.org>
2245
2246 * avr.h: Add support for
2247 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2248
2a309db0
AM		 22492004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2250
2251 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2252
b18c562e
NC		 22532004-08-24 Dmitry Diky <diwil@spec.ru>
2254
2255 * msp430.h (msp430_opc): Add new instructions.
2256 (msp430_rcodes): Declare new instructions.
2257 (msp430_hcodes): Likewise..
2258
45d313cd
NC		 22592004-08-13 Nick Clifton <nickc@redhat.com>
2260
2261 PR/301
2262 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2263 processors.
2264
30d1c836
ML		 22652004-08-30 Michal Ludvig <mludvig@suse.cz>
2266
2267 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2268
9a45f1c2
L		 22692004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2270
2271 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2272
543613e9
NC		 22732004-07-21 Jan Beulich <jbeulich@novell.com>
2274
2275 * i386.h: Adjust instruction descriptions to better match the
2276 specification.
2277
b781e558
RE		 22782004-07-16 Richard Earnshaw <rearnsha@arm.com>
2279
2280 * arm.h: Remove all old content. Replace with architecture defines
2281 from gas/config/tc-arm.c.
2282
8577e690
AS		 22832004-07-09 Andreas Schwab <schwab@suse.de>
2284
2285 * m68k.h: Fix comment.
2286
1fe1f39c
NC		 22872004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2288
2289 * crx.h: New file.
2290
1d9f512f
AM		 22912004-06-24 Alan Modra <amodra@bigpond.net.au>
2292
2293 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2294
be8c092b
NC		 22952004-05-24 Peter Barada <peter@the-baradas.com>
2296
2297 * m68k.h: Add 'size' to m68k_opcode.
2298
6b6e92f4
NC		 22992004-05-05 Peter Barada <peter@the-baradas.com>
2300
2301 * m68k.h: Switch from ColdFire chip name to core variant.
2302
23032004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 2304
2305 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2306 descriptions for new EMAC cases.
2307 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2308 handle Motorola MAC syntax.
2309 Allow disassembly of ColdFire V4e object files.
2310
fdd12ef3
AM		 23112004-03-16 Alan Modra <amodra@bigpond.net.au>
2312
2313 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2314
3922a64c
L		 23152004-03-12 Jakub Jelinek <jakub@redhat.com>
2316
2317 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2318
1f45d988
ML		 23192004-03-12 Michal Ludvig <mludvig@suse.cz>
2320
2321 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2322
0f10071e
ML		 23232004-03-12 Michal Ludvig <mludvig@suse.cz>
2324
2325 * i386.h (i386_optab): Added xstore/xcrypt insns.
2326
3255318a
NC		 23272004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2328
2329 * h8300.h (32bit ldc/stc): Add relaxing support.
2330
ca9a79a1 23312004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 2332
ca9a79a1
NC		 2333 * h8300.h (BITOP): Pass MEMRELAX flag.
2334
875a0b14
NC		 23352004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2336
2337 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2338 except for the H8S.
252b5132 2339
c9e214e5 2340For older changes see ChangeLog-9103
252b5132 2341\f
b90efa5b 2342Copyright (C) 2004-2015 Free Software Foundation, Inc.
752937aa
NC		 2343
2344Copying and distribution of this file, with or without modification,
2345are permitted in any medium without royalty provided the copyright
2346notice and this notice are preserved.
2347
252b5132 2348Local Variables:
c9e214e5
AM		 2349mode: change-log
2350left-margin: 8
2351fill-column: 74
252b5132
RH		 2352version-control: never
2353End:
GDB Binutils - Deliverables
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