projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| e21e1a51 NC |
1 | 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com> |
| 2 | ||
| 3 | PR binutils/15068 | |
| 4 | * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor. | |
| 5 | ||
| 51dcdd4d NC |
6 | 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com> |
| 7 | ||
| 8 | PR binutils/15068 | |
| 9 | * tic6xc-insn-formats.h (FLD): Add use of bitfield array. | |
| 10 | Add 16-bit opcodes. | |
| 11 | * tic6xc-opcode-table.h: Add 16-bit insns. | |
| 12 | * tic6x.h: Add support for 16-bit insns. | |
| 13 | ||
| 81f5558e NC |
14 | 2013-03-21 Michael Schewe <michael.schewe@gmx.net> |
| 15 | ||
| 16 | * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd | |
| 17 | and mov.b/w/l Rs,@(d:32,ERd). | |
| 18 | ||
| 165546ad NC |
19 | 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com> |
| 20 | ||
| 21 | PR gas/15082 | |
| 22 | * tic6x-opcode-table.h: Rename mpydp's specific operand type macro | |
| 23 | from ORREGD1324 to ORXREGD1324 and make it cross-path-able through | |
| 24 | tic6x_operand_xregpair operand coding type. | |
| 25 | Make mpydp instruction cross-path-able, ie: remove the FIXed 'x' | |
| 26 | opcode field, usu ORXREGD1324 for the src2 operand and remove the | |
| 27 | TIC6X_FLAG_NO_CROSS. | |
| 28 | ||
| 795b8e6b NC |
29 | 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com> |
| 30 | ||
| 31 | PR gas/15095 | |
| 32 | * tic6x.h (enum tic6x_coding_method): Add | |
| 33 | tic6x_coding_dreg_(msb|lsb) field coding type in order to encode | |
| 34 | separately the msb and lsb of a register pair. This is needed to | |
| 35 | encode the opcodes in the same way as TI assembler does. | |
| 36 | * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp | |
| 37 | and rsqrdp opcodes to use the new field coding types. | |
| 38 | ||
| dd5181d5 KT |
39 | 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> |
| 40 | ||
| 41 | * arm.h (CRC_EXT_ARMV8): New constant. | |
| 42 | (ARCH_CRC_ARMV8): New macro. | |
| 43 | ||
| e60bb1dd YZ |
44 | 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com> |
| 45 | ||
| 46 | * aarch64.h (AARCH64_FEATURE_CRC): New macro. | |
| 47 | ||
| 36591ba1 SL |
48 | 2013-02-06 Sandra Loosemore <sandra@codesourcery.com> |
| 49 | Andrew Jenner <andrew@codesourcery.com> | |
| 50 | ||
| 51 | Based on patches from Altera Corporation. | |
| 52 | ||
| 53 | * nios2.h: New file. | |
| 54 | ||
| e30181a5 YZ |
55 | 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com> |
| 56 | ||
| 57 | * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2. | |
| 58 | ||
| 0c9573f4 NC |
59 | 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com> |
| 60 | ||
| 61 | PR gas/15069 | |
| 62 | * tic6x-opcode-table.h: Fix encoding of BNOP instruction. | |
| 63 | ||
| 981dc7f1 NC |
64 | 2013-01-24 Nick Clifton <nickc@redhat.com> |
| 65 | ||
| 66 | * v850.h: Add e3v5 support. | |
| 67 | ||
| f5555712 YZ |
68 | 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> |
| 69 | ||
| 70 | * aarch64.h (aarch64_op): Remove OP_V_MOVI_B. | |
| 71 | ||
| 5817ffd1 PB |
72 | 2013-01-10 Peter Bergner <bergner@vnet.ibm.com> |
| 73 | ||
| 74 | * ppc.h (PPC_OPCODE_POWER8): New define. | |
| 75 | (PPC_OPCODE_HTM): Likewise. | |
| 76 | ||
| a3c62988 NC |
77 | 2013-01-10 Will Newton <will.newton@imgtec.com> |
| 78 | ||
| 79 | * metag.h: New file. | |
| 80 | ||
| 73335eae NC |
81 | 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com> |
| 82 | ||
| 83 | * cr16.h (make_instruction): Rename to cr16_make_instruction. | |
| 84 | (match_opcode): Rename to cr16_match_opcode. | |
| 85 | ||
| e407c74b NC |
86 | 2013-01-04 Juergen Urban <JuergenUrban@gmx.de> |
| 87 | ||
| 88 | * mips.h: Add support for r5900 instructions including lq and sq. | |
| 89 | ||
| bab4becb NC |
90 | 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com> |
| 91 | ||
| 92 | * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c | |
| 93 | (make_instruction,match_opcode): Added function prototypes. | |
| 94 | (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern. | |
| 95 | ||
| 776fc418 AM |
96 | 2012-11-23 Alan Modra <amodra@gmail.com> |
| 97 | ||
| 98 | * ppc.h (ppc_parse_cpu): Update prototype. | |
| 99 | ||
| f05682d4 DA |
100 | 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 101 | ||
| 102 | * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx | |
| 103 | opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes. | |
| 104 | ||
| cfc72779 AK |
105 | 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> |
| 106 | ||
| 107 | * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12. | |
| 108 | ||
| b3e14eda L |
109 | 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com> |
| 110 | ||
| 111 | * ia64.h (ia64_opnd): Add new operand types. | |
| 112 | ||
| 2c63854f DM |
113 | 2012-08-21 David S. Miller <davem@davemloft.net> |
| 114 | ||
| 115 | * sparc.h (F3F4): New macro. | |
| 116 | ||
| a06ea964 | 117 | 2012-08-13 Ian Bolton <ian.bolton@arm.com> |
| b3e14eda L |
118 | Laurent Desnogues <laurent.desnogues@arm.com> |
| 119 | Jim MacArthur <jim.macarthur@arm.com> | |
| 120 | Marcus Shawcroft <marcus.shawcroft@arm.com> | |
| 121 | Nigel Stephens <nigel.stephens@arm.com> | |
| 122 | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | |
| 123 | Richard Earnshaw <rearnsha@arm.com> | |
| 124 | Sofiane Naci <sofiane.naci@arm.com> | |
| 125 | Tejas Belagod <tejas.belagod@arm.com> | |
| 126 | Yufeng Zhang <yufeng.zhang@arm.com> | |
| a06ea964 NC |
127 | |
| 128 | * aarch64.h: New file. | |
| 129 | ||
| 35d0a169 | 130 | 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com> |
| b3e14eda | 131 | Maciej W. Rozycki <macro@codesourcery.com> |
| 35d0a169 MR |
132 | |
| 133 | * mips.h (mips_opcode): Add the exclusions field. | |
| 134 | (OPCODE_IS_MEMBER): Remove macro. | |
| 135 | (cpu_is_member): New inline function. | |
| 136 | (opcode_is_member): Likewise. | |
| 137 | ||
| 03f66e8a | 138 | 2012-07-31 Chao-Ying Fu <fu@mips.com> |
| b3e14eda L |
139 | Catherine Moore <clm@codesourcery.com> |
| 140 | Maciej W. Rozycki <macro@codesourcery.com> | |
| 03f66e8a MR |
141 | |
| 142 | * mips.h: Document microMIPS DSP ASE usage. | |
| 143 | (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for | |
| 144 | microMIPS DSP ASE support. | |
| 145 | (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. | |
| 146 | (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. | |
| 147 | (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. | |
| 148 | (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. | |
| 149 | (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. | |
| 150 | (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. | |
| 151 | (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. | |
| 152 | ||
| 9d7b4c23 MR |
153 | 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com> |
| 154 | ||
| 155 | * mips.h: Fix a typo in description. | |
| 156 | ||
| 76e879f8 NC |
157 | 2012-06-07 Georg-Johann Lay <avr@gjlay.de> |
| 158 | ||
| 159 | * avr.h: (AVR_ISA_XCH): New define. | |
| 160 | (AVR_ISA_XMEGA): Use it. | |
| 161 | (XCH, LAS, LAT, LAC): New XMEGA opcodes. | |
| 162 | ||
| 6927f982 NC |
163 | 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk> |
| 164 | ||
| 165 | * m68hc11.h: Add XGate definitions. | |
| 166 | (struct m68hc11_opcode): Add xg_mask field. | |
| 167 | ||
| b9c361e0 JL |
168 | 2012-05-14 Catherine Moore <clm@codesourcery.com> |
| 169 | Maciej W. Rozycki <macro@codesourcery.com> | |
| 170 | Rhonda Wittels <rhonda@codesourcery.com> | |
| 171 | ||
| 6927f982 | 172 | * ppc.h (PPC_OPCODE_VLE): New definition. |
| b9c361e0 JL |
173 | (PPC_OP_SA): New macro. |
| 174 | (PPC_OP_SE_VLE): New macro. | |
| 175 | (PPC_OP): Use a variable shift amount. | |
| 176 | (powerpc_operand): Update comments. | |
| 177 | (PPC_OPSHIFT_INV): New macro. | |
| 178 | (PPC_OPERAND_CR): Replace with... | |
| 179 | (PPC_OPERAND_CR_BIT): ...this and | |
| 180 | (PPC_OPERAND_CR_REG): ...this. | |
| 181 | ||
| 182 | ||
| f6c1a2d5 NC |
183 | 2012-05-03 Sean Keys <skeys@ipdatasys.com> |
| 184 | ||
| 185 | * xgate.h: Header file for XGATE assembler. | |
| 186 | ||
| ec668d69 DM |
187 | 2012-04-27 David S. Miller <davem@davemloft.net> |
| 188 | ||
| 6cda1326 DM |
189 | * sparc.h: Document new arg code' )' for crypto RS3 |
| 190 | immediates. | |
| 191 | ||
| ec668d69 DM |
192 | * sparc.h (struct sparc_opcode): New field 'hwcaps'. |
| 193 | F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, | |
| 194 | F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, | |
| 195 | F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete. | |
| 196 | (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC, | |
| 197 | HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF, | |
| 198 | HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU, | |
| 199 | HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES, | |
| 200 | HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1, | |
| 201 | HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE, | |
| 202 | HWCAP_CBCOND, HWCAP_CRC32): New defines. | |
| 203 | ||
| aea77599 AM |
204 | 2012-03-10 Edmar Wienskoski <edmar@freescale.com> |
| 205 | ||
| 206 | * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR. | |
| 207 | ||
| 1f42f8b3 AM |
208 | 2012-02-27 Alan Modra <amodra@gmail.com> |
| 209 | ||
| 210 | * crx.h (cst4_map): Update declaration. | |
| 211 | ||
| 6f7be959 WL |
212 | 2012-02-25 Walter Lee <walt@tilera.com> |
| 213 | ||
| 214 | * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS, | |
| 215 | TILEGX_OPC_LD_TLS. | |
| 216 | * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS, | |
| 217 | TILEPRO_OPC_LW_TLS_SN. | |
| 218 | ||
| 42164a71 L |
219 | 2012-02-08 H.J. Lu <hongjiu.lu@intel.com> |
| 220 | ||
| 221 | * i386.h (XACQUIRE_PREFIX_OPCODE): New. | |
| 222 | (XRELEASE_PREFIX_OPCODE): Likewise. | |
| 223 | ||
| 432233b3 | 224 | 2011-12-08 Andrew Pinski <apinski@cavium.com> |
| b3e14eda | 225 | Adam Nemet <anemet@caviumnetworks.com> |
| 432233b3 AP |
226 | |
| 227 | * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2. | |
| 228 | (INSN_OCTEON2): New macro. | |
| 229 | (CPU_OCTEON2): New macro. | |
| 230 | (OPCODE_IS_MEMBER): Add Octeon2. | |
| 231 | ||
| dd6a37e7 AP |
232 | 2011-11-29 Andrew Pinski <apinski@cavium.com> |
| 233 | ||
| 234 | * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP. | |
| 235 | (INSN_OCTEONP): New macro. | |
| 236 | (CPU_OCTEONP): New macro. | |
| 237 | (OPCODE_IS_MEMBER): Add Octeon+. | |
| 238 | (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values. | |
| 239 | ||
| 99c513f6 DD |
240 | 2011-11-01 DJ Delorie <dj@redhat.com> |
| 241 | ||
| 242 | * rl78.h: New file. | |
| 243 | ||
| 26f85d7a MR |
244 | 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com> |
| 245 | ||
| 246 | * mips.h: Fix a typo in description. | |
| 247 | ||
| 9e8c70f9 DM |
248 | 2011-09-21 David S. Miller <davem@davemloft.net> |
| 249 | ||
| 250 | * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int. | |
| 251 | (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2, | |
| 252 | F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS, | |
| 253 | F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits. | |
| 254 | ||
| dec0624d | 255 | 2011-08-09 Chao-ying Fu <fu@mips.com> |
| b3e14eda | 256 | Maciej W. Rozycki <macro@codesourcery.com> |
| dec0624d MR |
257 | |
| 258 | * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros. | |
| 259 | (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine. | |
| 260 | (INSN_ASE_MASK): Add the MCU bit. | |
| 261 | (INSN_MCU): New macro. | |
| 262 | (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values. | |
| 263 | (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros. | |
| 264 | ||
| 2b0c8b40 MR |
265 | 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com> |
| 266 | ||
| 267 | * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros. | |
| 268 | (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise. | |
| 269 | (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise. | |
| 270 | (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise. | |
| 271 | (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise. | |
| 272 | (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise. | |
| 273 | (INSN2_READ_GPR_MMN): Likewise. | |
| 274 | (INSN2_READ_FPR_D): Change the bit used. | |
| 275 | (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise. | |
| 276 | (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise. | |
| 277 | (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise. | |
| 278 | (INSN2_COND_BRANCH): Likewise. | |
| 279 | (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros. | |
| 280 | (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise. | |
| 281 | (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise. | |
| 282 | (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise. | |
| 283 | (INSN2_MOD_GPR_MN): Likewise. | |
| 284 | ||
| ea783ef3 DM |
285 | 2011-08-05 David S. Miller <davem@davemloft.net> |
| 286 | ||
| 287 | * sparc.h: Document new format codes '4', '5', and '('. | |
| 288 | (OPF_LOW4, RS3): New macros. | |
| 289 | ||
| 7c176fa8 MR |
290 | 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com> |
| 291 | ||
| 292 | * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the | |
| 293 | order of flags documented. | |
| 294 | ||
| 2309ddf2 MR |
295 | 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com> |
| 296 | ||
| 297 | * mips.h: Clarify the description of microMIPS instruction | |
| 298 | manipulation macros. | |
| 299 | (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros. | |
| 300 | ||
| df58fc94 | 301 | 2011-07-24 Chao-ying Fu <fu@mips.com> |
| b3e14eda | 302 | Maciej W. Rozycki <macro@codesourcery.com> |
| df58fc94 RS |
303 | |
| 304 | * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros. | |
| 305 | (OP_MASK_STYPE, OP_SH_STYPE): Likewise. | |
| 306 | (OP_MASK_CODE10, OP_SH_CODE10): Likewise. | |
| 307 | (OP_MASK_TRAP, OP_SH_TRAP): Likewise. | |
| 308 | (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise. | |
| 309 | (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise. | |
| 310 | (OP_MASK_RS3, OP_SH_RS3): Likewise. | |
| 311 | (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise. | |
| 312 | (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise. | |
| 313 | (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise. | |
| 314 | (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise. | |
| 315 | (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise. | |
| 316 | (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise. | |
| 317 | (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise. | |
| 318 | (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise. | |
| 319 | (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise. | |
| 320 | (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise. | |
| 321 | (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise. | |
| 322 | (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise. | |
| 323 | (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise. | |
| 324 | (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise. | |
| 325 | (INSN_WRITE_GPR_S): New macro. | |
| 326 | (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise. | |
| 327 | (INSN2_READ_FPR_D): Likewise. | |
| 328 | (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise. | |
| 329 | (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise. | |
| 330 | (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise. | |
| 331 | (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise. | |
| 332 | (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise. | |
| 333 | (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise. | |
| 334 | (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise. | |
| 335 | (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise. | |
| 336 | (CPU_MICROMIPS): New macro. | |
| 337 | (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values. | |
| 338 | (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise. | |
| 339 | (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise. | |
| 340 | (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise. | |
| 341 | (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise. | |
| 342 | (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise. | |
| 343 | (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise. | |
| 344 | (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise. | |
| 345 | (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise. | |
| 346 | (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise. | |
| 347 | (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise. | |
| 348 | (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise. | |
| 349 | (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise. | |
| 350 | (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros. | |
| 351 | (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise. | |
| 352 | (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise. | |
| 353 | (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise. | |
| 354 | (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise. | |
| 355 | (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise. | |
| 356 | (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise. | |
| 357 | (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise. | |
| 358 | (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise. | |
| 359 | (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise. | |
| 360 | (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise. | |
| 361 | (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise. | |
| 362 | (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise. | |
| 363 | (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise. | |
| 364 | (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise. | |
| 365 | (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise. | |
| 366 | (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise. | |
| 367 | (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise. | |
| 368 | (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise. | |
| 369 | (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise. | |
| 370 | (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise. | |
| 371 | (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise. | |
| 372 | (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise. | |
| 373 | (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise. | |
| 374 | (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise. | |
| 375 | (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise. | |
| 376 | (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise. | |
| 377 | (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise. | |
| 378 | (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise. | |
| 379 | (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise. | |
| 380 | (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise. | |
| 381 | (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise. | |
| 382 | (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise. | |
| 383 | (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise. | |
| 384 | (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise. | |
| 385 | (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise. | |
| 386 | (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise. | |
| 387 | (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise. | |
| 388 | (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise. | |
| 389 | (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise. | |
| 390 | (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise. | |
| 391 | (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise. | |
| 392 | (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise. | |
| 393 | (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise. | |
| 394 | (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise. | |
| 395 | (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise. | |
| 396 | (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise. | |
| 397 | (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise. | |
| 398 | (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise. | |
| 399 | (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise. | |
| 400 | (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise. | |
| 401 | (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise. | |
| 402 | (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise. | |
| 403 | (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise. | |
| 404 | (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise. | |
| 405 | (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise. | |
| 406 | (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise. | |
| 407 | (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise. | |
| 408 | (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise. | |
| 409 | (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise. | |
| 410 | (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise. | |
| 411 | (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise. | |
| 412 | (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise. | |
| 413 | (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise. | |
| 414 | (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise. | |
| 415 | (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise. | |
| 416 | (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise. | |
| 417 | (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise. | |
| 418 | (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise. | |
| 419 | (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise. | |
| 420 | (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise. | |
| 421 | (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise. | |
| 422 | (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise. | |
| 423 | (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise. | |
| 424 | (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise. | |
| 425 | (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. | |
| 426 | (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise. | |
| 427 | (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. | |
| 428 | (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. | |
| 429 | (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. | |
| 430 | (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. | |
| 431 | (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. | |
| 432 | (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise. | |
| 433 | (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. | |
| 434 | (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise. | |
| 435 | (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise. | |
| 436 | (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise. | |
| 437 | (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise. | |
| 438 | (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise. | |
| 439 | (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise. | |
| 440 | (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise. | |
| 441 | (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise. | |
| 442 | (micromips_opcodes): New declaration. | |
| 443 | (bfd_micromips_num_opcodes): Likewise. | |
| 444 | ||
| bcd530a7 RS |
445 | 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com> |
| 446 | ||
| 447 | * mips.h (INSN_TRAP): Rename to... | |
| 448 | (INSN_NO_DELAY_SLOT): ... this. | |
| 449 | (INSN_SYNC): Remove macro. | |
| 450 | ||
| 2dad5a91 EW |
451 | 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com> |
| 452 | ||
| 453 | * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually | |
| 454 | a duplicate of AVR_ISA_SPM. | |
| 455 | ||
| 5d73b1f1 NC |
456 | 2011-07-01 Nick Clifton <nickc@redhat.com> |
| 457 | ||
| 458 | * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX. | |
| 459 | ||
| ef26d60e MF |
460 | 2011-06-18 Robin Getz <robin.getz@analog.com> |
| 461 | ||
| 462 | * bfin.h (is_macmod_signed): New func | |
| 463 | ||
| 8fb8dca7 MF |
464 | 2011-06-18 Mike Frysinger <vapier@gentoo.org> |
| 465 | ||
| 466 | * bfin.h (is_macmod_pmove): Add missing space before func args. | |
| 467 | (is_macmod_hmove): Likewise. | |
| 468 | ||
| aa137e4d NC |
469 | 2011-06-13 Walter Lee <walt@tilera.com> |
| 470 | ||
| 471 | * tilegx.h: New file. | |
| 472 | * tilepro.h: New file. | |
| 473 | ||
| 3b2f0793 PB |
474 | 2011-05-31 Paul Brook <paul@codesourcery.com> |
| 475 | ||
| aa137e4d NC |
476 | * arm.h (ARM_ARCH_V7R_IDIV): Define. |
| 477 | ||
| 478 | 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> | |
| 479 | ||
| 480 | * s390.h: Replace S390_OPERAND_REG_EVEN with | |
| 481 | S390_OPERAND_REG_PAIR. | |
| 482 | ||
| 483 | 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> | |
| 484 | ||
| 485 | * s390.h: Add S390_OPCODE_REG_EVEN flag. | |
| 3b2f0793 | 486 | |
| ac7f631b NC |
487 | 2011-04-18 Julian Brown <julian@codesourcery.com> |
| 488 | ||
| 489 | * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask. | |
| 490 | ||
| 84701018 NC |
491 | 2011-04-11 Dan McDonald <dan@wellkeeper.com> |
| 492 | ||
| 493 | PR gas/12296 | |
| 494 | * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS. | |
| 495 | ||
| 8cc66334 EW |
496 | 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> |
| 497 | ||
| 498 | * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA): | |
| 499 | New instruction set flags. | |
| 500 | (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA. | |
| 501 | ||
| 3eebd5eb MR |
502 | 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com> |
| 503 | ||
| 504 | * mips.h (M_PREF_AB): New enum value. | |
| 505 | ||
| 26bb3ddd MF |
506 | 2011-02-12 Mike Frysinger <vapier@gentoo.org> |
| 507 | ||
| 89c0d58c MR |
508 | * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH, |
| 509 | M_IU): Define. | |
| 510 | (is_macmod_pmove, is_macmod_hmove): New functions. | |
| 26bb3ddd | 511 | |
| dd76fcb8 MF |
512 | 2011-02-11 Mike Frysinger <vapier@gentoo.org> |
| 513 | ||
| 514 | * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection. | |
| 515 | ||
| 98d23bef BS |
516 | 2011-02-04 Bernd Schmidt <bernds@codesourcery.com> |
| 517 | ||
| 518 | * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP. | |
| 519 | * tic6x.h (TIC6X_INSN_ATOMIC): Remove. | |
| 520 | ||
| 3c853d93 DA |
521 | 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 522 | ||
| 523 | PR gas/11395 | |
| 524 | * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit | |
| 525 | "bb" entries. | |
| 526 | ||
| 79676006 DA |
527 | 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 528 | ||
| 529 | PR gas/11395 | |
| 530 | * hppa.h: Clear "d" bit in "add" and "sub" patterns. | |
| 531 | ||
| 1bec78e9 RS |
532 | 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com> |
| 533 | ||
| 534 | * mips.h: Update commentary after last commit. | |
| 535 | ||
| 98675402 RS |
536 | 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com> |
| 537 | ||
| 538 | * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C) | |
| 539 | (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z) | |
| 540 | (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define. | |
| 541 | ||
| aa137e4d NC |
542 | 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> |
| 543 | ||
| 544 | * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU. | |
| 545 | ||
| 435b94a4 RS |
546 | 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com> |
| 547 | ||
| 548 | * mips.h: Fix previous commit. | |
| 549 | ||
| d051516a NC |
550 | 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org> |
| 551 | ||
| 552 | * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A. | |
| 553 | (INSN_LOONGSON_3A): Clear bit 31. | |
| 554 | ||
| 251665fc MGD |
555 | 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> |
| 556 | ||
| 557 | PR gas/12198 | |
| 558 | * arm.h (ARM_AEXT_V6M_ONLY): New define. | |
| 559 | (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY. | |
| 560 | (ARM_ARCH_V6M_ONLY): New define. | |
| 561 | ||
| fd503541 NC |
562 | 2010-11-11 Mingming Sun <mingm.sun@gmail.com> |
| 563 | ||
| 564 | * mips.h (INSN_LOONGSON_3A): Defined. | |
| 565 | (CPU_LOONGSON_3A): Defined. | |
| 566 | (OPCODE_IS_MEMBER): Add LOONGSON_3A. | |
| 567 | ||
| 4469d2be AM |
568 | 2010-10-09 Matt Rice <ratmice@gmail.com> |
| 569 | ||
| 570 | * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_. | |
| 571 | (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise. | |
| 572 | ||
| 90ec0d68 MGD |
573 | 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> |
| 574 | ||
| 575 | * arm.h (ARM_EXT_VIRT): New define. | |
| 576 | (ARM_ARCH_V7A_IDIV_MP_SEC): Rename... | |
| 577 | (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization | |
| 578 | Extensions. | |
| 579 | ||
| eea54501 | 580 | 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> |
| 4469d2be | 581 | |
| eea54501 MGD |
582 | * arm.h (ARM_AEXT_ADIV): New define. |
| 583 | (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise. | |
| 584 | ||
| b2a5fbdc MGD |
585 | 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> |
| 586 | ||
| 587 | * arm.h (ARM_EXT_OS): New define. | |
| 588 | (ARM_AEXT_V6SM): Likewise. | |
| 589 | (ARM_ARCH_V6SM): Likewise. | |
| 590 | ||
| 60e5ef9f MGD |
591 | 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> |
| 592 | ||
| 593 | * arm.h (ARM_EXT_MP): Add. | |
| 594 | (ARM_ARCH_V7A_MP): Likewise. | |
| 595 | ||
| 73a63ccf MF |
596 | 2010-09-22 Mike Frysinger <vapier@gentoo.org> |
| 597 | ||
| 598 | * bfin.h: Declare pseudoChr structs/defines. | |
| 599 | ||
| ee99860a MF |
600 | 2010-09-21 Mike Frysinger <vapier@gentoo.org> |
| 601 | ||
| 602 | * bfin.h: Strip trailing whitespace. | |
| 603 | ||
| f9c7014e DD |
604 | 2010-07-29 DJ Delorie <dj@redhat.com> |
| 605 | ||
| 606 | * rx.h (RX_Operand_Type): Add TwoReg. | |
| 607 | (RX_Opcode_ID): Remove ediv and ediv2. | |
| 608 | ||
| 93378652 DD |
609 | 2010-07-27 DJ Delorie <dj@redhat.com> |
| 610 | ||
| 611 | * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics. | |
| 612 | ||
| 1cd986c5 NC |
613 | 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com> |
| 614 | Ina Pandit <ina.pandit@kpitcummins.com> | |
| 615 | ||
| 616 | * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION, | |
| 617 | PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and | |
| 618 | PROCESSOR_V850E2_ALL. | |
| 619 | Remove PROCESSOR_V850EA support. | |
| 620 | (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC, | |
| 621 | V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI, | |
| 622 | V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED, | |
| 623 | V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP, | |
| 624 | V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and | |
| 625 | V850_OPERAND_PERCENT. | |
| 626 | Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and | |
| 627 | V850_NOT_R0. | |
| 628 | Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP | |
| 629 | and V850E_PUSH_POP | |
| 630 | ||
| 9a2c7088 MR |
631 | 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com> |
| 632 | ||
| 633 | * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro. | |
| 634 | (MIPS16_INSN_BRANCH): Rename to... | |
| 635 | (MIPS16_INSN_COND_BRANCH): ... this. | |
| 636 | ||
| bdc70b4a AM |
637 | 2010-07-03 Alan Modra <amodra@gmail.com> |
| 638 | ||
| 639 | * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete. | |
| 640 | Renumber other PPC_OPCODE defines. | |
| 641 | ||
| f2bae120 AM |
642 | 2010-07-03 Alan Modra <amodra@gmail.com> |
| 643 | ||
| 644 | * ppc.h (PPC_OPCODE_COMMON): Expand comment. | |
| 645 | ||
| 360cfc9c AM |
646 | 2010-06-29 Alan Modra <amodra@gmail.com> |
| 647 | ||
| 648 | * maxq.h: Delete file. | |
| 649 | ||
| e01d869a AM |
650 | 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de> |
| 651 | ||
| 652 | * ppc.h (PPC_OPCODE_E500): Define. | |
| 653 | ||
| f79e2745 CM |
654 | 2010-05-26 Catherine Moore <clm@codesourcery.com> |
| 655 | ||
| 656 | * opcode/mips.h (INSN_MIPS16): Remove. | |
| 657 | ||
| 2462afa1 JM |
658 | 2010-04-21 Joseph Myers <joseph@codesourcery.com> |
| 659 | ||
| 660 | * tic6x-insn-formats.h (s_branch): Correct typo in bitmask. | |
| 661 | ||
| e4e42b45 NC |
662 | 2010-04-15 Nick Clifton <nickc@redhat.com> |
| 663 | ||
| 664 | * alpha.h: Update copyright notice to use GPLv3. | |
| 665 | * arc.h: Likewise. | |
| 666 | * arm.h: Likewise. | |
| 667 | * avr.h: Likewise. | |
| 668 | * bfin.h: Likewise. | |
| 669 | * cgen.h: Likewise. | |
| 670 | * convex.h: Likewise. | |
| 671 | * cr16.h: Likewise. | |
| 672 | * cris.h: Likewise. | |
| 673 | * crx.h: Likewise. | |
| 674 | * d10v.h: Likewise. | |
| 675 | * d30v.h: Likewise. | |
| 676 | * dlx.h: Likewise. | |
| 677 | * h8300.h: Likewise. | |
| 678 | * hppa.h: Likewise. | |
| 679 | * i370.h: Likewise. | |
| 680 | * i386.h: Likewise. | |
| 681 | * i860.h: Likewise. | |
| 682 | * i960.h: Likewise. | |
| 683 | * ia64.h: Likewise. | |
| 684 | * m68hc11.h: Likewise. | |
| 685 | * m68k.h: Likewise. | |
| 686 | * m88k.h: Likewise. | |
| 687 | * maxq.h: Likewise. | |
| 688 | * mips.h: Likewise. | |
| 689 | * mmix.h: Likewise. | |
| 690 | * mn10200.h: Likewise. | |
| 691 | * mn10300.h: Likewise. | |
| 692 | * msp430.h: Likewise. | |
| 693 | * np1.h: Likewise. | |
| 694 | * ns32k.h: Likewise. | |
| 695 | * or32.h: Likewise. | |
| 696 | * pdp11.h: Likewise. | |
| 697 | * pj.h: Likewise. | |
| 698 | * pn.h: Likewise. | |
| 699 | * ppc.h: Likewise. | |
| 700 | * pyr.h: Likewise. | |
| 701 | * rx.h: Likewise. | |
| 702 | * s390.h: Likewise. | |
| 703 | * score-datadep.h: Likewise. | |
| 704 | * score-inst.h: Likewise. | |
| 705 | * sparc.h: Likewise. | |
| 706 | * spu-insns.h: Likewise. | |
| 707 | * spu.h: Likewise. | |
| 708 | * tic30.h: Likewise. | |
| 709 | * tic4x.h: Likewise. | |
| 710 | * tic54x.h: Likewise. | |
| 711 | * tic80.h: Likewise. | |
| 712 | * v850.h: Likewise. | |
| 713 | * vax.h: Likewise. | |
| 714 | ||
| 40b36596 JM |
715 | 2010-03-25 Joseph Myers <joseph@codesourcery.com> |
| 716 | ||
| 717 | * tic6x-control-registers.h, tic6x-insn-formats.h, | |
| 718 | tic6x-opcode-table.h, tic6x.h: New. | |
| 719 | ||
| c67a084a NC |
720 | 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com> |
| 721 | ||
| 722 | * mips.h: (LOONGSON2F_NOP_INSN): New macro. | |
| 723 | ||
| 466ef64f AM |
724 | 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
| 725 | ||
| 726 | * opcode/ppc.h (PPC_OPCODE_TITAN): Define. | |
| 727 | ||
| 1319d143 L |
728 | 2010-01-14 H.J. Lu <hongjiu.lu@intel.com> |
| 729 | ||
| 730 | * ia64.h (ia64_find_opcode): Remove argument name. | |
| 731 | (ia64_find_next_opcode): Likewise. | |
| 732 | (ia64_dis_opcode): Likewise. | |
| 733 | (ia64_free_opcode): Likewise. | |
| 734 | (ia64_find_dependency): Likewise. | |
| 735 | ||
| 1fbb9298 DE |
736 | 2009-11-22 Doug Evans <dje@sebabeach.org> |
| 737 | ||
| 738 | * cgen.h: Include bfd_stdint.h. | |
| 739 | (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types. | |
| 740 | ||
| ada65aa3 PB |
741 | 2009-11-18 Paul Brook <paul@codesourcery.com> |
| 742 | ||
| 743 | * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define. | |
| 744 | ||
| 9e3c6df6 PB |
745 | 2009-11-17 Paul Brook <paul@codesourcery.com> |
| 746 | Daniel Jacobowitz <dan@codesourcery.com> | |
| 747 | ||
| 748 | * arm.h (ARM_EXT_V6_DSP): Define. | |
| 749 | (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP. | |
| 750 | (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define. | |
| 751 | ||
| 0d734b5d DD |
752 | 2009-11-04 DJ Delorie <dj@redhat.com> |
| 753 | ||
| 754 | * rx.h (rx_decode_opcode) (mvtipl): Add. | |
| 755 | (mvtcp, mvfcp, opecp): Remove. | |
| 756 | ||
| 62f3b8c8 PB |
757 | 2009-11-02 Paul Brook <paul@codesourcery.com> |
| 758 | ||
| 759 | * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA, | |
| 760 | FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define. | |
| 761 | (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD, | |
| 762 | FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16, | |
| 763 | FPU_ARCH_NEON_VFP_V4): Define. | |
| 764 | ||
| ac1e9eca DE |
765 | 2009-10-23 Doug Evans <dje@sebabeach.org> |
| 766 | ||
| 767 | * cgen-bitset.h: Delete, moved to ../cgen/bitset.h. | |
| 768 | * cgen.h: Update. Improve multi-inclusion macro name. | |
| 769 | ||
| 9fe54b1c PB |
770 | 2009-10-02 Peter Bergner <bergner@vnet.ibm.com> |
| 771 | ||
| 772 | * ppc.h (PPC_OPCODE_476): Define. | |
| 773 | ||
| 634b50f2 PB |
774 | 2009-10-01 Peter Bergner <bergner@vnet.ibm.com> |
| 775 | ||
| 776 | * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2. | |
| 777 | ||
| c7927a3c NC |
778 | 2009-09-29 DJ Delorie <dj@redhat.com> |
| 779 | ||
| 780 | * rx.h: New file. | |
| 781 | ||
| b961e85b AM |
782 | 2009-09-22 Peter Bergner <bergner@vnet.ibm.com> |
| 783 | ||
| 784 | * ppc.h (ppc_cpu_t): Typedef to uint64_t. | |
| 785 | ||
| e0d602ec BE |
786 | 2009-09-21 Ben Elliston <bje@au.ibm.com> |
| 787 | ||
| 788 | * ppc.h (PPC_OPCODE_PPCA2): New. | |
| 789 | ||
| 96d56e9f NC |
790 | 2009-09-05 Martin Thuresson <martin@mtme.org> |
| 791 | ||
| 792 | * ia64.h (struct ia64_operand): Renamed member class to op_class. | |
| 793 | ||
| d3ce72d0 NC |
794 | 2009-08-29 Martin Thuresson <martin@mtme.org> |
| 795 | ||
| 796 | * tic30.h (template): Rename type template to | |
| 797 | insn_template. Updated code to use new name. | |
| 798 | * tic54x.h (template): Rename type template to | |
| 799 | insn_template. | |
| 800 | ||
| 824b28db NH |
801 | 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk> |
| 802 | ||
| 803 | * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT. | |
| 804 | ||
| f865a31d AG |
805 | 2009-06-11 Anthony Green <green@moxielogic.com> |
| 806 | ||
| 807 | * moxie.h (MOXIE_F3_PCREL): Define. | |
| 808 | (moxie_form3_opc_info): Grow. | |
| 809 | ||
| 0e7c7f11 AG |
810 | 2009-06-06 Anthony Green <green@moxielogic.com> |
| 811 | ||
| 812 | * moxie.h (MOXIE_F1_M): Define. | |
| 813 | ||
| 20135e4c NC |
814 | 2009-04-15 Anthony Green <green@moxielogic.com> |
| 815 | ||
| 816 | * moxie.h: Created. | |
| 817 | ||
| bcb012d3 DD |
818 | 2009-04-06 DJ Delorie <dj@redhat.com> |
| 819 | ||
| 820 | * h8300.h: Add relaxation attributes to MOVA opcodes. | |
| 821 | ||
| 69fe9ce5 AM |
822 | 2009-03-10 Alan Modra <amodra@bigpond.net.au> |
| 823 | ||
| 824 | * ppc.h (ppc_parse_cpu): Declare. | |
| 825 | ||
| c3b7224a NC |
826 | 2009-03-02 Qinwei <qinwei@sunnorth.com.cn> |
| 827 | ||
| 828 | * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5 | |
| 829 | and _IMM11 for mbitclr and mbitset. | |
| 830 | * score-datadep.h: Update dependency information. | |
| 831 | ||
| 066be9f7 PB |
832 | 2009-02-26 Peter Bergner <bergner@vnet.ibm.com> |
| 833 | ||
| 834 | * ppc.h (PPC_OPCODE_POWER7): New. | |
| 835 | ||
| fedc618e DE |
836 | 2009-02-06 Doug Evans <dje@google.com> |
| 837 | ||
| 838 | * i386.h: Add comment regarding sse* insns and prefixes. | |
| 839 | ||
| 52b6b6b9 JM |
840 | 2009-02-03 Sandip Matte <sandip@rmicorp.com> |
| 841 | ||
| 842 | * mips.h (INSN_XLR): Define. | |
| 843 | (INSN_CHIP_MASK): Update. | |
| 844 | (CPU_XLR): Define. | |
| 845 | (OPCODE_IS_MEMBER): Update. | |
| 846 | (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define. | |
| 847 | ||
| 35669430 DE |
848 | 2009-01-28 Doug Evans <dje@google.com> |
| 849 | ||
| 850 | * opcode/i386.h: Add multiple inclusion protection. | |
| 851 | (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM) | |
| 852 | (EDI_REG_NUM): New macros. | |
| 853 | (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros. | |
| 854 | (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros. | |
| 1d801e5f | 855 | (REX_PREFIX_P): New macro. |
| 35669430 | 856 | |
| 1cb0a767 PB |
857 | 2009-01-09 Peter Bergner <bergner@vnet.ibm.com> |
| 858 | ||
| 859 | * ppc.h (struct powerpc_opcode): New field "deprecated". | |
| 860 | (PPC_OPCODE_NOPOWER4): Delete. | |
| 861 | ||
| 3aa3176b TS |
862 | 2008-11-28 Joshua Kinard <kumba@gentoo.org> |
| 863 | ||
| 864 | * mips.h: Define CPU_R14000, CPU_R16000. | |
| b3e14eda | 865 | (OPCODE_IS_MEMBER): Include R14000, R16000 in test. |
| 3aa3176b | 866 | |
| 8e79c3df CM |
867 | 2008-11-18 Catherine Moore <clm@codesourcery.com> |
| 868 | ||
| 869 | * arm.h (FPU_NEON_FP16): New. | |
| 870 | (FPU_ARCH_NEON_FP16): New. | |
| 871 | ||
| de9a3e51 CF |
872 | 2008-11-06 Chao-ying Fu <fu@mips.com> |
| 873 | ||
| 874 | * mips.h: Doucument '1' for 5-bit sync type. | |
| 875 | ||
| 1ca35711 L |
876 | 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> |
| 877 | ||
| 878 | * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update | |
| 879 | IA64_RS_CR. | |
| 880 | ||
| 9b4e5766 PB |
881 | 2008-08-01 Peter Bergner <bergner@vnet.ibm.com> |
| 882 | ||
| 883 | * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New. | |
| 884 | ||
| 081ba1b3 AM |
885 | 2008-07-30 Michael J. Eager <eager@eagercon.com> |
| 886 | ||
| 887 | * ppc.h (PPC_OPCODE_405): Define. | |
| 888 | (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define. | |
| 889 | ||
| fa452fa6 PB |
890 | 2008-06-13 Peter Bergner <bergner@vnet.ibm.com> |
| 891 | ||
| 892 | * ppc.h (ppc_cpu_t): New typedef. | |
| 893 | (struct powerpc_opcode <flags>): Use it. | |
| 894 | (struct powerpc_operand <insert, extract>): Likewise. | |
| 895 | (struct powerpc_macro <flags>): Likewise. | |
| 896 | ||
| bb35fb24 NC |
897 | 2008-06-12 Adam Nemet <anemet@caviumnetworks.com> |
| 898 | ||
| 899 | * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S. | |
| 900 | Update comment before MIPS16 field descriptors to mention MIPS16. | |
| 901 | (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for | |
| 902 | BBIT. | |
| 903 | (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1): | |
| 904 | New bit masks and shift counts for cins and exts. | |
| 905 | ||
| dd3cbb7e NC |
906 | * mips.h: Document new field descriptors +Q. |
| 907 | (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI. | |
| 908 | ||
| d0799671 AN |
909 | 2008-04-28 Adam Nemet <anemet@caviumnetworks.com> |
| 910 | ||
| 911 | * mips.h (INSN_MACRO): Move it up to the the pinfo macros. | |
| 912 | (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros. | |
| 913 | ||
| 19a6653c AM |
914 | 2008-04-14 Edmar Wienskoski <edmar@freescale.com> |
| 915 | ||
| 916 | * ppc.h: (PPC_OPCODE_E500MC): New. | |
| 917 | ||
| c0f3af97 L |
918 | 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> |
| 919 | ||
| 920 | * i386.h (MAX_OPERANDS): Set to 5. | |
| 921 | (MAX_MNEM_SIZE): Changed to 20. | |
| 922 | ||
| e210c36b NC |
923 | 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com> |
| 924 | ||
| 925 | * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167. | |
| 926 | ||
| b1cc4aeb PB |
927 | 2008-03-09 Paul Brook <paul@codesourcery.com> |
| 928 | ||
| 929 | * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define. | |
| 930 | ||
| 7e806470 PB |
931 | 2008-03-04 Paul Brook <paul@codesourcery.com> |
| 932 | ||
| 933 | * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define. | |
| 934 | (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags. | |
| 935 | (ARM_AEXT_V6M, ARM_ARCH_V6M): Define. | |
| 936 | ||
| 7b2185f9 | 937 | 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com> |
| af7329f0 NC |
938 | Nick Clifton <nickc@redhat.com> |
| 939 | ||
| 940 | PR 3134 | |
| 941 | * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction | |
| 942 | with a 32-bit displacement but without the top bit of the 4th byte | |
| e4e42b45 | 943 | set. |
| af7329f0 | 944 | |
| 796d5313 NC |
945 | 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com> |
| 946 | ||
| 947 | * cr16.h (cr16_num_optab): Declared. | |
| 948 | ||
| d669d37f NC |
949 | 2008-02-14 Hakan Ardo <hakan@debian.org> |
| 950 | ||
| 951 | PR gas/2626 | |
| 952 | * avr.h (AVR_ISA_2xxe): Define. | |
| 953 | ||
| e6429699 AN |
954 | 2008-02-04 Adam Nemet <anemet@caviumnetworks.com> |
| 955 | ||
| 956 | * mips.h: Update copyright. | |
| 957 | (INSN_CHIP_MASK): New macro. | |
| 958 | (INSN_OCTEON): New macro. | |
| 959 | (CPU_OCTEON): New macro. | |
| 960 | (OPCODE_IS_MEMBER): Handle Octeon instructions. | |
| 961 | ||
| e210c36b NC |
962 | 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com> |
| 963 | ||
| 964 | * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401. | |
| 965 | ||
| 966 | 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com> | |
| 967 | ||
| 968 | * avr.h (AVR_ISA_USB162): Add new opcode set. | |
| 969 | (AVR_ISA_AVR3): Likewise. | |
| 970 | ||
| 350cc38d MS |
971 | 2007-11-29 Mark Shinwell <shinwell@codesourcery.com> |
| 972 | ||
| 973 | * mips.h (INSN_LOONGSON_2E): New. | |
| 974 | (INSN_LOONGSON_2F): New. | |
| 975 | (CPU_LOONGSON_2E): New. | |
| 976 | (CPU_LOONGSON_2F): New. | |
| 977 | (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags. | |
| 978 | ||
| 56950294 MS |
979 | 2007-11-29 Mark Shinwell <shinwell@codesourcery.com> |
| 980 | ||
| 981 | * mips.h (INSN_ISA*): Redefine certain values as an | |
| 982 | enumeration. Update comments. | |
| 983 | (mips_isa_table): New. | |
| 984 | (ISA_MIPS*): Redefine to match enumeration. | |
| 985 | (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA* | |
| 986 | values. | |
| 987 | ||
| c3d65c1c BE |
988 | 2007-08-08 Ben Elliston <bje@au.ibm.com> |
| 989 | ||
| 990 | * ppc.h (PPC_OPCODE_PPCPS): New. | |
| 991 | ||
| 0fdaa005 L |
992 | 2007-07-03 Nathan Sidwell <nathan@codesourcery.com> |
| 993 | ||
| 994 | * m68k.h: Document j K & E. | |
| 995 | ||
| 996 | 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> | |
| 3d3d428f NC |
997 | |
| 998 | * cr16.h: New file for CR16 target. | |
| 999 | ||
| 3896c469 AM |
1000 | 2007-05-02 Alan Modra <amodra@bigpond.net.au> |
| 1001 | ||
| 1002 | * ppc.h (PPC_OPERAND_PLUS1): Update comment. | |
| 1003 | ||
| 9a2e615a NS |
1004 | 2007-04-23 Nathan Sidwell <nathan@codesourcery.com> |
| 1005 | ||
| 1006 | * m68k.h (mcfisa_c): New. | |
| 1007 | (mcfusp, mcf_mask): Adjust. | |
| 1008 | ||
| b84bf58a AM |
1009 | 2007-04-20 Alan Modra <amodra@bigpond.net.au> |
| 1010 | ||
| 1011 | * ppc.h (struct powerpc_operand): Replace "bits" with "bitm". | |
| 1012 | (num_powerpc_operands): Declare. | |
| 1013 | (PPC_OPERAND_SIGNED et al): Redefine as hex. | |
| 1014 | (PPC_OPERAND_PLUS1): Define. | |
| 1015 | ||
| 831480e9 | 1016 | 2007-03-21 H.J. Lu <hongjiu.lu@intel.com> |
| 161a04f6 L |
1017 | |
| 1018 | * i386.h (REX_MODE64): Renamed to ... | |
| 1019 | (REX_W): This. | |
| 1020 | (REX_EXTX): Renamed to ... | |
| 1021 | (REX_R): This. | |
| 1022 | (REX_EXTY): Renamed to ... | |
| 1023 | (REX_X): This. | |
| 1024 | (REX_EXTZ): Renamed to ... | |
| 1025 | (REX_B): This. | |
| 1026 | ||
| 0b1cf022 L |
1027 | 2007-03-15 H.J. Lu <hongjiu.lu@intel.com> |
| 1028 | ||
| 1029 | * i386.h: Add entries from config/tc-i386.h and move tables | |
| 1030 | to opcodes/i386-opc.h. | |
| 1031 | ||
| d796c0ad L |
1032 | 2007-03-13 H.J. Lu <hongjiu.lu@intel.com> |
| 1033 | ||
| 1034 | * i386.h (FloatDR): Removed. | |
| 1035 | (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR. | |
| 1036 | ||
| 30ac7323 AM |
1037 | 2007-03-01 Alan Modra <amodra@bigpond.net.au> |
| 1038 | ||
| 1039 | * spu-insns.h: Add soma double-float insns. | |
| 1040 | ||
| 8b082fb1 | 1041 | 2007-02-20 Thiemo Seufer <ths@mips.com> |
| d796c0ad | 1042 | Chao-Ying Fu <fu@mips.com> |
| 8b082fb1 TS |
1043 | |
| 1044 | * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. | |
| 1045 | (INSN_DSPR2): Add flag for DSP R2 instructions. | |
| 1046 | (M_BALIGN): New macro. | |
| 1047 | ||
| 4eed87de AM |
1048 | 2007-02-14 Alan Modra <amodra@bigpond.net.au> |
| 1049 | ||
| 1050 | * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm | |
| 1051 | and Seg3ShortFrom with Shortform. | |
| 1052 | ||
| fda592e8 L |
1053 | 2007-02-11 H.J. Lu <hongjiu.lu@intel.com> |
| 1054 | ||
| 1055 | PR gas/4027 | |
| 1056 | * i386.h (i386_optab): Put the real "test" before the pseudo | |
| 1057 | one. | |
| 1058 | ||
| 3bdcfdf4 KH |
1059 | 2007-01-08 Kazu Hirata <kazu@codesourcery.com> |
| 1060 | ||
| 1061 | * m68k.h (m68010up): OR fido_a. | |
| 1062 | ||
| 9840d27e KH |
1063 | 2006-12-25 Kazu Hirata <kazu@codesourcery.com> |
| 1064 | ||
| 1065 | * m68k.h (fido_a): New. | |
| 1066 | ||
| c629cdac KH |
1067 | 2006-12-24 Kazu Hirata <kazu@codesourcery.com> |
| 1068 | ||
| 1069 | * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, | |
| 1070 | mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined | |
| 1071 | values. | |
| 1072 | ||
| b7d9ef37 L |
1073 | 2006-11-08 H.J. Lu <hongjiu.lu@intel.com> |
| 1074 | ||
| 1075 | * i386.h (i386_optab): Replace CpuPNI with CpuSSE3. | |
| 1076 | ||
| b138abaa NC |
1077 | 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn> |
| 1078 | ||
| 1079 | * score-inst.h (enum score_insn_type): Add Insn_internal. | |
| 1080 | ||
| e9f53129 AM |
1081 | 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> |
| 1082 | Yukishige Shibata <shibata@rd.scei.sony.co.jp> | |
| 1083 | Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> | |
| 1084 | Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> | |
| 1085 | Alan Modra <amodra@bigpond.net.au> | |
| 1086 | ||
| 1087 | * spu-insns.h: New file. | |
| 1088 | * spu.h: New file. | |
| 1089 | ||
| ede602d7 AM |
1090 | 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> |
| 1091 | ||
| 1092 | * ppc.h (PPC_OPCODE_CELL): Define. | |
| e4e42b45 | 1093 | |
| 7918206c MM |
1094 | 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> |
| 1095 | ||
| e4e42b45 | 1096 | * i386.h : Modify opcode to support for the change in POPCNT opcode |
| 7918206c MM |
1097 | in amdfam10 architecture. |
| 1098 | ||
| ef05d495 L |
1099 | 2006-09-28 H.J. Lu <hongjiu.lu@intel.com> |
| 1100 | ||
| 1101 | * i386.h: Replace CpuMNI with CpuSSSE3. | |
| 1102 | ||
| 2d447fca | 1103 | 2006-09-26 Mark Shinwell <shinwell@codesourcery.com> |
| b3e14eda L |
1104 | Joseph Myers <joseph@codesourcery.com> |
| 1105 | Ian Lance Taylor <ian@wasabisystems.com> | |
| 1106 | Ben Elliston <bje@wasabisystems.com> | |
| 2d447fca JM |
1107 | |
| 1108 | * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. | |
| 1109 | ||
| 1c0d3aa6 NC |
1110 | 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn> |
| 1111 | ||
| 1112 | * score-datadep.h: New file. | |
| 1113 | * score-inst.h: New file. | |
| 1114 | ||
| c2f0420e L |
1115 | 2006-07-14 H.J. Lu <hongjiu.lu@intel.com> |
| 1116 | ||
| 1117 | * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, | |
| 1118 | movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, | |
| 1119 | movdq2q and movq2dq. | |
| 1120 | ||
| 050dfa73 MM |
1121 | 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> |
| 1122 | Michael Meissner <michael.meissner@amd.com> | |
| 1123 | ||
| 1124 | * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions). | |
| 1125 | ||
| 15965411 L |
1126 | 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> |
| 1127 | ||
| 1128 | * i386.h (i386_optab): Add "nop" with memory reference. | |
| 1129 | ||
| 46e883c5 L |
1130 | 2006-06-12 H.J. Lu <hongjiu.lu@intel.com> |
| 1131 | ||
| 1132 | * i386.h (i386_optab): Update comment for 64bit NOP. | |
| 1133 | ||
| 9622b051 AM |
1134 | 2006-06-06 Ben Elliston <bje@au.ibm.com> |
| 1135 | Anton Blanchard <anton@samba.org> | |
| 1136 | ||
| 1137 | * ppc.h (PPC_OPCODE_POWER6): Define. | |
| 1138 | Adjust whitespace. | |
| 1139 | ||
| a9e24354 TS |
1140 | 2006-06-05 Thiemo Seufer <ths@mips.com> |
| 1141 | ||
| e4e42b45 | 1142 | * mips.h: Improve description of MT flags. |
| a9e24354 | 1143 | |
| a596001e RS |
1144 | 2006-05-25 Richard Sandiford <richard@codesourcery.com> |
| 1145 | ||
| 1146 | * m68k.h (mcf_mask): Define. | |
| 1147 | ||
| d43b4baf | 1148 | 2006-05-05 Thiemo Seufer <ths@mips.com> |
| b3e14eda | 1149 | David Ung <davidu@mips.com> |
| d43b4baf TS |
1150 | |
| 1151 | * mips.h (enum): Add macro M_CACHE_AB. | |
| 1152 | ||
| 39a7806d | 1153 | 2006-05-04 Thiemo Seufer <ths@mips.com> |
| b3e14eda | 1154 | Nigel Stephens <nigel@mips.com> |
| 39a7806d TS |
1155 | David Ung <davidu@mips.com> |
| 1156 | ||
| 1157 | * mips.h: Add INSN_SMARTMIPS define. | |
| 1158 | ||
| 9bcd4f99 | 1159 | 2006-04-30 Thiemo Seufer <ths@mips.com> |
| b3e14eda | 1160 | David Ung <davidu@mips.com> |
| 9bcd4f99 TS |
1161 | |
| 1162 | * mips.h: Defines udi bits and masks. Add description of | |
| 1163 | characters which may appear in the args field of udi | |
| 1164 | instructions. | |
| 1165 | ||
| ef0ee844 TS |
1166 | 2006-04-26 Thiemo Seufer <ths@networkno.de> |
| 1167 | ||
| 1168 | * mips.h: Improve comments describing the bitfield instruction | |
| 1169 | fields. | |
| 1170 | ||
| f7675147 L |
1171 | 2006-04-26 Julian Brown <julian@codesourcery.com> |
| 1172 | ||
| 1173 | * arm.h (FPU_VFP_EXT_V3): Define constant. | |
| 1174 | (FPU_NEON_EXT_V1): Likewise. | |
| 1175 | (FPU_VFP_HARD): Update. | |
| 1176 | (FPU_VFP_V3): Define macro. | |
| 1177 | (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. | |
| 1178 | ||
| ef0ee844 | 1179 | 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> |
| d727e8c2 NC |
1180 | |
| 1181 | * avr.h (AVR_ISA_PWMx): New. | |
| 1182 | ||
| 2da12c60 NS |
1183 | 2006-03-28 Nathan Sidwell <nathan@codesourcery.com> |
| 1184 | ||
| 1185 | * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, | |
| 1186 | cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, | |
| 1187 | cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, | |
| 1188 | cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, | |
| 1189 | cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. | |
| 1190 | ||
| 0715c387 PB |
1191 | 2006-03-10 Paul Brook <paul@codesourcery.com> |
| 1192 | ||
| 1193 | * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. | |
| 1194 | ||
| 34bdd094 DA |
1195 | 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 1196 | ||
| 1197 | * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come | |
| 1198 | first. Correct mask of bb "B" opcode. | |
| 1199 | ||
| 331d2d0d L |
1200 | 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> |
| 1201 | ||
| 1202 | * i386.h (i386_optab): Support Intel Merom New Instructions. | |
| 1203 | ||
| 62b3e311 PB |
1204 | 2006-02-24 Paul Brook <paul@codesourcery.com> |
| 1205 | ||
| 1206 | * arm.h: Add V7 feature bits. | |
| 1207 | ||
| 59cf82fe L |
1208 | 2006-02-23 H.J. Lu <hongjiu.lu@intel.com> |
| 1209 | ||
| 1210 | * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. | |
| 1211 | ||
| e74cfd16 PB |
1212 | 2006-01-31 Paul Brook <paul@codesourcery.com> |
| 1213 | Richard Earnshaw <rearnsha@arm.com> | |
| 1214 | ||
| 1215 | * arm.h: Use ARM_CPU_FEATURE. | |
| 1216 | (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. | |
| 1217 | (arm_feature_set): Change to a structure. | |
| 1218 | (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, | |
| 1219 | ARM_FEATURE): New macros. | |
| 1220 | ||
| 5b3f8a92 HPN |
1221 | 2005-12-07 Hans-Peter Nilsson <hp@axis.com> |
| 1222 | ||
| 1223 | * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) | |
| 1224 | (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. | |
| 1225 | (ADD_PC_INCR_OPCODE): Don't define. | |
| 1226 | ||
| cb712a9e L |
1227 | 2005-12-06 H.J. Lu <hongjiu.lu@intel.com> |
| 1228 | ||
| 1229 | PR gas/1874 | |
| 1230 | * i386.h (i386_optab): Add 64bit support for monitor and mwait. | |
| 1231 | ||
| 0499d65b TS |
1232 | 2005-11-14 David Ung <davidu@mips.com> |
| 1233 | ||
| 1234 | * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore | |
| 1235 | instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for | |
| 1236 | save/restore encoding of the args field. | |
| 1237 | ||
| ea5ca089 DB |
1238 | 2005-10-28 Dave Brolley <brolley@redhat.com> |
| 1239 | ||
| 1240 | Contribute the following changes: | |
| 1241 | 2005-02-16 Dave Brolley <brolley@redhat.com> | |
| 1242 | ||
| 1243 | * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename | |
| 1244 | cgen_isa_mask_* to cgen_bitset_*. | |
| 1245 | * cgen.h: Likewise. | |
| 1246 | ||
| 16175d96 DB |
1247 | 2003-10-21 Richard Sandiford <rsandifo@redhat.com> |
| 1248 | ||
| 1249 | * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. | |
| 1250 | (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". | |
| 1251 | (CGEN_CPU_TABLE): Make isas a ponter. | |
| 1252 | ||
| 1253 | 2003-09-29 Dave Brolley <brolley@redhat.com> | |
| 1254 | ||
| 1255 | * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. | |
| 1256 | (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. | |
| 1257 | (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. | |
| 1258 | ||
| 1259 | 2002-12-13 Dave Brolley <brolley@redhat.com> | |
| 1260 | ||
| 1261 | * cgen.h (symcat.h): #include it. | |
| 1262 | (cgen-bitset.h): #include it. | |
| 1263 | (CGEN_ATTR_VALUE_TYPE): Now a union. | |
| 1264 | (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h. | |
| 1265 | (CGEN_ATTR_ENTRY): 'value' now unsigned. | |
| 1266 | (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). | |
| 1267 | * cgen-bitset.h: New file. | |
| 1268 | ||
| 3c9b82ba NC |
1269 | 2005-09-30 Catherine Moore <clm@cm00re.com> |
| 1270 | ||
| 1271 | * bfin.h: New file. | |
| 1272 | ||
| 6a2375c6 JB |
1273 | 2005-10-24 Jan Beulich <jbeulich@novell.com> |
| 1274 | ||
| 1275 | * ia64.h (enum ia64_opnd): Move memory operand out of set of | |
| 1276 | indirect operands. | |
| 1277 | ||
| c06a12f8 DA |
1278 | 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 1279 | ||
| 1280 | * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. | |
| 1281 | Add FLAG_STRICT to pa10 ftest opcode. | |
| 1282 | ||
| 4d443107 DA |
1283 | 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 1284 | ||
| 1285 | * hppa.h (pa_opcodes): Remove lha entries. | |
| 1286 | ||
| f0a3b40f DA |
1287 | 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 1288 | ||
| 1289 | * hppa.h (FLAG_STRICT): Revise comment. | |
| 1290 | (pa_opcode): Revise ordering rules. Add/move strict pa10 variants | |
| 1291 | before corresponding pa11 opcodes. Add strict pa10 register-immediate | |
| 1292 | entries for "fdc". | |
| 1293 | ||
| e210c36b NC |
1294 | 2005-09-30 Catherine Moore <clm@cm00re.com> |
| 1295 | ||
| 1296 | * bfin.h: New file. | |
| 1297 | ||
| 1b7e1362 DA |
1298 | 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 1299 | ||
| 1300 | * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. | |
| 1301 | ||
| 089b39de CF |
1302 | 2005-09-06 Chao-ying Fu <fu@mips.com> |
| 1303 | ||
| 1304 | * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, | |
| 1305 | OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New | |
| 1306 | define. | |
| 1307 | Document !, $, *, &, g, +t, +T operand formats for MT instructions. | |
| 1308 | (INSN_ASE_MASK): Update to include INSN_MT. | |
| 1309 | (INSN_MT): New define for MT ASE. | |
| 1310 | ||
| 93c34b9b CF |
1311 | 2005-08-25 Chao-ying Fu <fu@mips.com> |
| 1312 | ||
| 1313 | * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, | |
| 1314 | OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, | |
| 1315 | OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, | |
| 1316 | OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, | |
| 1317 | OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. | |
| 1318 | Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP | |
| 1319 | instructions. | |
| 1320 | (INSN_DSP): New define for DSP ASE. | |
| 1321 | ||
| 848cf006 AM |
1322 | 2005-08-18 Alan Modra <amodra@bigpond.net.au> |
| 1323 | ||
| 1324 | * a29k.h: Delete. | |
| 1325 | ||
| 36ae0db3 DJ |
1326 | 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com> |
| 1327 | ||
| 1328 | * ppc.h (PPC_OPCODE_E300): Define. | |
| 1329 | ||
| 8c929562 MS |
1330 | 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> |
| 1331 | ||
| 1332 | * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. | |
| 1333 | ||
| f7b8cccc DA |
1334 | 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 1335 | ||
| 1336 | PR gas/336 | |
| 1337 | * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb | |
| 1338 | and pitlb. | |
| 1339 | ||
| 8b5328ac JB |
1340 | 2005-07-27 Jan Beulich <jbeulich@novell.com> |
| 1341 | ||
| 1342 | * i386.h (i386_optab): Add comment to movd. Use LongMem for all | |
| 1343 | movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. | |
| 1344 | Add movq-s as 64-bit variants of movd-s. | |
| 1345 | ||
| f417d200 DA |
1346 | 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 1347 | ||
| 18b3bdfc DA |
1348 | * hppa.h: Fix punctuation in comment. |
| 1349 | ||
| f417d200 DA |
1350 | * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for |
| 1351 | implicit space-register addressing. Set space-register bits on opcodes | |
| 1352 | using implicit space-register addressing. Add various missing pa20 | |
| 1353 | long-immediate opcodes. Remove various opcodes using implicit 3-bit | |
| 1354 | space-register addressing. Use "fE" instead of "fe" in various | |
| 1355 | fstw opcodes. | |
| 1356 | ||
| 9a145ce6 JB |
1357 | 2005-07-18 Jan Beulich <jbeulich@novell.com> |
| 1358 | ||
| 1359 | * i386.h (i386_optab): Operands of aam and aad are unsigned. | |
| 1360 | ||
| 90700ea2 L |
1361 | 2007-07-15 H.J. Lu <hongjiu.lu@intel.com> |
| 1362 | ||
| 1363 | * i386.h (i386_optab): Support Intel VMX Instructions. | |
| 1364 | ||
| 48f130a8 DA |
1365 | 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 1366 | ||
| 1367 | * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. | |
| 1368 | ||
| 30123838 JB |
1369 | 2005-07-05 Jan Beulich <jbeulich@novell.com> |
| 1370 | ||
| 1371 | * i386.h (i386_optab): Add new insns. | |
| 1372 | ||
| 47b0e7ad NC |
1373 | 2005-07-01 Nick Clifton <nickc@redhat.com> |
| 1374 | ||
| 1375 | * sparc.h: Add typedefs to structure declarations. | |
| 1376 | ||
| b300c311 L |
1377 | 2005-06-20 H.J. Lu <hongjiu.lu@intel.com> |
| 1378 | ||
| 1379 | PR 1013 | |
| 1380 | * i386.h (i386_optab): Update comments for 64bit addressing on | |
| 1381 | mov. Allow 64bit addressing for mov and movq. | |
| 1382 | ||
| 2db495be DA |
1383 | 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 1384 | ||
| 1385 | * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, | |
| 1386 | respectively, in various floating-point load and store patterns. | |
| 1387 | ||
| caa05036 DA |
1388 | 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> |
| 1389 | ||
| 1390 | * hppa.h (FLAG_STRICT): Correct comment. | |
| 1391 | (pa_opcodes): Update load and store entries to allow both PA 1.X and | |
| 1392 | PA 2.0 mneumonics when equivalent. Entries with cache control | |
| 1393 | completers now require PA 1.1. Adjust whitespace. | |
| 1394 | ||
| f4411256 AM |
1395 | 2005-05-19 Anton Blanchard <anton@samba.org> |
| 1396 | ||
| 1397 | * ppc.h (PPC_OPCODE_POWER5): Define. | |
| 1398 | ||
| e172dbf8 NC |
1399 | 2005-05-10 Nick Clifton <nickc@redhat.com> |
| 1400 | ||
| 1401 | * Update the address and phone number of the FSF organization in | |
| 1402 | the GPL notices in the following files: | |
| 1403 | a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, | |
| 1404 | crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, | |
| 1405 | i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, | |
| 1406 | mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, | |
| 1407 | pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, | |
| 1408 | tic54x.h, tic80.h, v850.h, vax.h | |
| 1409 | ||
| e44823cf JB |
1410 | 2005-05-09 Jan Beulich <jbeulich@novell.com> |
| 1411 | ||
| 1412 | * i386.h (i386_optab): Add ht and hnt. | |
| 1413 | ||
| 791fe849 MK |
1414 | 2005-04-18 Mark Kettenis <kettenis@gnu.org> |
| 1415 | ||
| 1416 | * i386.h: Insert hyphens into selected VIA PadLock extensions. | |
| 1417 | Add xcrypt-ctr. Provide aliases without hyphens. | |
| 1418 | ||
| faa7ef87 L |
1419 | 2005-04-13 H.J. Lu <hongjiu.lu@intel.com> |
| 1420 | ||
| a63027e5 L |
1421 | Moved from ../ChangeLog |
| 1422 | ||
| faa7ef87 L |
1423 | 2005-04-12 Paul Brook <paul@codesourcery.com> |
| 1424 | * m88k.h: Rename psr macros to avoid conflicts. | |
| 1425 | ||
| 1426 | 2005-03-12 Zack Weinberg <zack@codesourcery.com> | |
| 1427 | * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. | |
| 1428 | Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, | |
| 1429 | and ARM_ARCH_V6ZKT2. | |
| 1430 | ||
| 1431 | 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> | |
| 1432 | * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. | |
| 1433 | Remove redundant instruction types. | |
| 1434 | (struct argument): X_op - new field. | |
| 1435 | (struct cst4_entry): Remove. | |
| 1436 | (no_op_insn): Declare. | |
| 1437 | ||
| 1438 | 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> | |
| 1439 | * crx.h (enum argtype): Rename types, remove unused types. | |
| 1440 | ||
| 1441 | 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> | |
| 1442 | * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. | |
| 1443 | (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. | |
| 1444 | (enum operand_type): Rearrange operands, edit comments. | |
| 1445 | replace us<N> with ui<N> for unsigned immediate. | |
| 1446 | replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped | |
| 1447 | displacements (respectively). | |
| 1448 | replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. | |
| 1449 | (instruction type): Add NO_TYPE_INS. | |
| 1450 | (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. | |
| 1451 | (operand_entry): New field - 'flags'. | |
| 1452 | (operand flags): New. | |
| 1453 | ||
| 1454 | 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> | |
| 1455 | * crx.h (operand_type): Remove redundant types i3, i4, | |
| 1456 | i5, i8, i12. | |
| 1457 | Add new unsigned immediate types us3, us4, us5, us16. | |
| 1458 | ||
| bc4bd9ab MK |
1459 | 2005-04-12 Mark Kettenis <kettenis@gnu.org> |
| 1460 | ||
| 1461 | * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and | |
| 1462 | adjust them accordingly. | |
| 1463 | ||
| 373ff435 JB |
1464 | 2005-04-01 Jan Beulich <jbeulich@novell.com> |
| 1465 | ||
| 1466 | * i386.h (i386_optab): Add rdtscp. | |
| 1467 | ||
| 4cc91dba L |
1468 | 2005-03-29 H.J. Lu <hongjiu.lu@intel.com> |
| 1469 | ||
| 1470 | * i386.h (i386_optab): Don't allow the `l' suffix for moving | |
| 418a8fca AS |
1471 | between memory and segment register. Allow movq for moving between |
| 1472 | general-purpose register and segment register. | |
| 4cc91dba | 1473 | |
| 9ae09ff9 JB |
1474 | 2005-02-09 Jan Beulich <jbeulich@novell.com> |
| 1475 | ||
| 1476 | PR gas/707 | |
| 1477 | * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and | |
| 1478 | FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and | |
| 1479 | fnstsw. | |
| 1480 | ||
| 638e7a64 NS |
1481 | 2006-02-07 Nathan Sidwell <nathan@codesourcery.com> |
| 1482 | ||
| 1483 | * m68k.h (m68008, m68ec030, m68882): Remove. | |
| 1484 | (m68k_mask): New. | |
| 1485 | (cpu_m68k, cpu_cf): New. | |
| 1486 | (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, | |
| 1487 | mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. | |
| 1488 | ||
| 90219bd0 AO |
1489 | 2005-01-25 Alexandre Oliva <aoliva@redhat.com> |
| 1490 | ||
| 1491 | 2004-11-10 Alexandre Oliva <aoliva@redhat.com> | |
| 1492 | * cgen.h (enum cgen_parse_operand_type): Add | |
| 1493 | CGEN_PARSE_OPERAND_SYMBOLIC. | |
| 1494 | ||
| 239cb185 FF |
1495 | 2005-01-21 Fred Fish <fnf@specifixinc.com> |
| 1496 | ||
| 1497 | * mips.h: Change INSN_ALIAS to INSN2_ALIAS. | |
| 1498 | Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. | |
| 1499 | Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. | |
| 1500 | ||
| dc9a9f39 FF |
1501 | 2005-01-19 Fred Fish <fnf@specifixinc.com> |
| 1502 | ||
| 1503 | * mips.h (struct mips_opcode): Add new pinfo2 member. | |
| 1504 | (INSN_ALIAS): New define for opcode table entries that are | |
| 1505 | specific instances of another entry, such as 'move' for an 'or' | |
| 1506 | with a zero operand. | |
| 1507 | (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. | |
| 1508 | (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. | |
| 1509 | ||
| 98e7aba8 ILT |
1510 | 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com> |
| 1511 | ||
| 1512 | * mips.h (CPU_RM9000): Define. | |
| 1513 | (OPCODE_IS_MEMBER): Handle CPU_RM9000. | |
| 1514 | ||
| 37edbb65 JB |
1515 | 2004-11-25 Jan Beulich <jbeulich@novell.com> |
| 1516 | ||
| 1517 | * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves | |
| 1518 | to/from test registers are illegal in 64-bit mode. Add missing | |
| 1519 | NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix | |
| 1520 | (previously one had to explicitly encode a rex64 prefix). Re-enable | |
| 1521 | lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings | |
| 1522 | support it there. Add cmpxchg16b as per Intel's 64-bit documentation. | |
| 1523 | ||
| 1524 | 2004-11-23 Jan Beulich <jbeulich@novell.com> | |
| 5c6af06e JB |
1525 | |
| 1526 | * i386.h (i386_optab): paddq and psubq, even in their MMX form, are | |
| 1527 | available only with SSE2. Change the MMX additions introduced by SSE | |
| 1528 | and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A | |
| 1529 | instructions by their now designated identifier (since combining i686 | |
| 1530 | and 3DNow! does not really imply 3DNow!A). | |
| 1531 | ||
| f5c7edf4 AM |
1532 | 2004-11-19 Alan Modra <amodra@bigpond.net.au> |
| 1533 | ||
| 1534 | * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, | |
| 1535 | struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. | |
| 1536 | ||
| 7499d566 NC |
1537 | 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> |
| 1538 | Vineet Sharma <vineets@noida.hcltech.com> | |
| 1539 | ||
| 1540 | * maxq.h: New file: Disassembly information for the maxq port. | |
| 1541 | ||
| bcb9eebe L |
1542 | 2004-11-05 H.J. Lu <hongjiu.lu@intel.com> |
| 1543 | ||
| 1544 | * i386.h (i386_optab): Put back "movzb". | |
| 1545 | ||
| 94bb3d38 HPN |
1546 | 2004-11-04 Hans-Peter Nilsson <hp@axis.com> |
| 1547 | ||
| 1548 | * cris.h (enum cris_insn_version_usage): Tweak formatting and | |
| 1549 | comments. Remove member cris_ver_sim. Add members | |
| 1550 | cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, | |
| 1551 | cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. | |
| 1552 | (struct cris_support_reg, struct cris_cond15): New types. | |
| 1553 | (cris_conds15): Declare. | |
| 1554 | (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) | |
| 1555 | (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) | |
| 1556 | (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. | |
| 1557 | (NOP_Z_BITS): Define in terms of NOP_OPCODE. | |
| 1558 | (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and | |
| 1559 | SIZE_FIELD_UNSIGNED. | |
| 1560 | ||
| 37edbb65 | 1561 | 2004-11-04 Jan Beulich <jbeulich@novell.com> |
| 9306ca4a JB |
1562 | |
| 1563 | * i386.h (sldx_Suf): Remove. | |
| 1564 | (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. | |
| 1565 | (q_FP): Define, implying no REX64. | |
| 1566 | (x_FP, sl_FP): Imply FloatMF. | |
| 1567 | (i386_optab): Split reg and mem forms of moving from segment registers | |
| 1568 | so that the memory forms can ignore the 16-/32-bit operand size | |
| 1569 | distinction. Adjust a few others for Intel mode. Remove *FP uses from | |
| 1570 | all non-floating-point instructions. Unite 32- and 64-bit forms of | |
| 1571 | movsx, movzx, and movd. Adjust floating point operations for the above | |
| 1572 | changes to the *FP macros. Add DefaultSize to floating point control | |
| 1573 | insns operating on larger memory ranges. Remove left over comments | |
| 1574 | hinting at certain insns being Intel-syntax ones where the ones | |
| 1575 | actually meant are already gone. | |
| 1576 | ||
| 48c9f030 NC |
1577 | 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com> |
| 1578 | ||
| 1579 | * crx.h: Add COPS_REG_INS - Coprocessor Special register | |
| 1580 | instruction type. | |
| 1581 | ||
| 0dd132b6 NC |
1582 | 2004-09-30 Paul Brook <paul@codesourcery.com> |
| 1583 | ||
| 1584 | * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. | |
| 1585 | (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. | |
| 1586 | ||
| 23794b24 MM |
1587 | 2004-09-11 Theodore A. Roth <troth@openavr.org> |
| 1588 | ||
| 1589 | * avr.h: Add support for | |
| 1590 | atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. | |
| 1591 | ||
| 2a309db0 AM |
1592 | 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org> |
| 1593 | ||
| 1594 | * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. | |
| 1595 | ||
| b18c562e NC |
1596 | 2004-08-24 Dmitry Diky <diwil@spec.ru> |
| 1597 | ||
| 1598 | * msp430.h (msp430_opc): Add new instructions. | |
| 1599 | (msp430_rcodes): Declare new instructions. | |
| 1600 | (msp430_hcodes): Likewise.. | |
| 1601 | ||
| 45d313cd NC |
1602 | 2004-08-13 Nick Clifton <nickc@redhat.com> |
| 1603 | ||
| 1604 | PR/301 | |
| 1605 | * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX | |
| 1606 | processors. | |
| 1607 | ||
| 30d1c836 ML |
1608 | 2004-08-30 Michal Ludvig <mludvig@suse.cz> |
| 1609 | ||
| 1610 | * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. | |
| 1611 | ||
| 9a45f1c2 L |
1612 | 2004-07-22 H.J. Lu <hongjiu.lu@intel.com> |
| 1613 | ||
| 1614 | * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. | |
| 1615 | ||
| 543613e9 NC |
1616 | 2004-07-21 Jan Beulich <jbeulich@novell.com> |
| 1617 | ||
| 1618 | * i386.h: Adjust instruction descriptions to better match the | |
| 1619 | specification. | |
| 1620 | ||
| b781e558 RE |
1621 | 2004-07-16 Richard Earnshaw <rearnsha@arm.com> |
| 1622 | ||
| 1623 | * arm.h: Remove all old content. Replace with architecture defines | |
| 1624 | from gas/config/tc-arm.c. | |
| 1625 | ||
| 8577e690 AS |
1626 | 2004-07-09 Andreas Schwab <schwab@suse.de> |
| 1627 | ||
| 1628 | * m68k.h: Fix comment. | |
| 1629 | ||
| 1fe1f39c NC |
1630 | 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> |
| 1631 | ||
| 1632 | * crx.h: New file. | |
| 1633 | ||
| 1d9f512f AM |
1634 | 2004-06-24 Alan Modra <amodra@bigpond.net.au> |
| 1635 | ||
| 1636 | * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. | |
| 1637 | ||
| be8c092b NC |
1638 | 2004-05-24 Peter Barada <peter@the-baradas.com> |
| 1639 | ||
| 1640 | * m68k.h: Add 'size' to m68k_opcode. | |
| 1641 | ||
| 6b6e92f4 NC |
1642 | 2004-05-05 Peter Barada <peter@the-baradas.com> |
| 1643 | ||
| 1644 | * m68k.h: Switch from ColdFire chip name to core variant. | |
| 1645 | ||
| 1646 | 2004-04-22 Peter Barada <peter@the-baradas.com> | |
| fd99574b NC |
1647 | |
| 1648 | * m68k.h: Add mcfmac/mcfemac definitions. Update operand | |
| 1649 | descriptions for new EMAC cases. | |
| 1650 | Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly | |
| 1651 | handle Motorola MAC syntax. | |
| 1652 | Allow disassembly of ColdFire V4e object files. | |
| 1653 | ||
| fdd12ef3 AM |
1654 | 2004-03-16 Alan Modra <amodra@bigpond.net.au> |
| 1655 | ||
| 1656 | * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. | |
| 1657 | ||
| 3922a64c L |
1658 | 2004-03-12 Jakub Jelinek <jakub@redhat.com> |
| 1659 | ||
| 1660 | * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. | |
| 1661 | ||
| 1f45d988 ML |
1662 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
| 1663 | ||
| 1664 | * i386.h (i386_optab): Added xstore as an alias for xstorerng. | |
| 1665 | ||
| 0f10071e ML |
1666 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
| 1667 | ||
| 1668 | * i386.h (i386_optab): Added xstore/xcrypt insns. | |
| 1669 | ||
| 3255318a NC |
1670 | 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> |
| 1671 | ||
| 1672 | * h8300.h (32bit ldc/stc): Add relaxing support. | |
| 1673 | ||
| ca9a79a1 | 1674 | 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> |
| fdd12ef3 | 1675 | |
| ca9a79a1 NC |
1676 | * h8300.h (BITOP): Pass MEMRELAX flag. |
| 1677 | ||
| 875a0b14 NC |
1678 | 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> |
| 1679 | ||
| 1680 | * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 | |
| 1681 | except for the H8S. | |
| 252b5132 | 1682 | |
| c9e214e5 | 1683 | For older changes see ChangeLog-9103 |
| 252b5132 | 1684 | \f |
| 752937aa NC |
1685 | Copyright (C) 2004-2012 Free Software Foundation, Inc. |
| 1686 | ||
| 1687 | Copying and distribution of this file, with or without modification, | |
| 1688 | are permitted in any medium without royalty provided the copyright | |
| 1689 | notice and this notice are preserved. | |
| 1690 | ||
| 252b5132 | 1691 | Local Variables: |
| c9e214e5 AM |
1692 | mode: change-log |
| 1693 | left-margin: 8 | |
| 1694 | fill-column: 74 | |
| 252b5132 RH |
1695 | version-control: never |
| 1696 | End: |