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[deliverable/binutils-gdb.git] / include / opcode / ChangeLog
CommitLineData
e423441d
RS		 12013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips.h: Remove references to "+I" and imm2_expr.
4
5e0dc5ba
RS		 52013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
6
7 * mips.h (M_DEXT, M_DINS): Delete.
8
0f35dbc4
RS		 92013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
10
11 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
12 (mips_optional_operand_p): New function.
13
14daeee3
RS		 142013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
15 Richard Sandiford <rdsandiford@googlemail.com>
16
17 * mips.h: Document new VU0 operand characters.
18 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
19 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
20 (OP_REG_R5900_ACC): New mips_reg_operand_types.
21 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
22 (mips_vu0_channel_mask): Declare.
23
3ccad066
RS		 242013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
25
26 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
27 (mips_int_operand_min, mips_int_operand_max): New functions.
28 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
29
fc76e730
RS		 302013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
31
32 * mips.h (mips_decode_reg_operand): New function.
33 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
34 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
35 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
36 New macros.
37 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
38 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
39 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
40 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
41 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
42 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
43 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
44 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
45 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
46 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
47 macros to cover the gaps.
48 (INSN2_MOD_SP): Replace with...
49 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
50 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
51 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
52 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
53 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
54 Delete.
55
26545944
RS		 562013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
57
58 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
59 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
60 (MIPS16_INSN_COND_BRANCH): Delete.
61
7e8b059b
L		 622013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
63 Kirill Yukhin <kirill.yukhin@intel.com>
64 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
65
66 * i386.h (BND_PREFIX_OPCODE): New.
67
c3c07478
RS		 682013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
69
70 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
71 OP_SAVE_RESTORE_LIST.
72 (decode_mips16_operand): Declare.
73
ab902481
RS		 742013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
75
76 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
77 (mips_operand, mips_int_operand, mips_mapped_int_operand)
78 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
79 (mips_pcrel_operand): New structures.
80 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
81 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
82 (decode_mips_operand, decode_micromips_operand): Declare.
83
cc537e56
RS		 842013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
85
86 * mips.h: Document MIPS16 "I" opcode.
87
f2ae14a1
RS		 882013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
89
90 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
91 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
92 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
93 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
94 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
95 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
96 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
97 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
98 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
99 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
100 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
101 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
102 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
103 Rename to...
104 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
105 (M_USD_AB): ...these.
106
5c324c16
RS		 1072013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
108
109 * mips.h: Remove documentation of "[" and "]". Update documentation
110 of "k" and the MDMX formats.
111
23e69e47
RS		 1122013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
113
114 * mips.h: Update documentation of "+s" and "+S".
115
27c5c572
RS		 1162013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
117
118 * mips.h: Document "+i".
119
e76ff5ab
RS		 1202013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
121
122 * mips.h: Remove "mi" documentation. Update "mh" documentation.
123 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
124 Delete.
125 (INSN2_WRITE_GPR_MHI): Rename to...
126 (INSN2_WRITE_GPR_MH): ...this.
127
fa7616a4
RS		 1282013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
129
130 * mips.h: Remove documentation of "+D" and "+T".
131
18870af7
RS		 1322013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
133
134 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
135 Use "source" rather than "destination" for microMIPS "G".
136
833794fc
MR		 1372013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
138
139 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
140 values.
141
c3678916
RS		 1422013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
143
144 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
145
7f3c4072
CM		 1462013-06-17 Catherine Moore <clm@codesourcery.com>
147 Maciej W. Rozycki <macro@codesourcery.com>
148 Chao-Ying Fu <fu@mips.com>
149
150 * mips.h (OP_SH_EVAOFFSET): Define.
151 (OP_MASK_EVAOFFSET): Define.
152 (INSN_ASE_MASK): Delete.
153 (ASE_EVA): Define.
154 (M_CACHEE_AB, M_CACHEE_OB): New.
155 (M_LBE_OB, M_LBE_AB): New.
156 (M_LBUE_OB, M_LBUE_AB): New.
157 (M_LHE_OB, M_LHE_AB): New.
158 (M_LHUE_OB, M_LHUE_AB): New.
159 (M_LLE_AB, M_LLE_OB): New.
160 (M_LWE_OB, M_LWE_AB): New.
161 (M_LWLE_AB, M_LWLE_OB): New.
162 (M_LWRE_AB, M_LWRE_OB): New.
163 (M_PREFE_AB, M_PREFE_OB): New.
164 (M_SCE_AB, M_SCE_OB): New.
165 (M_SBE_OB, M_SBE_AB): New.
166 (M_SHE_OB, M_SHE_AB): New.
167 (M_SWE_OB, M_SWE_AB): New.
168 (M_SWLE_AB, M_SWLE_OB): New.
169 (M_SWRE_AB, M_SWRE_OB): New.
170 (MICROMIPSOP_SH_EVAOFFSET): Define.
171 (MICROMIPSOP_MASK_EVAOFFSET): Define.
172
0c8fe7cf
SL		 1732013-06-12 Sandra Loosemore <sandra@codesourcery.com>
174
175 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
176
c77c0862
RS		 1772013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
178
179 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
180
b015e599
AP		 1812013-05-09 Andrew Pinski <apinski@cavium.com>
182
183 * mips.h (OP_MASK_CODE10): Correct definition.
184 (OP_SH_CODE10): Likewise.
185 Add a comment that "+J" is used now for OP_*CODE10.
186 (INSN_ASE_MASK): Update.
187 (INSN_VIRT): New macro.
188 (INSN_VIRT64): New macro
189
13761a11
NC		 1902013-05-02 Nick Clifton <nickc@redhat.com>
191
192 * msp430.h: Add patterns for MSP430X instructions.
193
0afd1215
DM		 1942013-04-06 David S. Miller <davem@davemloft.net>
195
196 * sparc.h (F_PREFERRED): Define.
197 (F_PREF_ALIAS): Define.
198
41702d50
NC		 1992013-04-03 Nick Clifton <nickc@redhat.com>
200
201 * v850.h (V850_INVERSE_PCREL): Define.
202
e21e1a51
NC		 2032013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
204
205 PR binutils/15068
206 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
207
51dcdd4d
NC		 2082013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
209
210 PR binutils/15068
211 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
212 Add 16-bit opcodes.
213 * tic6xc-opcode-table.h: Add 16-bit insns.
214 * tic6x.h: Add support for 16-bit insns.
215
81f5558e
NC		 2162013-03-21 Michael Schewe <michael.schewe@gmx.net>
217
218 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
219 and mov.b/w/l Rs,@(d:32,ERd).
220
165546ad
NC		 2212013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
222
223 PR gas/15082
224 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
225 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
226 tic6x_operand_xregpair operand coding type.
227 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
228 opcode field, usu ORXREGD1324 for the src2 operand and remove the
229 TIC6X_FLAG_NO_CROSS.
230
795b8e6b
NC		 2312013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
232
233 PR gas/15095
234 * tic6x.h (enum tic6x_coding_method): Add
235 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
236 separately the msb and lsb of a register pair. This is needed to
237 encode the opcodes in the same way as TI assembler does.
238 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
239 and rsqrdp opcodes to use the new field coding types.
240
dd5181d5
KT		 2412013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
242
243 * arm.h (CRC_EXT_ARMV8): New constant.
244 (ARCH_CRC_ARMV8): New macro.
245
e60bb1dd
YZ		 2462013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
247
248 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
249
36591ba1
SL		 2502013-02-06 Sandra Loosemore <sandra@codesourcery.com>
251 Andrew Jenner <andrew@codesourcery.com>
252
253 Based on patches from Altera Corporation.
254
255 * nios2.h: New file.
256
e30181a5
YZ		 2572013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
258
259 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
260
0c9573f4
NC		 2612013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
262
263 PR gas/15069
264 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
265
981dc7f1
NC		 2662013-01-24 Nick Clifton <nickc@redhat.com>
267
268 * v850.h: Add e3v5 support.
269
f5555712
YZ		 2702013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
271
272 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
273
5817ffd1
PB		 2742013-01-10 Peter Bergner <bergner@vnet.ibm.com>
275
276 * ppc.h (PPC_OPCODE_POWER8): New define.
277 (PPC_OPCODE_HTM): Likewise.
278
a3c62988
NC		 2792013-01-10 Will Newton <will.newton@imgtec.com>
280
281 * metag.h: New file.
282
73335eae
NC		 2832013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
284
285 * cr16.h (make_instruction): Rename to cr16_make_instruction.
286 (match_opcode): Rename to cr16_match_opcode.
287
e407c74b
NC		 2882013-01-04 Juergen Urban <JuergenUrban@gmx.de>
289
290 * mips.h: Add support for r5900 instructions including lq and sq.
291
bab4becb
NC		 2922013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
293
294 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
295 (make_instruction,match_opcode): Added function prototypes.
296 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
297
776fc418
AM		 2982012-11-23 Alan Modra <amodra@gmail.com>
299
300 * ppc.h (ppc_parse_cpu): Update prototype.
301
f05682d4
DA		 3022012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
303
304 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
305 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
306
cfc72779
AK		 3072012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
308
309 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
310
b3e14eda
L		 3112012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
312
313 * ia64.h (ia64_opnd): Add new operand types.
314
2c63854f
DM		 3152012-08-21 David S. Miller <davem@davemloft.net>
316
317 * sparc.h (F3F4): New macro.
318
a06ea964 3192012-08-13 Ian Bolton <ian.bolton@arm.com>
b3e14eda
L		 320 Laurent Desnogues <laurent.desnogues@arm.com>
321 Jim MacArthur <jim.macarthur@arm.com>
322 Marcus Shawcroft <marcus.shawcroft@arm.com>
323 Nigel Stephens <nigel.stephens@arm.com>
324 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
325 Richard Earnshaw <rearnsha@arm.com>
326 Sofiane Naci <sofiane.naci@arm.com>
327 Tejas Belagod <tejas.belagod@arm.com>
328 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 329
330 * aarch64.h: New file.
331
35d0a169 3322012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
b3e14eda 333 Maciej W. Rozycki <macro@codesourcery.com>
35d0a169
MR		 334
335 * mips.h (mips_opcode): Add the exclusions field.
336 (OPCODE_IS_MEMBER): Remove macro.
337 (cpu_is_member): New inline function.
338 (opcode_is_member): Likewise.
339
03f66e8a 3402012-07-31 Chao-Ying Fu <fu@mips.com>
b3e14eda
L		 341 Catherine Moore <clm@codesourcery.com>
342 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 343
344 * mips.h: Document microMIPS DSP ASE usage.
345 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
346 microMIPS DSP ASE support.
347 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
348 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
349 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
350 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
351 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
352 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
353 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
354
9d7b4c23
MR		 3552012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
356
357 * mips.h: Fix a typo in description.
358
76e879f8
NC		 3592012-06-07 Georg-Johann Lay <avr@gjlay.de>
360
361 * avr.h: (AVR_ISA_XCH): New define.
362 (AVR_ISA_XMEGA): Use it.
363 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
364
6927f982
NC		 3652012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
366
367 * m68hc11.h: Add XGate definitions.
368 (struct m68hc11_opcode): Add xg_mask field.
369
b9c361e0
JL		 3702012-05-14 Catherine Moore <clm@codesourcery.com>
371 Maciej W. Rozycki <macro@codesourcery.com>
372 Rhonda Wittels <rhonda@codesourcery.com>
373
6927f982 374 * ppc.h (PPC_OPCODE_VLE): New definition.
b9c361e0
JL		 375 (PPC_OP_SA): New macro.
376 (PPC_OP_SE_VLE): New macro.
377 (PPC_OP): Use a variable shift amount.
378 (powerpc_operand): Update comments.
379 (PPC_OPSHIFT_INV): New macro.
380 (PPC_OPERAND_CR): Replace with...
381 (PPC_OPERAND_CR_BIT): ...this and
382 (PPC_OPERAND_CR_REG): ...this.
383
384
f6c1a2d5
NC		 3852012-05-03 Sean Keys <skeys@ipdatasys.com>
386
387 * xgate.h: Header file for XGATE assembler.
388
ec668d69
DM		 3892012-04-27 David S. Miller <davem@davemloft.net>
390
6cda1326
DM		 391 * sparc.h: Document new arg code' )' for crypto RS3
392 immediates.
393
ec668d69
DM		 394 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
395 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
396 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
397 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
398 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
399 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
400 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
401 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
402 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
403 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
404 HWCAP_CBCOND, HWCAP_CRC32): New defines.
405
aea77599
AM		 4062012-03-10 Edmar Wienskoski <edmar@freescale.com>
407
408 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
409
1f42f8b3
AM		 4102012-02-27 Alan Modra <amodra@gmail.com>
411
412 * crx.h (cst4_map): Update declaration.
413
6f7be959
WL		 4142012-02-25 Walter Lee <walt@tilera.com>
415
416 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
417 TILEGX_OPC_LD_TLS.
418 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
419 TILEPRO_OPC_LW_TLS_SN.
420
42164a71
L		 4212012-02-08 H.J. Lu <hongjiu.lu@intel.com>
422
423 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
424 (XRELEASE_PREFIX_OPCODE): Likewise.
425
432233b3 4262011-12-08 Andrew Pinski <apinski@cavium.com>
b3e14eda 427 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 428
429 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
430 (INSN_OCTEON2): New macro.
431 (CPU_OCTEON2): New macro.
432 (OPCODE_IS_MEMBER): Add Octeon2.
433
dd6a37e7
AP		 4342011-11-29 Andrew Pinski <apinski@cavium.com>
435
436 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
437 (INSN_OCTEONP): New macro.
438 (CPU_OCTEONP): New macro.
439 (OPCODE_IS_MEMBER): Add Octeon+.
440 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
441
99c513f6
DD		 4422011-11-01 DJ Delorie <dj@redhat.com>
443
444 * rl78.h: New file.
445
26f85d7a
MR		 4462011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
447
448 * mips.h: Fix a typo in description.
449
9e8c70f9
DM		 4502011-09-21 David S. Miller <davem@davemloft.net>
451
452 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
453 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
454 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
455 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
456
dec0624d 4572011-08-09 Chao-ying Fu <fu@mips.com>
b3e14eda 458 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 459
460 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
461 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
462 (INSN_ASE_MASK): Add the MCU bit.
463 (INSN_MCU): New macro.
464 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
465 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
466
2b0c8b40
MR		 4672011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
468
469 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
470 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
471 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
472 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
473 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
474 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
475 (INSN2_READ_GPR_MMN): Likewise.
476 (INSN2_READ_FPR_D): Change the bit used.
477 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
478 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
479 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
480 (INSN2_COND_BRANCH): Likewise.
481 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
482 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
483 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
484 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
485 (INSN2_MOD_GPR_MN): Likewise.
486
ea783ef3
DM		 4872011-08-05 David S. Miller <davem@davemloft.net>
488
489 * sparc.h: Document new format codes '4', '5', and '('.
490 (OPF_LOW4, RS3): New macros.
491
7c176fa8
MR		 4922011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
493
494 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
495 order of flags documented.
496
2309ddf2
MR		 4972011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
498
499 * mips.h: Clarify the description of microMIPS instruction
500 manipulation macros.
501 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
502
df58fc94 5032011-07-24 Chao-ying Fu <fu@mips.com>
b3e14eda 504 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 505
506 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
507 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
508 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
509 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
510 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
511 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
512 (OP_MASK_RS3, OP_SH_RS3): Likewise.
513 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
514 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
515 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
516 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
517 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
518 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
519 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
520 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
521 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
522 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
523 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
524 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
525 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
526 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
527 (INSN_WRITE_GPR_S): New macro.
528 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
529 (INSN2_READ_FPR_D): Likewise.
530 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
531 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
532 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
533 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
534 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
535 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
536 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
537 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
538 (CPU_MICROMIPS): New macro.
539 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
540 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
541 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
542 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
543 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
544 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
545 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
546 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
547 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
548 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
549 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
550 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
551 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
552 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
553 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
554 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
555 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
556 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
557 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
558 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
559 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
560 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
561 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
562 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
563 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
564 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
565 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
566 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
567 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
568 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
569 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
570 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
571 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
572 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
573 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
574 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
575 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
576 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
577 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
578 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
579 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
580 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
581 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
582 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
583 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
584 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
585 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
586 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
587 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
588 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
589 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
590 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
591 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
592 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
593 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
594 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
595 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
596 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
597 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
598 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
599 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
600 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
601 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
602 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
603 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
604 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
605 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
606 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
607 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
608 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
609 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
610 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
611 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
612 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
613 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
614 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
615 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
616 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
617 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
618 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
619 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
620 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
621 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
622 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
623 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
624 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
625 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
626 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
627 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
628 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
629 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
630 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
631 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
632 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
633 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
634 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
635 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
636 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
637 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
638 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
639 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
640 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
641 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
642 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
643 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
644 (micromips_opcodes): New declaration.
645 (bfd_micromips_num_opcodes): Likewise.
646
bcd530a7
RS		 6472011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
648
649 * mips.h (INSN_TRAP): Rename to...
650 (INSN_NO_DELAY_SLOT): ... this.
651 (INSN_SYNC): Remove macro.
652
2dad5a91
EW		 6532011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
654
655 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
656 a duplicate of AVR_ISA_SPM.
657
5d73b1f1
NC		 6582011-07-01 Nick Clifton <nickc@redhat.com>
659
660 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
661
ef26d60e
MF		 6622011-06-18 Robin Getz <robin.getz@analog.com>
663
664 * bfin.h (is_macmod_signed): New func
665
8fb8dca7
MF		 6662011-06-18 Mike Frysinger <vapier@gentoo.org>
667
668 * bfin.h (is_macmod_pmove): Add missing space before func args.
669 (is_macmod_hmove): Likewise.
670
aa137e4d
NC		 6712011-06-13 Walter Lee <walt@tilera.com>
672
673 * tilegx.h: New file.
674 * tilepro.h: New file.
675
3b2f0793
PB		 6762011-05-31 Paul Brook <paul@codesourcery.com>
677
aa137e4d
NC		 678 * arm.h (ARM_ARCH_V7R_IDIV): Define.
679
6802011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
681
682 * s390.h: Replace S390_OPERAND_REG_EVEN with
683 S390_OPERAND_REG_PAIR.
684
6852011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
686
687 * s390.h: Add S390_OPCODE_REG_EVEN flag.
3b2f0793 688
ac7f631b
NC		 6892011-04-18 Julian Brown <julian@codesourcery.com>
690
691 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
692
84701018
NC		 6932011-04-11 Dan McDonald <dan@wellkeeper.com>
694
695 PR gas/12296
696 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
697
8cc66334
EW		 6982011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
699
700 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
701 New instruction set flags.
702 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
703
3eebd5eb
MR		 7042011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
705
706 * mips.h (M_PREF_AB): New enum value.
707
26bb3ddd
MF		 7082011-02-12 Mike Frysinger <vapier@gentoo.org>
709
89c0d58c
MR		 710 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
711 M_IU): Define.
712 (is_macmod_pmove, is_macmod_hmove): New functions.
26bb3ddd 713
dd76fcb8
MF		 7142011-02-11 Mike Frysinger <vapier@gentoo.org>
715
716 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
717
98d23bef
BS		 7182011-02-04 Bernd Schmidt <bernds@codesourcery.com>
719
720 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
721 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
722
3c853d93
DA		 7232010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
724
725 PR gas/11395
726 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
727 "bb" entries.
728
79676006
DA		 7292010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
730
731 PR gas/11395
732 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
733
1bec78e9
RS		 7342010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
735
736 * mips.h: Update commentary after last commit.
737
98675402
RS		 7382010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
739
740 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
741 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
742 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
743
aa137e4d
NC		 7442010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
745
746 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
747
435b94a4
RS		 7482010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
749
750 * mips.h: Fix previous commit.
751
d051516a
NC		 7522010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
753
754 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
755 (INSN_LOONGSON_3A): Clear bit 31.
756
251665fc
MGD		 7572010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
758
759 PR gas/12198
760 * arm.h (ARM_AEXT_V6M_ONLY): New define.
761 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
762 (ARM_ARCH_V6M_ONLY): New define.
763
fd503541
NC		 7642010-11-11 Mingming Sun <mingm.sun@gmail.com>
765
766 * mips.h (INSN_LOONGSON_3A): Defined.
767 (CPU_LOONGSON_3A): Defined.
768 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
769
4469d2be
AM		 7702010-10-09 Matt Rice <ratmice@gmail.com>
771
772 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
773 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
774
90ec0d68
MGD		 7752010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
776
777 * arm.h (ARM_EXT_VIRT): New define.
778 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
779 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
780 Extensions.
781
eea54501 7822010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
4469d2be 783
eea54501
MGD		 784 * arm.h (ARM_AEXT_ADIV): New define.
785 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
786
b2a5fbdc
MGD		 7872010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
788
789 * arm.h (ARM_EXT_OS): New define.
790 (ARM_AEXT_V6SM): Likewise.
791 (ARM_ARCH_V6SM): Likewise.
792
60e5ef9f
MGD		 7932010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
794
795 * arm.h (ARM_EXT_MP): Add.
796 (ARM_ARCH_V7A_MP): Likewise.
797
73a63ccf
MF		 7982010-09-22 Mike Frysinger <vapier@gentoo.org>
799
800 * bfin.h: Declare pseudoChr structs/defines.
801
ee99860a
MF		 8022010-09-21 Mike Frysinger <vapier@gentoo.org>
803
804 * bfin.h: Strip trailing whitespace.
805
f9c7014e
DD		 8062010-07-29 DJ Delorie <dj@redhat.com>
807
808 * rx.h (RX_Operand_Type): Add TwoReg.
809 (RX_Opcode_ID): Remove ediv and ediv2.
810
93378652
DD		 8112010-07-27 DJ Delorie <dj@redhat.com>
812
813 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
814
1cd986c5
NC		 8152010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
816 Ina Pandit <ina.pandit@kpitcummins.com>
817
818 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
819 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
820 PROCESSOR_V850E2_ALL.
821 Remove PROCESSOR_V850EA support.
822 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
823 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
824 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
825 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
826 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
827 V850_OPERAND_PERCENT.
828 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
829 V850_NOT_R0.
830 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
831 and V850E_PUSH_POP
832
9a2c7088
MR		 8332010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
834
835 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
836 (MIPS16_INSN_BRANCH): Rename to...
837 (MIPS16_INSN_COND_BRANCH): ... this.
838
bdc70b4a
AM		 8392010-07-03 Alan Modra <amodra@gmail.com>
840
841 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
842 Renumber other PPC_OPCODE defines.
843
f2bae120
AM		 8442010-07-03 Alan Modra <amodra@gmail.com>
845
846 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
847
360cfc9c
AM		 8482010-06-29 Alan Modra <amodra@gmail.com>
849
850 * maxq.h: Delete file.
851
e01d869a
AM		 8522010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
853
854 * ppc.h (PPC_OPCODE_E500): Define.
855
f79e2745
CM		 8562010-05-26 Catherine Moore <clm@codesourcery.com>
857
858 * opcode/mips.h (INSN_MIPS16): Remove.
859
2462afa1
JM		 8602010-04-21 Joseph Myers <joseph@codesourcery.com>
861
862 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
863
e4e42b45
NC		 8642010-04-15 Nick Clifton <nickc@redhat.com>
865
866 * alpha.h: Update copyright notice to use GPLv3.
867 * arc.h: Likewise.
868 * arm.h: Likewise.
869 * avr.h: Likewise.
870 * bfin.h: Likewise.
871 * cgen.h: Likewise.
872 * convex.h: Likewise.
873 * cr16.h: Likewise.
874 * cris.h: Likewise.
875 * crx.h: Likewise.
876 * d10v.h: Likewise.
877 * d30v.h: Likewise.
878 * dlx.h: Likewise.
879 * h8300.h: Likewise.
880 * hppa.h: Likewise.
881 * i370.h: Likewise.
882 * i386.h: Likewise.
883 * i860.h: Likewise.
884 * i960.h: Likewise.
885 * ia64.h: Likewise.
886 * m68hc11.h: Likewise.
887 * m68k.h: Likewise.
888 * m88k.h: Likewise.
889 * maxq.h: Likewise.
890 * mips.h: Likewise.
891 * mmix.h: Likewise.
892 * mn10200.h: Likewise.
893 * mn10300.h: Likewise.
894 * msp430.h: Likewise.
895 * np1.h: Likewise.
896 * ns32k.h: Likewise.
897 * or32.h: Likewise.
898 * pdp11.h: Likewise.
899 * pj.h: Likewise.
900 * pn.h: Likewise.
901 * ppc.h: Likewise.
902 * pyr.h: Likewise.
903 * rx.h: Likewise.
904 * s390.h: Likewise.
905 * score-datadep.h: Likewise.
906 * score-inst.h: Likewise.
907 * sparc.h: Likewise.
908 * spu-insns.h: Likewise.
909 * spu.h: Likewise.
910 * tic30.h: Likewise.
911 * tic4x.h: Likewise.
912 * tic54x.h: Likewise.
913 * tic80.h: Likewise.
914 * v850.h: Likewise.
915 * vax.h: Likewise.
916
40b36596
JM		 9172010-03-25 Joseph Myers <joseph@codesourcery.com>
918
919 * tic6x-control-registers.h, tic6x-insn-formats.h,
920 tic6x-opcode-table.h, tic6x.h: New.
921
c67a084a
NC		 9222010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
923
924 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
925
466ef64f
AM		 9262010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
927
928 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
929
1319d143
L		 9302010-01-14 H.J. Lu <hongjiu.lu@intel.com>
931
932 * ia64.h (ia64_find_opcode): Remove argument name.
933 (ia64_find_next_opcode): Likewise.
934 (ia64_dis_opcode): Likewise.
935 (ia64_free_opcode): Likewise.
936 (ia64_find_dependency): Likewise.
937
1fbb9298
DE		 9382009-11-22 Doug Evans <dje@sebabeach.org>
939
940 * cgen.h: Include bfd_stdint.h.
941 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
942
ada65aa3
PB		 9432009-11-18 Paul Brook <paul@codesourcery.com>
944
945 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
946
9e3c6df6
PB		 9472009-11-17 Paul Brook <paul@codesourcery.com>
948 Daniel Jacobowitz <dan@codesourcery.com>
949
950 * arm.h (ARM_EXT_V6_DSP): Define.
951 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
952 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
953
0d734b5d
DD		 9542009-11-04 DJ Delorie <dj@redhat.com>
955
956 * rx.h (rx_decode_opcode) (mvtipl): Add.
957 (mvtcp, mvfcp, opecp): Remove.
958
62f3b8c8
PB		 9592009-11-02 Paul Brook <paul@codesourcery.com>
960
961 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
962 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
963 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
964 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
965 FPU_ARCH_NEON_VFP_V4): Define.
966
ac1e9eca
DE		 9672009-10-23 Doug Evans <dje@sebabeach.org>
968
969 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
970 * cgen.h: Update. Improve multi-inclusion macro name.
971
9fe54b1c
PB		 9722009-10-02 Peter Bergner <bergner@vnet.ibm.com>
973
974 * ppc.h (PPC_OPCODE_476): Define.
975
634b50f2
PB		 9762009-10-01 Peter Bergner <bergner@vnet.ibm.com>
977
978 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
979
c7927a3c
NC		 9802009-09-29 DJ Delorie <dj@redhat.com>
981
982 * rx.h: New file.
983
b961e85b
AM		 9842009-09-22 Peter Bergner <bergner@vnet.ibm.com>
985
986 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
987
e0d602ec
BE		 9882009-09-21 Ben Elliston <bje@au.ibm.com>
989
990 * ppc.h (PPC_OPCODE_PPCA2): New.
991
96d56e9f
NC		 9922009-09-05 Martin Thuresson <martin@mtme.org>
993
994 * ia64.h (struct ia64_operand): Renamed member class to op_class.
995
d3ce72d0
NC		 9962009-08-29 Martin Thuresson <martin@mtme.org>
997
998 * tic30.h (template): Rename type template to
999 insn_template. Updated code to use new name.
1000 * tic54x.h (template): Rename type template to
1001 insn_template.
1002
824b28db
NH		 10032009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1004
1005 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1006
f865a31d
AG		 10072009-06-11 Anthony Green <green@moxielogic.com>
1008
1009 * moxie.h (MOXIE_F3_PCREL): Define.
1010 (moxie_form3_opc_info): Grow.
1011
0e7c7f11
AG		 10122009-06-06 Anthony Green <green@moxielogic.com>
1013
1014 * moxie.h (MOXIE_F1_M): Define.
1015
20135e4c
NC		 10162009-04-15 Anthony Green <green@moxielogic.com>
1017
1018 * moxie.h: Created.
1019
bcb012d3
DD		 10202009-04-06 DJ Delorie <dj@redhat.com>
1021
1022 * h8300.h: Add relaxation attributes to MOVA opcodes.
1023
69fe9ce5
AM		 10242009-03-10 Alan Modra <amodra@bigpond.net.au>
1025
1026 * ppc.h (ppc_parse_cpu): Declare.
1027
c3b7224a
NC		 10282009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1029
1030 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1031 and _IMM11 for mbitclr and mbitset.
1032 * score-datadep.h: Update dependency information.
1033
066be9f7
PB		 10342009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1035
1036 * ppc.h (PPC_OPCODE_POWER7): New.
1037
fedc618e
DE		 10382009-02-06 Doug Evans <dje@google.com>
1039
1040 * i386.h: Add comment regarding sse* insns and prefixes.
1041
52b6b6b9
JM		 10422009-02-03 Sandip Matte <sandip@rmicorp.com>
1043
1044 * mips.h (INSN_XLR): Define.
1045 (INSN_CHIP_MASK): Update.
1046 (CPU_XLR): Define.
1047 (OPCODE_IS_MEMBER): Update.
1048 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1049
35669430
DE		 10502009-01-28 Doug Evans <dje@google.com>
1051
1052 * opcode/i386.h: Add multiple inclusion protection.
1053 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1054 (EDI_REG_NUM): New macros.
1055 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1056 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1d801e5f 1057 (REX_PREFIX_P): New macro.
35669430 1058
1cb0a767
PB		 10592009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1060
1061 * ppc.h (struct powerpc_opcode): New field "deprecated".
1062 (PPC_OPCODE_NOPOWER4): Delete.
1063
3aa3176b
TS		 10642008-11-28 Joshua Kinard <kumba@gentoo.org>
1065
1066 * mips.h: Define CPU_R14000, CPU_R16000.
b3e14eda 1067 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
3aa3176b 1068
8e79c3df
CM		 10692008-11-18 Catherine Moore <clm@codesourcery.com>
1070
1071 * arm.h (FPU_NEON_FP16): New.
1072 (FPU_ARCH_NEON_FP16): New.
1073
de9a3e51
CF		 10742008-11-06 Chao-ying Fu <fu@mips.com>
1075
1076 * mips.h: Doucument '1' for 5-bit sync type.
1077
1ca35711
L		 10782008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1079
1080 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1081 IA64_RS_CR.
1082
9b4e5766
PB		 10832008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1084
1085 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1086
081ba1b3
AM		 10872008-07-30 Michael J. Eager <eager@eagercon.com>
1088
1089 * ppc.h (PPC_OPCODE_405): Define.
1090 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1091
fa452fa6
PB		 10922008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1093
1094 * ppc.h (ppc_cpu_t): New typedef.
1095 (struct powerpc_opcode <flags>): Use it.
1096 (struct powerpc_operand <insert, extract>): Likewise.
1097 (struct powerpc_macro <flags>): Likewise.
1098
bb35fb24
NC		 10992008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1100
1101 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1102 Update comment before MIPS16 field descriptors to mention MIPS16.
1103 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1104 BBIT.
1105 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1106 New bit masks and shift counts for cins and exts.
1107
dd3cbb7e
NC		 1108 * mips.h: Document new field descriptors +Q.
1109 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1110
d0799671
AN		 11112008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1112
1113 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
1114 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1115
19a6653c
AM		 11162008-04-14 Edmar Wienskoski <edmar@freescale.com>
1117
1118 * ppc.h: (PPC_OPCODE_E500MC): New.
1119
c0f3af97
L		 11202008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1121
1122 * i386.h (MAX_OPERANDS): Set to 5.
1123 (MAX_MNEM_SIZE): Changed to 20.
1124
e210c36b
NC		 11252008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1126
1127 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1128
b1cc4aeb
PB		 11292008-03-09 Paul Brook <paul@codesourcery.com>
1130
1131 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1132
7e806470
PB		 11332008-03-04 Paul Brook <paul@codesourcery.com>
1134
1135 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1136 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1137 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1138
7b2185f9 11392008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
af7329f0
NC		 1140 Nick Clifton <nickc@redhat.com>
1141
1142 PR 3134
1143 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1144 with a 32-bit displacement but without the top bit of the 4th byte
e4e42b45 1145 set.
af7329f0 1146
796d5313
NC		 11472008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1148
1149 * cr16.h (cr16_num_optab): Declared.
1150
d669d37f
NC		 11512008-02-14 Hakan Ardo <hakan@debian.org>
1152
1153 PR gas/2626
1154 * avr.h (AVR_ISA_2xxe): Define.
1155
e6429699
AN		 11562008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1157
1158 * mips.h: Update copyright.
1159 (INSN_CHIP_MASK): New macro.
1160 (INSN_OCTEON): New macro.
1161 (CPU_OCTEON): New macro.
1162 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1163
e210c36b
NC		 11642008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1165
1166 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1167
11682008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1169
1170 * avr.h (AVR_ISA_USB162): Add new opcode set.
1171 (AVR_ISA_AVR3): Likewise.
1172
350cc38d
MS		 11732007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1174
1175 * mips.h (INSN_LOONGSON_2E): New.
1176 (INSN_LOONGSON_2F): New.
1177 (CPU_LOONGSON_2E): New.
1178 (CPU_LOONGSON_2F): New.
1179 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1180
56950294
MS		 11812007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1182
1183 * mips.h (INSN_ISA*): Redefine certain values as an
1184 enumeration. Update comments.
1185 (mips_isa_table): New.
1186 (ISA_MIPS*): Redefine to match enumeration.
1187 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1188 values.
1189
c3d65c1c
BE		 11902007-08-08 Ben Elliston <bje@au.ibm.com>
1191
1192 * ppc.h (PPC_OPCODE_PPCPS): New.
1193
0fdaa005
L		 11942007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1195
1196 * m68k.h: Document j K & E.
1197
11982007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
3d3d428f
NC		 1199
1200 * cr16.h: New file for CR16 target.
1201
3896c469
AM		 12022007-05-02 Alan Modra <amodra@bigpond.net.au>
1203
1204 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1205
9a2e615a
NS		 12062007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1207
1208 * m68k.h (mcfisa_c): New.
1209 (mcfusp, mcf_mask): Adjust.
1210
b84bf58a
AM		 12112007-04-20 Alan Modra <amodra@bigpond.net.au>
1212
1213 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1214 (num_powerpc_operands): Declare.
1215 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1216 (PPC_OPERAND_PLUS1): Define.
1217
831480e9 12182007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 1219
1220 * i386.h (REX_MODE64): Renamed to ...
1221 (REX_W): This.
1222 (REX_EXTX): Renamed to ...
1223 (REX_R): This.
1224 (REX_EXTY): Renamed to ...
1225 (REX_X): This.
1226 (REX_EXTZ): Renamed to ...
1227 (REX_B): This.
1228
0b1cf022
L		 12292007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1230
1231 * i386.h: Add entries from config/tc-i386.h and move tables
1232 to opcodes/i386-opc.h.
1233
d796c0ad
L		 12342007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1235
1236 * i386.h (FloatDR): Removed.
1237 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1238
30ac7323
AM		 12392007-03-01 Alan Modra <amodra@bigpond.net.au>
1240
1241 * spu-insns.h: Add soma double-float insns.
1242
8b082fb1 12432007-02-20 Thiemo Seufer <ths@mips.com>
d796c0ad 1244 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 1245
1246 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1247 (INSN_DSPR2): Add flag for DSP R2 instructions.
1248 (M_BALIGN): New macro.
1249
4eed87de
AM		 12502007-02-14 Alan Modra <amodra@bigpond.net.au>
1251
1252 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1253 and Seg3ShortFrom with Shortform.
1254
fda592e8
L		 12552007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1256
1257 PR gas/4027
1258 * i386.h (i386_optab): Put the real "test" before the pseudo
1259 one.
1260
3bdcfdf4
KH		 12612007-01-08 Kazu Hirata <kazu@codesourcery.com>
1262
1263 * m68k.h (m68010up): OR fido_a.
1264
9840d27e
KH		 12652006-12-25 Kazu Hirata <kazu@codesourcery.com>
1266
1267 * m68k.h (fido_a): New.
1268
c629cdac
KH		 12692006-12-24 Kazu Hirata <kazu@codesourcery.com>
1270
1271 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1272 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1273 values.
1274
b7d9ef37
L		 12752006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1276
1277 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1278
b138abaa
NC		 12792006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1280
1281 * score-inst.h (enum score_insn_type): Add Insn_internal.
1282
e9f53129
AM		 12832006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1284 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1285 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1286 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1287 Alan Modra <amodra@bigpond.net.au>
1288
1289 * spu-insns.h: New file.
1290 * spu.h: New file.
1291
ede602d7
AM		 12922006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1293
1294 * ppc.h (PPC_OPCODE_CELL): Define.
e4e42b45 1295
7918206c
MM		 12962006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1297
e4e42b45 1298 * i386.h : Modify opcode to support for the change in POPCNT opcode
7918206c
MM		 1299 in amdfam10 architecture.
1300
ef05d495
L		 13012006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1302
1303 * i386.h: Replace CpuMNI with CpuSSSE3.
1304
2d447fca 13052006-09-26 Mark Shinwell <shinwell@codesourcery.com>
b3e14eda
L		 1306 Joseph Myers <joseph@codesourcery.com>
1307 Ian Lance Taylor <ian@wasabisystems.com>
1308 Ben Elliston <bje@wasabisystems.com>
2d447fca
JM		 1309
1310 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1311
1c0d3aa6
NC		 13122006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1313
1314 * score-datadep.h: New file.
1315 * score-inst.h: New file.
1316
c2f0420e
L		 13172006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1318
1319 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1320 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1321 movdq2q and movq2dq.
1322
050dfa73
MM		 13232006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1324 Michael Meissner <michael.meissner@amd.com>
1325
1326 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1327
15965411
L		 13282006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1329
1330 * i386.h (i386_optab): Add "nop" with memory reference.
1331
46e883c5
L		 13322006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1333
1334 * i386.h (i386_optab): Update comment for 64bit NOP.
1335
9622b051
AM		 13362006-06-06 Ben Elliston <bje@au.ibm.com>
1337 Anton Blanchard <anton@samba.org>
1338
1339 * ppc.h (PPC_OPCODE_POWER6): Define.
1340 Adjust whitespace.
1341
a9e24354
TS		 13422006-06-05 Thiemo Seufer <ths@mips.com>
1343
e4e42b45 1344 * mips.h: Improve description of MT flags.
a9e24354 1345
a596001e
RS		 13462006-05-25 Richard Sandiford <richard@codesourcery.com>
1347
1348 * m68k.h (mcf_mask): Define.
1349
d43b4baf 13502006-05-05 Thiemo Seufer <ths@mips.com>
b3e14eda 1351 David Ung <davidu@mips.com>
d43b4baf
TS		 1352
1353 * mips.h (enum): Add macro M_CACHE_AB.
1354
39a7806d 13552006-05-04 Thiemo Seufer <ths@mips.com>
b3e14eda 1356 Nigel Stephens <nigel@mips.com>
39a7806d
TS		 1357 David Ung <davidu@mips.com>
1358
1359 * mips.h: Add INSN_SMARTMIPS define.
1360
9bcd4f99 13612006-04-30 Thiemo Seufer <ths@mips.com>
b3e14eda 1362 David Ung <davidu@mips.com>
9bcd4f99
TS		 1363
1364 * mips.h: Defines udi bits and masks. Add description of
1365 characters which may appear in the args field of udi
1366 instructions.
1367
ef0ee844
TS		 13682006-04-26 Thiemo Seufer <ths@networkno.de>
1369
1370 * mips.h: Improve comments describing the bitfield instruction
1371 fields.
1372
f7675147
L		 13732006-04-26 Julian Brown <julian@codesourcery.com>
1374
1375 * arm.h (FPU_VFP_EXT_V3): Define constant.
1376 (FPU_NEON_EXT_V1): Likewise.
1377 (FPU_VFP_HARD): Update.
1378 (FPU_VFP_V3): Define macro.
1379 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1380
ef0ee844 13812006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
d727e8c2
NC		 1382
1383 * avr.h (AVR_ISA_PWMx): New.
1384
2da12c60
NS		 13852006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1386
1387 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1388 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1389 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1390 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1391 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1392
0715c387
PB		 13932006-03-10 Paul Brook <paul@codesourcery.com>
1394
1395 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1396
34bdd094
DA		 13972006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1398
1399 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1400 first. Correct mask of bb "B" opcode.
1401
331d2d0d
L		 14022006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1403
1404 * i386.h (i386_optab): Support Intel Merom New Instructions.
1405
62b3e311
PB		 14062006-02-24 Paul Brook <paul@codesourcery.com>
1407
1408 * arm.h: Add V7 feature bits.
1409
59cf82fe
L		 14102006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1411
1412 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1413
e74cfd16
PB		 14142006-01-31 Paul Brook <paul@codesourcery.com>
1415 Richard Earnshaw <rearnsha@arm.com>
1416
1417 * arm.h: Use ARM_CPU_FEATURE.
1418 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1419 (arm_feature_set): Change to a structure.
1420 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1421 ARM_FEATURE): New macros.
1422
5b3f8a92
HPN		 14232005-12-07 Hans-Peter Nilsson <hp@axis.com>
1424
1425 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1426 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1427 (ADD_PC_INCR_OPCODE): Don't define.
1428
cb712a9e
L		 14292005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1430
1431 PR gas/1874
1432 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1433
0499d65b
TS		 14342005-11-14 David Ung <davidu@mips.com>
1435
1436 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1437 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1438 save/restore encoding of the args field.
1439
ea5ca089
DB		 14402005-10-28 Dave Brolley <brolley@redhat.com>
1441
1442 Contribute the following changes:
1443 2005-02-16 Dave Brolley <brolley@redhat.com>
1444
1445 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1446 cgen_isa_mask_* to cgen_bitset_*.
1447 * cgen.h: Likewise.
1448
16175d96
DB		 1449 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1450
1451 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1452 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1453 (CGEN_CPU_TABLE): Make isas a ponter.
1454
1455 2003-09-29 Dave Brolley <brolley@redhat.com>
1456
1457 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1458 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1459 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1460
1461 2002-12-13 Dave Brolley <brolley@redhat.com>
1462
1463 * cgen.h (symcat.h): #include it.
1464 (cgen-bitset.h): #include it.
1465 (CGEN_ATTR_VALUE_TYPE): Now a union.
1466 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1467 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1468 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1469 * cgen-bitset.h: New file.
1470
3c9b82ba
NC		 14712005-09-30 Catherine Moore <clm@cm00re.com>
1472
1473 * bfin.h: New file.
1474
6a2375c6
JB		 14752005-10-24 Jan Beulich <jbeulich@novell.com>
1476
1477 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1478 indirect operands.
1479
c06a12f8
DA		 14802005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1481
1482 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1483 Add FLAG_STRICT to pa10 ftest opcode.
1484
4d443107
DA		 14852005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1486
1487 * hppa.h (pa_opcodes): Remove lha entries.
1488
f0a3b40f
DA		 14892005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1490
1491 * hppa.h (FLAG_STRICT): Revise comment.
1492 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1493 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1494 entries for "fdc".
1495
e210c36b
NC		 14962005-09-30 Catherine Moore <clm@cm00re.com>
1497
1498 * bfin.h: New file.
1499
1b7e1362
DA		 15002005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1501
1502 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1503
089b39de
CF		 15042005-09-06 Chao-ying Fu <fu@mips.com>
1505
1506 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1507 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1508 define.
1509 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1510 (INSN_ASE_MASK): Update to include INSN_MT.
1511 (INSN_MT): New define for MT ASE.
1512
93c34b9b
CF		 15132005-08-25 Chao-ying Fu <fu@mips.com>
1514
1515 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1516 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1517 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1518 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1519 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1520 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1521 instructions.
1522 (INSN_DSP): New define for DSP ASE.
1523
848cf006
AM		 15242005-08-18 Alan Modra <amodra@bigpond.net.au>
1525
1526 * a29k.h: Delete.
1527
36ae0db3
DJ		 15282005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1529
1530 * ppc.h (PPC_OPCODE_E300): Define.
1531
8c929562
MS		 15322005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1533
1534 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1535
f7b8cccc
DA		 15362005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1537
1538 PR gas/336
1539 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1540 and pitlb.
1541
8b5328ac
JB		 15422005-07-27 Jan Beulich <jbeulich@novell.com>
1543
1544 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1545 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1546 Add movq-s as 64-bit variants of movd-s.
1547
f417d200
DA		 15482005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1549
18b3bdfc
DA		 1550 * hppa.h: Fix punctuation in comment.
1551
f417d200
DA		 1552 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1553 implicit space-register addressing. Set space-register bits on opcodes
1554 using implicit space-register addressing. Add various missing pa20
1555 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1556 space-register addressing. Use "fE" instead of "fe" in various
1557 fstw opcodes.
1558
9a145ce6
JB		 15592005-07-18 Jan Beulich <jbeulich@novell.com>
1560
1561 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1562
90700ea2
L		 15632007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1564
1565 * i386.h (i386_optab): Support Intel VMX Instructions.
1566
48f130a8
DA		 15672005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1568
1569 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1570
30123838
JB		 15712005-07-05 Jan Beulich <jbeulich@novell.com>
1572
1573 * i386.h (i386_optab): Add new insns.
1574
47b0e7ad
NC		 15752005-07-01 Nick Clifton <nickc@redhat.com>
1576
1577 * sparc.h: Add typedefs to structure declarations.
1578
b300c311
L		 15792005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1580
1581 PR 1013
1582 * i386.h (i386_optab): Update comments for 64bit addressing on
1583 mov. Allow 64bit addressing for mov and movq.
1584
2db495be
DA		 15852005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1586
1587 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1588 respectively, in various floating-point load and store patterns.
1589
caa05036
DA		 15902005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1591
1592 * hppa.h (FLAG_STRICT): Correct comment.
1593 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1594 PA 2.0 mneumonics when equivalent. Entries with cache control
1595 completers now require PA 1.1. Adjust whitespace.
1596
f4411256
AM		 15972005-05-19 Anton Blanchard <anton@samba.org>
1598
1599 * ppc.h (PPC_OPCODE_POWER5): Define.
1600
e172dbf8
NC		 16012005-05-10 Nick Clifton <nickc@redhat.com>
1602
1603 * Update the address and phone number of the FSF organization in
1604 the GPL notices in the following files:
1605 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1606 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1607 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1608 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1609 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1610 tic54x.h, tic80.h, v850.h, vax.h
1611
e44823cf
JB		 16122005-05-09 Jan Beulich <jbeulich@novell.com>
1613
1614 * i386.h (i386_optab): Add ht and hnt.
1615
791fe849
MK		 16162005-04-18 Mark Kettenis <kettenis@gnu.org>
1617
1618 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1619 Add xcrypt-ctr. Provide aliases without hyphens.
1620
faa7ef87
L		 16212005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1622
a63027e5
L		 1623 Moved from ../ChangeLog
1624
faa7ef87
L		 1625 2005-04-12 Paul Brook <paul@codesourcery.com>
1626 * m88k.h: Rename psr macros to avoid conflicts.
1627
1628 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1629 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1630 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1631 and ARM_ARCH_V6ZKT2.
1632
1633 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1634 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1635 Remove redundant instruction types.
1636 (struct argument): X_op - new field.
1637 (struct cst4_entry): Remove.
1638 (no_op_insn): Declare.
1639
1640 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1641 * crx.h (enum argtype): Rename types, remove unused types.
1642
1643 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1644 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1645 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1646 (enum operand_type): Rearrange operands, edit comments.
1647 replace us<N> with ui<N> for unsigned immediate.
1648 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1649 displacements (respectively).
1650 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1651 (instruction type): Add NO_TYPE_INS.
1652 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1653 (operand_entry): New field - 'flags'.
1654 (operand flags): New.
1655
1656 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1657 * crx.h (operand_type): Remove redundant types i3, i4,
1658 i5, i8, i12.
1659 Add new unsigned immediate types us3, us4, us5, us16.
1660
bc4bd9ab
MK		 16612005-04-12 Mark Kettenis <kettenis@gnu.org>
1662
1663 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1664 adjust them accordingly.
1665
373ff435
JB		 16662005-04-01 Jan Beulich <jbeulich@novell.com>
1667
1668 * i386.h (i386_optab): Add rdtscp.
1669
4cc91dba
L		 16702005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1671
1672 * i386.h (i386_optab): Don't allow the `l' suffix for moving
418a8fca
AS		 1673 between memory and segment register. Allow movq for moving between
1674 general-purpose register and segment register.
4cc91dba 1675
9ae09ff9
JB		 16762005-02-09 Jan Beulich <jbeulich@novell.com>
1677
1678 PR gas/707
1679 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1680 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1681 fnstsw.
1682
638e7a64
NS		 16832006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1684
1685 * m68k.h (m68008, m68ec030, m68882): Remove.
1686 (m68k_mask): New.
1687 (cpu_m68k, cpu_cf): New.
1688 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1689 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1690
90219bd0
AO		 16912005-01-25 Alexandre Oliva <aoliva@redhat.com>
1692
1693 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1694 * cgen.h (enum cgen_parse_operand_type): Add
1695 CGEN_PARSE_OPERAND_SYMBOLIC.
1696
239cb185
FF		 16972005-01-21 Fred Fish <fnf@specifixinc.com>
1698
1699 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1700 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1701 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1702
dc9a9f39
FF		 17032005-01-19 Fred Fish <fnf@specifixinc.com>
1704
1705 * mips.h (struct mips_opcode): Add new pinfo2 member.
1706 (INSN_ALIAS): New define for opcode table entries that are
1707 specific instances of another entry, such as 'move' for an 'or'
1708 with a zero operand.
1709 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1710 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1711
98e7aba8
ILT		 17122004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1713
1714 * mips.h (CPU_RM9000): Define.
1715 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1716
37edbb65
JB		 17172004-11-25 Jan Beulich <jbeulich@novell.com>
1718
1719 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1720 to/from test registers are illegal in 64-bit mode. Add missing
1721 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1722 (previously one had to explicitly encode a rex64 prefix). Re-enable
1723 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1724 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1725
17262004-11-23 Jan Beulich <jbeulich@novell.com>
5c6af06e
JB		 1727
1728 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1729 available only with SSE2. Change the MMX additions introduced by SSE
1730 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1731 instructions by their now designated identifier (since combining i686
1732 and 3DNow! does not really imply 3DNow!A).
1733
f5c7edf4
AM		 17342004-11-19 Alan Modra <amodra@bigpond.net.au>
1735
1736 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1737 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1738
7499d566
NC		 17392004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1740 Vineet Sharma <vineets@noida.hcltech.com>
1741
1742 * maxq.h: New file: Disassembly information for the maxq port.
1743
bcb9eebe
L		 17442004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1745
1746 * i386.h (i386_optab): Put back "movzb".
1747
94bb3d38
HPN		 17482004-11-04 Hans-Peter Nilsson <hp@axis.com>
1749
1750 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1751 comments. Remove member cris_ver_sim. Add members
1752 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1753 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1754 (struct cris_support_reg, struct cris_cond15): New types.
1755 (cris_conds15): Declare.
1756 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1757 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1758 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1759 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1760 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1761 SIZE_FIELD_UNSIGNED.
1762
37edbb65 17632004-11-04 Jan Beulich <jbeulich@novell.com>
9306ca4a
JB		 1764
1765 * i386.h (sldx_Suf): Remove.
1766 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1767 (q_FP): Define, implying no REX64.
1768 (x_FP, sl_FP): Imply FloatMF.
1769 (i386_optab): Split reg and mem forms of moving from segment registers
1770 so that the memory forms can ignore the 16-/32-bit operand size
1771 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1772 all non-floating-point instructions. Unite 32- and 64-bit forms of
1773 movsx, movzx, and movd. Adjust floating point operations for the above
1774 changes to the *FP macros. Add DefaultSize to floating point control
1775 insns operating on larger memory ranges. Remove left over comments
1776 hinting at certain insns being Intel-syntax ones where the ones
1777 actually meant are already gone.
1778
48c9f030
NC		 17792004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1780
1781 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1782 instruction type.
1783
0dd132b6
NC		 17842004-09-30 Paul Brook <paul@codesourcery.com>
1785
1786 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1787 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1788
23794b24
MM		 17892004-09-11 Theodore A. Roth <troth@openavr.org>
1790
1791 * avr.h: Add support for
1792 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1793
2a309db0
AM		 17942004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1795
1796 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1797
b18c562e
NC		 17982004-08-24 Dmitry Diky <diwil@spec.ru>
1799
1800 * msp430.h (msp430_opc): Add new instructions.
1801 (msp430_rcodes): Declare new instructions.
1802 (msp430_hcodes): Likewise..
1803
45d313cd
NC		 18042004-08-13 Nick Clifton <nickc@redhat.com>
1805
1806 PR/301
1807 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1808 processors.
1809
30d1c836
ML		 18102004-08-30 Michal Ludvig <mludvig@suse.cz>
1811
1812 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1813
9a45f1c2
L		 18142004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1815
1816 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1817
543613e9
NC		 18182004-07-21 Jan Beulich <jbeulich@novell.com>
1819
1820 * i386.h: Adjust instruction descriptions to better match the
1821 specification.
1822
b781e558
RE		 18232004-07-16 Richard Earnshaw <rearnsha@arm.com>
1824
1825 * arm.h: Remove all old content. Replace with architecture defines
1826 from gas/config/tc-arm.c.
1827
8577e690
AS		 18282004-07-09 Andreas Schwab <schwab@suse.de>
1829
1830 * m68k.h: Fix comment.
1831
1fe1f39c
NC		 18322004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1833
1834 * crx.h: New file.
1835
1d9f512f
AM		 18362004-06-24 Alan Modra <amodra@bigpond.net.au>
1837
1838 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1839
be8c092b
NC		 18402004-05-24 Peter Barada <peter@the-baradas.com>
1841
1842 * m68k.h: Add 'size' to m68k_opcode.
1843
6b6e92f4
NC		 18442004-05-05 Peter Barada <peter@the-baradas.com>
1845
1846 * m68k.h: Switch from ColdFire chip name to core variant.
1847
18482004-04-22 Peter Barada <peter@the-baradas.com>
fd99574b
NC		 1849
1850 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1851 descriptions for new EMAC cases.
1852 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1853 handle Motorola MAC syntax.
1854 Allow disassembly of ColdFire V4e object files.
1855
fdd12ef3
AM		 18562004-03-16 Alan Modra <amodra@bigpond.net.au>
1857
1858 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1859
3922a64c
L		 18602004-03-12 Jakub Jelinek <jakub@redhat.com>
1861
1862 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1863
1f45d988
ML		 18642004-03-12 Michal Ludvig <mludvig@suse.cz>
1865
1866 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1867
0f10071e
ML		 18682004-03-12 Michal Ludvig <mludvig@suse.cz>
1869
1870 * i386.h (i386_optab): Added xstore/xcrypt insns.
1871
3255318a
NC		 18722004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1873
1874 * h8300.h (32bit ldc/stc): Add relaxing support.
1875
ca9a79a1 18762004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
fdd12ef3 1877
ca9a79a1
NC		 1878 * h8300.h (BITOP): Pass MEMRELAX flag.
1879
875a0b14
NC		 18802004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1881
1882 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1883 except for the H8S.
252b5132 1884
c9e214e5 1885For older changes see ChangeLog-9103
252b5132 1886\f
752937aa
NC		 1887Copyright (C) 2004-2012 Free Software Foundation, Inc.
1888
1889Copying and distribution of this file, with or without modification,
1890are permitted in any medium without royalty provided the copyright
1891notice and this notice are preserved.
1892
252b5132 1893Local Variables:
c9e214e5
AM		 1894mode: change-log
1895left-margin: 8
1896fill-column: 74
252b5132
RH		 1897version-control: never
1898End:
GDB Binutils - Deliverables
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