Commit | Line | Data |
---|---|---|
9ae09ff9 JB |
1 | 2005-02-09 Jan Beulich <jbeulich@novell.com> |
2 | ||
3 | PR gas/707 | |
4 | * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and | |
5 | FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and | |
6 | fnstsw. | |
7 | ||
90219bd0 AO |
8 | 2005-01-25 Alexandre Oliva <aoliva@redhat.com> |
9 | ||
10 | 2004-11-10 Alexandre Oliva <aoliva@redhat.com> | |
11 | * cgen.h (enum cgen_parse_operand_type): Add | |
12 | CGEN_PARSE_OPERAND_SYMBOLIC. | |
13 | ||
239cb185 FF |
14 | 2005-01-21 Fred Fish <fnf@specifixinc.com> |
15 | ||
16 | * mips.h: Change INSN_ALIAS to INSN2_ALIAS. | |
17 | Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. | |
18 | Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. | |
19 | ||
dc9a9f39 FF |
20 | 2005-01-19 Fred Fish <fnf@specifixinc.com> |
21 | ||
22 | * mips.h (struct mips_opcode): Add new pinfo2 member. | |
23 | (INSN_ALIAS): New define for opcode table entries that are | |
24 | specific instances of another entry, such as 'move' for an 'or' | |
25 | with a zero operand. | |
26 | (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. | |
27 | (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. | |
28 | ||
98e7aba8 ILT |
29 | 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com> |
30 | ||
31 | * mips.h (CPU_RM9000): Define. | |
32 | (OPCODE_IS_MEMBER): Handle CPU_RM9000. | |
33 | ||
37edbb65 JB |
34 | 2004-11-25 Jan Beulich <jbeulich@novell.com> |
35 | ||
36 | * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves | |
37 | to/from test registers are illegal in 64-bit mode. Add missing | |
38 | NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix | |
39 | (previously one had to explicitly encode a rex64 prefix). Re-enable | |
40 | lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings | |
41 | support it there. Add cmpxchg16b as per Intel's 64-bit documentation. | |
42 | ||
43 | 2004-11-23 Jan Beulich <jbeulich@novell.com> | |
5c6af06e JB |
44 | |
45 | * i386.h (i386_optab): paddq and psubq, even in their MMX form, are | |
46 | available only with SSE2. Change the MMX additions introduced by SSE | |
47 | and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A | |
48 | instructions by their now designated identifier (since combining i686 | |
49 | and 3DNow! does not really imply 3DNow!A). | |
50 | ||
f5c7edf4 AM |
51 | 2004-11-19 Alan Modra <amodra@bigpond.net.au> |
52 | ||
53 | * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, | |
54 | struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. | |
55 | ||
7499d566 NC |
56 | 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> |
57 | Vineet Sharma <vineets@noida.hcltech.com> | |
58 | ||
59 | * maxq.h: New file: Disassembly information for the maxq port. | |
60 | ||
bcb9eebe L |
61 | 2004-11-05 H.J. Lu <hongjiu.lu@intel.com> |
62 | ||
63 | * i386.h (i386_optab): Put back "movzb". | |
64 | ||
94bb3d38 HPN |
65 | 2004-11-04 Hans-Peter Nilsson <hp@axis.com> |
66 | ||
67 | * cris.h (enum cris_insn_version_usage): Tweak formatting and | |
68 | comments. Remove member cris_ver_sim. Add members | |
69 | cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, | |
70 | cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. | |
71 | (struct cris_support_reg, struct cris_cond15): New types. | |
72 | (cris_conds15): Declare. | |
73 | (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) | |
74 | (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) | |
75 | (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. | |
76 | (NOP_Z_BITS): Define in terms of NOP_OPCODE. | |
77 | (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and | |
78 | SIZE_FIELD_UNSIGNED. | |
79 | ||
37edbb65 | 80 | 2004-11-04 Jan Beulich <jbeulich@novell.com> |
9306ca4a JB |
81 | |
82 | * i386.h (sldx_Suf): Remove. | |
83 | (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. | |
84 | (q_FP): Define, implying no REX64. | |
85 | (x_FP, sl_FP): Imply FloatMF. | |
86 | (i386_optab): Split reg and mem forms of moving from segment registers | |
87 | so that the memory forms can ignore the 16-/32-bit operand size | |
88 | distinction. Adjust a few others for Intel mode. Remove *FP uses from | |
89 | all non-floating-point instructions. Unite 32- and 64-bit forms of | |
90 | movsx, movzx, and movd. Adjust floating point operations for the above | |
91 | changes to the *FP macros. Add DefaultSize to floating point control | |
92 | insns operating on larger memory ranges. Remove left over comments | |
93 | hinting at certain insns being Intel-syntax ones where the ones | |
94 | actually meant are already gone. | |
95 | ||
48c9f030 NC |
96 | 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com> |
97 | ||
98 | * crx.h: Add COPS_REG_INS - Coprocessor Special register | |
99 | instruction type. | |
100 | ||
0dd132b6 NC |
101 | 2004-09-30 Paul Brook <paul@codesourcery.com> |
102 | ||
103 | * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. | |
104 | (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. | |
105 | ||
23794b24 MM |
106 | 2004-09-11 Theodore A. Roth <troth@openavr.org> |
107 | ||
108 | * avr.h: Add support for | |
109 | atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. | |
110 | ||
2a309db0 AM |
111 | 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org> |
112 | ||
113 | * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. | |
114 | ||
b18c562e NC |
115 | 2004-08-24 Dmitry Diky <diwil@spec.ru> |
116 | ||
117 | * msp430.h (msp430_opc): Add new instructions. | |
118 | (msp430_rcodes): Declare new instructions. | |
119 | (msp430_hcodes): Likewise.. | |
120 | ||
45d313cd NC |
121 | 2004-08-13 Nick Clifton <nickc@redhat.com> |
122 | ||
123 | PR/301 | |
124 | * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX | |
125 | processors. | |
126 | ||
30d1c836 ML |
127 | 2004-08-30 Michal Ludvig <mludvig@suse.cz> |
128 | ||
129 | * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. | |
130 | ||
9a45f1c2 L |
131 | 2004-07-22 H.J. Lu <hongjiu.lu@intel.com> |
132 | ||
133 | * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. | |
134 | ||
543613e9 NC |
135 | 2004-07-21 Jan Beulich <jbeulich@novell.com> |
136 | ||
137 | * i386.h: Adjust instruction descriptions to better match the | |
138 | specification. | |
139 | ||
b781e558 RE |
140 | 2004-07-16 Richard Earnshaw <rearnsha@arm.com> |
141 | ||
142 | * arm.h: Remove all old content. Replace with architecture defines | |
143 | from gas/config/tc-arm.c. | |
144 | ||
8577e690 AS |
145 | 2004-07-09 Andreas Schwab <schwab@suse.de> |
146 | ||
147 | * m68k.h: Fix comment. | |
148 | ||
1fe1f39c NC |
149 | 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> |
150 | ||
151 | * crx.h: New file. | |
152 | ||
1d9f512f AM |
153 | 2004-06-24 Alan Modra <amodra@bigpond.net.au> |
154 | ||
155 | * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. | |
156 | ||
be8c092b NC |
157 | 2004-05-24 Peter Barada <peter@the-baradas.com> |
158 | ||
159 | * m68k.h: Add 'size' to m68k_opcode. | |
160 | ||
6b6e92f4 NC |
161 | 2004-05-05 Peter Barada <peter@the-baradas.com> |
162 | ||
163 | * m68k.h: Switch from ColdFire chip name to core variant. | |
164 | ||
165 | 2004-04-22 Peter Barada <peter@the-baradas.com> | |
fd99574b NC |
166 | |
167 | * m68k.h: Add mcfmac/mcfemac definitions. Update operand | |
168 | descriptions for new EMAC cases. | |
169 | Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly | |
170 | handle Motorola MAC syntax. | |
171 | Allow disassembly of ColdFire V4e object files. | |
172 | ||
fdd12ef3 AM |
173 | 2004-03-16 Alan Modra <amodra@bigpond.net.au> |
174 | ||
175 | * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. | |
176 | ||
3922a64c L |
177 | 2004-03-12 Jakub Jelinek <jakub@redhat.com> |
178 | ||
179 | * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. | |
180 | ||
1f45d988 ML |
181 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
182 | ||
183 | * i386.h (i386_optab): Added xstore as an alias for xstorerng. | |
184 | ||
0f10071e ML |
185 | 2004-03-12 Michal Ludvig <mludvig@suse.cz> |
186 | ||
187 | * i386.h (i386_optab): Added xstore/xcrypt insns. | |
188 | ||
3255318a NC |
189 | 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> |
190 | ||
191 | * h8300.h (32bit ldc/stc): Add relaxing support. | |
192 | ||
ca9a79a1 | 193 | 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> |
fdd12ef3 | 194 | |
ca9a79a1 NC |
195 | * h8300.h (BITOP): Pass MEMRELAX flag. |
196 | ||
875a0b14 NC |
197 | 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> |
198 | ||
199 | * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 | |
200 | except for the H8S. | |
252b5132 | 201 | |
c9e214e5 | 202 | For older changes see ChangeLog-9103 |
252b5132 RH |
203 | \f |
204 | Local Variables: | |
c9e214e5 AM |
205 | mode: change-log |
206 | left-margin: 8 | |
207 | fill-column: 74 | |
252b5132 RH |
208 | version-control: never |
209 | End: |