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[deliverable/binutils-gdb.git] / include / opcode / aarch64.h
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a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
82704155 3 Copyright (C) 2009-2019 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
c0e7cef7
NC		 40#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
b6b9ca0c
TC		 42#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
a06ea964 45#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 46#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 47#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 48#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 51#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 52#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 53#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 54#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 55#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 56#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 57#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 58#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 59#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 60#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 61#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
f482d304 62#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
65a55fbb 63#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
d0f7791c 64#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
70d56181 65#define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */
a06ea964 66
13c60ad7
SD		 67/* Flag Manipulation insns. */
68#define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL
69/* FRINT[32,64][Z,X] insns. */
70#define AARCH64_FEATURE_FRINTTS 0x8000000000ULL
68dfbb92
SD		 71/* SB instruction. */
72#define AARCH64_FEATURE_SB 0x10000000000ULL
2ac435d4
SD		 73/* Execution and Data Prediction Restriction instructions. */
74#define AARCH64_FEATURE_PREDRES 0x20000000000ULL
3fd229a4
SD		 75/* DC CVADP. */
76#define AARCH64_FEATURE_CVADP 0x40000000000ULL
af4bcb4c
SD		 77/* Random Number instructions. */
78#define AARCH64_FEATURE_RNG 0x80000000000ULL
ff605452
SD		 79/* BTI instructions. */
80#define AARCH64_FEATURE_BTI 0x100000000000ULL
a97330e7
SD		 81/* SCXTNUM_ELx. */
82#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
83/* ID_PFR2 instructions. */
84#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
104fefee
SD		 85/* SSBS mechanism enabled. */
86#define AARCH64_FEATURE_SSBS 0x800000000000ULL
73b605ec
SD		 87/* Memory Tagging Extension. */
88#define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL
a97330e7 89
13c60ad7 90
a06ea964
NC		 91/* Architectures are the sum of the base and extensions. */
92#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
93 AARCH64_FEATURE_FP \
94 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 95#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
96 AARCH64_FEATURE_CRC \
250aafa4 97 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 98 | AARCH64_FEATURE_LSE \
99 | AARCH64_FEATURE_PAN \
100 | AARCH64_FEATURE_LOR \
101 | AARCH64_FEATURE_RDMA)
1924ff75 102#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 103 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 104 | AARCH64_FEATURE_RAS)
105#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 106 AARCH64_FEATURE_V8_3 \
f482d304
RS		 107 | AARCH64_FEATURE_RCPC \
108 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 109#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 110 AARCH64_FEATURE_V8_4 \
d0f7791c
TC		 111 | AARCH64_FEATURE_DOTPROD \
112 | AARCH64_FEATURE_F16_FML)
70d56181 113#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
13c60ad7
SD		 114 AARCH64_FEATURE_V8_5 \
115 | AARCH64_FEATURE_FLAGMANIP \
68dfbb92 116 | AARCH64_FEATURE_FRINTTS \
2ac435d4 117 | AARCH64_FEATURE_SB \
3fd229a4 118 | AARCH64_FEATURE_PREDRES \
ff605452 119 | AARCH64_FEATURE_CVADP \
a97330e7
SD		 120 | AARCH64_FEATURE_BTI \
121 | AARCH64_FEATURE_SCXTNUM \
104fefee
SD		 122 | AARCH64_FEATURE_ID_PFR2 \
123 | AARCH64_FEATURE_SSBS)
70d56181 124
88f0ea34 125
a06ea964
NC		 126#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
127#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
128
129/* CPU-specific features. */
21b81e67 130typedef unsigned long long aarch64_feature_set;
a06ea964 131
93d8990c
SN		 132#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
133 ((~(CPU) & (FEAT)) == 0)
134
135#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 136 (((CPU) & (FEAT)) != 0)
137
93d8990c
SN		 138#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
139 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
140
a06ea964
NC		 141#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
142 do \
143 { \
144 (TARG) = (F1) | (F2); \
145 } \
146 while (0)
147
148#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
149 do \
150 { \
151 (TARG) = (F1) &~ (F2); \
152 } \
153 while (0)
154
155#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
156
a06ea964
NC		 157enum aarch64_operand_class
158{
159 AARCH64_OPND_CLASS_NIL,
160 AARCH64_OPND_CLASS_INT_REG,
161 AARCH64_OPND_CLASS_MODIFIED_REG,
162 AARCH64_OPND_CLASS_FP_REG,
163 AARCH64_OPND_CLASS_SIMD_REG,
164 AARCH64_OPND_CLASS_SIMD_ELEMENT,
165 AARCH64_OPND_CLASS_SISD_REG,
166 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 167 AARCH64_OPND_CLASS_SVE_REG,
168 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 169 AARCH64_OPND_CLASS_ADDRESS,
170 AARCH64_OPND_CLASS_IMMEDIATE,
171 AARCH64_OPND_CLASS_SYSTEM,
68a64283 172 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 173};
174
175/* Operand code that helps both parsing and coding.
176 Keep AARCH64_OPERANDS synced. */
177
178enum aarch64_opnd
179{
180 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
181
182 AARCH64_OPND_Rd, /* Integer register as destination. */
183 AARCH64_OPND_Rn, /* Integer register as source. */
184 AARCH64_OPND_Rm, /* Integer register as source. */
185 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
186 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
187 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
188 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
189 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
190
191 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
192 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 193 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 194 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 195 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
196 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
197
198 AARCH64_OPND_Fd, /* Floating-point Fd. */
199 AARCH64_OPND_Fn, /* Floating-point Fn. */
200 AARCH64_OPND_Fm, /* Floating-point Fm. */
201 AARCH64_OPND_Fa, /* Floating-point Fa. */
202 AARCH64_OPND_Ft, /* Floating-point Ft. */
203 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
204
205 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
206 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
207 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
208
f42f1a1d 209 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 210 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
211 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
212 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
213 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
214 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
215 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
216 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
217 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
369c9167
TC		 218 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
219 qualifier is S_H. */
a06ea964
NC		 220 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
221 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
222 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
223 structure to all lanes. */
224 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
225
a6a51754
RL		 226 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
227 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 228
229 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 230 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 231 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
232 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
233 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
234 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
235 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
236 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
237 (no encoding). */
238 AARCH64_OPND_IMM0, /* Immediate for #0. */
239 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
240 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
241 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
242 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
243 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
244 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 245 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 246 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
247 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
248 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
193614f2 249 AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
a06ea964 250 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
193614f2 251 AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
a06ea964
NC		 252 AARCH64_OPND_BIT_NUM, /* Immediate. */
253 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
254 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 255 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 256 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
257 each condition flag. */
258
259 AARCH64_OPND_LIMM, /* Logical Immediate. */
260 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
261 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
262 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
263 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 264 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
265 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
266 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 267
268 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 269 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 270
271 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
272 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
273 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
274 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
275 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
276
277 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
278 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
279 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
280 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
281 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
282 negative or unaligned and there is
283 no writeback allowed. This operand code
284 is only used to support the programmer-
285 friendly feature of using LDR/STR as the
286 the mnemonic name for LDUR/STUR instructions
287 wherever there is no ambiguity. */
3f06e550 288 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
fb3265b3
SD		 289 AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
290 16) immediate. */
a06ea964 291 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
fb3265b3
SD		 292 AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
293 16) immediate. */
a06ea964 294 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 295 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 296 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
297
298 AARCH64_OPND_SYSREG, /* System register operand. */
299 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
300 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
301 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
302 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
303 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
2ac435d4 304 AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
a06ea964
NC		 305 AARCH64_OPND_BARRIER, /* Barrier operand. */
306 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
307 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 308 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
ff605452 309 AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
f11ad6bc 310
582e12bf 311 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
98907a70
RS		 312 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
313 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
314 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
315 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
316 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
317 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 318 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
319 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
320 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
321 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 322 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS		 323 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
324 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
325 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
326 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
327 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
328 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
329 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
330 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
331 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
332 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
333 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
334 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
335 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
336 Bit 14 controls S/U choice. */
337 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
338 Bit 22 controls S/U choice. */
339 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
340 Bit 14 controls S/U choice. */
341 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
342 Bit 22 controls S/U choice. */
343 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
344 Bit 14 controls S/U choice. */
345 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
346 Bit 22 controls S/U choice. */
347 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
348 Bit 14 controls S/U choice. */
349 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
350 Bit 22 controls S/U choice. */
351 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
352 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
353 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
354 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
355 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
356 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
357 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 358 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
359 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 360 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
361 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
362 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
363 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 364 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
365 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
e950b345
RS		 366 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
367 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
368 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 369 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 370 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 371 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 372 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
373 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
374 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
375 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
376 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
377 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
378 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
379 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 380 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
381 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 382 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
383 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
384 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
385 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
386 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
387 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
388 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
389 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
390 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
391 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
392 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
393 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 394 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
395 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
396 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
397 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 398 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
399 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
400 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
401 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
402 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 403 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
404 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
405 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 406 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
407 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
408 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
409 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
410 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
f42f1a1d 411 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC		 412};
413
414/* Qualifier constrains an operand. It either specifies a variant of an
415 operand type or limits values available to an operand type.
416
417 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
418
419enum aarch64_opnd_qualifier
420{
421 /* Indicating no further qualification on an operand. */
422 AARCH64_OPND_QLF_NIL,
423
424 /* Qualifying an operand which is a general purpose (integer) register;
425 indicating the operand data size or a specific register. */
426 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
427 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
428 AARCH64_OPND_QLF_WSP, /* WSP. */
429 AARCH64_OPND_QLF_SP, /* SP. */
430
431 /* Qualifying an operand which is a floating-point register, a SIMD
432 vector element or a SIMD vector element list; indicating operand data
433 size or the size of each SIMD vector element in the case of a SIMD
434 vector element list.
435 These qualifiers are also used to qualify an address operand to
436 indicate the size of data element a load/store instruction is
437 accessing.
438 They are also used for the immediate shift operand in e.g. SSHR. Such
439 a use is only for the ease of operand encoding/decoding and qualifier
440 sequence matching; such a use should not be applied widely; use the value
441 constraint qualifiers for immediate operands wherever possible. */
442 AARCH64_OPND_QLF_S_B,
443 AARCH64_OPND_QLF_S_H,
444 AARCH64_OPND_QLF_S_S,
445 AARCH64_OPND_QLF_S_D,
446 AARCH64_OPND_QLF_S_Q,
00c2093f
TC		 447 /* This type qualifier has a special meaning in that it means that 4 x 1 byte
448 are selected by the instruction. Other than that it has no difference
449 with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
450 reasons and is an exception from normal AArch64 disassembly scheme. */
451 AARCH64_OPND_QLF_S_4B,
a06ea964
NC		 452
453 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
454 register list; indicating register shape.
455 They are also used for the immediate shift operand in e.g. SSHR. Such
456 a use is only for the ease of operand encoding/decoding and qualifier
457 sequence matching; such a use should not be applied widely; use the value
458 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 459 AARCH64_OPND_QLF_V_4B,
a06ea964
NC		 460 AARCH64_OPND_QLF_V_8B,
461 AARCH64_OPND_QLF_V_16B,
3067d3b9 462 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 463 AARCH64_OPND_QLF_V_4H,
464 AARCH64_OPND_QLF_V_8H,
465 AARCH64_OPND_QLF_V_2S,
466 AARCH64_OPND_QLF_V_4S,
467 AARCH64_OPND_QLF_V_1D,
468 AARCH64_OPND_QLF_V_2D,
469 AARCH64_OPND_QLF_V_1Q,
470
d50c751e
RS		 471 AARCH64_OPND_QLF_P_Z,
472 AARCH64_OPND_QLF_P_M,
fb3265b3
SD		 473
474 /* Used in scaled signed immediate that are scaled by a Tag granule
475 like in stg, st2g, etc. */
476 AARCH64_OPND_QLF_imm_tag,
d50c751e 477
a06ea964 478 /* Constraint on value. */
a6a51754 479 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 480 AARCH64_OPND_QLF_imm_0_7,
481 AARCH64_OPND_QLF_imm_0_15,
482 AARCH64_OPND_QLF_imm_0_31,
483 AARCH64_OPND_QLF_imm_0_63,
484 AARCH64_OPND_QLF_imm_1_32,
485 AARCH64_OPND_QLF_imm_1_64,
486
487 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
488 or shift-ones. */
489 AARCH64_OPND_QLF_LSL,
490 AARCH64_OPND_QLF_MSL,
491
492 /* Special qualifier helping retrieve qualifier information during the
493 decoding time (currently not in use). */
494 AARCH64_OPND_QLF_RETRIEVE,
495};
496\f
497/* Instruction class. */
498
499enum aarch64_insn_class
500{
501 addsub_carry,
502 addsub_ext,
503 addsub_imm,
504 addsub_shift,
505 asimdall,
506 asimddiff,
507 asimdelem,
508 asimdext,
509 asimdimm,
510 asimdins,
511 asimdmisc,
512 asimdperm,
513 asimdsame,
514 asimdshf,
515 asimdtbl,
516 asisddiff,
517 asisdelem,
518 asisdlse,
519 asisdlsep,
520 asisdlso,
521 asisdlsop,
522 asisdmisc,
523 asisdone,
524 asisdpair,
525 asisdsame,
526 asisdshf,
527 bitfield,
528 branch_imm,
529 branch_reg,
530 compbranch,
531 condbranch,
532 condcmp_imm,
533 condcmp_reg,
534 condsel,
535 cryptoaes,
536 cryptosha2,
537 cryptosha3,
538 dp_1src,
539 dp_2src,
540 dp_3src,
541 exception,
542 extract,
543 float2fix,
544 float2int,
545 floatccmp,
546 floatcmp,
547 floatdp1,
548 floatdp2,
549 floatdp3,
550 floatimm,
551 floatsel,
552 ldst_immpost,
553 ldst_immpre,
554 ldst_imm9, /* immpost or immpre */
3f06e550 555 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 556 ldst_pos,
557 ldst_regoff,
558 ldst_unpriv,
559 ldst_unscaled,
560 ldstexcl,
561 ldstnapair_offs,
562 ldstpair_off,
563 ldstpair_indexed,
564 loadlit,
565 log_imm,
566 log_shift,
ee804238 567 lse_atomic,
a06ea964
NC		 568 movewide,
569 pcreladdr,
570 ic_system,
116b6019
RS		 571 sve_cpy,
572 sve_index,
573 sve_limm,
574 sve_misc,
575 sve_movprfx,
576 sve_pred_zm,
577 sve_shift_pred,
578 sve_shift_unpred,
579 sve_size_bhs,
580 sve_size_bhsd,
581 sve_size_hsd,
582 sve_size_sd,
a06ea964 583 testbranch,
f42f1a1d
TC		 584 cryptosm3,
585 cryptosm4,
65a55fbb 586 dotproduct,
a06ea964
NC		 587};
588
589/* Opcode enumerators. */
590
591enum aarch64_op
592{
593 OP_NIL,
594 OP_STRB_POS,
595 OP_LDRB_POS,
596 OP_LDRSB_POS,
597 OP_STRH_POS,
598 OP_LDRH_POS,
599 OP_LDRSH_POS,
600 OP_STR_POS,
601 OP_LDR_POS,
602 OP_STRF_POS,
603 OP_LDRF_POS,
604 OP_LDRSW_POS,
605 OP_PRFM_POS,
606
607 OP_STURB,
608 OP_LDURB,
609 OP_LDURSB,
610 OP_STURH,
611 OP_LDURH,
612 OP_LDURSH,
613 OP_STUR,
614 OP_LDUR,
615 OP_STURV,
616 OP_LDURV,
617 OP_LDURSW,
618 OP_PRFUM,
619
620 OP_LDR_LIT,
621 OP_LDRV_LIT,
622 OP_LDRSW_LIT,
623 OP_PRFM_LIT,
624
625 OP_ADD,
626 OP_B,
627 OP_BL,
628
629 OP_MOVN,
630 OP_MOVZ,
631 OP_MOVK,
632
633 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
634 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
635 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
636
637 OP_MOV_V, /* MOV alias for moving vector register. */
638
639 OP_ASR_IMM,
640 OP_LSR_IMM,
641 OP_LSL_IMM,
642
643 OP_BIC,
644
645 OP_UBFX,
646 OP_BFXIL,
647 OP_SBFX,
648 OP_SBFIZ,
649 OP_BFI,
d685192a 650 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 651 OP_UBFIZ,
652 OP_UXTB,
653 OP_UXTH,
654 OP_UXTW,
655
a06ea964
NC		 656 OP_CINC,
657 OP_CINV,
658 OP_CNEG,
659 OP_CSET,
660 OP_CSETM,
661
662 OP_FCVT,
663 OP_FCVTN,
664 OP_FCVTN2,
665 OP_FCVTL,
666 OP_FCVTL2,
667 OP_FCVTXN_S, /* Scalar version. */
668
669 OP_ROR_IMM,
670
e30181a5
YZ		 671 OP_SXTL,
672 OP_SXTL2,
673 OP_UXTL,
674 OP_UXTL2,
675
c0890d26
RS		 676 OP_MOV_P_P,
677 OP_MOV_Z_P_Z,
678 OP_MOV_Z_V,
679 OP_MOV_Z_Z,
680 OP_MOV_Z_Zi,
681 OP_MOVM_P_P_P,
682 OP_MOVS_P_P,
683 OP_MOVZS_P_P_P,
684 OP_MOVZ_P_P_P,
685 OP_NOTS_P_P_P_Z,
686 OP_NOT_P_P_P_Z,
687
c2c4ff8d
SN		 688 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
689
a06ea964
NC		 690 OP_TOTAL_NUM, /* Pseudo. */
691};
692
1d482394
TC		 693/* Error types. */
694enum err_type
695{
696 ERR_OK,
697 ERR_UND,
698 ERR_UNP,
699 ERR_NYI,
a68f4cd2 700 ERR_VFI,
1d482394
TC		 701 ERR_NR_ENTRIES
702};
703
a06ea964
NC		 704/* Maximum number of operands an instruction can have. */
705#define AARCH64_MAX_OPND_NUM 6
706/* Maximum number of qualifier sequences an instruction can have. */
707#define AARCH64_MAX_QLF_SEQ_NUM 10
708/* Operand qualifier typedef; optimized for the size. */
709typedef unsigned char aarch64_opnd_qualifier_t;
710/* Operand qualifier sequence typedef. */
711typedef aarch64_opnd_qualifier_t \
712 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
713
714/* FIXME: improve the efficiency. */
715static inline bfd_boolean
716empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
717{
718 int i;
719 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
720 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
721 return FALSE;
722 return TRUE;
723}
724
7e84b55d
TC		 725/* Forward declare error reporting type. */
726typedef struct aarch64_operand_error aarch64_operand_error;
727/* Forward declare instruction sequence type. */
728typedef struct aarch64_instr_sequence aarch64_instr_sequence;
729/* Forward declare instruction definition. */
730typedef struct aarch64_inst aarch64_inst;
731
a06ea964
NC		 732/* This structure holds information for a particular opcode. */
733
734struct aarch64_opcode
735{
736 /* The name of the mnemonic. */
737 const char *name;
738
739 /* The opcode itself. Those bits which will be filled in with
740 operands are zeroes. */
741 aarch64_insn opcode;
742
743 /* The opcode mask. This is used by the disassembler. This is a
744 mask containing ones indicating those bits which must match the
745 opcode field, and zeroes indicating those bits which need not
746 match (and are presumably filled in by operands). */
747 aarch64_insn mask;
748
749 /* Instruction class. */
750 enum aarch64_insn_class iclass;
751
752 /* Enumerator identifier. */
753 enum aarch64_op op;
754
755 /* Which architecture variant provides this instruction. */
756 const aarch64_feature_set *avariant;
757
758 /* An array of operand codes. Each code is an index into the
759 operand table. They appear in the order which the operands must
760 appear in assembly code, and are terminated by a zero. */
761 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
762
763 /* A list of operand qualifier code sequence. Each operand qualifier
764 code qualifies the corresponding operand code. Each operand
765 qualifier sequence specifies a valid opcode variant and related
766 constraint on operands. */
767 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
768
769 /* Flags providing information about this instruction */
eae424ae
TC		 770 uint64_t flags;
771
772 /* Extra constraints on the instruction that the verifier checks. */
773 uint32_t constraints;
4bd13cde 774
0c608d6b
RS		 775 /* If nonzero, this operand and operand 0 are both registers and
776 are required to have the same register number. */
777 unsigned char tied_operand;
778
4bd13cde 779 /* If non-NULL, a function to verify that a given instruction is valid. */
755b748f
TC		 780 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
781 bfd_vma, bfd_boolean, aarch64_operand_error *,
782 struct aarch64_instr_sequence *);
a06ea964
NC		 783};
784
785typedef struct aarch64_opcode aarch64_opcode;
786
787/* Table describing all the AArch64 opcodes. */
788extern aarch64_opcode aarch64_opcode_table[];
789
790/* Opcode flags. */
791#define F_ALIAS (1 << 0)
792#define F_HAS_ALIAS (1 << 1)
793/* Disassembly preference priority 1-3 (the larger the higher). If nothing
794 is specified, it is the priority 0 by default, i.e. the lowest priority. */
795#define F_P1 (1 << 2)
796#define F_P2 (2 << 2)
797#define F_P3 (3 << 2)
798/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
799#define F_COND (1 << 4)
800/* Instruction has the field of 'sf'. */
801#define F_SF (1 << 5)
802/* Instruction has the field of 'size:Q'. */
803#define F_SIZEQ (1 << 6)
804/* Floating-point instruction has the field of 'type'. */
805#define F_FPTYPE (1 << 7)
806/* AdvSIMD scalar instruction has the field of 'size'. */
807#define F_SSIZE (1 << 8)
808/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
809#define F_T (1 << 9)
810/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
811#define F_GPRSIZE_IN_Q (1 << 10)
812/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
813#define F_LDS_SIZE (1 << 11)
814/* Optional operand; assume maximum of 1 operand can be optional. */
815#define F_OPD0_OPT (1 << 12)
816#define F_OPD1_OPT (2 << 12)
817#define F_OPD2_OPT (3 << 12)
818#define F_OPD3_OPT (4 << 12)
819#define F_OPD4_OPT (5 << 12)
820/* Default value for the optional operand when omitted from the assembly. */
821#define F_DEFAULT(X) (((X) & 0x1f) << 15)
822/* Instruction that is an alias of another instruction needs to be
823 encoded/decoded by converting it to/from the real form, followed by
824 the encoding/decoding according to the rules of the real opcode.
825 This compares to the direct coding using the alias's information.
826 N.B. this flag requires F_ALIAS to be used together. */
827#define F_CONV (1 << 20)
828/* Use together with F_ALIAS to indicate an alias opcode is a programmer
829 friendly pseudo instruction available only in the assembly code (thus will
830 not show up in the disassembly). */
831#define F_PSEUDO (1 << 21)
832/* Instruction has miscellaneous encoding/decoding rules. */
833#define F_MISC (1 << 22)
834/* Instruction has the field of 'N'; used in conjunction with F_SF. */
835#define F_N (1 << 23)
836/* Opcode dependent field. */
837#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 838/* Instruction has the field of 'sz'. */
839#define F_LSE_SZ (1 << 27)
4989adac
RS		 840/* Require an exact qualifier match, even for NIL qualifiers. */
841#define F_STRICT (1ULL << 28)
f9830ec1
TC		 842/* This system instruction is used to read system registers. */
843#define F_SYS_READ (1ULL << 29)
844/* This system instruction is used to write system registers. */
845#define F_SYS_WRITE (1ULL << 30)
eae424ae
TC		 846/* This instruction has an extra constraint on it that imposes a requirement on
847 subsequent instructions. */
848#define F_SCAN (1ULL << 31)
849/* Next bit is 32. */
850
851/* Instruction constraints. */
852/* This instruction has a predication constraint on the instruction at PC+4. */
853#define C_SCAN_MOVPRFX (1U << 0)
854/* This instruction's operation width is determined by the operand with the
855 largest element size. */
856#define C_MAX_ELEM (1U << 1)
857/* Next bit is 2. */
a06ea964
NC		 858
859static inline bfd_boolean
860alias_opcode_p (const aarch64_opcode *opcode)
861{
862 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
863}
864
865static inline bfd_boolean
866opcode_has_alias (const aarch64_opcode *opcode)
867{
868 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
869}
870
871/* Priority for disassembling preference. */
872static inline int
873opcode_priority (const aarch64_opcode *opcode)
874{
875 return (opcode->flags >> 2) & 0x3;
876}
877
878static inline bfd_boolean
879pseudo_opcode_p (const aarch64_opcode *opcode)
880{
881 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
882}
883
884static inline bfd_boolean
885optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
886{
887 return (((opcode->flags >> 12) & 0x7) == idx + 1)
888 ? TRUE : FALSE;
889}
890
891static inline aarch64_insn
892get_optional_operand_default_value (const aarch64_opcode *opcode)
893{
894 return (opcode->flags >> 15) & 0x1f;
895}
896
897static inline unsigned int
898get_opcode_dependent_value (const aarch64_opcode *opcode)
899{
900 return (opcode->flags >> 24) & 0x7;
901}
902
903static inline bfd_boolean
904opcode_has_special_coder (const aarch64_opcode *opcode)
905{
ee804238 906 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 907 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
908 : FALSE;
909}
910\f
911struct aarch64_name_value_pair
912{
913 const char * name;
914 aarch64_insn value;
915};
916
917extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 918extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
919extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 920extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 921
49eec193
YZ		 922typedef struct
923{
924 const char * name;
925 aarch64_insn value;
926 uint32_t flags;
927} aarch64_sys_reg;
928
929extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 930extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 931extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 932extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
933 const aarch64_sys_reg *);
934extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
935 const aarch64_sys_reg *);
49eec193 936
a06ea964
NC		 937typedef struct
938{
875880c6 939 const char *name;
a06ea964 940 uint32_t value;
ea2deeec 941 uint32_t flags ;
a06ea964
NC		 942} aarch64_sys_ins_reg;
943
ea2deeec 944extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 945extern bfd_boolean
946aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
947 const aarch64_sys_ins_reg *);
ea2deeec 948
a06ea964
NC		 949extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
950extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
951extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
952extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
2ac435d4 953extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
a06ea964
NC		 954
955/* Shift/extending operator kinds.
956 N.B. order is important; keep aarch64_operand_modifiers synced. */
957enum aarch64_modifier_kind
958{
959 AARCH64_MOD_NONE,
960 AARCH64_MOD_MSL,
961 AARCH64_MOD_ROR,
962 AARCH64_MOD_ASR,
963 AARCH64_MOD_LSR,
964 AARCH64_MOD_LSL,
965 AARCH64_MOD_UXTB,
966 AARCH64_MOD_UXTH,
967 AARCH64_MOD_UXTW,
968 AARCH64_MOD_UXTX,
969 AARCH64_MOD_SXTB,
970 AARCH64_MOD_SXTH,
971 AARCH64_MOD_SXTW,
972 AARCH64_MOD_SXTX,
2442d846 973 AARCH64_MOD_MUL,
98907a70 974 AARCH64_MOD_MUL_VL,
a06ea964
NC		 975};
976
977bfd_boolean
978aarch64_extend_operator_p (enum aarch64_modifier_kind);
979
980enum aarch64_modifier_kind
981aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
982/* Condition. */
983
984typedef struct
985{
986 /* A list of names with the first one as the disassembly preference;
987 terminated by NULL if fewer than 3. */
bb7eff52 988 const char *names[4];
a06ea964
NC		 989 aarch64_insn value;
990} aarch64_cond;
991
992extern const aarch64_cond aarch64_conds[16];
993
994const aarch64_cond* get_cond_from_value (aarch64_insn value);
995const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
996\f
997/* Structure representing an operand. */
998
999struct aarch64_opnd_info
1000{
1001 enum aarch64_opnd type;
1002 aarch64_opnd_qualifier_t qualifier;
1003 int idx;
1004
1005 union
1006 {
1007 struct
1008 {
1009 unsigned regno;
1010 } reg;
1011 struct
1012 {
dab26bf4
RS		 1013 unsigned int regno;
1014 int64_t index;
a06ea964
NC		 1015 } reglane;
1016 /* e.g. LVn. */
1017 struct
1018 {
1019 unsigned first_regno : 5;
1020 unsigned num_regs : 3;
1021 /* 1 if it is a list of reg element. */
1022 unsigned has_index : 1;
1023 /* Lane index; valid only when has_index is 1. */
dab26bf4 1024 int64_t index;
a06ea964
NC		 1025 } reglist;
1026 /* e.g. immediate or pc relative address offset. */
1027 struct
1028 {
1029 int64_t value;
1030 unsigned is_fp : 1;
1031 } imm;
1032 /* e.g. address in STR (register offset). */
1033 struct
1034 {
1035 unsigned base_regno;
1036 struct
1037 {
1038 union
1039 {
1040 int imm;
1041 unsigned regno;
1042 };
1043 unsigned is_reg;
1044 } offset;
1045 unsigned pcrel : 1; /* PC-relative. */
1046 unsigned writeback : 1;
1047 unsigned preind : 1; /* Pre-indexed. */
1048 unsigned postind : 1; /* Post-indexed. */
1049 } addr;
561a72d4
TC		 1050
1051 struct
1052 {
1053 /* The encoding of the system register. */
1054 aarch64_insn value;
1055
1056 /* The system register flags. */
1057 uint32_t flags;
1058 } sysreg;
1059
a06ea964 1060 const aarch64_cond *cond;
a06ea964
NC		 1061 /* The encoding of the PSTATE field. */
1062 aarch64_insn pstatefield;
1063 const aarch64_sys_ins_reg *sysins_op;
1064 const struct aarch64_name_value_pair *barrier;
9ed608f9 1065 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 1066 const struct aarch64_name_value_pair *prfop;
1067 };
1068
1069 /* Operand shifter; in use when the operand is a register offset address,
1070 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1071 struct
1072 {
1073 enum aarch64_modifier_kind kind;
a06ea964
NC		 1074 unsigned operator_present: 1; /* Only valid during encoding. */
1075 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1076 unsigned amount_present: 1;
2442d846 1077 int64_t amount;
a06ea964
NC		 1078 } shifter;
1079
1080 unsigned skip:1; /* Operand is not completed if there is a fixup needed
1081 to be done on it. In some (but not all) of these
1082 cases, we need to tell libopcodes to skip the
1083 constraint checking and the encoding for this
1084 operand, so that the libopcodes can pick up the
1085 right opcode before the operand is fixed-up. This
1086 flag should only be used during the
1087 assembling/encoding. */
1088 unsigned present:1; /* Whether this operand is present in the assembly
1089 line; not used during the disassembly. */
1090};
1091
1092typedef struct aarch64_opnd_info aarch64_opnd_info;
1093
1094/* Structure representing an instruction.
1095
1096 It is used during both the assembling and disassembling. The assembler
1097 fills an aarch64_inst after a successful parsing and then passes it to the
1098 encoding routine to do the encoding. During the disassembling, the
1099 disassembler calls the decoding routine to decode a binary instruction; on a
1100 successful return, such a structure will be filled with information of the
1101 instruction; then the disassembler uses the information to print out the
1102 instruction. */
1103
1104struct aarch64_inst
1105{
1106 /* The value of the binary instruction. */
1107 aarch64_insn value;
1108
1109 /* Corresponding opcode entry. */
1110 const aarch64_opcode *opcode;
1111
1112 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1113 const aarch64_cond *cond;
1114
1115 /* Operands information. */
1116 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1117};
1118
ff605452
SD		 1119/* Defining the HINT #imm values for the aarch64_hint_options. */
1120#define HINT_OPD_CSYNC 0x11
1121#define HINT_OPD_C 0x22
1122#define HINT_OPD_J 0x24
1123#define HINT_OPD_JC 0x26
1124#define HINT_OPD_NULL 0x00
1125
a06ea964
NC		 1126\f
1127/* Diagnosis related declaration and interface. */
1128
1129/* Operand error kind enumerators.
1130
1131 AARCH64_OPDE_RECOVERABLE
1132 Less severe error found during the parsing, very possibly because that
1133 GAS has picked up a wrong instruction template for the parsing.
1134
1135 AARCH64_OPDE_SYNTAX_ERROR
1136 General syntax error; it can be either a user error, or simply because
1137 that GAS is trying a wrong instruction template.
1138
1139 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1140 Definitely a user syntax error.
1141
1142 AARCH64_OPDE_INVALID_VARIANT
1143 No syntax error, but the operands are not a valid combination, e.g.
1144 FMOV D0,S0
1145
0c608d6b
RS		 1146 AARCH64_OPDE_UNTIED_OPERAND
1147 The asm failed to use the same register for a destination operand
1148 and a tied source operand.
1149
a06ea964
NC		 1150 AARCH64_OPDE_OUT_OF_RANGE
1151 Error about some immediate value out of a valid range.
1152
1153 AARCH64_OPDE_UNALIGNED
1154 Error about some immediate value not properly aligned (i.e. not being a
1155 multiple times of a certain value).
1156
1157 AARCH64_OPDE_REG_LIST
1158 Error about the register list operand having unexpected number of
1159 registers.
1160
1161 AARCH64_OPDE_OTHER_ERROR
1162 Error of the highest severity and used for any severe issue that does not
1163 fall into any of the above categories.
1164
1165 The enumerators are only interesting to GAS. They are declared here (in
1166 libopcodes) because that some errors are detected (and then notified to GAS)
1167 by libopcodes (rather than by GAS solely).
1168
1169 The first three errors are only deteced by GAS while the
1170 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1171 only libopcodes has the information about the valid variants of each
1172 instruction.
1173
1174 The enumerators have an increasing severity. This is helpful when there are
1175 multiple instruction templates available for a given mnemonic name (e.g.
1176 FMOV); this mechanism will help choose the most suitable template from which
1177 the generated diagnostics can most closely describe the issues, if any. */
1178
1179enum aarch64_operand_error_kind
1180{
1181 AARCH64_OPDE_NIL,
1182 AARCH64_OPDE_RECOVERABLE,
1183 AARCH64_OPDE_SYNTAX_ERROR,
1184 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1185 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1186 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1187 AARCH64_OPDE_OUT_OF_RANGE,
1188 AARCH64_OPDE_UNALIGNED,
1189 AARCH64_OPDE_REG_LIST,
1190 AARCH64_OPDE_OTHER_ERROR
1191};
1192
1193/* N.B. GAS assumes that this structure work well with shallow copy. */
1194struct aarch64_operand_error
1195{
1196 enum aarch64_operand_error_kind kind;
1197 int index;
1198 const char *error;
1199 int data[3]; /* Some data for extra information. */
7d02540a 1200 bfd_boolean non_fatal;
a06ea964
NC		 1201};
1202
7e84b55d
TC		 1203/* AArch64 sequence structure used to track instructions with F_SCAN
1204 dependencies for both assembler and disassembler. */
1205struct aarch64_instr_sequence
1206{
1207 /* The instruction that caused this sequence to be opened. */
1208 aarch64_inst *instr;
1209 /* The number of instructions the above instruction allows to be kept in the
1210 sequence before an automatic close is done. */
1211 int num_insns;
1212 /* The instructions currently added to the sequence. */
1213 aarch64_inst **current_insns;
1214 /* The number of instructions already in the sequence. */
1215 int next_insn;
1216};
a06ea964
NC		 1217
1218/* Encoding entrypoint. */
1219
1220extern int
1221aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1222 aarch64_insn *, aarch64_opnd_qualifier_t *,
7e84b55d 1223 aarch64_operand_error *, aarch64_instr_sequence *);
a06ea964
NC		 1224
1225extern const aarch64_opcode *
1226aarch64_replace_opcode (struct aarch64_inst *,
1227 const aarch64_opcode *);
1228
1229/* Given the opcode enumerator OP, return the pointer to the corresponding
1230 opcode entry. */
1231
1232extern const aarch64_opcode *
1233aarch64_get_opcode (enum aarch64_op);
1234
1235/* Generate the string representation of an operand. */
1236extern void
1237aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a
TC		 1238 const aarch64_opnd_info *, int, int *, bfd_vma *,
1239 char **);
a06ea964
NC		 1240
1241/* Miscellaneous interface. */
1242
1243extern int
1244aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1245
1246extern aarch64_opnd_qualifier_t
1247aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1248 const aarch64_opnd_qualifier_t, int);
1249
a68f4cd2
TC		 1250extern bfd_boolean
1251aarch64_is_destructive_by_operands (const aarch64_opcode *);
1252
a06ea964
NC		 1253extern int
1254aarch64_num_of_operands (const aarch64_opcode *);
1255
1256extern int
1257aarch64_stack_pointer_p (const aarch64_opnd_info *);
1258
e141d84e
YQ		 1259extern int
1260aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1261
1d482394 1262extern enum err_type
561a72d4 1263aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
a68f4cd2
TC		 1264 aarch64_operand_error *);
1265
1266extern void
1267init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
36f4aab1 1268
a06ea964
NC		 1269/* Given an operand qualifier, return the expected data element size
1270 of a qualified operand. */
1271extern unsigned char
1272aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1273
1274extern enum aarch64_operand_class
1275aarch64_get_operand_class (enum aarch64_opnd);
1276
1277extern const char *
1278aarch64_get_operand_name (enum aarch64_opnd);
1279
1280extern const char *
1281aarch64_get_operand_desc (enum aarch64_opnd);
1282
e950b345
RS		 1283extern bfd_boolean
1284aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1285
a06ea964
NC		 1286#ifdef DEBUG_AARCH64
1287extern int debug_dump;
1288
1289extern void
1290aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1291
1292#define DEBUG_TRACE(M, ...) \
1293 { \
1294 if (debug_dump) \
1295 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1296 }
1297
1298#define DEBUG_TRACE_IF(C, M, ...) \
1299 { \
1300 if (debug_dump && (C)) \
1301 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1302 }
1303#else /* !DEBUG_AARCH64 */
1304#define DEBUG_TRACE(M, ...) ;
1305#define DEBUG_TRACE_IF(C, M, ...) ;
1306#endif /* DEBUG_AARCH64 */
1307
245d2e3f
RS		 1308extern const char *const aarch64_sve_pattern_array[32];
1309extern const char *const aarch64_sve_prfop_array[16];
1310
d3e12b29
YQ		 1311#ifdef __cplusplus
1312}
1313#endif
1314
a06ea964 1315#endif /* OPCODE_AARCH64_H */
GDB Binutils - Deliverables
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