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[PATCH, BINUTILS, AARCH64, 2/9] Add Data procoessing instructions for ARMv8.5-A
[deliverable/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
219d1afa 3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
c0e7cef7
NC		 40#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
b6b9ca0c
TC		 42#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
a06ea964 45#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 46#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 47#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 48#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 51#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 52#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 53#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 54#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 55#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 56#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 57#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 58#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 59#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 60#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 61#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
f482d304 62#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
65a55fbb 63#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
d0f7791c 64#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
70d56181 65#define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */
a06ea964 66
13c60ad7
SD		 67/* Flag Manipulation insns. */
68#define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL
69/* FRINT[32,64][Z,X] insns. */
70#define AARCH64_FEATURE_FRINTTS 0x8000000000ULL
71
a06ea964
NC		 72/* Architectures are the sum of the base and extensions. */
73#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
74 AARCH64_FEATURE_FP \
75 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 76#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
77 AARCH64_FEATURE_CRC \
250aafa4 78 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 79 | AARCH64_FEATURE_LSE \
80 | AARCH64_FEATURE_PAN \
81 | AARCH64_FEATURE_LOR \
82 | AARCH64_FEATURE_RDMA)
1924ff75 83#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 84 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 85 | AARCH64_FEATURE_RAS)
86#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 87 AARCH64_FEATURE_V8_3 \
f482d304
RS		 88 | AARCH64_FEATURE_RCPC \
89 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 90#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 91 AARCH64_FEATURE_V8_4 \
d0f7791c
TC		 92 | AARCH64_FEATURE_DOTPROD \
93 | AARCH64_FEATURE_F16_FML)
70d56181 94#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
13c60ad7
SD		 95 AARCH64_FEATURE_V8_5 \
96 | AARCH64_FEATURE_FLAGMANIP \
97 | AARCH64_FEATURE_FRINTTS)
70d56181 98
88f0ea34 99
a06ea964
NC		 100#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
101#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
102
103/* CPU-specific features. */
21b81e67 104typedef unsigned long long aarch64_feature_set;
a06ea964 105
93d8990c
SN		 106#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
107 ((~(CPU) & (FEAT)) == 0)
108
109#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 110 (((CPU) & (FEAT)) != 0)
111
93d8990c
SN		 112#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
113 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
114
a06ea964
NC		 115#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
116 do \
117 { \
118 (TARG) = (F1) | (F2); \
119 } \
120 while (0)
121
122#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
123 do \
124 { \
125 (TARG) = (F1) &~ (F2); \
126 } \
127 while (0)
128
129#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
130
a06ea964
NC		 131enum aarch64_operand_class
132{
133 AARCH64_OPND_CLASS_NIL,
134 AARCH64_OPND_CLASS_INT_REG,
135 AARCH64_OPND_CLASS_MODIFIED_REG,
136 AARCH64_OPND_CLASS_FP_REG,
137 AARCH64_OPND_CLASS_SIMD_REG,
138 AARCH64_OPND_CLASS_SIMD_ELEMENT,
139 AARCH64_OPND_CLASS_SISD_REG,
140 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 141 AARCH64_OPND_CLASS_SVE_REG,
142 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 143 AARCH64_OPND_CLASS_ADDRESS,
144 AARCH64_OPND_CLASS_IMMEDIATE,
145 AARCH64_OPND_CLASS_SYSTEM,
68a64283 146 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 147};
148
149/* Operand code that helps both parsing and coding.
150 Keep AARCH64_OPERANDS synced. */
151
152enum aarch64_opnd
153{
154 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
155
156 AARCH64_OPND_Rd, /* Integer register as destination. */
157 AARCH64_OPND_Rn, /* Integer register as source. */
158 AARCH64_OPND_Rm, /* Integer register as source. */
159 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
160 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
161 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
162 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
163 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
164
165 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
166 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 167 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 168 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 169 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
170 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
171
172 AARCH64_OPND_Fd, /* Floating-point Fd. */
173 AARCH64_OPND_Fn, /* Floating-point Fn. */
174 AARCH64_OPND_Fm, /* Floating-point Fm. */
175 AARCH64_OPND_Fa, /* Floating-point Fa. */
176 AARCH64_OPND_Ft, /* Floating-point Ft. */
177 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
178
179 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
180 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
181 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
182
f42f1a1d 183 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 184 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
185 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
186 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
187 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
188 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
189 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
190 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
191 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
369c9167
TC		 192 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
193 qualifier is S_H. */
a06ea964
NC		 194 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
195 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
196 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
197 structure to all lanes. */
198 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
199
a6a51754
RL		 200 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
201 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 202
203 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 204 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 205 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
206 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
207 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
208 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
209 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
210 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
211 (no encoding). */
212 AARCH64_OPND_IMM0, /* Immediate for #0. */
213 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
214 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
215 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
216 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
217 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
218 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 219 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 220 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
221 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
222 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
223 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
224 AARCH64_OPND_BIT_NUM, /* Immediate. */
225 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
226 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 227 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 228 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
229 each condition flag. */
230
231 AARCH64_OPND_LIMM, /* Logical Immediate. */
232 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
233 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
234 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
235 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 236 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
237 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
238 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 239
240 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 241 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 242
243 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
244 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
245 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
246 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
247 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
248
249 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
250 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
251 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
252 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
253 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
254 negative or unaligned and there is
255 no writeback allowed. This operand code
256 is only used to support the programmer-
257 friendly feature of using LDR/STR as the
258 the mnemonic name for LDUR/STUR instructions
259 wherever there is no ambiguity. */
3f06e550 260 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
a06ea964
NC		 261 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
262 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 263 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 264 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
265
266 AARCH64_OPND_SYSREG, /* System register operand. */
267 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
268 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
269 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
270 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
271 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
272 AARCH64_OPND_BARRIER, /* Barrier operand. */
273 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
274 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 275 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
f11ad6bc 276
582e12bf 277 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
98907a70
RS		 278 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
279 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
280 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
281 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
282 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
283 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 284 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
285 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
286 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
287 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 288 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS		 289 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
290 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
291 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
292 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
293 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
294 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
295 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
296 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
297 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
298 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
299 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
300 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
301 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
302 Bit 14 controls S/U choice. */
303 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
304 Bit 22 controls S/U choice. */
305 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
306 Bit 14 controls S/U choice. */
307 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
308 Bit 22 controls S/U choice. */
309 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
310 Bit 14 controls S/U choice. */
311 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
312 Bit 22 controls S/U choice. */
313 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
314 Bit 14 controls S/U choice. */
315 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
316 Bit 22 controls S/U choice. */
317 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
318 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
319 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
320 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
321 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
322 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
323 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 324 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
325 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 326 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
327 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
328 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
329 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 330 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
331 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
e950b345
RS		 332 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
333 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
334 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 335 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 336 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 337 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 338 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
339 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
340 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
341 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
342 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
343 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
344 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
345 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 346 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
347 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 348 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
349 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
350 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
351 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
352 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
353 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
354 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
355 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
356 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
357 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
358 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
359 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 360 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
361 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
362 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
363 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 364 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
365 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
366 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
367 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
368 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 369 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
370 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
371 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 372 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
373 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
374 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
375 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
376 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
f42f1a1d 377 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC		 378};
379
380/* Qualifier constrains an operand. It either specifies a variant of an
381 operand type or limits values available to an operand type.
382
383 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
384
385enum aarch64_opnd_qualifier
386{
387 /* Indicating no further qualification on an operand. */
388 AARCH64_OPND_QLF_NIL,
389
390 /* Qualifying an operand which is a general purpose (integer) register;
391 indicating the operand data size or a specific register. */
392 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
393 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
394 AARCH64_OPND_QLF_WSP, /* WSP. */
395 AARCH64_OPND_QLF_SP, /* SP. */
396
397 /* Qualifying an operand which is a floating-point register, a SIMD
398 vector element or a SIMD vector element list; indicating operand data
399 size or the size of each SIMD vector element in the case of a SIMD
400 vector element list.
401 These qualifiers are also used to qualify an address operand to
402 indicate the size of data element a load/store instruction is
403 accessing.
404 They are also used for the immediate shift operand in e.g. SSHR. Such
405 a use is only for the ease of operand encoding/decoding and qualifier
406 sequence matching; such a use should not be applied widely; use the value
407 constraint qualifiers for immediate operands wherever possible. */
408 AARCH64_OPND_QLF_S_B,
409 AARCH64_OPND_QLF_S_H,
410 AARCH64_OPND_QLF_S_S,
411 AARCH64_OPND_QLF_S_D,
412 AARCH64_OPND_QLF_S_Q,
00c2093f
TC		 413 /* This type qualifier has a special meaning in that it means that 4 x 1 byte
414 are selected by the instruction. Other than that it has no difference
415 with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
416 reasons and is an exception from normal AArch64 disassembly scheme. */
417 AARCH64_OPND_QLF_S_4B,
a06ea964
NC		 418
419 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
420 register list; indicating register shape.
421 They are also used for the immediate shift operand in e.g. SSHR. Such
422 a use is only for the ease of operand encoding/decoding and qualifier
423 sequence matching; such a use should not be applied widely; use the value
424 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 425 AARCH64_OPND_QLF_V_4B,
a06ea964
NC		 426 AARCH64_OPND_QLF_V_8B,
427 AARCH64_OPND_QLF_V_16B,
3067d3b9 428 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 429 AARCH64_OPND_QLF_V_4H,
430 AARCH64_OPND_QLF_V_8H,
431 AARCH64_OPND_QLF_V_2S,
432 AARCH64_OPND_QLF_V_4S,
433 AARCH64_OPND_QLF_V_1D,
434 AARCH64_OPND_QLF_V_2D,
435 AARCH64_OPND_QLF_V_1Q,
436
d50c751e
RS		 437 AARCH64_OPND_QLF_P_Z,
438 AARCH64_OPND_QLF_P_M,
439
a06ea964 440 /* Constraint on value. */
a6a51754 441 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 442 AARCH64_OPND_QLF_imm_0_7,
443 AARCH64_OPND_QLF_imm_0_15,
444 AARCH64_OPND_QLF_imm_0_31,
445 AARCH64_OPND_QLF_imm_0_63,
446 AARCH64_OPND_QLF_imm_1_32,
447 AARCH64_OPND_QLF_imm_1_64,
448
449 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
450 or shift-ones. */
451 AARCH64_OPND_QLF_LSL,
452 AARCH64_OPND_QLF_MSL,
453
454 /* Special qualifier helping retrieve qualifier information during the
455 decoding time (currently not in use). */
456 AARCH64_OPND_QLF_RETRIEVE,
457};
458\f
459/* Instruction class. */
460
461enum aarch64_insn_class
462{
463 addsub_carry,
464 addsub_ext,
465 addsub_imm,
466 addsub_shift,
467 asimdall,
468 asimddiff,
469 asimdelem,
470 asimdext,
471 asimdimm,
472 asimdins,
473 asimdmisc,
474 asimdperm,
475 asimdsame,
476 asimdshf,
477 asimdtbl,
478 asisddiff,
479 asisdelem,
480 asisdlse,
481 asisdlsep,
482 asisdlso,
483 asisdlsop,
484 asisdmisc,
485 asisdone,
486 asisdpair,
487 asisdsame,
488 asisdshf,
489 bitfield,
490 branch_imm,
491 branch_reg,
492 compbranch,
493 condbranch,
494 condcmp_imm,
495 condcmp_reg,
496 condsel,
497 cryptoaes,
498 cryptosha2,
499 cryptosha3,
500 dp_1src,
501 dp_2src,
502 dp_3src,
503 exception,
504 extract,
505 float2fix,
506 float2int,
507 floatccmp,
508 floatcmp,
509 floatdp1,
510 floatdp2,
511 floatdp3,
512 floatimm,
513 floatsel,
514 ldst_immpost,
515 ldst_immpre,
516 ldst_imm9, /* immpost or immpre */
3f06e550 517 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 518 ldst_pos,
519 ldst_regoff,
520 ldst_unpriv,
521 ldst_unscaled,
522 ldstexcl,
523 ldstnapair_offs,
524 ldstpair_off,
525 ldstpair_indexed,
526 loadlit,
527 log_imm,
528 log_shift,
ee804238 529 lse_atomic,
a06ea964
NC		 530 movewide,
531 pcreladdr,
532 ic_system,
116b6019
RS		 533 sve_cpy,
534 sve_index,
535 sve_limm,
536 sve_misc,
537 sve_movprfx,
538 sve_pred_zm,
539 sve_shift_pred,
540 sve_shift_unpred,
541 sve_size_bhs,
542 sve_size_bhsd,
543 sve_size_hsd,
544 sve_size_sd,
a06ea964 545 testbranch,
f42f1a1d
TC		 546 cryptosm3,
547 cryptosm4,
65a55fbb 548 dotproduct,
a06ea964
NC		 549};
550
551/* Opcode enumerators. */
552
553enum aarch64_op
554{
555 OP_NIL,
556 OP_STRB_POS,
557 OP_LDRB_POS,
558 OP_LDRSB_POS,
559 OP_STRH_POS,
560 OP_LDRH_POS,
561 OP_LDRSH_POS,
562 OP_STR_POS,
563 OP_LDR_POS,
564 OP_STRF_POS,
565 OP_LDRF_POS,
566 OP_LDRSW_POS,
567 OP_PRFM_POS,
568
569 OP_STURB,
570 OP_LDURB,
571 OP_LDURSB,
572 OP_STURH,
573 OP_LDURH,
574 OP_LDURSH,
575 OP_STUR,
576 OP_LDUR,
577 OP_STURV,
578 OP_LDURV,
579 OP_LDURSW,
580 OP_PRFUM,
581
582 OP_LDR_LIT,
583 OP_LDRV_LIT,
584 OP_LDRSW_LIT,
585 OP_PRFM_LIT,
586
587 OP_ADD,
588 OP_B,
589 OP_BL,
590
591 OP_MOVN,
592 OP_MOVZ,
593 OP_MOVK,
594
595 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
596 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
597 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
598
599 OP_MOV_V, /* MOV alias for moving vector register. */
600
601 OP_ASR_IMM,
602 OP_LSR_IMM,
603 OP_LSL_IMM,
604
605 OP_BIC,
606
607 OP_UBFX,
608 OP_BFXIL,
609 OP_SBFX,
610 OP_SBFIZ,
611 OP_BFI,
d685192a 612 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 613 OP_UBFIZ,
614 OP_UXTB,
615 OP_UXTH,
616 OP_UXTW,
617
a06ea964
NC		 618 OP_CINC,
619 OP_CINV,
620 OP_CNEG,
621 OP_CSET,
622 OP_CSETM,
623
624 OP_FCVT,
625 OP_FCVTN,
626 OP_FCVTN2,
627 OP_FCVTL,
628 OP_FCVTL2,
629 OP_FCVTXN_S, /* Scalar version. */
630
631 OP_ROR_IMM,
632
e30181a5
YZ		 633 OP_SXTL,
634 OP_SXTL2,
635 OP_UXTL,
636 OP_UXTL2,
637
c0890d26
RS		 638 OP_MOV_P_P,
639 OP_MOV_Z_P_Z,
640 OP_MOV_Z_V,
641 OP_MOV_Z_Z,
642 OP_MOV_Z_Zi,
643 OP_MOVM_P_P_P,
644 OP_MOVS_P_P,
645 OP_MOVZS_P_P_P,
646 OP_MOVZ_P_P_P,
647 OP_NOTS_P_P_P_Z,
648 OP_NOT_P_P_P_Z,
649
c2c4ff8d
SN		 650 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
651
a06ea964
NC		 652 OP_TOTAL_NUM, /* Pseudo. */
653};
654
1d482394
TC		 655/* Error types. */
656enum err_type
657{
658 ERR_OK,
659 ERR_UND,
660 ERR_UNP,
661 ERR_NYI,
a68f4cd2 662 ERR_VFI,
1d482394
TC		 663 ERR_NR_ENTRIES
664};
665
a06ea964
NC		 666/* Maximum number of operands an instruction can have. */
667#define AARCH64_MAX_OPND_NUM 6
668/* Maximum number of qualifier sequences an instruction can have. */
669#define AARCH64_MAX_QLF_SEQ_NUM 10
670/* Operand qualifier typedef; optimized for the size. */
671typedef unsigned char aarch64_opnd_qualifier_t;
672/* Operand qualifier sequence typedef. */
673typedef aarch64_opnd_qualifier_t \
674 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
675
676/* FIXME: improve the efficiency. */
677static inline bfd_boolean
678empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
679{
680 int i;
681 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
682 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
683 return FALSE;
684 return TRUE;
685}
686
7e84b55d
TC		 687/* Forward declare error reporting type. */
688typedef struct aarch64_operand_error aarch64_operand_error;
689/* Forward declare instruction sequence type. */
690typedef struct aarch64_instr_sequence aarch64_instr_sequence;
691/* Forward declare instruction definition. */
692typedef struct aarch64_inst aarch64_inst;
693
a06ea964
NC		 694/* This structure holds information for a particular opcode. */
695
696struct aarch64_opcode
697{
698 /* The name of the mnemonic. */
699 const char *name;
700
701 /* The opcode itself. Those bits which will be filled in with
702 operands are zeroes. */
703 aarch64_insn opcode;
704
705 /* The opcode mask. This is used by the disassembler. This is a
706 mask containing ones indicating those bits which must match the
707 opcode field, and zeroes indicating those bits which need not
708 match (and are presumably filled in by operands). */
709 aarch64_insn mask;
710
711 /* Instruction class. */
712 enum aarch64_insn_class iclass;
713
714 /* Enumerator identifier. */
715 enum aarch64_op op;
716
717 /* Which architecture variant provides this instruction. */
718 const aarch64_feature_set *avariant;
719
720 /* An array of operand codes. Each code is an index into the
721 operand table. They appear in the order which the operands must
722 appear in assembly code, and are terminated by a zero. */
723 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
724
725 /* A list of operand qualifier code sequence. Each operand qualifier
726 code qualifies the corresponding operand code. Each operand
727 qualifier sequence specifies a valid opcode variant and related
728 constraint on operands. */
729 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
730
731 /* Flags providing information about this instruction */
eae424ae
TC		 732 uint64_t flags;
733
734 /* Extra constraints on the instruction that the verifier checks. */
735 uint32_t constraints;
4bd13cde 736
0c608d6b
RS		 737 /* If nonzero, this operand and operand 0 are both registers and
738 are required to have the same register number. */
739 unsigned char tied_operand;
740
4bd13cde 741 /* If non-NULL, a function to verify that a given instruction is valid. */
755b748f
TC		 742 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
743 bfd_vma, bfd_boolean, aarch64_operand_error *,
744 struct aarch64_instr_sequence *);
a06ea964
NC		 745};
746
747typedef struct aarch64_opcode aarch64_opcode;
748
749/* Table describing all the AArch64 opcodes. */
750extern aarch64_opcode aarch64_opcode_table[];
751
752/* Opcode flags. */
753#define F_ALIAS (1 << 0)
754#define F_HAS_ALIAS (1 << 1)
755/* Disassembly preference priority 1-3 (the larger the higher). If nothing
756 is specified, it is the priority 0 by default, i.e. the lowest priority. */
757#define F_P1 (1 << 2)
758#define F_P2 (2 << 2)
759#define F_P3 (3 << 2)
760/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
761#define F_COND (1 << 4)
762/* Instruction has the field of 'sf'. */
763#define F_SF (1 << 5)
764/* Instruction has the field of 'size:Q'. */
765#define F_SIZEQ (1 << 6)
766/* Floating-point instruction has the field of 'type'. */
767#define F_FPTYPE (1 << 7)
768/* AdvSIMD scalar instruction has the field of 'size'. */
769#define F_SSIZE (1 << 8)
770/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
771#define F_T (1 << 9)
772/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
773#define F_GPRSIZE_IN_Q (1 << 10)
774/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
775#define F_LDS_SIZE (1 << 11)
776/* Optional operand; assume maximum of 1 operand can be optional. */
777#define F_OPD0_OPT (1 << 12)
778#define F_OPD1_OPT (2 << 12)
779#define F_OPD2_OPT (3 << 12)
780#define F_OPD3_OPT (4 << 12)
781#define F_OPD4_OPT (5 << 12)
782/* Default value for the optional operand when omitted from the assembly. */
783#define F_DEFAULT(X) (((X) & 0x1f) << 15)
784/* Instruction that is an alias of another instruction needs to be
785 encoded/decoded by converting it to/from the real form, followed by
786 the encoding/decoding according to the rules of the real opcode.
787 This compares to the direct coding using the alias's information.
788 N.B. this flag requires F_ALIAS to be used together. */
789#define F_CONV (1 << 20)
790/* Use together with F_ALIAS to indicate an alias opcode is a programmer
791 friendly pseudo instruction available only in the assembly code (thus will
792 not show up in the disassembly). */
793#define F_PSEUDO (1 << 21)
794/* Instruction has miscellaneous encoding/decoding rules. */
795#define F_MISC (1 << 22)
796/* Instruction has the field of 'N'; used in conjunction with F_SF. */
797#define F_N (1 << 23)
798/* Opcode dependent field. */
799#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 800/* Instruction has the field of 'sz'. */
801#define F_LSE_SZ (1 << 27)
4989adac
RS		 802/* Require an exact qualifier match, even for NIL qualifiers. */
803#define F_STRICT (1ULL << 28)
f9830ec1
TC		 804/* This system instruction is used to read system registers. */
805#define F_SYS_READ (1ULL << 29)
806/* This system instruction is used to write system registers. */
807#define F_SYS_WRITE (1ULL << 30)
eae424ae
TC		 808/* This instruction has an extra constraint on it that imposes a requirement on
809 subsequent instructions. */
810#define F_SCAN (1ULL << 31)
811/* Next bit is 32. */
812
813/* Instruction constraints. */
814/* This instruction has a predication constraint on the instruction at PC+4. */
815#define C_SCAN_MOVPRFX (1U << 0)
816/* This instruction's operation width is determined by the operand with the
817 largest element size. */
818#define C_MAX_ELEM (1U << 1)
819/* Next bit is 2. */
a06ea964
NC		 820
821static inline bfd_boolean
822alias_opcode_p (const aarch64_opcode *opcode)
823{
824 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
825}
826
827static inline bfd_boolean
828opcode_has_alias (const aarch64_opcode *opcode)
829{
830 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
831}
832
833/* Priority for disassembling preference. */
834static inline int
835opcode_priority (const aarch64_opcode *opcode)
836{
837 return (opcode->flags >> 2) & 0x3;
838}
839
840static inline bfd_boolean
841pseudo_opcode_p (const aarch64_opcode *opcode)
842{
843 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
844}
845
846static inline bfd_boolean
847optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
848{
849 return (((opcode->flags >> 12) & 0x7) == idx + 1)
850 ? TRUE : FALSE;
851}
852
853static inline aarch64_insn
854get_optional_operand_default_value (const aarch64_opcode *opcode)
855{
856 return (opcode->flags >> 15) & 0x1f;
857}
858
859static inline unsigned int
860get_opcode_dependent_value (const aarch64_opcode *opcode)
861{
862 return (opcode->flags >> 24) & 0x7;
863}
864
865static inline bfd_boolean
866opcode_has_special_coder (const aarch64_opcode *opcode)
867{
ee804238 868 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 869 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
870 : FALSE;
871}
872\f
873struct aarch64_name_value_pair
874{
875 const char * name;
876 aarch64_insn value;
877};
878
879extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 880extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
881extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 882extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 883
49eec193
YZ		 884typedef struct
885{
886 const char * name;
887 aarch64_insn value;
888 uint32_t flags;
889} aarch64_sys_reg;
890
891extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 892extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 893extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 894extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
895 const aarch64_sys_reg *);
896extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
897 const aarch64_sys_reg *);
49eec193 898
a06ea964
NC		 899typedef struct
900{
875880c6 901 const char *name;
a06ea964 902 uint32_t value;
ea2deeec 903 uint32_t flags ;
a06ea964
NC		 904} aarch64_sys_ins_reg;
905
ea2deeec 906extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 907extern bfd_boolean
908aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
909 const aarch64_sys_ins_reg *);
ea2deeec 910
a06ea964
NC		 911extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
912extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
913extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
914extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
915
916/* Shift/extending operator kinds.
917 N.B. order is important; keep aarch64_operand_modifiers synced. */
918enum aarch64_modifier_kind
919{
920 AARCH64_MOD_NONE,
921 AARCH64_MOD_MSL,
922 AARCH64_MOD_ROR,
923 AARCH64_MOD_ASR,
924 AARCH64_MOD_LSR,
925 AARCH64_MOD_LSL,
926 AARCH64_MOD_UXTB,
927 AARCH64_MOD_UXTH,
928 AARCH64_MOD_UXTW,
929 AARCH64_MOD_UXTX,
930 AARCH64_MOD_SXTB,
931 AARCH64_MOD_SXTH,
932 AARCH64_MOD_SXTW,
933 AARCH64_MOD_SXTX,
2442d846 934 AARCH64_MOD_MUL,
98907a70 935 AARCH64_MOD_MUL_VL,
a06ea964
NC		 936};
937
938bfd_boolean
939aarch64_extend_operator_p (enum aarch64_modifier_kind);
940
941enum aarch64_modifier_kind
942aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
943/* Condition. */
944
945typedef struct
946{
947 /* A list of names with the first one as the disassembly preference;
948 terminated by NULL if fewer than 3. */
bb7eff52 949 const char *names[4];
a06ea964
NC		 950 aarch64_insn value;
951} aarch64_cond;
952
953extern const aarch64_cond aarch64_conds[16];
954
955const aarch64_cond* get_cond_from_value (aarch64_insn value);
956const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
957\f
958/* Structure representing an operand. */
959
960struct aarch64_opnd_info
961{
962 enum aarch64_opnd type;
963 aarch64_opnd_qualifier_t qualifier;
964 int idx;
965
966 union
967 {
968 struct
969 {
970 unsigned regno;
971 } reg;
972 struct
973 {
dab26bf4
RS		 974 unsigned int regno;
975 int64_t index;
a06ea964
NC		 976 } reglane;
977 /* e.g. LVn. */
978 struct
979 {
980 unsigned first_regno : 5;
981 unsigned num_regs : 3;
982 /* 1 if it is a list of reg element. */
983 unsigned has_index : 1;
984 /* Lane index; valid only when has_index is 1. */
dab26bf4 985 int64_t index;
a06ea964
NC		 986 } reglist;
987 /* e.g. immediate or pc relative address offset. */
988 struct
989 {
990 int64_t value;
991 unsigned is_fp : 1;
992 } imm;
993 /* e.g. address in STR (register offset). */
994 struct
995 {
996 unsigned base_regno;
997 struct
998 {
999 union
1000 {
1001 int imm;
1002 unsigned regno;
1003 };
1004 unsigned is_reg;
1005 } offset;
1006 unsigned pcrel : 1; /* PC-relative. */
1007 unsigned writeback : 1;
1008 unsigned preind : 1; /* Pre-indexed. */
1009 unsigned postind : 1; /* Post-indexed. */
1010 } addr;
561a72d4
TC		 1011
1012 struct
1013 {
1014 /* The encoding of the system register. */
1015 aarch64_insn value;
1016
1017 /* The system register flags. */
1018 uint32_t flags;
1019 } sysreg;
1020
a06ea964 1021 const aarch64_cond *cond;
a06ea964
NC		 1022 /* The encoding of the PSTATE field. */
1023 aarch64_insn pstatefield;
1024 const aarch64_sys_ins_reg *sysins_op;
1025 const struct aarch64_name_value_pair *barrier;
9ed608f9 1026 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 1027 const struct aarch64_name_value_pair *prfop;
1028 };
1029
1030 /* Operand shifter; in use when the operand is a register offset address,
1031 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1032 struct
1033 {
1034 enum aarch64_modifier_kind kind;
a06ea964
NC		 1035 unsigned operator_present: 1; /* Only valid during encoding. */
1036 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1037 unsigned amount_present: 1;
2442d846 1038 int64_t amount;
a06ea964
NC		 1039 } shifter;
1040
1041 unsigned skip:1; /* Operand is not completed if there is a fixup needed
1042 to be done on it. In some (but not all) of these
1043 cases, we need to tell libopcodes to skip the
1044 constraint checking and the encoding for this
1045 operand, so that the libopcodes can pick up the
1046 right opcode before the operand is fixed-up. This
1047 flag should only be used during the
1048 assembling/encoding. */
1049 unsigned present:1; /* Whether this operand is present in the assembly
1050 line; not used during the disassembly. */
1051};
1052
1053typedef struct aarch64_opnd_info aarch64_opnd_info;
1054
1055/* Structure representing an instruction.
1056
1057 It is used during both the assembling and disassembling. The assembler
1058 fills an aarch64_inst after a successful parsing and then passes it to the
1059 encoding routine to do the encoding. During the disassembling, the
1060 disassembler calls the decoding routine to decode a binary instruction; on a
1061 successful return, such a structure will be filled with information of the
1062 instruction; then the disassembler uses the information to print out the
1063 instruction. */
1064
1065struct aarch64_inst
1066{
1067 /* The value of the binary instruction. */
1068 aarch64_insn value;
1069
1070 /* Corresponding opcode entry. */
1071 const aarch64_opcode *opcode;
1072
1073 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1074 const aarch64_cond *cond;
1075
1076 /* Operands information. */
1077 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1078};
1079
a06ea964
NC		 1080\f
1081/* Diagnosis related declaration and interface. */
1082
1083/* Operand error kind enumerators.
1084
1085 AARCH64_OPDE_RECOVERABLE
1086 Less severe error found during the parsing, very possibly because that
1087 GAS has picked up a wrong instruction template for the parsing.
1088
1089 AARCH64_OPDE_SYNTAX_ERROR
1090 General syntax error; it can be either a user error, or simply because
1091 that GAS is trying a wrong instruction template.
1092
1093 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1094 Definitely a user syntax error.
1095
1096 AARCH64_OPDE_INVALID_VARIANT
1097 No syntax error, but the operands are not a valid combination, e.g.
1098 FMOV D0,S0
1099
0c608d6b
RS		 1100 AARCH64_OPDE_UNTIED_OPERAND
1101 The asm failed to use the same register for a destination operand
1102 and a tied source operand.
1103
a06ea964
NC		 1104 AARCH64_OPDE_OUT_OF_RANGE
1105 Error about some immediate value out of a valid range.
1106
1107 AARCH64_OPDE_UNALIGNED
1108 Error about some immediate value not properly aligned (i.e. not being a
1109 multiple times of a certain value).
1110
1111 AARCH64_OPDE_REG_LIST
1112 Error about the register list operand having unexpected number of
1113 registers.
1114
1115 AARCH64_OPDE_OTHER_ERROR
1116 Error of the highest severity and used for any severe issue that does not
1117 fall into any of the above categories.
1118
1119 The enumerators are only interesting to GAS. They are declared here (in
1120 libopcodes) because that some errors are detected (and then notified to GAS)
1121 by libopcodes (rather than by GAS solely).
1122
1123 The first three errors are only deteced by GAS while the
1124 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1125 only libopcodes has the information about the valid variants of each
1126 instruction.
1127
1128 The enumerators have an increasing severity. This is helpful when there are
1129 multiple instruction templates available for a given mnemonic name (e.g.
1130 FMOV); this mechanism will help choose the most suitable template from which
1131 the generated diagnostics can most closely describe the issues, if any. */
1132
1133enum aarch64_operand_error_kind
1134{
1135 AARCH64_OPDE_NIL,
1136 AARCH64_OPDE_RECOVERABLE,
1137 AARCH64_OPDE_SYNTAX_ERROR,
1138 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1139 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1140 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1141 AARCH64_OPDE_OUT_OF_RANGE,
1142 AARCH64_OPDE_UNALIGNED,
1143 AARCH64_OPDE_REG_LIST,
1144 AARCH64_OPDE_OTHER_ERROR
1145};
1146
1147/* N.B. GAS assumes that this structure work well with shallow copy. */
1148struct aarch64_operand_error
1149{
1150 enum aarch64_operand_error_kind kind;
1151 int index;
1152 const char *error;
1153 int data[3]; /* Some data for extra information. */
7d02540a 1154 bfd_boolean non_fatal;
a06ea964
NC		 1155};
1156
7e84b55d
TC		 1157/* AArch64 sequence structure used to track instructions with F_SCAN
1158 dependencies for both assembler and disassembler. */
1159struct aarch64_instr_sequence
1160{
1161 /* The instruction that caused this sequence to be opened. */
1162 aarch64_inst *instr;
1163 /* The number of instructions the above instruction allows to be kept in the
1164 sequence before an automatic close is done. */
1165 int num_insns;
1166 /* The instructions currently added to the sequence. */
1167 aarch64_inst **current_insns;
1168 /* The number of instructions already in the sequence. */
1169 int next_insn;
1170};
a06ea964
NC		 1171
1172/* Encoding entrypoint. */
1173
1174extern int
1175aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1176 aarch64_insn *, aarch64_opnd_qualifier_t *,
7e84b55d 1177 aarch64_operand_error *, aarch64_instr_sequence *);
a06ea964
NC		 1178
1179extern const aarch64_opcode *
1180aarch64_replace_opcode (struct aarch64_inst *,
1181 const aarch64_opcode *);
1182
1183/* Given the opcode enumerator OP, return the pointer to the corresponding
1184 opcode entry. */
1185
1186extern const aarch64_opcode *
1187aarch64_get_opcode (enum aarch64_op);
1188
1189/* Generate the string representation of an operand. */
1190extern void
1191aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a
TC		 1192 const aarch64_opnd_info *, int, int *, bfd_vma *,
1193 char **);
a06ea964
NC		 1194
1195/* Miscellaneous interface. */
1196
1197extern int
1198aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1199
1200extern aarch64_opnd_qualifier_t
1201aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1202 const aarch64_opnd_qualifier_t, int);
1203
a68f4cd2
TC		 1204extern bfd_boolean
1205aarch64_is_destructive_by_operands (const aarch64_opcode *);
1206
a06ea964
NC		 1207extern int
1208aarch64_num_of_operands (const aarch64_opcode *);
1209
1210extern int
1211aarch64_stack_pointer_p (const aarch64_opnd_info *);
1212
e141d84e
YQ		 1213extern int
1214aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1215
1d482394 1216extern enum err_type
561a72d4 1217aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
a68f4cd2
TC		 1218 aarch64_operand_error *);
1219
1220extern void
1221init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
36f4aab1 1222
a06ea964
NC		 1223/* Given an operand qualifier, return the expected data element size
1224 of a qualified operand. */
1225extern unsigned char
1226aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1227
1228extern enum aarch64_operand_class
1229aarch64_get_operand_class (enum aarch64_opnd);
1230
1231extern const char *
1232aarch64_get_operand_name (enum aarch64_opnd);
1233
1234extern const char *
1235aarch64_get_operand_desc (enum aarch64_opnd);
1236
e950b345
RS		 1237extern bfd_boolean
1238aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1239
a06ea964
NC		 1240#ifdef DEBUG_AARCH64
1241extern int debug_dump;
1242
1243extern void
1244aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1245
1246#define DEBUG_TRACE(M, ...) \
1247 { \
1248 if (debug_dump) \
1249 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1250 }
1251
1252#define DEBUG_TRACE_IF(C, M, ...) \
1253 { \
1254 if (debug_dump && (C)) \
1255 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1256 }
1257#else /* !DEBUG_AARCH64 */
1258#define DEBUG_TRACE(M, ...) ;
1259#define DEBUG_TRACE_IF(C, M, ...) ;
1260#endif /* DEBUG_AARCH64 */
1261
245d2e3f
RS		 1262extern const char *const aarch64_sve_pattern_array[32];
1263extern const char *const aarch64_sve_prfop_array[16];
1264
d3e12b29
YQ		 1265#ifdef __cplusplus
1266}
1267#endif
1268
a06ea964 1269#endif /* OPCODE_AARCH64_H */
GDB Binutils - Deliverables
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