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[BINUTILS, AARCH64, 2/8] Add Tag generation instructions in Memory Tagging Extension
[deliverable/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
219d1afa 3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
c0e7cef7
NC		 40#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
b6b9ca0c
TC		 42#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
a06ea964 45#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 46#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 47#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 48#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 51#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 52#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 53#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 54#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 55#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 56#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 57#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 58#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 59#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 60#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 61#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
f482d304 62#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
65a55fbb 63#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
d0f7791c 64#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
70d56181 65#define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */
a06ea964 66
13c60ad7
SD		 67/* Flag Manipulation insns. */
68#define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL
69/* FRINT[32,64][Z,X] insns. */
70#define AARCH64_FEATURE_FRINTTS 0x8000000000ULL
68dfbb92
SD		 71/* SB instruction. */
72#define AARCH64_FEATURE_SB 0x10000000000ULL
2ac435d4
SD		 73/* Execution and Data Prediction Restriction instructions. */
74#define AARCH64_FEATURE_PREDRES 0x20000000000ULL
3fd229a4
SD		 75/* DC CVADP. */
76#define AARCH64_FEATURE_CVADP 0x40000000000ULL
af4bcb4c
SD		 77/* Random Number instructions. */
78#define AARCH64_FEATURE_RNG 0x80000000000ULL
ff605452
SD		 79/* BTI instructions. */
80#define AARCH64_FEATURE_BTI 0x100000000000ULL
a97330e7
SD		 81/* SCXTNUM_ELx. */
82#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
83/* ID_PFR2 instructions. */
84#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
104fefee
SD		 85/* SSBS mechanism enabled. */
86#define AARCH64_FEATURE_SSBS 0x800000000000ULL
73b605ec
SD		 87/* Memory Tagging Extension. */
88#define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL
a97330e7 89
13c60ad7 90
a06ea964
NC		 91/* Architectures are the sum of the base and extensions. */
92#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
93 AARCH64_FEATURE_FP \
94 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 95#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
96 AARCH64_FEATURE_CRC \
250aafa4 97 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 98 | AARCH64_FEATURE_LSE \
99 | AARCH64_FEATURE_PAN \
100 | AARCH64_FEATURE_LOR \
101 | AARCH64_FEATURE_RDMA)
1924ff75 102#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 103 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 104 | AARCH64_FEATURE_RAS)
105#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 106 AARCH64_FEATURE_V8_3 \
f482d304
RS		 107 | AARCH64_FEATURE_RCPC \
108 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 109#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 110 AARCH64_FEATURE_V8_4 \
d0f7791c
TC		 111 | AARCH64_FEATURE_DOTPROD \
112 | AARCH64_FEATURE_F16_FML)
70d56181 113#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
13c60ad7
SD		 114 AARCH64_FEATURE_V8_5 \
115 | AARCH64_FEATURE_FLAGMANIP \
68dfbb92 116 | AARCH64_FEATURE_FRINTTS \
2ac435d4 117 | AARCH64_FEATURE_SB \
3fd229a4 118 | AARCH64_FEATURE_PREDRES \
ff605452 119 | AARCH64_FEATURE_CVADP \
a97330e7
SD		 120 | AARCH64_FEATURE_BTI \
121 | AARCH64_FEATURE_SCXTNUM \
104fefee
SD		 122 | AARCH64_FEATURE_ID_PFR2 \
123 | AARCH64_FEATURE_SSBS)
70d56181 124
88f0ea34 125
a06ea964
NC		 126#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
127#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
128
129/* CPU-specific features. */
21b81e67 130typedef unsigned long long aarch64_feature_set;
a06ea964 131
93d8990c
SN		 132#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
133 ((~(CPU) & (FEAT)) == 0)
134
135#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 136 (((CPU) & (FEAT)) != 0)
137
93d8990c
SN		 138#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
139 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
140
a06ea964
NC		 141#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
142 do \
143 { \
144 (TARG) = (F1) | (F2); \
145 } \
146 while (0)
147
148#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
149 do \
150 { \
151 (TARG) = (F1) &~ (F2); \
152 } \
153 while (0)
154
155#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
156
a06ea964
NC		 157enum aarch64_operand_class
158{
159 AARCH64_OPND_CLASS_NIL,
160 AARCH64_OPND_CLASS_INT_REG,
161 AARCH64_OPND_CLASS_MODIFIED_REG,
162 AARCH64_OPND_CLASS_FP_REG,
163 AARCH64_OPND_CLASS_SIMD_REG,
164 AARCH64_OPND_CLASS_SIMD_ELEMENT,
165 AARCH64_OPND_CLASS_SISD_REG,
166 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 167 AARCH64_OPND_CLASS_SVE_REG,
168 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 169 AARCH64_OPND_CLASS_ADDRESS,
170 AARCH64_OPND_CLASS_IMMEDIATE,
171 AARCH64_OPND_CLASS_SYSTEM,
68a64283 172 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 173};
174
175/* Operand code that helps both parsing and coding.
176 Keep AARCH64_OPERANDS synced. */
177
178enum aarch64_opnd
179{
180 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
181
182 AARCH64_OPND_Rd, /* Integer register as destination. */
183 AARCH64_OPND_Rn, /* Integer register as source. */
184 AARCH64_OPND_Rm, /* Integer register as source. */
185 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
186 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
187 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
188 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
189 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
190
191 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
192 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 193 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 194 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 195 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
196 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
197
198 AARCH64_OPND_Fd, /* Floating-point Fd. */
199 AARCH64_OPND_Fn, /* Floating-point Fn. */
200 AARCH64_OPND_Fm, /* Floating-point Fm. */
201 AARCH64_OPND_Fa, /* Floating-point Fa. */
202 AARCH64_OPND_Ft, /* Floating-point Ft. */
203 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
204
205 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
206 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
207 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
208
f42f1a1d 209 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 210 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
211 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
212 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
213 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
214 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
215 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
216 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
217 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
369c9167
TC		 218 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
219 qualifier is S_H. */
a06ea964
NC		 220 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
221 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
222 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
223 structure to all lanes. */
224 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
225
a6a51754
RL		 226 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
227 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 228
229 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 230 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 231 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
232 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
233 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
234 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
235 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
236 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
237 (no encoding). */
238 AARCH64_OPND_IMM0, /* Immediate for #0. */
239 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
240 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
241 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
242 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
243 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
244 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 245 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 246 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
247 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
248 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
193614f2 249 AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
a06ea964 250 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
193614f2 251 AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
a06ea964
NC		 252 AARCH64_OPND_BIT_NUM, /* Immediate. */
253 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
254 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 255 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 256 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
257 each condition flag. */
258
259 AARCH64_OPND_LIMM, /* Logical Immediate. */
260 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
261 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
262 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
263 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 264 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
265 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
266 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 267
268 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 269 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 270
271 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
272 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
273 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
274 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
275 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
276
277 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
278 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
279 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
280 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
281 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
282 negative or unaligned and there is
283 no writeback allowed. This operand code
284 is only used to support the programmer-
285 friendly feature of using LDR/STR as the
286 the mnemonic name for LDUR/STUR instructions
287 wherever there is no ambiguity. */
3f06e550 288 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
a06ea964
NC		 289 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
290 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 291 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 292 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
293
294 AARCH64_OPND_SYSREG, /* System register operand. */
295 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
296 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
297 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
298 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
299 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
2ac435d4 300 AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
a06ea964
NC		 301 AARCH64_OPND_BARRIER, /* Barrier operand. */
302 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
303 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 304 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
ff605452 305 AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
f11ad6bc 306
582e12bf 307 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
98907a70
RS		 308 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
309 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
310 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
311 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
312 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
313 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 314 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
315 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
316 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
317 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 318 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS		 319 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
320 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
321 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
322 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
323 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
324 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
325 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
326 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
327 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
328 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
329 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
330 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
331 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
332 Bit 14 controls S/U choice. */
333 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
334 Bit 22 controls S/U choice. */
335 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
336 Bit 14 controls S/U choice. */
337 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
338 Bit 22 controls S/U choice. */
339 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
340 Bit 14 controls S/U choice. */
341 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
342 Bit 22 controls S/U choice. */
343 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
344 Bit 14 controls S/U choice. */
345 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
346 Bit 22 controls S/U choice. */
347 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
348 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
349 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
350 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
351 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
352 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
353 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 354 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
355 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 356 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
357 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
358 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
359 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 360 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
361 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
e950b345
RS		 362 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
363 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
364 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 365 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 366 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 367 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 368 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
369 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
370 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
371 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
372 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
373 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
374 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
375 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 376 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
377 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 378 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
379 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
380 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
381 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
382 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
383 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
384 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
385 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
386 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
387 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
388 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
389 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 390 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
391 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
392 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
393 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 394 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
395 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
396 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
397 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
398 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 399 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
400 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
401 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 402 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
403 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
404 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
405 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
406 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
f42f1a1d 407 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC		 408};
409
410/* Qualifier constrains an operand. It either specifies a variant of an
411 operand type or limits values available to an operand type.
412
413 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
414
415enum aarch64_opnd_qualifier
416{
417 /* Indicating no further qualification on an operand. */
418 AARCH64_OPND_QLF_NIL,
419
420 /* Qualifying an operand which is a general purpose (integer) register;
421 indicating the operand data size or a specific register. */
422 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
423 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
424 AARCH64_OPND_QLF_WSP, /* WSP. */
425 AARCH64_OPND_QLF_SP, /* SP. */
426
427 /* Qualifying an operand which is a floating-point register, a SIMD
428 vector element or a SIMD vector element list; indicating operand data
429 size or the size of each SIMD vector element in the case of a SIMD
430 vector element list.
431 These qualifiers are also used to qualify an address operand to
432 indicate the size of data element a load/store instruction is
433 accessing.
434 They are also used for the immediate shift operand in e.g. SSHR. Such
435 a use is only for the ease of operand encoding/decoding and qualifier
436 sequence matching; such a use should not be applied widely; use the value
437 constraint qualifiers for immediate operands wherever possible. */
438 AARCH64_OPND_QLF_S_B,
439 AARCH64_OPND_QLF_S_H,
440 AARCH64_OPND_QLF_S_S,
441 AARCH64_OPND_QLF_S_D,
442 AARCH64_OPND_QLF_S_Q,
00c2093f
TC		 443 /* This type qualifier has a special meaning in that it means that 4 x 1 byte
444 are selected by the instruction. Other than that it has no difference
445 with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
446 reasons and is an exception from normal AArch64 disassembly scheme. */
447 AARCH64_OPND_QLF_S_4B,
a06ea964
NC		 448
449 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
450 register list; indicating register shape.
451 They are also used for the immediate shift operand in e.g. SSHR. Such
452 a use is only for the ease of operand encoding/decoding and qualifier
453 sequence matching; such a use should not be applied widely; use the value
454 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 455 AARCH64_OPND_QLF_V_4B,
a06ea964
NC		 456 AARCH64_OPND_QLF_V_8B,
457 AARCH64_OPND_QLF_V_16B,
3067d3b9 458 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 459 AARCH64_OPND_QLF_V_4H,
460 AARCH64_OPND_QLF_V_8H,
461 AARCH64_OPND_QLF_V_2S,
462 AARCH64_OPND_QLF_V_4S,
463 AARCH64_OPND_QLF_V_1D,
464 AARCH64_OPND_QLF_V_2D,
465 AARCH64_OPND_QLF_V_1Q,
466
d50c751e
RS		 467 AARCH64_OPND_QLF_P_Z,
468 AARCH64_OPND_QLF_P_M,
469
a06ea964 470 /* Constraint on value. */
a6a51754 471 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 472 AARCH64_OPND_QLF_imm_0_7,
473 AARCH64_OPND_QLF_imm_0_15,
474 AARCH64_OPND_QLF_imm_0_31,
475 AARCH64_OPND_QLF_imm_0_63,
476 AARCH64_OPND_QLF_imm_1_32,
477 AARCH64_OPND_QLF_imm_1_64,
478
479 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
480 or shift-ones. */
481 AARCH64_OPND_QLF_LSL,
482 AARCH64_OPND_QLF_MSL,
483
484 /* Special qualifier helping retrieve qualifier information during the
485 decoding time (currently not in use). */
486 AARCH64_OPND_QLF_RETRIEVE,
487};
488\f
489/* Instruction class. */
490
491enum aarch64_insn_class
492{
493 addsub_carry,
494 addsub_ext,
495 addsub_imm,
496 addsub_shift,
497 asimdall,
498 asimddiff,
499 asimdelem,
500 asimdext,
501 asimdimm,
502 asimdins,
503 asimdmisc,
504 asimdperm,
505 asimdsame,
506 asimdshf,
507 asimdtbl,
508 asisddiff,
509 asisdelem,
510 asisdlse,
511 asisdlsep,
512 asisdlso,
513 asisdlsop,
514 asisdmisc,
515 asisdone,
516 asisdpair,
517 asisdsame,
518 asisdshf,
519 bitfield,
520 branch_imm,
521 branch_reg,
522 compbranch,
523 condbranch,
524 condcmp_imm,
525 condcmp_reg,
526 condsel,
527 cryptoaes,
528 cryptosha2,
529 cryptosha3,
530 dp_1src,
531 dp_2src,
532 dp_3src,
533 exception,
534 extract,
535 float2fix,
536 float2int,
537 floatccmp,
538 floatcmp,
539 floatdp1,
540 floatdp2,
541 floatdp3,
542 floatimm,
543 floatsel,
544 ldst_immpost,
545 ldst_immpre,
546 ldst_imm9, /* immpost or immpre */
3f06e550 547 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 548 ldst_pos,
549 ldst_regoff,
550 ldst_unpriv,
551 ldst_unscaled,
552 ldstexcl,
553 ldstnapair_offs,
554 ldstpair_off,
555 ldstpair_indexed,
556 loadlit,
557 log_imm,
558 log_shift,
ee804238 559 lse_atomic,
a06ea964
NC		 560 movewide,
561 pcreladdr,
562 ic_system,
116b6019
RS		 563 sve_cpy,
564 sve_index,
565 sve_limm,
566 sve_misc,
567 sve_movprfx,
568 sve_pred_zm,
569 sve_shift_pred,
570 sve_shift_unpred,
571 sve_size_bhs,
572 sve_size_bhsd,
573 sve_size_hsd,
574 sve_size_sd,
a06ea964 575 testbranch,
f42f1a1d
TC		 576 cryptosm3,
577 cryptosm4,
65a55fbb 578 dotproduct,
a06ea964
NC		 579};
580
581/* Opcode enumerators. */
582
583enum aarch64_op
584{
585 OP_NIL,
586 OP_STRB_POS,
587 OP_LDRB_POS,
588 OP_LDRSB_POS,
589 OP_STRH_POS,
590 OP_LDRH_POS,
591 OP_LDRSH_POS,
592 OP_STR_POS,
593 OP_LDR_POS,
594 OP_STRF_POS,
595 OP_LDRF_POS,
596 OP_LDRSW_POS,
597 OP_PRFM_POS,
598
599 OP_STURB,
600 OP_LDURB,
601 OP_LDURSB,
602 OP_STURH,
603 OP_LDURH,
604 OP_LDURSH,
605 OP_STUR,
606 OP_LDUR,
607 OP_STURV,
608 OP_LDURV,
609 OP_LDURSW,
610 OP_PRFUM,
611
612 OP_LDR_LIT,
613 OP_LDRV_LIT,
614 OP_LDRSW_LIT,
615 OP_PRFM_LIT,
616
617 OP_ADD,
618 OP_B,
619 OP_BL,
620
621 OP_MOVN,
622 OP_MOVZ,
623 OP_MOVK,
624
625 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
626 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
627 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
628
629 OP_MOV_V, /* MOV alias for moving vector register. */
630
631 OP_ASR_IMM,
632 OP_LSR_IMM,
633 OP_LSL_IMM,
634
635 OP_BIC,
636
637 OP_UBFX,
638 OP_BFXIL,
639 OP_SBFX,
640 OP_SBFIZ,
641 OP_BFI,
d685192a 642 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 643 OP_UBFIZ,
644 OP_UXTB,
645 OP_UXTH,
646 OP_UXTW,
647
a06ea964
NC		 648 OP_CINC,
649 OP_CINV,
650 OP_CNEG,
651 OP_CSET,
652 OP_CSETM,
653
654 OP_FCVT,
655 OP_FCVTN,
656 OP_FCVTN2,
657 OP_FCVTL,
658 OP_FCVTL2,
659 OP_FCVTXN_S, /* Scalar version. */
660
661 OP_ROR_IMM,
662
e30181a5
YZ		 663 OP_SXTL,
664 OP_SXTL2,
665 OP_UXTL,
666 OP_UXTL2,
667
c0890d26
RS		 668 OP_MOV_P_P,
669 OP_MOV_Z_P_Z,
670 OP_MOV_Z_V,
671 OP_MOV_Z_Z,
672 OP_MOV_Z_Zi,
673 OP_MOVM_P_P_P,
674 OP_MOVS_P_P,
675 OP_MOVZS_P_P_P,
676 OP_MOVZ_P_P_P,
677 OP_NOTS_P_P_P_Z,
678 OP_NOT_P_P_P_Z,
679
c2c4ff8d
SN		 680 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
681
a06ea964
NC		 682 OP_TOTAL_NUM, /* Pseudo. */
683};
684
1d482394
TC		 685/* Error types. */
686enum err_type
687{
688 ERR_OK,
689 ERR_UND,
690 ERR_UNP,
691 ERR_NYI,
a68f4cd2 692 ERR_VFI,
1d482394
TC		 693 ERR_NR_ENTRIES
694};
695
a06ea964
NC		 696/* Maximum number of operands an instruction can have. */
697#define AARCH64_MAX_OPND_NUM 6
698/* Maximum number of qualifier sequences an instruction can have. */
699#define AARCH64_MAX_QLF_SEQ_NUM 10
700/* Operand qualifier typedef; optimized for the size. */
701typedef unsigned char aarch64_opnd_qualifier_t;
702/* Operand qualifier sequence typedef. */
703typedef aarch64_opnd_qualifier_t \
704 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
705
706/* FIXME: improve the efficiency. */
707static inline bfd_boolean
708empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
709{
710 int i;
711 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
712 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
713 return FALSE;
714 return TRUE;
715}
716
7e84b55d
TC		 717/* Forward declare error reporting type. */
718typedef struct aarch64_operand_error aarch64_operand_error;
719/* Forward declare instruction sequence type. */
720typedef struct aarch64_instr_sequence aarch64_instr_sequence;
721/* Forward declare instruction definition. */
722typedef struct aarch64_inst aarch64_inst;
723
a06ea964
NC		 724/* This structure holds information for a particular opcode. */
725
726struct aarch64_opcode
727{
728 /* The name of the mnemonic. */
729 const char *name;
730
731 /* The opcode itself. Those bits which will be filled in with
732 operands are zeroes. */
733 aarch64_insn opcode;
734
735 /* The opcode mask. This is used by the disassembler. This is a
736 mask containing ones indicating those bits which must match the
737 opcode field, and zeroes indicating those bits which need not
738 match (and are presumably filled in by operands). */
739 aarch64_insn mask;
740
741 /* Instruction class. */
742 enum aarch64_insn_class iclass;
743
744 /* Enumerator identifier. */
745 enum aarch64_op op;
746
747 /* Which architecture variant provides this instruction. */
748 const aarch64_feature_set *avariant;
749
750 /* An array of operand codes. Each code is an index into the
751 operand table. They appear in the order which the operands must
752 appear in assembly code, and are terminated by a zero. */
753 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
754
755 /* A list of operand qualifier code sequence. Each operand qualifier
756 code qualifies the corresponding operand code. Each operand
757 qualifier sequence specifies a valid opcode variant and related
758 constraint on operands. */
759 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
760
761 /* Flags providing information about this instruction */
eae424ae
TC		 762 uint64_t flags;
763
764 /* Extra constraints on the instruction that the verifier checks. */
765 uint32_t constraints;
4bd13cde 766
0c608d6b
RS		 767 /* If nonzero, this operand and operand 0 are both registers and
768 are required to have the same register number. */
769 unsigned char tied_operand;
770
4bd13cde 771 /* If non-NULL, a function to verify that a given instruction is valid. */
755b748f
TC		 772 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
773 bfd_vma, bfd_boolean, aarch64_operand_error *,
774 struct aarch64_instr_sequence *);
a06ea964
NC		 775};
776
777typedef struct aarch64_opcode aarch64_opcode;
778
779/* Table describing all the AArch64 opcodes. */
780extern aarch64_opcode aarch64_opcode_table[];
781
782/* Opcode flags. */
783#define F_ALIAS (1 << 0)
784#define F_HAS_ALIAS (1 << 1)
785/* Disassembly preference priority 1-3 (the larger the higher). If nothing
786 is specified, it is the priority 0 by default, i.e. the lowest priority. */
787#define F_P1 (1 << 2)
788#define F_P2 (2 << 2)
789#define F_P3 (3 << 2)
790/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
791#define F_COND (1 << 4)
792/* Instruction has the field of 'sf'. */
793#define F_SF (1 << 5)
794/* Instruction has the field of 'size:Q'. */
795#define F_SIZEQ (1 << 6)
796/* Floating-point instruction has the field of 'type'. */
797#define F_FPTYPE (1 << 7)
798/* AdvSIMD scalar instruction has the field of 'size'. */
799#define F_SSIZE (1 << 8)
800/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
801#define F_T (1 << 9)
802/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
803#define F_GPRSIZE_IN_Q (1 << 10)
804/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
805#define F_LDS_SIZE (1 << 11)
806/* Optional operand; assume maximum of 1 operand can be optional. */
807#define F_OPD0_OPT (1 << 12)
808#define F_OPD1_OPT (2 << 12)
809#define F_OPD2_OPT (3 << 12)
810#define F_OPD3_OPT (4 << 12)
811#define F_OPD4_OPT (5 << 12)
812/* Default value for the optional operand when omitted from the assembly. */
813#define F_DEFAULT(X) (((X) & 0x1f) << 15)
814/* Instruction that is an alias of another instruction needs to be
815 encoded/decoded by converting it to/from the real form, followed by
816 the encoding/decoding according to the rules of the real opcode.
817 This compares to the direct coding using the alias's information.
818 N.B. this flag requires F_ALIAS to be used together. */
819#define F_CONV (1 << 20)
820/* Use together with F_ALIAS to indicate an alias opcode is a programmer
821 friendly pseudo instruction available only in the assembly code (thus will
822 not show up in the disassembly). */
823#define F_PSEUDO (1 << 21)
824/* Instruction has miscellaneous encoding/decoding rules. */
825#define F_MISC (1 << 22)
826/* Instruction has the field of 'N'; used in conjunction with F_SF. */
827#define F_N (1 << 23)
828/* Opcode dependent field. */
829#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 830/* Instruction has the field of 'sz'. */
831#define F_LSE_SZ (1 << 27)
4989adac
RS		 832/* Require an exact qualifier match, even for NIL qualifiers. */
833#define F_STRICT (1ULL << 28)
f9830ec1
TC		 834/* This system instruction is used to read system registers. */
835#define F_SYS_READ (1ULL << 29)
836/* This system instruction is used to write system registers. */
837#define F_SYS_WRITE (1ULL << 30)
eae424ae
TC		 838/* This instruction has an extra constraint on it that imposes a requirement on
839 subsequent instructions. */
840#define F_SCAN (1ULL << 31)
841/* Next bit is 32. */
842
843/* Instruction constraints. */
844/* This instruction has a predication constraint on the instruction at PC+4. */
845#define C_SCAN_MOVPRFX (1U << 0)
846/* This instruction's operation width is determined by the operand with the
847 largest element size. */
848#define C_MAX_ELEM (1U << 1)
849/* Next bit is 2. */
a06ea964
NC		 850
851static inline bfd_boolean
852alias_opcode_p (const aarch64_opcode *opcode)
853{
854 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
855}
856
857static inline bfd_boolean
858opcode_has_alias (const aarch64_opcode *opcode)
859{
860 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
861}
862
863/* Priority for disassembling preference. */
864static inline int
865opcode_priority (const aarch64_opcode *opcode)
866{
867 return (opcode->flags >> 2) & 0x3;
868}
869
870static inline bfd_boolean
871pseudo_opcode_p (const aarch64_opcode *opcode)
872{
873 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
874}
875
876static inline bfd_boolean
877optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
878{
879 return (((opcode->flags >> 12) & 0x7) == idx + 1)
880 ? TRUE : FALSE;
881}
882
883static inline aarch64_insn
884get_optional_operand_default_value (const aarch64_opcode *opcode)
885{
886 return (opcode->flags >> 15) & 0x1f;
887}
888
889static inline unsigned int
890get_opcode_dependent_value (const aarch64_opcode *opcode)
891{
892 return (opcode->flags >> 24) & 0x7;
893}
894
895static inline bfd_boolean
896opcode_has_special_coder (const aarch64_opcode *opcode)
897{
ee804238 898 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 899 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
900 : FALSE;
901}
902\f
903struct aarch64_name_value_pair
904{
905 const char * name;
906 aarch64_insn value;
907};
908
909extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 910extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
911extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 912extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 913
49eec193
YZ		 914typedef struct
915{
916 const char * name;
917 aarch64_insn value;
918 uint32_t flags;
919} aarch64_sys_reg;
920
921extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 922extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 923extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 924extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
925 const aarch64_sys_reg *);
926extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
927 const aarch64_sys_reg *);
49eec193 928
a06ea964
NC		 929typedef struct
930{
875880c6 931 const char *name;
a06ea964 932 uint32_t value;
ea2deeec 933 uint32_t flags ;
a06ea964
NC		 934} aarch64_sys_ins_reg;
935
ea2deeec 936extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 937extern bfd_boolean
938aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
939 const aarch64_sys_ins_reg *);
ea2deeec 940
a06ea964
NC		 941extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
942extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
943extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
944extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
2ac435d4 945extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
a06ea964
NC		 946
947/* Shift/extending operator kinds.
948 N.B. order is important; keep aarch64_operand_modifiers synced. */
949enum aarch64_modifier_kind
950{
951 AARCH64_MOD_NONE,
952 AARCH64_MOD_MSL,
953 AARCH64_MOD_ROR,
954 AARCH64_MOD_ASR,
955 AARCH64_MOD_LSR,
956 AARCH64_MOD_LSL,
957 AARCH64_MOD_UXTB,
958 AARCH64_MOD_UXTH,
959 AARCH64_MOD_UXTW,
960 AARCH64_MOD_UXTX,
961 AARCH64_MOD_SXTB,
962 AARCH64_MOD_SXTH,
963 AARCH64_MOD_SXTW,
964 AARCH64_MOD_SXTX,
2442d846 965 AARCH64_MOD_MUL,
98907a70 966 AARCH64_MOD_MUL_VL,
a06ea964
NC		 967};
968
969bfd_boolean
970aarch64_extend_operator_p (enum aarch64_modifier_kind);
971
972enum aarch64_modifier_kind
973aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
974/* Condition. */
975
976typedef struct
977{
978 /* A list of names with the first one as the disassembly preference;
979 terminated by NULL if fewer than 3. */
bb7eff52 980 const char *names[4];
a06ea964
NC		 981 aarch64_insn value;
982} aarch64_cond;
983
984extern const aarch64_cond aarch64_conds[16];
985
986const aarch64_cond* get_cond_from_value (aarch64_insn value);
987const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
988\f
989/* Structure representing an operand. */
990
991struct aarch64_opnd_info
992{
993 enum aarch64_opnd type;
994 aarch64_opnd_qualifier_t qualifier;
995 int idx;
996
997 union
998 {
999 struct
1000 {
1001 unsigned regno;
1002 } reg;
1003 struct
1004 {
dab26bf4
RS		 1005 unsigned int regno;
1006 int64_t index;
a06ea964
NC		 1007 } reglane;
1008 /* e.g. LVn. */
1009 struct
1010 {
1011 unsigned first_regno : 5;
1012 unsigned num_regs : 3;
1013 /* 1 if it is a list of reg element. */
1014 unsigned has_index : 1;
1015 /* Lane index; valid only when has_index is 1. */
dab26bf4 1016 int64_t index;
a06ea964
NC		 1017 } reglist;
1018 /* e.g. immediate or pc relative address offset. */
1019 struct
1020 {
1021 int64_t value;
1022 unsigned is_fp : 1;
1023 } imm;
1024 /* e.g. address in STR (register offset). */
1025 struct
1026 {
1027 unsigned base_regno;
1028 struct
1029 {
1030 union
1031 {
1032 int imm;
1033 unsigned regno;
1034 };
1035 unsigned is_reg;
1036 } offset;
1037 unsigned pcrel : 1; /* PC-relative. */
1038 unsigned writeback : 1;
1039 unsigned preind : 1; /* Pre-indexed. */
1040 unsigned postind : 1; /* Post-indexed. */
1041 } addr;
561a72d4
TC		 1042
1043 struct
1044 {
1045 /* The encoding of the system register. */
1046 aarch64_insn value;
1047
1048 /* The system register flags. */
1049 uint32_t flags;
1050 } sysreg;
1051
a06ea964 1052 const aarch64_cond *cond;
a06ea964
NC		 1053 /* The encoding of the PSTATE field. */
1054 aarch64_insn pstatefield;
1055 const aarch64_sys_ins_reg *sysins_op;
1056 const struct aarch64_name_value_pair *barrier;
9ed608f9 1057 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 1058 const struct aarch64_name_value_pair *prfop;
1059 };
1060
1061 /* Operand shifter; in use when the operand is a register offset address,
1062 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1063 struct
1064 {
1065 enum aarch64_modifier_kind kind;
a06ea964
NC		 1066 unsigned operator_present: 1; /* Only valid during encoding. */
1067 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1068 unsigned amount_present: 1;
2442d846 1069 int64_t amount;
a06ea964
NC		 1070 } shifter;
1071
1072 unsigned skip:1; /* Operand is not completed if there is a fixup needed
1073 to be done on it. In some (but not all) of these
1074 cases, we need to tell libopcodes to skip the
1075 constraint checking and the encoding for this
1076 operand, so that the libopcodes can pick up the
1077 right opcode before the operand is fixed-up. This
1078 flag should only be used during the
1079 assembling/encoding. */
1080 unsigned present:1; /* Whether this operand is present in the assembly
1081 line; not used during the disassembly. */
1082};
1083
1084typedef struct aarch64_opnd_info aarch64_opnd_info;
1085
1086/* Structure representing an instruction.
1087
1088 It is used during both the assembling and disassembling. The assembler
1089 fills an aarch64_inst after a successful parsing and then passes it to the
1090 encoding routine to do the encoding. During the disassembling, the
1091 disassembler calls the decoding routine to decode a binary instruction; on a
1092 successful return, such a structure will be filled with information of the
1093 instruction; then the disassembler uses the information to print out the
1094 instruction. */
1095
1096struct aarch64_inst
1097{
1098 /* The value of the binary instruction. */
1099 aarch64_insn value;
1100
1101 /* Corresponding opcode entry. */
1102 const aarch64_opcode *opcode;
1103
1104 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1105 const aarch64_cond *cond;
1106
1107 /* Operands information. */
1108 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1109};
1110
ff605452
SD		 1111/* Defining the HINT #imm values for the aarch64_hint_options. */
1112#define HINT_OPD_CSYNC 0x11
1113#define HINT_OPD_C 0x22
1114#define HINT_OPD_J 0x24
1115#define HINT_OPD_JC 0x26
1116#define HINT_OPD_NULL 0x00
1117
a06ea964
NC		 1118\f
1119/* Diagnosis related declaration and interface. */
1120
1121/* Operand error kind enumerators.
1122
1123 AARCH64_OPDE_RECOVERABLE
1124 Less severe error found during the parsing, very possibly because that
1125 GAS has picked up a wrong instruction template for the parsing.
1126
1127 AARCH64_OPDE_SYNTAX_ERROR
1128 General syntax error; it can be either a user error, or simply because
1129 that GAS is trying a wrong instruction template.
1130
1131 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1132 Definitely a user syntax error.
1133
1134 AARCH64_OPDE_INVALID_VARIANT
1135 No syntax error, but the operands are not a valid combination, e.g.
1136 FMOV D0,S0
1137
0c608d6b
RS		 1138 AARCH64_OPDE_UNTIED_OPERAND
1139 The asm failed to use the same register for a destination operand
1140 and a tied source operand.
1141
a06ea964
NC		 1142 AARCH64_OPDE_OUT_OF_RANGE
1143 Error about some immediate value out of a valid range.
1144
1145 AARCH64_OPDE_UNALIGNED
1146 Error about some immediate value not properly aligned (i.e. not being a
1147 multiple times of a certain value).
1148
1149 AARCH64_OPDE_REG_LIST
1150 Error about the register list operand having unexpected number of
1151 registers.
1152
1153 AARCH64_OPDE_OTHER_ERROR
1154 Error of the highest severity and used for any severe issue that does not
1155 fall into any of the above categories.
1156
1157 The enumerators are only interesting to GAS. They are declared here (in
1158 libopcodes) because that some errors are detected (and then notified to GAS)
1159 by libopcodes (rather than by GAS solely).
1160
1161 The first three errors are only deteced by GAS while the
1162 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1163 only libopcodes has the information about the valid variants of each
1164 instruction.
1165
1166 The enumerators have an increasing severity. This is helpful when there are
1167 multiple instruction templates available for a given mnemonic name (e.g.
1168 FMOV); this mechanism will help choose the most suitable template from which
1169 the generated diagnostics can most closely describe the issues, if any. */
1170
1171enum aarch64_operand_error_kind
1172{
1173 AARCH64_OPDE_NIL,
1174 AARCH64_OPDE_RECOVERABLE,
1175 AARCH64_OPDE_SYNTAX_ERROR,
1176 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1177 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1178 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1179 AARCH64_OPDE_OUT_OF_RANGE,
1180 AARCH64_OPDE_UNALIGNED,
1181 AARCH64_OPDE_REG_LIST,
1182 AARCH64_OPDE_OTHER_ERROR
1183};
1184
1185/* N.B. GAS assumes that this structure work well with shallow copy. */
1186struct aarch64_operand_error
1187{
1188 enum aarch64_operand_error_kind kind;
1189 int index;
1190 const char *error;
1191 int data[3]; /* Some data for extra information. */
7d02540a 1192 bfd_boolean non_fatal;
a06ea964
NC		 1193};
1194
7e84b55d
TC		 1195/* AArch64 sequence structure used to track instructions with F_SCAN
1196 dependencies for both assembler and disassembler. */
1197struct aarch64_instr_sequence
1198{
1199 /* The instruction that caused this sequence to be opened. */
1200 aarch64_inst *instr;
1201 /* The number of instructions the above instruction allows to be kept in the
1202 sequence before an automatic close is done. */
1203 int num_insns;
1204 /* The instructions currently added to the sequence. */
1205 aarch64_inst **current_insns;
1206 /* The number of instructions already in the sequence. */
1207 int next_insn;
1208};
a06ea964
NC		 1209
1210/* Encoding entrypoint. */
1211
1212extern int
1213aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1214 aarch64_insn *, aarch64_opnd_qualifier_t *,
7e84b55d 1215 aarch64_operand_error *, aarch64_instr_sequence *);
a06ea964
NC		 1216
1217extern const aarch64_opcode *
1218aarch64_replace_opcode (struct aarch64_inst *,
1219 const aarch64_opcode *);
1220
1221/* Given the opcode enumerator OP, return the pointer to the corresponding
1222 opcode entry. */
1223
1224extern const aarch64_opcode *
1225aarch64_get_opcode (enum aarch64_op);
1226
1227/* Generate the string representation of an operand. */
1228extern void
1229aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a
TC		 1230 const aarch64_opnd_info *, int, int *, bfd_vma *,
1231 char **);
a06ea964
NC		 1232
1233/* Miscellaneous interface. */
1234
1235extern int
1236aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1237
1238extern aarch64_opnd_qualifier_t
1239aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1240 const aarch64_opnd_qualifier_t, int);
1241
a68f4cd2
TC		 1242extern bfd_boolean
1243aarch64_is_destructive_by_operands (const aarch64_opcode *);
1244
a06ea964
NC		 1245extern int
1246aarch64_num_of_operands (const aarch64_opcode *);
1247
1248extern int
1249aarch64_stack_pointer_p (const aarch64_opnd_info *);
1250
e141d84e
YQ		 1251extern int
1252aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1253
1d482394 1254extern enum err_type
561a72d4 1255aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
a68f4cd2
TC		 1256 aarch64_operand_error *);
1257
1258extern void
1259init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
36f4aab1 1260
a06ea964
NC		 1261/* Given an operand qualifier, return the expected data element size
1262 of a qualified operand. */
1263extern unsigned char
1264aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1265
1266extern enum aarch64_operand_class
1267aarch64_get_operand_class (enum aarch64_opnd);
1268
1269extern const char *
1270aarch64_get_operand_name (enum aarch64_opnd);
1271
1272extern const char *
1273aarch64_get_operand_desc (enum aarch64_opnd);
1274
e950b345
RS		 1275extern bfd_boolean
1276aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1277
a06ea964
NC		 1278#ifdef DEBUG_AARCH64
1279extern int debug_dump;
1280
1281extern void
1282aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1283
1284#define DEBUG_TRACE(M, ...) \
1285 { \
1286 if (debug_dump) \
1287 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1288 }
1289
1290#define DEBUG_TRACE_IF(C, M, ...) \
1291 { \
1292 if (debug_dump && (C)) \
1293 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1294 }
1295#else /* !DEBUG_AARCH64 */
1296#define DEBUG_TRACE(M, ...) ;
1297#define DEBUG_TRACE_IF(C, M, ...) ;
1298#endif /* DEBUG_AARCH64 */
1299
245d2e3f
RS		 1300extern const char *const aarch64_sve_pattern_array[32];
1301extern const char *const aarch64_sve_prfop_array[16];
1302
d3e12b29
YQ		 1303#ifdef __cplusplus
1304}
1305#endif
1306
a06ea964 1307#endif /* OPCODE_AARCH64_H */
GDB Binutils - Deliverables
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