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[BINUTILS, AARCH64, 6/8] Add Tag getting instruction in Memory Tagging Extension
[deliverable/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
219d1afa 3 Copyright (C) 2009-2018 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
c0e7cef7
NC		 40#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
41#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
b6b9ca0c
TC		 42#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
43#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
44#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
a06ea964 45#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
acb787b0 46#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
1924ff75 47#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
a06ea964
NC		 48#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
49#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
50#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
e60bb1dd 51#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
ee804238 52#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
f21cce2c 53#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
290806fd 54#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
9e1f0fa7 55#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
250aafa4 56#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
af117b3c 57#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
c8a6db6f 58#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
73af8ed6 59#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
c0890d26 60#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
d74d4880 61#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
f482d304 62#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
65a55fbb 63#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
d0f7791c 64#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
70d56181 65#define AARCH64_FEATURE_V8_5 0x2000000000ULL /* ARMv8.5 processors. */
a06ea964 66
13c60ad7
SD		 67/* Flag Manipulation insns. */
68#define AARCH64_FEATURE_FLAGMANIP 0x4000000000ULL
69/* FRINT[32,64][Z,X] insns. */
70#define AARCH64_FEATURE_FRINTTS 0x8000000000ULL
68dfbb92
SD		 71/* SB instruction. */
72#define AARCH64_FEATURE_SB 0x10000000000ULL
2ac435d4
SD		 73/* Execution and Data Prediction Restriction instructions. */
74#define AARCH64_FEATURE_PREDRES 0x20000000000ULL
3fd229a4
SD		 75/* DC CVADP. */
76#define AARCH64_FEATURE_CVADP 0x40000000000ULL
af4bcb4c
SD		 77/* Random Number instructions. */
78#define AARCH64_FEATURE_RNG 0x80000000000ULL
ff605452
SD		 79/* BTI instructions. */
80#define AARCH64_FEATURE_BTI 0x100000000000ULL
a97330e7
SD		 81/* SCXTNUM_ELx. */
82#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL
83/* ID_PFR2 instructions. */
84#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
104fefee
SD		 85/* SSBS mechanism enabled. */
86#define AARCH64_FEATURE_SSBS 0x800000000000ULL
73b605ec
SD		 87/* Memory Tagging Extension. */
88#define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL
a97330e7 89
13c60ad7 90
a06ea964
NC		 91/* Architectures are the sum of the base and extensions. */
92#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
93 AARCH64_FEATURE_FP \
94 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 95#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
96 AARCH64_FEATURE_CRC \
250aafa4 97 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 98 | AARCH64_FEATURE_LSE \
99 | AARCH64_FEATURE_PAN \
100 | AARCH64_FEATURE_LOR \
101 | AARCH64_FEATURE_RDMA)
1924ff75 102#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 103 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 104 | AARCH64_FEATURE_RAS)
105#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 106 AARCH64_FEATURE_V8_3 \
f482d304
RS		 107 | AARCH64_FEATURE_RCPC \
108 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 109#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 110 AARCH64_FEATURE_V8_4 \
d0f7791c
TC		 111 | AARCH64_FEATURE_DOTPROD \
112 | AARCH64_FEATURE_F16_FML)
70d56181 113#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
13c60ad7
SD		 114 AARCH64_FEATURE_V8_5 \
115 | AARCH64_FEATURE_FLAGMANIP \
68dfbb92 116 | AARCH64_FEATURE_FRINTTS \
2ac435d4 117 | AARCH64_FEATURE_SB \
3fd229a4 118 | AARCH64_FEATURE_PREDRES \
ff605452 119 | AARCH64_FEATURE_CVADP \
a97330e7
SD		 120 | AARCH64_FEATURE_BTI \
121 | AARCH64_FEATURE_SCXTNUM \
104fefee
SD		 122 | AARCH64_FEATURE_ID_PFR2 \
123 | AARCH64_FEATURE_SSBS)
70d56181 124
88f0ea34 125
a06ea964
NC		 126#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
127#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
128
129/* CPU-specific features. */
21b81e67 130typedef unsigned long long aarch64_feature_set;
a06ea964 131
93d8990c
SN		 132#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
133 ((~(CPU) & (FEAT)) == 0)
134
135#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 136 (((CPU) & (FEAT)) != 0)
137
93d8990c
SN		 138#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
139 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
140
a06ea964
NC		 141#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
142 do \
143 { \
144 (TARG) = (F1) | (F2); \
145 } \
146 while (0)
147
148#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
149 do \
150 { \
151 (TARG) = (F1) &~ (F2); \
152 } \
153 while (0)
154
155#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
156
a06ea964
NC		 157enum aarch64_operand_class
158{
159 AARCH64_OPND_CLASS_NIL,
160 AARCH64_OPND_CLASS_INT_REG,
161 AARCH64_OPND_CLASS_MODIFIED_REG,
162 AARCH64_OPND_CLASS_FP_REG,
163 AARCH64_OPND_CLASS_SIMD_REG,
164 AARCH64_OPND_CLASS_SIMD_ELEMENT,
165 AARCH64_OPND_CLASS_SISD_REG,
166 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 167 AARCH64_OPND_CLASS_SVE_REG,
168 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 169 AARCH64_OPND_CLASS_ADDRESS,
170 AARCH64_OPND_CLASS_IMMEDIATE,
171 AARCH64_OPND_CLASS_SYSTEM,
68a64283 172 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 173};
174
175/* Operand code that helps both parsing and coding.
176 Keep AARCH64_OPERANDS synced. */
177
178enum aarch64_opnd
179{
180 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
181
182 AARCH64_OPND_Rd, /* Integer register as destination. */
183 AARCH64_OPND_Rn, /* Integer register as source. */
184 AARCH64_OPND_Rm, /* Integer register as source. */
185 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
186 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
187 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
188 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
189 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
190
191 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
192 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 193 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 194 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 195 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
196 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
197
198 AARCH64_OPND_Fd, /* Floating-point Fd. */
199 AARCH64_OPND_Fn, /* Floating-point Fn. */
200 AARCH64_OPND_Fm, /* Floating-point Fm. */
201 AARCH64_OPND_Fa, /* Floating-point Fa. */
202 AARCH64_OPND_Ft, /* Floating-point Ft. */
203 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
204
205 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
206 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
207 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
208
f42f1a1d 209 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 210 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
211 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
212 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
213 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
214 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
215 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
216 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
217 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
369c9167
TC		 218 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
219 qualifier is S_H. */
a06ea964
NC		 220 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
221 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
222 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
223 structure to all lanes. */
224 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
225
a6a51754
RL		 226 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
227 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 228
229 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 230 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 231 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
232 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
233 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
234 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
235 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
236 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
237 (no encoding). */
238 AARCH64_OPND_IMM0, /* Immediate for #0. */
239 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
240 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
241 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
242 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
243 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
244 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 245 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 246 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
247 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
248 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
193614f2 249 AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
a06ea964 250 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
193614f2 251 AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
a06ea964
NC		 252 AARCH64_OPND_BIT_NUM, /* Immediate. */
253 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
254 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 255 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 256 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
257 each condition flag. */
258
259 AARCH64_OPND_LIMM, /* Logical Immediate. */
260 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
261 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
262 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
263 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 264 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
265 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
266 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 267
268 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 269 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 270
271 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
272 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
273 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
274 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
275 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
276
277 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
503ba600 278 AARCH64_OPND_ADDR_SIMPLE_2, /* Address of ld/stgv. */
a06ea964
NC		 279 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
280 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
281 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
282 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
283 negative or unaligned and there is
284 no writeback allowed. This operand code
285 is only used to support the programmer-
286 friendly feature of using LDR/STR as the
287 the mnemonic name for LDUR/STUR instructions
288 wherever there is no ambiguity. */
3f06e550 289 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
fb3265b3
SD		 290 AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
291 16) immediate. */
a06ea964 292 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
fb3265b3
SD		 293 AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
294 16) immediate. */
a06ea964 295 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 296 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 297 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
298
299 AARCH64_OPND_SYSREG, /* System register operand. */
300 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
301 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
302 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
303 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
304 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
2ac435d4 305 AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
a06ea964
NC		 306 AARCH64_OPND_BARRIER, /* Barrier operand. */
307 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
308 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 309 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
ff605452 310 AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
f11ad6bc 311
582e12bf 312 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
98907a70
RS		 313 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
314 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
315 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
316 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
317 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
318 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 319 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
320 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
321 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
322 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 323 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS		 324 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
325 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
326 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
327 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
328 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
329 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
330 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
331 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
332 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
333 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
334 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
335 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
336 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
337 Bit 14 controls S/U choice. */
338 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
339 Bit 22 controls S/U choice. */
340 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
341 Bit 14 controls S/U choice. */
342 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
343 Bit 22 controls S/U choice. */
344 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
345 Bit 14 controls S/U choice. */
346 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
347 Bit 22 controls S/U choice. */
348 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
349 Bit 14 controls S/U choice. */
350 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
351 Bit 22 controls S/U choice. */
352 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
353 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
354 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
355 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
356 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
357 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
358 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 359 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
360 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 361 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
362 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
363 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
364 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 365 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
366 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
e950b345
RS		 367 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
368 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
369 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 370 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 371 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 372 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 373 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
374 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
375 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
376 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
377 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
378 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
379 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
380 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 381 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
382 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 383 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
384 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
385 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
386 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
387 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
388 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
389 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
390 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
391 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
392 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
393 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
394 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 395 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
396 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
397 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
398 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 399 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
400 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
401 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
402 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
403 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 404 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
405 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
406 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 407 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
408 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
409 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
410 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
411 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
f42f1a1d 412 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
a06ea964
NC		 413};
414
415/* Qualifier constrains an operand. It either specifies a variant of an
416 operand type or limits values available to an operand type.
417
418 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
419
420enum aarch64_opnd_qualifier
421{
422 /* Indicating no further qualification on an operand. */
423 AARCH64_OPND_QLF_NIL,
424
425 /* Qualifying an operand which is a general purpose (integer) register;
426 indicating the operand data size or a specific register. */
427 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
428 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
429 AARCH64_OPND_QLF_WSP, /* WSP. */
430 AARCH64_OPND_QLF_SP, /* SP. */
431
432 /* Qualifying an operand which is a floating-point register, a SIMD
433 vector element or a SIMD vector element list; indicating operand data
434 size or the size of each SIMD vector element in the case of a SIMD
435 vector element list.
436 These qualifiers are also used to qualify an address operand to
437 indicate the size of data element a load/store instruction is
438 accessing.
439 They are also used for the immediate shift operand in e.g. SSHR. Such
440 a use is only for the ease of operand encoding/decoding and qualifier
441 sequence matching; such a use should not be applied widely; use the value
442 constraint qualifiers for immediate operands wherever possible. */
443 AARCH64_OPND_QLF_S_B,
444 AARCH64_OPND_QLF_S_H,
445 AARCH64_OPND_QLF_S_S,
446 AARCH64_OPND_QLF_S_D,
447 AARCH64_OPND_QLF_S_Q,
00c2093f
TC		 448 /* This type qualifier has a special meaning in that it means that 4 x 1 byte
449 are selected by the instruction. Other than that it has no difference
450 with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
451 reasons and is an exception from normal AArch64 disassembly scheme. */
452 AARCH64_OPND_QLF_S_4B,
a06ea964
NC		 453
454 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
455 register list; indicating register shape.
456 They are also used for the immediate shift operand in e.g. SSHR. Such
457 a use is only for the ease of operand encoding/decoding and qualifier
458 sequence matching; such a use should not be applied widely; use the value
459 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 460 AARCH64_OPND_QLF_V_4B,
a06ea964
NC		 461 AARCH64_OPND_QLF_V_8B,
462 AARCH64_OPND_QLF_V_16B,
3067d3b9 463 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 464 AARCH64_OPND_QLF_V_4H,
465 AARCH64_OPND_QLF_V_8H,
466 AARCH64_OPND_QLF_V_2S,
467 AARCH64_OPND_QLF_V_4S,
468 AARCH64_OPND_QLF_V_1D,
469 AARCH64_OPND_QLF_V_2D,
470 AARCH64_OPND_QLF_V_1Q,
471
d50c751e
RS		 472 AARCH64_OPND_QLF_P_Z,
473 AARCH64_OPND_QLF_P_M,
fb3265b3
SD		 474
475 /* Used in scaled signed immediate that are scaled by a Tag granule
476 like in stg, st2g, etc. */
477 AARCH64_OPND_QLF_imm_tag,
d50c751e 478
a06ea964 479 /* Constraint on value. */
a6a51754 480 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 481 AARCH64_OPND_QLF_imm_0_7,
482 AARCH64_OPND_QLF_imm_0_15,
483 AARCH64_OPND_QLF_imm_0_31,
484 AARCH64_OPND_QLF_imm_0_63,
485 AARCH64_OPND_QLF_imm_1_32,
486 AARCH64_OPND_QLF_imm_1_64,
487
488 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
489 or shift-ones. */
490 AARCH64_OPND_QLF_LSL,
491 AARCH64_OPND_QLF_MSL,
492
493 /* Special qualifier helping retrieve qualifier information during the
494 decoding time (currently not in use). */
495 AARCH64_OPND_QLF_RETRIEVE,
496};
497\f
498/* Instruction class. */
499
500enum aarch64_insn_class
501{
502 addsub_carry,
503 addsub_ext,
504 addsub_imm,
505 addsub_shift,
506 asimdall,
507 asimddiff,
508 asimdelem,
509 asimdext,
510 asimdimm,
511 asimdins,
512 asimdmisc,
513 asimdperm,
514 asimdsame,
515 asimdshf,
516 asimdtbl,
517 asisddiff,
518 asisdelem,
519 asisdlse,
520 asisdlsep,
521 asisdlso,
522 asisdlsop,
523 asisdmisc,
524 asisdone,
525 asisdpair,
526 asisdsame,
527 asisdshf,
528 bitfield,
529 branch_imm,
530 branch_reg,
531 compbranch,
532 condbranch,
533 condcmp_imm,
534 condcmp_reg,
535 condsel,
536 cryptoaes,
537 cryptosha2,
538 cryptosha3,
539 dp_1src,
540 dp_2src,
541 dp_3src,
542 exception,
543 extract,
544 float2fix,
545 float2int,
546 floatccmp,
547 floatcmp,
548 floatdp1,
549 floatdp2,
550 floatdp3,
551 floatimm,
552 floatsel,
553 ldst_immpost,
554 ldst_immpre,
555 ldst_imm9, /* immpost or immpre */
3f06e550 556 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 557 ldst_pos,
558 ldst_regoff,
559 ldst_unpriv,
560 ldst_unscaled,
561 ldstexcl,
562 ldstnapair_offs,
563 ldstpair_off,
564 ldstpair_indexed,
503ba600 565 ldstgv_indexed,
a06ea964
NC		 566 loadlit,
567 log_imm,
568 log_shift,
ee804238 569 lse_atomic,
a06ea964
NC		 570 movewide,
571 pcreladdr,
572 ic_system,
116b6019
RS		 573 sve_cpy,
574 sve_index,
575 sve_limm,
576 sve_misc,
577 sve_movprfx,
578 sve_pred_zm,
579 sve_shift_pred,
580 sve_shift_unpred,
581 sve_size_bhs,
582 sve_size_bhsd,
583 sve_size_hsd,
584 sve_size_sd,
a06ea964 585 testbranch,
f42f1a1d
TC		 586 cryptosm3,
587 cryptosm4,
65a55fbb 588 dotproduct,
a06ea964
NC		 589};
590
591/* Opcode enumerators. */
592
593enum aarch64_op
594{
595 OP_NIL,
596 OP_STRB_POS,
597 OP_LDRB_POS,
598 OP_LDRSB_POS,
599 OP_STRH_POS,
600 OP_LDRH_POS,
601 OP_LDRSH_POS,
602 OP_STR_POS,
603 OP_LDR_POS,
604 OP_STRF_POS,
605 OP_LDRF_POS,
606 OP_LDRSW_POS,
607 OP_PRFM_POS,
608
609 OP_STURB,
610 OP_LDURB,
611 OP_LDURSB,
612 OP_STURH,
613 OP_LDURH,
614 OP_LDURSH,
615 OP_STUR,
616 OP_LDUR,
617 OP_STURV,
618 OP_LDURV,
619 OP_LDURSW,
620 OP_PRFUM,
621
622 OP_LDR_LIT,
623 OP_LDRV_LIT,
624 OP_LDRSW_LIT,
625 OP_PRFM_LIT,
626
627 OP_ADD,
628 OP_B,
629 OP_BL,
630
631 OP_MOVN,
632 OP_MOVZ,
633 OP_MOVK,
634
635 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
636 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
637 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
638
639 OP_MOV_V, /* MOV alias for moving vector register. */
640
641 OP_ASR_IMM,
642 OP_LSR_IMM,
643 OP_LSL_IMM,
644
645 OP_BIC,
646
647 OP_UBFX,
648 OP_BFXIL,
649 OP_SBFX,
650 OP_SBFIZ,
651 OP_BFI,
d685192a 652 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 653 OP_UBFIZ,
654 OP_UXTB,
655 OP_UXTH,
656 OP_UXTW,
657
a06ea964
NC		 658 OP_CINC,
659 OP_CINV,
660 OP_CNEG,
661 OP_CSET,
662 OP_CSETM,
663
664 OP_FCVT,
665 OP_FCVTN,
666 OP_FCVTN2,
667 OP_FCVTL,
668 OP_FCVTL2,
669 OP_FCVTXN_S, /* Scalar version. */
670
671 OP_ROR_IMM,
672
e30181a5
YZ		 673 OP_SXTL,
674 OP_SXTL2,
675 OP_UXTL,
676 OP_UXTL2,
677
c0890d26
RS		 678 OP_MOV_P_P,
679 OP_MOV_Z_P_Z,
680 OP_MOV_Z_V,
681 OP_MOV_Z_Z,
682 OP_MOV_Z_Zi,
683 OP_MOVM_P_P_P,
684 OP_MOVS_P_P,
685 OP_MOVZS_P_P_P,
686 OP_MOVZ_P_P_P,
687 OP_NOTS_P_P_P_Z,
688 OP_NOT_P_P_P_Z,
689
c2c4ff8d
SN		 690 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
691
a06ea964
NC		 692 OP_TOTAL_NUM, /* Pseudo. */
693};
694
1d482394
TC		 695/* Error types. */
696enum err_type
697{
698 ERR_OK,
699 ERR_UND,
700 ERR_UNP,
701 ERR_NYI,
a68f4cd2 702 ERR_VFI,
1d482394
TC		 703 ERR_NR_ENTRIES
704};
705
a06ea964
NC		 706/* Maximum number of operands an instruction can have. */
707#define AARCH64_MAX_OPND_NUM 6
708/* Maximum number of qualifier sequences an instruction can have. */
709#define AARCH64_MAX_QLF_SEQ_NUM 10
710/* Operand qualifier typedef; optimized for the size. */
711typedef unsigned char aarch64_opnd_qualifier_t;
712/* Operand qualifier sequence typedef. */
713typedef aarch64_opnd_qualifier_t \
714 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
715
716/* FIXME: improve the efficiency. */
717static inline bfd_boolean
718empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
719{
720 int i;
721 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
722 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
723 return FALSE;
724 return TRUE;
725}
726
7e84b55d
TC		 727/* Forward declare error reporting type. */
728typedef struct aarch64_operand_error aarch64_operand_error;
729/* Forward declare instruction sequence type. */
730typedef struct aarch64_instr_sequence aarch64_instr_sequence;
731/* Forward declare instruction definition. */
732typedef struct aarch64_inst aarch64_inst;
733
a06ea964
NC		 734/* This structure holds information for a particular opcode. */
735
736struct aarch64_opcode
737{
738 /* The name of the mnemonic. */
739 const char *name;
740
741 /* The opcode itself. Those bits which will be filled in with
742 operands are zeroes. */
743 aarch64_insn opcode;
744
745 /* The opcode mask. This is used by the disassembler. This is a
746 mask containing ones indicating those bits which must match the
747 opcode field, and zeroes indicating those bits which need not
748 match (and are presumably filled in by operands). */
749 aarch64_insn mask;
750
751 /* Instruction class. */
752 enum aarch64_insn_class iclass;
753
754 /* Enumerator identifier. */
755 enum aarch64_op op;
756
757 /* Which architecture variant provides this instruction. */
758 const aarch64_feature_set *avariant;
759
760 /* An array of operand codes. Each code is an index into the
761 operand table. They appear in the order which the operands must
762 appear in assembly code, and are terminated by a zero. */
763 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
764
765 /* A list of operand qualifier code sequence. Each operand qualifier
766 code qualifies the corresponding operand code. Each operand
767 qualifier sequence specifies a valid opcode variant and related
768 constraint on operands. */
769 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
770
771 /* Flags providing information about this instruction */
eae424ae
TC		 772 uint64_t flags;
773
774 /* Extra constraints on the instruction that the verifier checks. */
775 uint32_t constraints;
4bd13cde 776
0c608d6b
RS		 777 /* If nonzero, this operand and operand 0 are both registers and
778 are required to have the same register number. */
779 unsigned char tied_operand;
780
4bd13cde 781 /* If non-NULL, a function to verify that a given instruction is valid. */
755b748f
TC		 782 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
783 bfd_vma, bfd_boolean, aarch64_operand_error *,
784 struct aarch64_instr_sequence *);
a06ea964
NC		 785};
786
787typedef struct aarch64_opcode aarch64_opcode;
788
789/* Table describing all the AArch64 opcodes. */
790extern aarch64_opcode aarch64_opcode_table[];
791
792/* Opcode flags. */
793#define F_ALIAS (1 << 0)
794#define F_HAS_ALIAS (1 << 1)
795/* Disassembly preference priority 1-3 (the larger the higher). If nothing
796 is specified, it is the priority 0 by default, i.e. the lowest priority. */
797#define F_P1 (1 << 2)
798#define F_P2 (2 << 2)
799#define F_P3 (3 << 2)
800/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
801#define F_COND (1 << 4)
802/* Instruction has the field of 'sf'. */
803#define F_SF (1 << 5)
804/* Instruction has the field of 'size:Q'. */
805#define F_SIZEQ (1 << 6)
806/* Floating-point instruction has the field of 'type'. */
807#define F_FPTYPE (1 << 7)
808/* AdvSIMD scalar instruction has the field of 'size'. */
809#define F_SSIZE (1 << 8)
810/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
811#define F_T (1 << 9)
812/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
813#define F_GPRSIZE_IN_Q (1 << 10)
814/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
815#define F_LDS_SIZE (1 << 11)
816/* Optional operand; assume maximum of 1 operand can be optional. */
817#define F_OPD0_OPT (1 << 12)
818#define F_OPD1_OPT (2 << 12)
819#define F_OPD2_OPT (3 << 12)
820#define F_OPD3_OPT (4 << 12)
821#define F_OPD4_OPT (5 << 12)
822/* Default value for the optional operand when omitted from the assembly. */
823#define F_DEFAULT(X) (((X) & 0x1f) << 15)
824/* Instruction that is an alias of another instruction needs to be
825 encoded/decoded by converting it to/from the real form, followed by
826 the encoding/decoding according to the rules of the real opcode.
827 This compares to the direct coding using the alias's information.
828 N.B. this flag requires F_ALIAS to be used together. */
829#define F_CONV (1 << 20)
830/* Use together with F_ALIAS to indicate an alias opcode is a programmer
831 friendly pseudo instruction available only in the assembly code (thus will
832 not show up in the disassembly). */
833#define F_PSEUDO (1 << 21)
834/* Instruction has miscellaneous encoding/decoding rules. */
835#define F_MISC (1 << 22)
836/* Instruction has the field of 'N'; used in conjunction with F_SF. */
837#define F_N (1 << 23)
838/* Opcode dependent field. */
839#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 840/* Instruction has the field of 'sz'. */
841#define F_LSE_SZ (1 << 27)
4989adac
RS		 842/* Require an exact qualifier match, even for NIL qualifiers. */
843#define F_STRICT (1ULL << 28)
f9830ec1
TC		 844/* This system instruction is used to read system registers. */
845#define F_SYS_READ (1ULL << 29)
846/* This system instruction is used to write system registers. */
847#define F_SYS_WRITE (1ULL << 30)
eae424ae
TC		 848/* This instruction has an extra constraint on it that imposes a requirement on
849 subsequent instructions. */
850#define F_SCAN (1ULL << 31)
851/* Next bit is 32. */
852
853/* Instruction constraints. */
854/* This instruction has a predication constraint on the instruction at PC+4. */
855#define C_SCAN_MOVPRFX (1U << 0)
856/* This instruction's operation width is determined by the operand with the
857 largest element size. */
858#define C_MAX_ELEM (1U << 1)
859/* Next bit is 2. */
a06ea964
NC		 860
861static inline bfd_boolean
862alias_opcode_p (const aarch64_opcode *opcode)
863{
864 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
865}
866
867static inline bfd_boolean
868opcode_has_alias (const aarch64_opcode *opcode)
869{
870 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
871}
872
873/* Priority for disassembling preference. */
874static inline int
875opcode_priority (const aarch64_opcode *opcode)
876{
877 return (opcode->flags >> 2) & 0x3;
878}
879
880static inline bfd_boolean
881pseudo_opcode_p (const aarch64_opcode *opcode)
882{
883 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
884}
885
886static inline bfd_boolean
887optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
888{
889 return (((opcode->flags >> 12) & 0x7) == idx + 1)
890 ? TRUE : FALSE;
891}
892
893static inline aarch64_insn
894get_optional_operand_default_value (const aarch64_opcode *opcode)
895{
896 return (opcode->flags >> 15) & 0x1f;
897}
898
899static inline unsigned int
900get_opcode_dependent_value (const aarch64_opcode *opcode)
901{
902 return (opcode->flags >> 24) & 0x7;
903}
904
905static inline bfd_boolean
906opcode_has_special_coder (const aarch64_opcode *opcode)
907{
ee804238 908 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 909 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
910 : FALSE;
911}
912\f
913struct aarch64_name_value_pair
914{
915 const char * name;
916 aarch64_insn value;
917};
918
919extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964
NC		 920extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
921extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 922extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 923
49eec193
YZ		 924typedef struct
925{
926 const char * name;
927 aarch64_insn value;
928 uint32_t flags;
929} aarch64_sys_reg;
930
931extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 932extern const aarch64_sys_reg aarch64_pstatefields [];
49eec193 933extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
f21cce2c
MW		 934extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
935 const aarch64_sys_reg *);
936extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
937 const aarch64_sys_reg *);
49eec193 938
a06ea964
NC		 939typedef struct
940{
875880c6 941 const char *name;
a06ea964 942 uint32_t value;
ea2deeec 943 uint32_t flags ;
a06ea964
NC		 944} aarch64_sys_ins_reg;
945
ea2deeec 946extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6
MW		 947extern bfd_boolean
948aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
949 const aarch64_sys_ins_reg *);
ea2deeec 950
a06ea964
NC		 951extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
952extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
953extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
954extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
2ac435d4 955extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
a06ea964
NC		 956
957/* Shift/extending operator kinds.
958 N.B. order is important; keep aarch64_operand_modifiers synced. */
959enum aarch64_modifier_kind
960{
961 AARCH64_MOD_NONE,
962 AARCH64_MOD_MSL,
963 AARCH64_MOD_ROR,
964 AARCH64_MOD_ASR,
965 AARCH64_MOD_LSR,
966 AARCH64_MOD_LSL,
967 AARCH64_MOD_UXTB,
968 AARCH64_MOD_UXTH,
969 AARCH64_MOD_UXTW,
970 AARCH64_MOD_UXTX,
971 AARCH64_MOD_SXTB,
972 AARCH64_MOD_SXTH,
973 AARCH64_MOD_SXTW,
974 AARCH64_MOD_SXTX,
2442d846 975 AARCH64_MOD_MUL,
98907a70 976 AARCH64_MOD_MUL_VL,
a06ea964
NC		 977};
978
979bfd_boolean
980aarch64_extend_operator_p (enum aarch64_modifier_kind);
981
982enum aarch64_modifier_kind
983aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
984/* Condition. */
985
986typedef struct
987{
988 /* A list of names with the first one as the disassembly preference;
989 terminated by NULL if fewer than 3. */
bb7eff52 990 const char *names[4];
a06ea964
NC		 991 aarch64_insn value;
992} aarch64_cond;
993
994extern const aarch64_cond aarch64_conds[16];
995
996const aarch64_cond* get_cond_from_value (aarch64_insn value);
997const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
998\f
999/* Structure representing an operand. */
1000
1001struct aarch64_opnd_info
1002{
1003 enum aarch64_opnd type;
1004 aarch64_opnd_qualifier_t qualifier;
1005 int idx;
1006
1007 union
1008 {
1009 struct
1010 {
1011 unsigned regno;
1012 } reg;
1013 struct
1014 {
dab26bf4
RS		 1015 unsigned int regno;
1016 int64_t index;
a06ea964
NC		 1017 } reglane;
1018 /* e.g. LVn. */
1019 struct
1020 {
1021 unsigned first_regno : 5;
1022 unsigned num_regs : 3;
1023 /* 1 if it is a list of reg element. */
1024 unsigned has_index : 1;
1025 /* Lane index; valid only when has_index is 1. */
dab26bf4 1026 int64_t index;
a06ea964
NC		 1027 } reglist;
1028 /* e.g. immediate or pc relative address offset. */
1029 struct
1030 {
1031 int64_t value;
1032 unsigned is_fp : 1;
1033 } imm;
1034 /* e.g. address in STR (register offset). */
1035 struct
1036 {
1037 unsigned base_regno;
1038 struct
1039 {
1040 union
1041 {
1042 int imm;
1043 unsigned regno;
1044 };
1045 unsigned is_reg;
1046 } offset;
1047 unsigned pcrel : 1; /* PC-relative. */
1048 unsigned writeback : 1;
1049 unsigned preind : 1; /* Pre-indexed. */
1050 unsigned postind : 1; /* Post-indexed. */
1051 } addr;
561a72d4
TC		 1052
1053 struct
1054 {
1055 /* The encoding of the system register. */
1056 aarch64_insn value;
1057
1058 /* The system register flags. */
1059 uint32_t flags;
1060 } sysreg;
1061
a06ea964 1062 const aarch64_cond *cond;
a06ea964
NC		 1063 /* The encoding of the PSTATE field. */
1064 aarch64_insn pstatefield;
1065 const aarch64_sys_ins_reg *sysins_op;
1066 const struct aarch64_name_value_pair *barrier;
9ed608f9 1067 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 1068 const struct aarch64_name_value_pair *prfop;
1069 };
1070
1071 /* Operand shifter; in use when the operand is a register offset address,
1072 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1073 struct
1074 {
1075 enum aarch64_modifier_kind kind;
a06ea964
NC		 1076 unsigned operator_present: 1; /* Only valid during encoding. */
1077 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1078 unsigned amount_present: 1;
2442d846 1079 int64_t amount;
a06ea964
NC		 1080 } shifter;
1081
1082 unsigned skip:1; /* Operand is not completed if there is a fixup needed
1083 to be done on it. In some (but not all) of these
1084 cases, we need to tell libopcodes to skip the
1085 constraint checking and the encoding for this
1086 operand, so that the libopcodes can pick up the
1087 right opcode before the operand is fixed-up. This
1088 flag should only be used during the
1089 assembling/encoding. */
1090 unsigned present:1; /* Whether this operand is present in the assembly
1091 line; not used during the disassembly. */
1092};
1093
1094typedef struct aarch64_opnd_info aarch64_opnd_info;
1095
1096/* Structure representing an instruction.
1097
1098 It is used during both the assembling and disassembling. The assembler
1099 fills an aarch64_inst after a successful parsing and then passes it to the
1100 encoding routine to do the encoding. During the disassembling, the
1101 disassembler calls the decoding routine to decode a binary instruction; on a
1102 successful return, such a structure will be filled with information of the
1103 instruction; then the disassembler uses the information to print out the
1104 instruction. */
1105
1106struct aarch64_inst
1107{
1108 /* The value of the binary instruction. */
1109 aarch64_insn value;
1110
1111 /* Corresponding opcode entry. */
1112 const aarch64_opcode *opcode;
1113
1114 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1115 const aarch64_cond *cond;
1116
1117 /* Operands information. */
1118 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1119};
1120
ff605452
SD		 1121/* Defining the HINT #imm values for the aarch64_hint_options. */
1122#define HINT_OPD_CSYNC 0x11
1123#define HINT_OPD_C 0x22
1124#define HINT_OPD_J 0x24
1125#define HINT_OPD_JC 0x26
1126#define HINT_OPD_NULL 0x00
1127
a06ea964
NC		 1128\f
1129/* Diagnosis related declaration and interface. */
1130
1131/* Operand error kind enumerators.
1132
1133 AARCH64_OPDE_RECOVERABLE
1134 Less severe error found during the parsing, very possibly because that
1135 GAS has picked up a wrong instruction template for the parsing.
1136
1137 AARCH64_OPDE_SYNTAX_ERROR
1138 General syntax error; it can be either a user error, or simply because
1139 that GAS is trying a wrong instruction template.
1140
1141 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1142 Definitely a user syntax error.
1143
1144 AARCH64_OPDE_INVALID_VARIANT
1145 No syntax error, but the operands are not a valid combination, e.g.
1146 FMOV D0,S0
1147
0c608d6b
RS		 1148 AARCH64_OPDE_UNTIED_OPERAND
1149 The asm failed to use the same register for a destination operand
1150 and a tied source operand.
1151
a06ea964
NC		 1152 AARCH64_OPDE_OUT_OF_RANGE
1153 Error about some immediate value out of a valid range.
1154
1155 AARCH64_OPDE_UNALIGNED
1156 Error about some immediate value not properly aligned (i.e. not being a
1157 multiple times of a certain value).
1158
1159 AARCH64_OPDE_REG_LIST
1160 Error about the register list operand having unexpected number of
1161 registers.
1162
1163 AARCH64_OPDE_OTHER_ERROR
1164 Error of the highest severity and used for any severe issue that does not
1165 fall into any of the above categories.
1166
1167 The enumerators are only interesting to GAS. They are declared here (in
1168 libopcodes) because that some errors are detected (and then notified to GAS)
1169 by libopcodes (rather than by GAS solely).
1170
1171 The first three errors are only deteced by GAS while the
1172 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1173 only libopcodes has the information about the valid variants of each
1174 instruction.
1175
1176 The enumerators have an increasing severity. This is helpful when there are
1177 multiple instruction templates available for a given mnemonic name (e.g.
1178 FMOV); this mechanism will help choose the most suitable template from which
1179 the generated diagnostics can most closely describe the issues, if any. */
1180
1181enum aarch64_operand_error_kind
1182{
1183 AARCH64_OPDE_NIL,
1184 AARCH64_OPDE_RECOVERABLE,
1185 AARCH64_OPDE_SYNTAX_ERROR,
1186 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1187 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1188 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1189 AARCH64_OPDE_OUT_OF_RANGE,
1190 AARCH64_OPDE_UNALIGNED,
1191 AARCH64_OPDE_REG_LIST,
1192 AARCH64_OPDE_OTHER_ERROR
1193};
1194
1195/* N.B. GAS assumes that this structure work well with shallow copy. */
1196struct aarch64_operand_error
1197{
1198 enum aarch64_operand_error_kind kind;
1199 int index;
1200 const char *error;
1201 int data[3]; /* Some data for extra information. */
7d02540a 1202 bfd_boolean non_fatal;
a06ea964
NC		 1203};
1204
7e84b55d
TC		 1205/* AArch64 sequence structure used to track instructions with F_SCAN
1206 dependencies for both assembler and disassembler. */
1207struct aarch64_instr_sequence
1208{
1209 /* The instruction that caused this sequence to be opened. */
1210 aarch64_inst *instr;
1211 /* The number of instructions the above instruction allows to be kept in the
1212 sequence before an automatic close is done. */
1213 int num_insns;
1214 /* The instructions currently added to the sequence. */
1215 aarch64_inst **current_insns;
1216 /* The number of instructions already in the sequence. */
1217 int next_insn;
1218};
a06ea964
NC		 1219
1220/* Encoding entrypoint. */
1221
1222extern int
1223aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1224 aarch64_insn *, aarch64_opnd_qualifier_t *,
7e84b55d 1225 aarch64_operand_error *, aarch64_instr_sequence *);
a06ea964
NC		 1226
1227extern const aarch64_opcode *
1228aarch64_replace_opcode (struct aarch64_inst *,
1229 const aarch64_opcode *);
1230
1231/* Given the opcode enumerator OP, return the pointer to the corresponding
1232 opcode entry. */
1233
1234extern const aarch64_opcode *
1235aarch64_get_opcode (enum aarch64_op);
1236
1237/* Generate the string representation of an operand. */
1238extern void
1239aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a
TC		 1240 const aarch64_opnd_info *, int, int *, bfd_vma *,
1241 char **);
a06ea964
NC		 1242
1243/* Miscellaneous interface. */
1244
1245extern int
1246aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1247
1248extern aarch64_opnd_qualifier_t
1249aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1250 const aarch64_opnd_qualifier_t, int);
1251
a68f4cd2
TC		 1252extern bfd_boolean
1253aarch64_is_destructive_by_operands (const aarch64_opcode *);
1254
a06ea964
NC		 1255extern int
1256aarch64_num_of_operands (const aarch64_opcode *);
1257
1258extern int
1259aarch64_stack_pointer_p (const aarch64_opnd_info *);
1260
e141d84e
YQ		 1261extern int
1262aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1263
1d482394 1264extern enum err_type
561a72d4 1265aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
a68f4cd2
TC		 1266 aarch64_operand_error *);
1267
1268extern void
1269init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
36f4aab1 1270
a06ea964
NC		 1271/* Given an operand qualifier, return the expected data element size
1272 of a qualified operand. */
1273extern unsigned char
1274aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1275
1276extern enum aarch64_operand_class
1277aarch64_get_operand_class (enum aarch64_opnd);
1278
1279extern const char *
1280aarch64_get_operand_name (enum aarch64_opnd);
1281
1282extern const char *
1283aarch64_get_operand_desc (enum aarch64_opnd);
1284
e950b345
RS		 1285extern bfd_boolean
1286aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1287
a06ea964
NC		 1288#ifdef DEBUG_AARCH64
1289extern int debug_dump;
1290
1291extern void
1292aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1293
1294#define DEBUG_TRACE(M, ...) \
1295 { \
1296 if (debug_dump) \
1297 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1298 }
1299
1300#define DEBUG_TRACE_IF(C, M, ...) \
1301 { \
1302 if (debug_dump && (C)) \
1303 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1304 }
1305#else /* !DEBUG_AARCH64 */
1306#define DEBUG_TRACE(M, ...) ;
1307#define DEBUG_TRACE_IF(C, M, ...) ;
1308#endif /* DEBUG_AARCH64 */
1309
245d2e3f
RS		 1310extern const char *const aarch64_sve_pattern_array[32];
1311extern const char *const aarch64_sve_prfop_array[16];
1312
d3e12b29
YQ		 1313#ifdef __cplusplus
1314}
1315#endif
1316
a06ea964 1317#endif /* OPCODE_AARCH64_H */
GDB Binutils - Deliverables
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