Commit | Line | Data |
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252b5132 | 1 | /* Opcode table for the ARC. |
4f1d9bd8 | 2 | Copyright 1994, 1995, 1997, 2001 Free Software Foundation, Inc. |
252b5132 RH |
3 | Contributed by Doug Evans (dje@cygnus.com). |
4 | ||
0d2bcfaf NC |
5 | This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and |
6 | the GNU Binutils. | |
252b5132 | 7 | |
0d2bcfaf NC |
8 | GAS/GDB is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
252b5132 | 12 | |
0d2bcfaf NC |
13 | GAS/GDB is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS or GDB; see the file COPYING. If not, write to | |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
252b5132 | 21 | |
252b5132 RH |
22 | |
23 | /* List of the various cpu types. | |
24 | The tables currently use bit masks to say whether the instruction or | |
25 | whatever is supported by a particular cpu. This lets us have one entry | |
26 | apply to several cpus. | |
27 | ||
0d2bcfaf NC |
28 | The `base' cpu must be 0. The cpu type is treated independently of |
29 | endianness. The complete `mach' number includes endianness. | |
252b5132 | 30 | These values are internal to opcodes/bfd/binutils/gas. */ |
0d2bcfaf NC |
31 | #define ARC_MACH_5 0 |
32 | #define ARC_MACH_6 1 | |
33 | #define ARC_MACH_7 2 | |
34 | #define ARC_MACH_8 4 | |
35 | ||
252b5132 | 36 | /* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ |
0d2bcfaf | 37 | #define ARC_MACH_BIG 16 |
252b5132 RH |
38 | |
39 | /* Mask of number of bits necessary to record cpu type. */ | |
0d2bcfaf NC |
40 | #define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1) |
41 | ||
252b5132 | 42 | /* Mask of number of bits necessary to record cpu type + endianness. */ |
0d2bcfaf | 43 | #define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1) |
252b5132 RH |
44 | |
45 | /* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ | |
0d2bcfaf | 46 | |
252b5132 RH |
47 | typedef unsigned int arc_insn; |
48 | ||
49 | struct arc_opcode { | |
0d2bcfaf NC |
50 | char *syntax; /* syntax of insn */ |
51 | unsigned long mask, value; /* recognize insn if (op&mask) == value */ | |
52 | int flags; /* various flag bits */ | |
252b5132 RH |
53 | |
54 | /* Values for `flags'. */ | |
55 | ||
56 | /* Return CPU number, given flag bits. */ | |
57 | #define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) | |
0d2bcfaf | 58 | |
252b5132 RH |
59 | /* Return MACH number, given flag bits. */ |
60 | #define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) | |
0d2bcfaf | 61 | |
252b5132 | 62 | /* First opcode flag bit available after machine mask. */ |
0d2bcfaf NC |
63 | #define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1) |
64 | ||
252b5132 RH |
65 | /* This insn is a conditional branch. */ |
66 | #define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) | |
0d2bcfaf NC |
67 | #define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1) |
68 | #define SYNTAX_LENGTH (SYNTAX_3OP ) | |
69 | #define SYNTAX_2OP (SYNTAX_3OP << 1) | |
70 | #define OP1_MUST_BE_IMM (SYNTAX_2OP << 1) | |
71 | #define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) | |
72 | #define SYNTAX_VALID (OP1_IMM_IMPLIED << 1) | |
73 | ||
74 | #define I(x) (((x) & 31) << 27) | |
75 | #define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) | |
76 | #define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) | |
77 | #define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) | |
78 | #define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ | |
79 | ||
80 | /* These values are used to optimize assembly and disassembly. Each insn | |
81 | is on a list of related insns (same first letter for assembly, same | |
82 | insn code for disassembly). */ | |
83 | ||
84 | struct arc_opcode *next_asm; /* Next instr to try during assembly. */ | |
85 | struct arc_opcode *next_dis; /* Next instr to try during disassembly. */ | |
86 | ||
87 | /* Macros to create the hash values for the lists. */ | |
252b5132 RH |
88 | #define ARC_HASH_OPCODE(string) \ |
89 | ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) | |
90 | #define ARC_HASH_ICODE(insn) \ | |
91 | ((unsigned int) (insn) >> 27) | |
92 | ||
0d2bcfaf NC |
93 | /* Macros to access `next_asm', `next_dis' so users needn't care about the |
94 | underlying mechanism. */ | |
252b5132 RH |
95 | #define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) |
96 | #define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) | |
97 | }; | |
98 | ||
0d2bcfaf NC |
99 | /* this is an "insert at front" linked list per Metaware spec |
100 | that new definitions override older ones. */ | |
84037f8c | 101 | extern struct arc_opcode *arc_ext_opcodes; |
0d2bcfaf | 102 | |
252b5132 | 103 | struct arc_operand_value { |
0d2bcfaf NC |
104 | char *name; /* eg: "eq" */ |
105 | short value; /* eg: 1 */ | |
106 | unsigned char type; /* index into `arc_operands' */ | |
107 | unsigned char flags; /* various flag bits */ | |
252b5132 RH |
108 | |
109 | /* Values for `flags'. */ | |
110 | ||
111 | /* Return CPU number, given flag bits. */ | |
112 | #define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) | |
113 | /* Return MACH number, given flag bits. */ | |
114 | #define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) | |
115 | }; | |
116 | ||
0d2bcfaf NC |
117 | struct arc_ext_operand_value { |
118 | struct arc_ext_operand_value *next; | |
119 | struct arc_operand_value operand; | |
84037f8c KD |
120 | }; |
121 | ||
122 | extern struct arc_ext_operand_value *arc_ext_operands; | |
0d2bcfaf | 123 | |
252b5132 | 124 | struct arc_operand { |
0d2bcfaf | 125 | /* One of the insn format chars. */ |
252b5132 RH |
126 | unsigned char fmt; |
127 | ||
0d2bcfaf | 128 | /* The number of bits in the operand (may be unused for a modifier). */ |
252b5132 RH |
129 | unsigned char bits; |
130 | ||
0d2bcfaf NC |
131 | /* How far the operand is left shifted in the instruction, or |
132 | the modifier's flag bit (may be unused for a modifier. */ | |
252b5132 RH |
133 | unsigned char shift; |
134 | ||
0d2bcfaf | 135 | /* Various flag bits. */ |
252b5132 RH |
136 | int flags; |
137 | ||
138 | /* Values for `flags'. */ | |
139 | ||
140 | /* This operand is a suffix to the opcode. */ | |
141 | #define ARC_OPERAND_SUFFIX 1 | |
142 | ||
143 | /* This operand is a relative branch displacement. The disassembler | |
144 | prints these symbolically if possible. */ | |
145 | #define ARC_OPERAND_RELATIVE_BRANCH 2 | |
146 | ||
147 | /* This operand is an absolute branch address. The disassembler | |
148 | prints these symbolically if possible. */ | |
149 | #define ARC_OPERAND_ABSOLUTE_BRANCH 4 | |
150 | ||
151 | /* This operand is an address. The disassembler | |
152 | prints these symbolically if possible. */ | |
153 | #define ARC_OPERAND_ADDRESS 8 | |
154 | ||
155 | /* This operand is a long immediate value. */ | |
156 | #define ARC_OPERAND_LIMM 0x10 | |
157 | ||
158 | /* This operand takes signed values. */ | |
159 | #define ARC_OPERAND_SIGNED 0x20 | |
160 | ||
161 | /* This operand takes signed values, but also accepts a full positive | |
162 | range of values. That is, if bits is 16, it takes any value from | |
163 | -0x8000 to 0xffff. */ | |
164 | #define ARC_OPERAND_SIGNOPT 0x40 | |
165 | ||
166 | /* This operand should be regarded as a negative number for the | |
167 | purposes of overflow checking (i.e., the normal most negative | |
168 | number is disallowed and one more than the normal most positive | |
169 | number is allowed). This flag will only be set for a signed | |
170 | operand. */ | |
171 | #define ARC_OPERAND_NEGATIVE 0x80 | |
172 | ||
173 | /* This operand doesn't really exist. The program uses these operands | |
174 | in special ways. */ | |
175 | #define ARC_OPERAND_FAKE 0x100 | |
176 | ||
0d2bcfaf NC |
177 | /* separate flags operand for j and jl instructions */ |
178 | #define ARC_OPERAND_JUMPFLAGS 0x200 | |
179 | ||
180 | /* allow warnings and errors to be issued after call to insert_xxxxxx */ | |
181 | #define ARC_OPERAND_WARN 0x400 | |
182 | #define ARC_OPERAND_ERROR 0x800 | |
183 | ||
184 | /* this is a load operand */ | |
185 | #define ARC_OPERAND_LOAD 0x8000 | |
186 | ||
187 | /* this is a store operand */ | |
188 | #define ARC_OPERAND_STORE 0x10000 | |
189 | ||
252b5132 RH |
190 | /* Modifier values. */ |
191 | /* A dot is required before a suffix. Eg: .le */ | |
192 | #define ARC_MOD_DOT 0x1000 | |
193 | ||
194 | /* A normal register is allowed (not used, but here for completeness). */ | |
195 | #define ARC_MOD_REG 0x2000 | |
196 | ||
197 | /* An auxiliary register name is expected. */ | |
198 | #define ARC_MOD_AUXREG 0x4000 | |
199 | ||
200 | /* Sum of all ARC_MOD_XXX bits. */ | |
201 | #define ARC_MOD_BITS 0x7000 | |
202 | ||
203 | /* Non-zero if the operand type is really a modifier. */ | |
204 | #define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) | |
205 | ||
0d2bcfaf NC |
206 | /* enforce read/write only register restrictions */ |
207 | #define ARC_REGISTER_READONLY 0x01 | |
208 | #define ARC_REGISTER_WRITEONLY 0x02 | |
209 | #define ARC_REGISTER_NOSHORT_CUT 0x04 | |
210 | ||
211 | /* Insertion function. This is used by the assembler. To insert an | |
212 | operand value into an instruction, check this field. | |
213 | ||
214 | If it is NULL, execute | |
215 | i |= (p & ((1 << o->bits) - 1)) << o->shift; | |
216 | (I is the instruction which we are filling in, O is a pointer to | |
217 | this structure, and OP is the opcode value; this assumes twos | |
218 | complement arithmetic). | |
219 | ||
220 | If this field is not NULL, then simply call it with the | |
221 | instruction and the operand value. It will return the new value | |
222 | of the instruction. If the ERRMSG argument is not NULL, then if | |
223 | the operand value is illegal, *ERRMSG will be set to a warning | |
224 | string (the operand will be inserted in any case). If the | |
225 | operand value is legal, *ERRMSG will be unchanged. | |
226 | ||
227 | REG is non-NULL when inserting a register value. */ | |
252b5132 RH |
228 | |
229 | arc_insn (*insert) PARAMS ((arc_insn insn, | |
230 | const struct arc_operand *operand, int mods, | |
231 | const struct arc_operand_value *reg, long value, | |
232 | const char **errmsg)); | |
233 | ||
0d2bcfaf NC |
234 | /* Extraction function. This is used by the disassembler. To |
235 | extract this operand type from an instruction, check this field. | |
236 | ||
237 | If it is NULL, compute | |
238 | op = ((i) >> o->shift) & ((1 << o->bits) - 1); | |
239 | if ((o->flags & ARC_OPERAND_SIGNED) != 0 | |
240 | && (op & (1 << (o->bits - 1))) != 0) | |
241 | op -= 1 << o->bits; | |
242 | (I is the instruction, O is a pointer to this structure, and OP | |
243 | is the result; this assumes twos complement arithmetic). | |
244 | ||
245 | If this field is not NULL, then simply call it with the | |
246 | instruction value. It will return the value of the operand. If | |
247 | the INVALID argument is not NULL, *INVALID will be set to | |
248 | non-zero if this operand type can not actually be extracted from | |
249 | this operand (i.e., the instruction does not match). If the | |
250 | operand is valid, *INVALID will not be changed. | |
251 | ||
252 | INSN is a pointer to an array of two `arc_insn's. The first element is | |
253 | the insn, the second is the limm if present. | |
254 | ||
255 | Operands that have a printable form like registers and suffixes have | |
256 | their struct arc_operand_value pointer stored in OPVAL. */ | |
252b5132 RH |
257 | |
258 | long (*extract) PARAMS ((arc_insn *insn, | |
259 | const struct arc_operand *operand, | |
260 | int mods, const struct arc_operand_value **opval, | |
261 | int *invalid)); | |
262 | }; | |
263 | ||
0d2bcfaf NC |
264 | /* Bits that say what version of cpu we have. These should be passed to |
265 | arc_init_opcode_tables. At present, all there is is the cpu type. */ | |
252b5132 RH |
266 | |
267 | /* CPU number, given value passed to `arc_init_opcode_tables'. */ | |
268 | #define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) | |
269 | /* MACH number, given value passed to `arc_init_opcode_tables'. */ | |
270 | #define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) | |
271 | ||
272 | /* Special register values: */ | |
273 | #define ARC_REG_SHIMM_UPDATE 61 | |
274 | #define ARC_REG_SHIMM 63 | |
275 | #define ARC_REG_LIMM 62 | |
276 | ||
277 | /* Non-zero if REG is a constant marker. */ | |
278 | #define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) | |
279 | ||
280 | /* Positions and masks of various fields: */ | |
281 | #define ARC_SHIFT_REGA 21 | |
282 | #define ARC_SHIFT_REGB 15 | |
283 | #define ARC_SHIFT_REGC 9 | |
284 | #define ARC_MASK_REG 63 | |
285 | ||
286 | /* Delay slot types. */ | |
0d2bcfaf NC |
287 | #define ARC_DELAY_NONE 0 /* no delay slot */ |
288 | #define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ | |
289 | #define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ | |
252b5132 RH |
290 | |
291 | /* Non-zero if X will fit in a signed 9 bit field. */ | |
292 | #define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) | |
293 | ||
294 | extern const struct arc_operand arc_operands[]; | |
295 | extern const int arc_operand_count; | |
0d2bcfaf | 296 | extern struct arc_opcode arc_opcodes[]; |
252b5132 RH |
297 | extern const int arc_opcodes_count; |
298 | extern const struct arc_operand_value arc_suffixes[]; | |
299 | extern const int arc_suffixes_count; | |
300 | extern const struct arc_operand_value arc_reg_names[]; | |
301 | extern const int arc_reg_names_count; | |
302 | extern unsigned char arc_operand_map[]; | |
303 | ||
304 | /* Utility fns in arc-opc.c. */ | |
305 | int arc_get_opcode_mach PARAMS ((int, int)); | |
0d2bcfaf | 306 | |
252b5132 RH |
307 | /* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ |
308 | void arc_opcode_init_tables PARAMS ((int)); | |
309 | void arc_opcode_init_insert PARAMS ((void)); | |
310 | void arc_opcode_init_extract PARAMS ((void)); | |
311 | const struct arc_opcode *arc_opcode_lookup_asm PARAMS ((const char *)); | |
312 | const struct arc_opcode *arc_opcode_lookup_dis PARAMS ((unsigned int)); | |
313 | int arc_opcode_limm_p PARAMS ((long *)); | |
0d2bcfaf NC |
314 | const struct arc_operand_value *arc_opcode_lookup_suffix |
315 | PARAMS ((const struct arc_operand *type, int value)); | |
252b5132 RH |
316 | int arc_opcode_supported PARAMS ((const struct arc_opcode *)); |
317 | int arc_opval_supported PARAMS ((const struct arc_operand_value *)); | |
d83c6548 AJ |
318 | int arc_limm_fixup_adjust PARAMS ((arc_insn)); |
319 | int arc_insn_is_j PARAMS ((arc_insn)); | |
320 | int arc_insn_not_jl PARAMS ((arc_insn)); | |
321 | int arc_operand_type PARAMS ((int)); | |
322 | struct arc_operand_value *get_ext_suffix PARAMS ((char *)); | |
323 | int arc_get_noshortcut_flag PARAMS ((void)); |