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252b5132 RH |
1 | /* Opcode table for the ARC. |
2 | Copyright 1994, 1995, 1997 Free Software Foundation, Inc. | |
3 | Contributed by Doug Evans (dje@cygnus.com). | |
4 | ||
5 | This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and | |
6 | the GNU Binutils. | |
7 | ||
8 | GAS/GDB is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GAS/GDB is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS or GDB; see the file COPYING. If not, write to | |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | /* List of the various cpu types. | |
24 | The tables currently use bit masks to say whether the instruction or | |
25 | whatever is supported by a particular cpu. This lets us have one entry | |
26 | apply to several cpus. | |
27 | ||
28 | This duplicates bfd_mach_arc_xxx. For now I wish to isolate this from bfd | |
29 | and bfd from this. Also note that these numbers are bit values as we want | |
30 | to allow for things available on more than one ARC (but not necessarily all | |
31 | ARCs). */ | |
32 | ||
33 | /* The `base' cpu must be 0 (table entries are omitted for the base cpu). | |
34 | The cpu type is treated independently of endianness. | |
35 | The complete `mach' number includes endianness. | |
36 | These values are internal to opcodes/bfd/binutils/gas. */ | |
37 | #define ARC_MACH_BASE 0 | |
38 | #define ARC_MACH_UNUSED1 1 | |
39 | #define ARC_MACH_UNUSED2 2 | |
40 | #define ARC_MACH_UNUSED4 4 | |
41 | /* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ | |
42 | #define ARC_MACH_BIG 8 | |
43 | ||
44 | /* Mask of number of bits necessary to record cpu type. */ | |
45 | #define ARC_MACH_CPU_MASK 7 | |
46 | /* Mask of number of bits necessary to record cpu type + endianness. */ | |
47 | #define ARC_MACH_MASK 15 | |
48 | ||
49 | /* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ | |
50 | typedef unsigned int arc_insn; | |
51 | ||
52 | struct arc_opcode { | |
53 | char *syntax; /* syntax of insn */ | |
54 | unsigned long mask, value; /* recognize insn if (op&mask)==value */ | |
55 | int flags; /* various flag bits */ | |
56 | ||
57 | /* Values for `flags'. */ | |
58 | ||
59 | /* Return CPU number, given flag bits. */ | |
60 | #define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) | |
61 | /* Return MACH number, given flag bits. */ | |
62 | #define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) | |
63 | /* First opcode flag bit available after machine mask. */ | |
64 | #define ARC_OPCODE_FLAG_START ((ARC_MACH_MASK + 1) << 0) | |
65 | /* This insn is a conditional branch. */ | |
66 | #define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) | |
67 | ||
68 | /* These values are used to optimize assembly and disassembly. Each insn is | |
69 | on a list of related insns (same first letter for assembly, same insn code | |
70 | for disassembly). */ | |
71 | struct arc_opcode *next_asm; /* Next instruction to try during assembly. */ | |
72 | struct arc_opcode *next_dis; /* Next instruction to try during disassembly. */ | |
73 | ||
74 | /* Macros to create the hash values for the lists. */ | |
75 | #define ARC_HASH_OPCODE(string) \ | |
76 | ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) | |
77 | #define ARC_HASH_ICODE(insn) \ | |
78 | ((unsigned int) (insn) >> 27) | |
79 | ||
80 | /* Macros to access `next_asm', `next_dis' so users needn't care about the | |
81 | underlying mechanism. */ | |
82 | #define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) | |
83 | #define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) | |
84 | }; | |
85 | ||
86 | struct arc_operand_value { | |
87 | char *name; /* eg: "eq" */ | |
88 | short value; /* eg: 1 */ | |
89 | unsigned char type; /* index into `arc_operands' */ | |
90 | unsigned char flags; /* various flag bits */ | |
91 | ||
92 | /* Values for `flags'. */ | |
93 | ||
94 | /* Return CPU number, given flag bits. */ | |
95 | #define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) | |
96 | /* Return MACH number, given flag bits. */ | |
97 | #define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) | |
98 | }; | |
99 | ||
100 | struct arc_operand { | |
101 | /* One of the insn format chars. */ | |
102 | unsigned char fmt; | |
103 | ||
104 | /* The number of bits in the operand (may be unused for a modifier). */ | |
105 | unsigned char bits; | |
106 | ||
107 | /* How far the operand is left shifted in the instruction, or | |
108 | the modifier's flag bit (may be unused for a modifier. */ | |
109 | unsigned char shift; | |
110 | ||
111 | /* Various flag bits. */ | |
112 | int flags; | |
113 | ||
114 | /* Values for `flags'. */ | |
115 | ||
116 | /* This operand is a suffix to the opcode. */ | |
117 | #define ARC_OPERAND_SUFFIX 1 | |
118 | ||
119 | /* This operand is a relative branch displacement. The disassembler | |
120 | prints these symbolically if possible. */ | |
121 | #define ARC_OPERAND_RELATIVE_BRANCH 2 | |
122 | ||
123 | /* This operand is an absolute branch address. The disassembler | |
124 | prints these symbolically if possible. */ | |
125 | #define ARC_OPERAND_ABSOLUTE_BRANCH 4 | |
126 | ||
127 | /* This operand is an address. The disassembler | |
128 | prints these symbolically if possible. */ | |
129 | #define ARC_OPERAND_ADDRESS 8 | |
130 | ||
131 | /* This operand is a long immediate value. */ | |
132 | #define ARC_OPERAND_LIMM 0x10 | |
133 | ||
134 | /* This operand takes signed values. */ | |
135 | #define ARC_OPERAND_SIGNED 0x20 | |
136 | ||
137 | /* This operand takes signed values, but also accepts a full positive | |
138 | range of values. That is, if bits is 16, it takes any value from | |
139 | -0x8000 to 0xffff. */ | |
140 | #define ARC_OPERAND_SIGNOPT 0x40 | |
141 | ||
142 | /* This operand should be regarded as a negative number for the | |
143 | purposes of overflow checking (i.e., the normal most negative | |
144 | number is disallowed and one more than the normal most positive | |
145 | number is allowed). This flag will only be set for a signed | |
146 | operand. */ | |
147 | #define ARC_OPERAND_NEGATIVE 0x80 | |
148 | ||
149 | /* This operand doesn't really exist. The program uses these operands | |
150 | in special ways. */ | |
151 | #define ARC_OPERAND_FAKE 0x100 | |
152 | ||
153 | /* Modifier values. */ | |
154 | /* A dot is required before a suffix. Eg: .le */ | |
155 | #define ARC_MOD_DOT 0x1000 | |
156 | ||
157 | /* A normal register is allowed (not used, but here for completeness). */ | |
158 | #define ARC_MOD_REG 0x2000 | |
159 | ||
160 | /* An auxiliary register name is expected. */ | |
161 | #define ARC_MOD_AUXREG 0x4000 | |
162 | ||
163 | /* Sum of all ARC_MOD_XXX bits. */ | |
164 | #define ARC_MOD_BITS 0x7000 | |
165 | ||
166 | /* Non-zero if the operand type is really a modifier. */ | |
167 | #define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) | |
168 | ||
169 | /* Insertion function. This is used by the assembler. To insert an | |
170 | operand value into an instruction, check this field. | |
171 | ||
172 | If it is NULL, execute | |
173 | i |= (p & ((1 << o->bits) - 1)) << o->shift; | |
174 | (I is the instruction which we are filling in, O is a pointer to | |
175 | this structure, and OP is the opcode value; this assumes twos | |
176 | complement arithmetic). | |
177 | ||
178 | If this field is not NULL, then simply call it with the | |
179 | instruction and the operand value. It will return the new value | |
180 | of the instruction. If the ERRMSG argument is not NULL, then if | |
181 | the operand value is illegal, *ERRMSG will be set to a warning | |
182 | string (the operand will be inserted in any case). If the | |
183 | operand value is legal, *ERRMSG will be unchanged. | |
184 | ||
185 | REG is non-NULL when inserting a register value. */ | |
186 | ||
187 | arc_insn (*insert) PARAMS ((arc_insn insn, | |
188 | const struct arc_operand *operand, int mods, | |
189 | const struct arc_operand_value *reg, long value, | |
190 | const char **errmsg)); | |
191 | ||
192 | /* Extraction function. This is used by the disassembler. To | |
193 | extract this operand type from an instruction, check this field. | |
194 | ||
195 | If it is NULL, compute | |
196 | op = ((i) >> o->shift) & ((1 << o->bits) - 1); | |
197 | if ((o->flags & ARC_OPERAND_SIGNED) != 0 | |
198 | && (op & (1 << (o->bits - 1))) != 0) | |
199 | op -= 1 << o->bits; | |
200 | (I is the instruction, O is a pointer to this structure, and OP | |
201 | is the result; this assumes twos complement arithmetic). | |
202 | ||
203 | If this field is not NULL, then simply call it with the | |
204 | instruction value. It will return the value of the operand. If | |
205 | the INVALID argument is not NULL, *INVALID will be set to | |
206 | non-zero if this operand type can not actually be extracted from | |
207 | this operand (i.e., the instruction does not match). If the | |
208 | operand is valid, *INVALID will not be changed. | |
209 | ||
210 | INSN is a pointer to an array of two `arc_insn's. The first element is | |
211 | the insn, the second is the limm if present. | |
212 | ||
213 | Operands that have a printable form like registers and suffixes have | |
214 | their struct arc_operand_value pointer stored in OPVAL. */ | |
215 | ||
216 | long (*extract) PARAMS ((arc_insn *insn, | |
217 | const struct arc_operand *operand, | |
218 | int mods, const struct arc_operand_value **opval, | |
219 | int *invalid)); | |
220 | }; | |
221 | ||
222 | /* Bits that say what version of cpu we have. | |
223 | These should be passed to arc_init_opcode_tables. | |
224 | At present, all there is is the cpu type. */ | |
225 | ||
226 | /* CPU number, given value passed to `arc_init_opcode_tables'. */ | |
227 | #define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) | |
228 | /* MACH number, given value passed to `arc_init_opcode_tables'. */ | |
229 | #define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) | |
230 | ||
231 | /* Special register values: */ | |
232 | #define ARC_REG_SHIMM_UPDATE 61 | |
233 | #define ARC_REG_SHIMM 63 | |
234 | #define ARC_REG_LIMM 62 | |
235 | ||
236 | /* Non-zero if REG is a constant marker. */ | |
237 | #define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) | |
238 | ||
239 | /* Positions and masks of various fields: */ | |
240 | #define ARC_SHIFT_REGA 21 | |
241 | #define ARC_SHIFT_REGB 15 | |
242 | #define ARC_SHIFT_REGC 9 | |
243 | #define ARC_MASK_REG 63 | |
244 | ||
245 | /* Delay slot types. */ | |
246 | #define ARC_DELAY_NONE 0 /* no delay slot */ | |
247 | #define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ | |
248 | #define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ | |
249 | ||
250 | /* Non-zero if X will fit in a signed 9 bit field. */ | |
251 | #define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) | |
252 | ||
253 | extern const struct arc_operand arc_operands[]; | |
254 | extern const int arc_operand_count; | |
255 | extern /*const*/ struct arc_opcode arc_opcodes[]; | |
256 | extern const int arc_opcodes_count; | |
257 | extern const struct arc_operand_value arc_suffixes[]; | |
258 | extern const int arc_suffixes_count; | |
259 | extern const struct arc_operand_value arc_reg_names[]; | |
260 | extern const int arc_reg_names_count; | |
261 | extern unsigned char arc_operand_map[]; | |
262 | ||
263 | /* Utility fns in arc-opc.c. */ | |
264 | int arc_get_opcode_mach PARAMS ((int, int)); | |
265 | /* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ | |
266 | void arc_opcode_init_tables PARAMS ((int)); | |
267 | void arc_opcode_init_insert PARAMS ((void)); | |
268 | void arc_opcode_init_extract PARAMS ((void)); | |
269 | const struct arc_opcode *arc_opcode_lookup_asm PARAMS ((const char *)); | |
270 | const struct arc_opcode *arc_opcode_lookup_dis PARAMS ((unsigned int)); | |
271 | int arc_opcode_limm_p PARAMS ((long *)); | |
272 | const struct arc_operand_value *arc_opcode_lookup_suffix PARAMS ((const struct arc_operand *type, int value)); | |
273 | int arc_opcode_supported PARAMS ((const struct arc_opcode *)); | |
274 | int arc_opval_supported PARAMS ((const struct arc_operand_value *)); |