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arc: Change max instruction length to 64-bits
[deliverable/binutils-gdb.git] / include / opcode / arc.h
CommitLineData
252b5132 1/* Opcode table for the ARC.
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132 5
0d2bcfaf
NC		 6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
7 the GNU Binutils.
252b5132 8
0d2bcfaf
NC		 9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
e4e42b45 11 the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf 12 any later version.
252b5132 13
0d2bcfaf
NC		 14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf
NC		 17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
e4e42b45 20 along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8
NC		 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
886a2506
NC		 24#ifndef OPCODE_ARC_H
25#define OPCODE_ARC_H
26
6b477896
TS		 27#ifdef __cplusplus
28extern "C" {
29#endif
30
4670103e 31#ifndef MAX_INSN_ARGS
4eb6f892 32#define MAX_INSN_ARGS 16
4670103e
CZ		 33#endif
34
35#ifndef MAX_INSN_FLGS
886a2506 36#define MAX_INSN_FLGS 3
4670103e 37#endif
886a2506
NC		 38
39/* Instruction Class. */
40typedef enum
db18dbab
GM		 41{
42 ACL,
43 ARITH,
44 AUXREG,
45 BITOP,
2b848ebd 46 BITSTREAM,
db18dbab
GM		 47 BMU,
48 BRANCH,
49 CONTROL,
50 DPI,
51 DSP,
52 FLOAT,
53 INVALID,
54 JUMP,
55 KERNEL,
56 LOGICAL,
57 MEMORY,
58 NET,
2b848ebd
CZ		 59 PMU,
60 XY
db18dbab 61} insn_class_t;
886a2506
NC		 62
63/* Instruction Subclass. */
64typedef enum
db18dbab
GM		 65{
66 NONE,
67 CVT,
68 BTSCN,
69 CD1,
70 CD2,
71 COND,
72 DIV,
73 DP,
74 DPA,
75 DPX,
76 MPY1E,
77 MPY6E,
78 MPY7E,
79 MPY8E,
80 MPY9E,
81 NPS400,
82 QUARKSE,
83 SHFT1,
84 SHFT2,
85 SWAP,
86 SP,
87 SPX
88} insn_subclass_t;
886a2506
NC		 89
90/* Flags class. */
91typedef enum
db18dbab
GM		 92{
93 F_CLASS_NONE = 0,
1ae8ab47 94
db18dbab
GM		 95 /* At most one flag from the set of flags can appear in the
96 instruction. */
97 F_CLASS_OPTIONAL = (1 << 0),
1ae8ab47 98
db18dbab
GM		 99 /* Exactly one from from the set of flags must appear in the
100 instruction. */
101 F_CLASS_REQUIRED = (1 << 1),
f36e33da 102
db18dbab
GM		 103 /* The conditional code can be extended over the standard variants
104 via .extCondCode pseudo-op. */
105 F_CLASS_EXTEND = (1 << 2),
d9eca1df 106
db18dbab
GM		 107 /* Condition code flag. */
108 F_CLASS_COND = (1 << 3)
109} flag_class_t;
886a2506
NC		 110
111/* The opcode table is an array of struct arc_opcode. */
112struct arc_opcode
113{
114 /* The opcode name. */
115 const char *name;
116
117 /* The opcode itself. Those bits which will be filled in with
118 operands are zeroes. */
bdfe53e3 119 unsigned long long opcode;
886a2506
NC		 120
121 /* The opcode mask. This is used by the disassembler. This is a
122 mask containing ones indicating those bits which must match the
123 opcode field, and zeroes indicating those bits which need not
124 match (and are presumably filled in by operands). */
bdfe53e3 125 unsigned long long mask;
886a2506
NC		 126
127 /* One bit flags for the opcode. These are primarily used to
128 indicate specific processors and environments support the
129 instructions. The defined values are listed below. */
130 unsigned cpu;
131
132 /* The instruction class. This is used by gdb. */
c810e0b8 133 insn_class_t insn_class;
886a2506
NC		 134
135 /* The instruction subclass. */
136 insn_subclass_t subclass;
137
138 /* An array of operand codes. Each code is an index into the
139 operand table. They appear in the order which the operands must
140 appear in assembly code, and are terminated by a zero. */
141 unsigned char operands[MAX_INSN_ARGS + 1];
142
143 /* An array of flag codes. Each code is an index into the flag
144 table. They appear in the order which the flags must appear in
145 assembly code, and are terminated by a zero. */
146 unsigned char flags[MAX_INSN_FLGS + 1];
147};
252b5132 148
886a2506
NC		 149/* The table itself is sorted by major opcode number, and is otherwise
150 in the order in which the disassembler should consider
151 instructions. */
152extern const struct arc_opcode arc_opcodes[];
886a2506 153
06fe285f
GM		 154/* Return length of an instruction represented by OPCODE, in bytes. */
155extern int arc_opcode_len (const struct arc_opcode *opcode);
156
886a2506 157/* CPU Availability. */
f36e33da 158#define ARC_OPCODE_NONE 0x0000
886a2506
NC		 159#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
160#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
161#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
162#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
163
f36e33da
CZ		 164/* CPU combi. */
165#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
166 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
167#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
e5b06ef0 168#define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
f36e33da 169
886a2506
NC		 170/* CPU extensions. */
171#define ARC_EA 0x0001
172#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
173#define ARC_LLOCK 0x0002
174#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
175#define ARC_MPY 0x0004
176#define ARC_MULT 0x0004
bdd582db 177#define ARC_NPS400 0x0008
886a2506
NC		 178
179/* Floating point support. */
180#define ARC_DPFP 0x0010
181#define ARC_SPFP 0x0020
182#define ARC_FPU 0x0030
8ddf6b2a 183#define ARC_FPUDA 0x0040
886a2506
NC		 184
185/* NORM & SWAP. */
186#define ARC_SWAP 0x0100
187#define ARC_NORM 0x0200
188#define ARC_BSCAN 0x0200
189
190/* A7 specific. */
191#define ARC_UIX 0x1000
192#define ARC_TSTAMP 0x1000
193
194/* A6 specific. */
195#define ARC_VBFDW 0x1000
196#define ARC_BARREL 0x1000
197#define ARC_DSPA 0x1000
198
199/* EM specific. */
200#define ARC_SHIFT 0x1000
201
202/* V2 specific. */
203#define ARC_INTR 0x1000
204#define ARC_DIV 0x1000
205
206/* V1 specific. */
207#define ARC_XMAC 0x1000
208#define ARC_CRC 0x1000
209
886a2506
NC		 210/* The operands table is an array of struct arc_operand. */
211struct arc_operand
212{
213 /* The number of bits in the operand. */
214 unsigned int bits;
215
216 /* How far the operand is left shifted in the instruction. */
217 unsigned int shift;
218
219 /* The default relocation type for this operand. */
220 signed int default_reloc;
221
222 /* One bit syntax flags. */
223 unsigned int flags;
224
225 /* Insertion function. This is used by the assembler. To insert an
226 operand value into an instruction, check this field.
227
228 If it is NULL, execute
229 i |= (op & ((1 << o->bits) - 1)) << o->shift;
230 (i is the instruction which we are filling in, o is a pointer to
231 this structure, and op is the opcode value; this assumes twos
232 complement arithmetic).
233
234 If this field is not NULL, then simply call it with the
235 instruction and the operand value. It will return the new value
236 of the instruction. If the ERRMSG argument is not NULL, then if
237 the operand value is illegal, *ERRMSG will be set to a warning
238 string (the operand will be inserted in any case). If the
239 operand value is legal, *ERRMSG will be unchanged (most operands
240 can accept any value). */
bdfe53e3
AB		 241 unsigned long long (*insert) (unsigned long long instruction,
242 long long int op,
243 const char **errmsg);
886a2506
NC		 244
245 /* Extraction function. This is used by the disassembler. To
246 extract this operand type from an instruction, check this field.
247
248 If it is NULL, compute
249 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
250 if ((o->flags & ARC_OPERAND_SIGNED) != 0
251 && (op & (1 << (o->bits - 1))) != 0)
252 op -= 1 << o->bits;
253 (i is the instruction, o is a pointer to this structure, and op
254 is the result; this assumes twos complement arithmetic).
255
256 If this field is not NULL, then simply call it with the
257 instruction value. It will return the value of the operand. If
258 the INVALID argument is not NULL, *INVALID will be set to
259 TRUE if this operand type can not actually be extracted from
260 this operand (i.e., the instruction does not match). If the
261 operand is valid, *INVALID will not be changed. */
bdfe53e3
AB		 262 long long int (*extract) (unsigned long long instruction,
263 bfd_boolean *invalid);
886a2506 264};
0d2bcfaf 265
886a2506
NC		 266/* Elements in the table are retrieved by indexing with values from
267 the operands field of the arc_opcodes table. */
268extern const struct arc_operand arc_operands[];
269extern const unsigned arc_num_operands;
270extern const unsigned arc_Toperand;
271extern const unsigned arc_NToperand;
252b5132 272
886a2506 273/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf 274
886a2506
NC		 275/* This operand does not actually exist in the assembler input. This
276 is used to support extended mnemonics, for which two operands fields
277 are identical. The assembler should call the insert function with
278 any op value. The disassembler should call the extract function,
279 ignore the return value, and check the value placed in the invalid
280 argument. */
281#define ARC_OPERAND_FAKE 0x0001
252b5132 282
886a2506
NC		 283/* This operand names an integer register. */
284#define ARC_OPERAND_IR 0x0002
0d2bcfaf 285
886a2506
NC		 286/* This operand takes signed values. */
287#define ARC_OPERAND_SIGNED 0x0004
252b5132 288
886a2506
NC		 289/* This operand takes unsigned values. This exists primarily so that
290 a flags value of 0 can be treated as end-of-arguments. */
291#define ARC_OPERAND_UNSIGNED 0x0008
252b5132 292
886a2506
NC		 293/* This operand takes long immediate values. */
294#define ARC_OPERAND_LIMM 0x0010
252b5132 295
886a2506
NC		 296/* This operand is identical like the previous one. */
297#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf 298
886a2506
NC		 299/* This operand is PC relative. Used for internal relocs. */
300#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf 301
886a2506
NC		 302/* This operand is truncated. The truncation is done accordingly to
303 operand alignment attribute. */
304#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf 305
886a2506
NC		 306/* This operand is 16bit aligned. */
307#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf 308
886a2506
NC		 309/* This operand is 32bit aligned. */
310#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf 311
886a2506
NC		 312/* This operand can be ignored by matching process if it is not
313 present. */
314#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf 315
886a2506
NC		 316/* Don't check the range when matching. */
317#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf 318
886a2506
NC		 319/* Mark the braket possition. */
320#define ARC_OPERAND_BRAKET 0x1000
252b5132 321
db18dbab
GM		 322/* Address type operand for NPS400. */
323#define ARC_OPERAND_ADDRTYPE 0x2000
324
325/* Mark the colon position. */
326#define ARC_OPERAND_COLON 0x4000
327
886a2506 328/* Mask for selecting the type for typecheck purposes. */
db18dbab
GM		 329#define ARC_OPERAND_TYPECHECK_MASK \
330 (ARC_OPERAND_IR \
331 | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \
332 | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET \
333 | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
334
335/* Macro to determine if an operand is a fake operand. */
336#define ARC_OPERAND_IS_FAKE(op) \
337 ((operand->flags & ARC_OPERAND_FAKE) \
338 && !((operand->flags & ARC_OPERAND_BRAKET) \
339 || (operand->flags & ARC_OPERAND_COLON)))
252b5132 340
886a2506
NC		 341/* The flags structure. */
342struct arc_flag_operand
343{
344 /* The flag name. */
345 const char *name;
0d2bcfaf 346
886a2506
NC		 347 /* The flag code. */
348 unsigned code;
252b5132 349
886a2506
NC		 350 /* The number of bits in the operand. */
351 unsigned int bits;
252b5132 352
886a2506
NC		 353 /* How far the operand is left shifted in the instruction. */
354 unsigned int shift;
252b5132 355
886a2506
NC		 356 /* Available for disassembler. */
357 unsigned char favail;
84037f8c
KD		 358};
359
886a2506
NC		 360/* The flag operands table. */
361extern const struct arc_flag_operand arc_flag_operands[];
362extern const unsigned arc_num_flag_operands;
0d2bcfaf 363
886a2506
NC		 364/* The flag's class structure. */
365struct arc_flag_class
366{
367 /* Flag class. */
c810e0b8 368 flag_class_t flag_class;
252b5132 369
886a2506
NC		 370 /* List of valid flags (codes). */
371 unsigned flags[256];
372};
252b5132 373
886a2506 374extern const struct arc_flag_class arc_flag_classes[];
252b5132 375
886a2506
NC		 376/* Structure for special cases. */
377struct arc_flag_special
378{
379 /* Name of special case instruction. */
380 const char *name;
252b5132 381
886a2506
NC		 382 /* List of flags applicable for special case instruction. */
383 unsigned flags[32];
384};
252b5132 385
886a2506
NC		 386extern const struct arc_flag_special arc_flag_special_cases[];
387extern const unsigned arc_num_flag_special;
388
389/* Relocation equivalence structure. */
390struct arc_reloc_equiv_tab
391{
392 const char * name; /* String to lookup. */
393 const char * mnemonic; /* Extra matching condition. */
24b368f8 394 unsigned flags[32]; /* Extra matching condition. */
886a2506
NC		 395 signed int oldreloc; /* Old relocation. */
396 signed int newreloc; /* New relocation. */
397};
252b5132 398
886a2506
NC		 399extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
400extern const unsigned arc_num_equiv_tab;
252b5132 401
886a2506
NC		 402/* Structure for operand operations for pseudo/alias instructions. */
403struct arc_operand_operation
404{
405 /* The index for operand from operand array. */
406 unsigned operand_idx;
252b5132 407
886a2506
NC		 408 /* Defines if it needs the operand inserted by the assembler or
409 whether this operand comes from the pseudo instruction's
410 operands. */
411 unsigned char needs_insert;
252b5132 412
886a2506
NC		 413 /* Count we have to add to the operand. Use negative number to
414 subtract from the operand. Also use this number to add to 0 if
415 the operand needs to be inserted (i.e. needs_insert == 1). */
416 int count;
252b5132 417
886a2506
NC		 418 /* Index of the operand to swap with. To be done AFTER applying
419 inc_count. */
420 unsigned swap_operand_idx;
252b5132
RH		 421};
422
886a2506
NC		 423/* Structure for pseudo/alias instructions. */
424struct arc_pseudo_insn
425{
426 /* Mnemonic for pseudo/alias insn. */
427 const char *mnemonic_p;
252b5132 428
886a2506
NC		 429 /* Mnemonic for real instruction. */
430 const char *mnemonic_r;
252b5132 431
886a2506
NC		 432 /* Flag that will have to be added (if any). */
433 const char *flag_r;
252b5132 434
886a2506
NC		 435 /* Amount of operands. */
436 unsigned operand_cnt;
252b5132 437
886a2506
NC		 438 /* Array of operand operations. */
439 struct arc_operand_operation operand[6];
440};
252b5132 441
886a2506
NC		 442extern const struct arc_pseudo_insn arc_pseudo_insns[];
443extern const unsigned arc_num_pseudo_insn;
252b5132 444
886a2506
NC		 445/* Structure for AUXILIARY registers. */
446struct arc_aux_reg
447{
448 /* Register address. */
449 int address;
252b5132 450
f36e33da
CZ		 451 /* One bit flags for the opcode. These are primarily used to
452 indicate specific processors and environments support the
453 instructions. */
454 unsigned cpu;
455
8ddf6b2a
CZ		 456 /* AUX register subclass. */
457 insn_subclass_t subclass;
458
459 /* Register name. */
886a2506
NC		 460 const char *name;
461
462 /* Size of the string. */
463 size_t length;
464};
465
466extern const struct arc_aux_reg arc_aux_regs[];
467extern const unsigned arc_num_aux_regs;
468
4670103e
CZ		 469extern const struct arc_opcode arc_relax_opcodes[];
470extern const unsigned arc_num_relax_opcodes;
471
4b0c052e
AB		 472/* Macro used for generating one class of NPS instructions. */
473#define NPS_CMEM_HIGH_VALUE 0x57f0
474
f2dd8838
CZ		 475/* Macros to help generating regular pattern instructions. */
476#define FIELDA(word) (word & 0x3F)
477#define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
478#define FIELDC(word) ((word & 0x3F) << 6)
479#define FIELDF (0x01 << 15)
480#define FIELDQ (0x1F)
481
482#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
483#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
484#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
485
486#define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
487#define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
488#define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
489#define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
490#define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
491#define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
492#define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
493#define INSN3OP_0LL(MOP,SOP) \
494 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
495#define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
496#define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
497#define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
498#define INSN3OP_0LU(MOP,SOP) \
499 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
500#define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
501#define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
502#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
503#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
504#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
505#define INSN3OP_C0LL(MOP,SOP) \
506 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
507#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
508#define INSN3OP_C0LU(MOP,SOP) \
509 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
510
2e272202
GM		 511#define MASK_32BIT(VAL) (0xffffffff & (VAL))
512
513#define MINSN3OP_ABC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
514#define MINSN3OP_ALC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
515#define MINSN3OP_ABL (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63))))
516#define MINSN3OP_ALL (MASK_32BIT (~(FIELDF | FIELDA (63))))
517#define MINSN3OP_0BC (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
518#define MINSN3OP_0LC (MASK_32BIT (~(FIELDF | FIELDC (63))))
519#define MINSN3OP_0BL (MASK_32BIT (~(FIELDF | FIELDB (63))))
520#define MINSN3OP_0LL (MASK_32BIT (~(FIELDF)))
521#define MINSN3OP_ABU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
522#define MINSN3OP_ALU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
523#define MINSN3OP_0BU (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
524#define MINSN3OP_0LU (MASK_32BIT (~(FIELDF | FIELDC (63))))
525#define MINSN3OP_BBS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
526#define MINSN3OP_0LS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
527#define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
528#define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63))))
529#define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
530#define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ)))
531#define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
532#define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
f2dd8838
CZ		 533
534#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
535#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
536#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
537#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
538#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
539#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
540
2e272202
GM		 541#define MINSN2OP_BC (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
542#define MINSN2OP_BL (MASK_32BIT ((~(FIELDF | FIELDB (63)))))
543#define MINSN2OP_0C (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
544#define MINSN2OP_0L (MASK_32BIT ((~(FIELDF))))
545#define MINSN2OP_BU (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
546#define MINSN2OP_0U (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
f2dd8838 547
b99747ae
CZ		 548/* Various constants used when defining an extension instruction. */
549#define ARC_SYNTAX_3OP (1 << 0)
550#define ARC_SYNTAX_2OP (1 << 1)
945e0f82
CZ		 551#define ARC_SYNTAX_1OP (1 << 2)
552#define ARC_SYNTAX_NOP (1 << 3)
553#define ARC_SYNTAX_MASK (0x0F)
554
555#define ARC_OP1_MUST_BE_IMM (1 << 0)
556#define ARC_OP1_IMM_IMPLIED (1 << 1)
b99747ae
CZ		 557
558#define ARC_SUFFIX_NONE (1 << 0)
559#define ARC_SUFFIX_COND (1 << 1)
560#define ARC_SUFFIX_FLAG (1 << 2)
561
f36e33da
CZ		 562#define ARC_REGISTER_READONLY (1 << 0)
563#define ARC_REGISTER_WRITEONLY (1 << 1)
564#define ARC_REGISTER_NOSHORT_CUT (1 << 2)
b99747ae
CZ		 565
566/* Constants needed to initialize extension instructions. */
567extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
568extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
569extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
570extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
571
572extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
573extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
574extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
575extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
576extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
577extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
578extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
579extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
580extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
581extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
582extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
583extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
584
585extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
586extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
587extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
588
589extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
590extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
591extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
592
593extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
594extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
595extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
596extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
597extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
598extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
599
600extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
601extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
602extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
603extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
604
945e0f82
CZ		 605extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
606extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
607extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
608
db18dbab
GM		 609/* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
610 Instruction Set Reference Manual v2.4 for a description of address types. */
611
612typedef enum
613{
614 /* Addresses in memory. */
615
616 /* Buffer descriptor. */
617 ARC_NPS400_ADDRTYPE_BD,
618
619 /* Job identifier. */
620 ARC_NPS400_ADDRTYPE_JID,
621
622 /* Linked Buffer Descriptor. */
623 ARC_NPS400_ADDRTYPE_LBD,
624
625 /* Multicast Buffer Descriptor. */
626 ARC_NPS400_ADDRTYPE_MBD,
627
628 /* Summarized Address. */
629 ARC_NPS400_ADDRTYPE_SD,
630
631 /* SMEM Security Context Local Memory. */
632 ARC_NPS400_ADDRTYPE_SM,
633
634 /* Extended Address. */
635 ARC_NPS400_ADDRTYPE_XA,
636
637 /* Extended Summarized Address. */
638 ARC_NPS400_ADDRTYPE_XD,
639
640 /* CMEM offset addresses. */
641
642 /* On-demand Counter Descriptor. */
643 ARC_NPS400_ADDRTYPE_CD,
644
645 /* CMEM Buffer Descriptor. */
646 ARC_NPS400_ADDRTYPE_CBD,
647
648 /* CMEM Job Identifier. */
649 ARC_NPS400_ADDRTYPE_CJID,
650
651 /* CMEM Linked Buffer Descriptor. */
652 ARC_NPS400_ADDRTYPE_CLBD,
653
654 /* CMEM Offset. */
655 ARC_NPS400_ADDRTYPE_CM,
656
657 /* CMEM Summarized Address. */
658 ARC_NPS400_ADDRTYPE_CSD,
659
660 /* CMEM Extended Address. */
661 ARC_NPS400_ADDRTYPE_CXA,
662
663 /* CMEM Extended Summarized Address. */
664 ARC_NPS400_ADDRTYPE_CXD
665
666} arc_nps_address_type;
667
668#define ARC_NUM_ADDRTYPES 16
669
6b477896
TS		 670#ifdef __cplusplus
671}
672#endif
673
886a2506 674#endif /* OPCODE_ARC_H */
GDB Binutils - Deliverables
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