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[deliverable/binutils-gdb.git] / include / opcode / arc.h
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252b5132 1/* Opcode table for the ARC.
2571583a 2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132 5
0d2bcfaf
NC		 6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
7 the GNU Binutils.
252b5132 8
0d2bcfaf
NC		 9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
e4e42b45 11 the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf 12 any later version.
252b5132 13
0d2bcfaf
NC		 14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf
NC		 17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
e4e42b45 20 along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8
NC		 21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
252b5132 23
886a2506
NC		 24#ifndef OPCODE_ARC_H
25#define OPCODE_ARC_H
26
6b477896
TS		 27#ifdef __cplusplus
28extern "C" {
29#endif
30
4670103e 31#ifndef MAX_INSN_ARGS
4eb6f892 32#define MAX_INSN_ARGS 16
4670103e
CZ		 33#endif
34
35#ifndef MAX_INSN_FLGS
886a2506 36#define MAX_INSN_FLGS 3
4670103e 37#endif
886a2506
NC		 38
39/* Instruction Class. */
40typedef enum
db18dbab
GM		 41{
42 ACL,
43 ARITH,
44 AUXREG,
6ec7c1ae
CZ		 45 BBIT0,
46 BBIT1,
47 BI,
48 BIH,
db18dbab 49 BITOP,
2b848ebd 50 BITSTREAM,
db18dbab
GM		 51 BMU,
52 BRANCH,
6ec7c1ae 53 BRCC,
db18dbab 54 CONTROL,
abe7c33b 55 DIVREM,
645d3342 56 DMA,
db18dbab
GM		 57 DPI,
58 DSP,
6ec7c1ae
CZ		 59 EI,
60 ENTER,
db18dbab
GM		 61 FLOAT,
62 INVALID,
6ec7c1ae 63 JLI,
db18dbab
GM		 64 JUMP,
65 KERNEL,
6ec7c1ae 66 LEAVE,
abe7c33b 67 LOAD,
db18dbab 68 LOGICAL,
6ec7c1ae 69 LOOP,
db18dbab 70 MEMORY,
abe7c33b
CZ		 71 MOVE,
72 MPY,
db18dbab 73 NET,
5a736821 74 PROTOCOL_DECODE,
2b848ebd 75 PMU,
6ec7c1ae
CZ		 76 POP,
77 PUSH,
abe7c33b 78 STORE,
6ec7c1ae 79 SUB,
2b848ebd 80 XY
db18dbab 81} insn_class_t;
886a2506
NC		 82
83/* Instruction Subclass. */
84typedef enum
db18dbab
GM		 85{
86 NONE,
87 CVT,
88 BTSCN,
89 CD1,
90 CD2,
91 COND,
92 DIV,
93 DP,
94 DPA,
95 DPX,
96 MPY1E,
97 MPY6E,
98 MPY7E,
99 MPY8E,
100 MPY9E,
101 NPS400,
102 QUARKSE,
103 SHFT1,
104 SHFT2,
105 SWAP,
106 SP,
107 SPX
108} insn_subclass_t;
886a2506
NC		 109
110/* Flags class. */
111typedef enum
db18dbab
GM		 112{
113 F_CLASS_NONE = 0,
1ae8ab47 114
db18dbab
GM		 115 /* At most one flag from the set of flags can appear in the
116 instruction. */
117 F_CLASS_OPTIONAL = (1 << 0),
1ae8ab47 118
db18dbab
GM		 119 /* Exactly one from from the set of flags must appear in the
120 instruction. */
121 F_CLASS_REQUIRED = (1 << 1),
f36e33da 122
db18dbab
GM		 123 /* The conditional code can be extended over the standard variants
124 via .extCondCode pseudo-op. */
125 F_CLASS_EXTEND = (1 << 2),
d9eca1df 126
db18dbab 127 /* Condition code flag. */
6ec7c1ae
CZ		 128 F_CLASS_COND = (1 << 3),
129
130 /* Write back mode. */
131 F_CLASS_WB = (1 << 4),
132
133 /* Data size. */
134 F_CLASS_ZZ = (1 << 5),
135
136 /* Implicit flag. */
137 F_CLASS_IMPLICIT = (1 << 6)
db18dbab 138} flag_class_t;
886a2506
NC		 139
140/* The opcode table is an array of struct arc_opcode. */
141struct arc_opcode
142{
143 /* The opcode name. */
144 const char *name;
145
146 /* The opcode itself. Those bits which will be filled in with
147 operands are zeroes. */
bdfe53e3 148 unsigned long long opcode;
886a2506
NC		 149
150 /* The opcode mask. This is used by the disassembler. This is a
151 mask containing ones indicating those bits which must match the
152 opcode field, and zeroes indicating those bits which need not
153 match (and are presumably filled in by operands). */
bdfe53e3 154 unsigned long long mask;
886a2506
NC		 155
156 /* One bit flags for the opcode. These are primarily used to
157 indicate specific processors and environments support the
158 instructions. The defined values are listed below. */
159 unsigned cpu;
160
161 /* The instruction class. This is used by gdb. */
c810e0b8 162 insn_class_t insn_class;
886a2506
NC		 163
164 /* The instruction subclass. */
165 insn_subclass_t subclass;
166
167 /* An array of operand codes. Each code is an index into the
168 operand table. They appear in the order which the operands must
169 appear in assembly code, and are terminated by a zero. */
170 unsigned char operands[MAX_INSN_ARGS + 1];
171
172 /* An array of flag codes. Each code is an index into the flag
173 table. They appear in the order which the flags must appear in
174 assembly code, and are terminated by a zero. */
175 unsigned char flags[MAX_INSN_FLGS + 1];
176};
252b5132 177
886a2506
NC		 178/* The table itself is sorted by major opcode number, and is otherwise
179 in the order in which the disassembler should consider
180 instructions. */
181extern const struct arc_opcode arc_opcodes[];
886a2506 182
06fe285f
GM		 183/* Return length of an instruction represented by OPCODE, in bytes. */
184extern int arc_opcode_len (const struct arc_opcode *opcode);
185
886a2506 186/* CPU Availability. */
f36e33da 187#define ARC_OPCODE_NONE 0x0000
886a2506
NC		 188#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
189#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
190#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
191#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
192
f36e33da
CZ		 193/* CPU combi. */
194#define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
195 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
196#define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
e5b06ef0 197#define ARC_OPCODE_ARCV2 (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
f36e33da 198
886a2506
NC		 199/* CPU extensions. */
200#define ARC_EA 0x0001
201#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
202#define ARC_LLOCK 0x0002
203#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
204#define ARC_MPY 0x0004
205#define ARC_MULT 0x0004
bdd582db 206#define ARC_NPS400 0x0008
886a2506
NC		 207
208/* Floating point support. */
209#define ARC_DPFP 0x0010
210#define ARC_SPFP 0x0020
211#define ARC_FPU 0x0030
8ddf6b2a 212#define ARC_FPUDA 0x0040
886a2506
NC		 213
214/* NORM & SWAP. */
215#define ARC_SWAP 0x0100
216#define ARC_NORM 0x0200
217#define ARC_BSCAN 0x0200
218
219/* A7 specific. */
220#define ARC_UIX 0x1000
221#define ARC_TSTAMP 0x1000
222
223/* A6 specific. */
224#define ARC_VBFDW 0x1000
225#define ARC_BARREL 0x1000
226#define ARC_DSPA 0x1000
227
228/* EM specific. */
229#define ARC_SHIFT 0x1000
230
231/* V2 specific. */
232#define ARC_INTR 0x1000
233#define ARC_DIV 0x1000
234
235/* V1 specific. */
236#define ARC_XMAC 0x1000
237#define ARC_CRC 0x1000
238
886a2506
NC		 239/* The operands table is an array of struct arc_operand. */
240struct arc_operand
241{
242 /* The number of bits in the operand. */
243 unsigned int bits;
244
245 /* How far the operand is left shifted in the instruction. */
246 unsigned int shift;
247
248 /* The default relocation type for this operand. */
249 signed int default_reloc;
250
251 /* One bit syntax flags. */
252 unsigned int flags;
253
254 /* Insertion function. This is used by the assembler. To insert an
255 operand value into an instruction, check this field.
256
257 If it is NULL, execute
258 i |= (op & ((1 << o->bits) - 1)) << o->shift;
259 (i is the instruction which we are filling in, o is a pointer to
260 this structure, and op is the opcode value; this assumes twos
261 complement arithmetic).
262
263 If this field is not NULL, then simply call it with the
264 instruction and the operand value. It will return the new value
265 of the instruction. If the ERRMSG argument is not NULL, then if
266 the operand value is illegal, *ERRMSG will be set to a warning
267 string (the operand will be inserted in any case). If the
268 operand value is legal, *ERRMSG will be unchanged (most operands
269 can accept any value). */
bdfe53e3
AB		 270 unsigned long long (*insert) (unsigned long long instruction,
271 long long int op,
272 const char **errmsg);
886a2506
NC		 273
274 /* Extraction function. This is used by the disassembler. To
275 extract this operand type from an instruction, check this field.
276
277 If it is NULL, compute
278 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
279 if ((o->flags & ARC_OPERAND_SIGNED) != 0
280 && (op & (1 << (o->bits - 1))) != 0)
281 op -= 1 << o->bits;
282 (i is the instruction, o is a pointer to this structure, and op
283 is the result; this assumes twos complement arithmetic).
284
285 If this field is not NULL, then simply call it with the
286 instruction value. It will return the value of the operand. If
287 the INVALID argument is not NULL, *INVALID will be set to
288 TRUE if this operand type can not actually be extracted from
289 this operand (i.e., the instruction does not match). If the
290 operand is valid, *INVALID will not be changed. */
bdfe53e3
AB		 291 long long int (*extract) (unsigned long long instruction,
292 bfd_boolean *invalid);
886a2506 293};
0d2bcfaf 294
886a2506
NC		 295/* Elements in the table are retrieved by indexing with values from
296 the operands field of the arc_opcodes table. */
297extern const struct arc_operand arc_operands[];
298extern const unsigned arc_num_operands;
299extern const unsigned arc_Toperand;
300extern const unsigned arc_NToperand;
252b5132 301
886a2506 302/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf 303
886a2506
NC		 304/* This operand does not actually exist in the assembler input. This
305 is used to support extended mnemonics, for which two operands fields
306 are identical. The assembler should call the insert function with
307 any op value. The disassembler should call the extract function,
308 ignore the return value, and check the value placed in the invalid
309 argument. */
310#define ARC_OPERAND_FAKE 0x0001
252b5132 311
886a2506
NC		 312/* This operand names an integer register. */
313#define ARC_OPERAND_IR 0x0002
0d2bcfaf 314
886a2506
NC		 315/* This operand takes signed values. */
316#define ARC_OPERAND_SIGNED 0x0004
252b5132 317
886a2506
NC		 318/* This operand takes unsigned values. This exists primarily so that
319 a flags value of 0 can be treated as end-of-arguments. */
320#define ARC_OPERAND_UNSIGNED 0x0008
252b5132 321
886a2506
NC		 322/* This operand takes long immediate values. */
323#define ARC_OPERAND_LIMM 0x0010
252b5132 324
886a2506
NC		 325/* This operand is identical like the previous one. */
326#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf 327
886a2506
NC		 328/* This operand is PC relative. Used for internal relocs. */
329#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf 330
886a2506
NC		 331/* This operand is truncated. The truncation is done accordingly to
332 operand alignment attribute. */
333#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf 334
886a2506
NC		 335/* This operand is 16bit aligned. */
336#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf 337
886a2506
NC		 338/* This operand is 32bit aligned. */
339#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf 340
886a2506
NC		 341/* This operand can be ignored by matching process if it is not
342 present. */
343#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf 344
886a2506
NC		 345/* Don't check the range when matching. */
346#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf 347
886a2506
NC		 348/* Mark the braket possition. */
349#define ARC_OPERAND_BRAKET 0x1000
252b5132 350
db18dbab
GM		 351/* Address type operand for NPS400. */
352#define ARC_OPERAND_ADDRTYPE 0x2000
353
354/* Mark the colon position. */
355#define ARC_OPERAND_COLON 0x4000
356
886a2506 357/* Mask for selecting the type for typecheck purposes. */
db18dbab
GM		 358#define ARC_OPERAND_TYPECHECK_MASK \
359 (ARC_OPERAND_IR \
360 | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED \
361 | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET \
362 | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
363
364/* Macro to determine if an operand is a fake operand. */
365#define ARC_OPERAND_IS_FAKE(op) \
366 ((operand->flags & ARC_OPERAND_FAKE) \
367 && !((operand->flags & ARC_OPERAND_BRAKET) \
368 || (operand->flags & ARC_OPERAND_COLON)))
252b5132 369
886a2506
NC		 370/* The flags structure. */
371struct arc_flag_operand
372{
373 /* The flag name. */
374 const char *name;
0d2bcfaf 375
886a2506
NC		 376 /* The flag code. */
377 unsigned code;
252b5132 378
886a2506
NC		 379 /* The number of bits in the operand. */
380 unsigned int bits;
252b5132 381
886a2506
NC		 382 /* How far the operand is left shifted in the instruction. */
383 unsigned int shift;
252b5132 384
886a2506
NC		 385 /* Available for disassembler. */
386 unsigned char favail;
84037f8c
KD		 387};
388
886a2506
NC		 389/* The flag operands table. */
390extern const struct arc_flag_operand arc_flag_operands[];
391extern const unsigned arc_num_flag_operands;
0d2bcfaf 392
886a2506
NC		 393/* The flag's class structure. */
394struct arc_flag_class
395{
396 /* Flag class. */
c810e0b8 397 flag_class_t flag_class;
252b5132 398
886a2506
NC		 399 /* List of valid flags (codes). */
400 unsigned flags[256];
401};
252b5132 402
886a2506 403extern const struct arc_flag_class arc_flag_classes[];
252b5132 404
886a2506
NC		 405/* Structure for special cases. */
406struct arc_flag_special
407{
408 /* Name of special case instruction. */
409 const char *name;
252b5132 410
886a2506
NC		 411 /* List of flags applicable for special case instruction. */
412 unsigned flags[32];
413};
252b5132 414
886a2506
NC		 415extern const struct arc_flag_special arc_flag_special_cases[];
416extern const unsigned arc_num_flag_special;
417
418/* Relocation equivalence structure. */
419struct arc_reloc_equiv_tab
420{
421 const char * name; /* String to lookup. */
422 const char * mnemonic; /* Extra matching condition. */
24b368f8 423 unsigned flags[32]; /* Extra matching condition. */
886a2506
NC		 424 signed int oldreloc; /* Old relocation. */
425 signed int newreloc; /* New relocation. */
426};
252b5132 427
886a2506
NC		 428extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
429extern const unsigned arc_num_equiv_tab;
252b5132 430
886a2506
NC		 431/* Structure for operand operations for pseudo/alias instructions. */
432struct arc_operand_operation
433{
434 /* The index for operand from operand array. */
435 unsigned operand_idx;
252b5132 436
886a2506
NC		 437 /* Defines if it needs the operand inserted by the assembler or
438 whether this operand comes from the pseudo instruction's
439 operands. */
440 unsigned char needs_insert;
252b5132 441
886a2506
NC		 442 /* Count we have to add to the operand. Use negative number to
443 subtract from the operand. Also use this number to add to 0 if
444 the operand needs to be inserted (i.e. needs_insert == 1). */
445 int count;
252b5132 446
886a2506
NC		 447 /* Index of the operand to swap with. To be done AFTER applying
448 inc_count. */
449 unsigned swap_operand_idx;
252b5132
RH		 450};
451
886a2506
NC		 452/* Structure for pseudo/alias instructions. */
453struct arc_pseudo_insn
454{
455 /* Mnemonic for pseudo/alias insn. */
456 const char *mnemonic_p;
252b5132 457
886a2506
NC		 458 /* Mnemonic for real instruction. */
459 const char *mnemonic_r;
252b5132 460
886a2506
NC		 461 /* Flag that will have to be added (if any). */
462 const char *flag_r;
252b5132 463
886a2506
NC		 464 /* Amount of operands. */
465 unsigned operand_cnt;
252b5132 466
886a2506
NC		 467 /* Array of operand operations. */
468 struct arc_operand_operation operand[6];
469};
252b5132 470
886a2506
NC		 471extern const struct arc_pseudo_insn arc_pseudo_insns[];
472extern const unsigned arc_num_pseudo_insn;
252b5132 473
886a2506
NC		 474/* Structure for AUXILIARY registers. */
475struct arc_aux_reg
476{
477 /* Register address. */
478 int address;
252b5132 479
f36e33da
CZ		 480 /* One bit flags for the opcode. These are primarily used to
481 indicate specific processors and environments support the
482 instructions. */
483 unsigned cpu;
484
8ddf6b2a
CZ		 485 /* AUX register subclass. */
486 insn_subclass_t subclass;
487
488 /* Register name. */
886a2506
NC		 489 const char *name;
490
491 /* Size of the string. */
492 size_t length;
493};
494
495extern const struct arc_aux_reg arc_aux_regs[];
496extern const unsigned arc_num_aux_regs;
497
4670103e
CZ		 498extern const struct arc_opcode arc_relax_opcodes[];
499extern const unsigned arc_num_relax_opcodes;
500
4b0c052e
AB		 501/* Macro used for generating one class of NPS instructions. */
502#define NPS_CMEM_HIGH_VALUE 0x57f0
503
f2dd8838
CZ		 504/* Macros to help generating regular pattern instructions. */
505#define FIELDA(word) (word & 0x3F)
506#define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
507#define FIELDC(word) ((word & 0x3F) << 6)
508#define FIELDF (0x01 << 15)
509#define FIELDQ (0x1F)
510
511#define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
512#define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
513#define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
514
515#define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
516#define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
517#define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
518#define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
519#define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
520#define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
521#define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
522#define INSN3OP_0LL(MOP,SOP) \
523 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
524#define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
525#define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
526#define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
527#define INSN3OP_0LU(MOP,SOP) \
528 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
529#define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
530#define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
531#define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
532#define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
533#define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
534#define INSN3OP_C0LL(MOP,SOP) \
535 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
536#define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
537#define INSN3OP_C0LU(MOP,SOP) \
538 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
539
2e272202
GM		 540#define MASK_32BIT(VAL) (0xffffffff & (VAL))
541
542#define MINSN3OP_ABC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
543#define MINSN3OP_ALC (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
544#define MINSN3OP_ABL (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63))))
545#define MINSN3OP_ALL (MASK_32BIT (~(FIELDF | FIELDA (63))))
546#define MINSN3OP_0BC (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
547#define MINSN3OP_0LC (MASK_32BIT (~(FIELDF | FIELDC (63))))
548#define MINSN3OP_0BL (MASK_32BIT (~(FIELDF | FIELDB (63))))
549#define MINSN3OP_0LL (MASK_32BIT (~(FIELDF)))
550#define MINSN3OP_ABU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
551#define MINSN3OP_ALU (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
552#define MINSN3OP_0BU (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
553#define MINSN3OP_0LU (MASK_32BIT (~(FIELDF | FIELDC (63))))
554#define MINSN3OP_BBS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
555#define MINSN3OP_0LS (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
556#define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
557#define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63))))
558#define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
559#define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ)))
560#define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
561#define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
f2dd8838
CZ		 562
563#define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
564#define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
565#define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
566#define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
567#define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
568#define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
569
2e272202
GM		 570#define MINSN2OP_BC (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
571#define MINSN2OP_BL (MASK_32BIT ((~(FIELDF | FIELDB (63)))))
572#define MINSN2OP_0C (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
573#define MINSN2OP_0L (MASK_32BIT ((~(FIELDF))))
574#define MINSN2OP_BU (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
575#define MINSN2OP_0U (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
f2dd8838 576
b99747ae
CZ		 577/* Various constants used when defining an extension instruction. */
578#define ARC_SYNTAX_3OP (1 << 0)
579#define ARC_SYNTAX_2OP (1 << 1)
945e0f82
CZ		 580#define ARC_SYNTAX_1OP (1 << 2)
581#define ARC_SYNTAX_NOP (1 << 3)
582#define ARC_SYNTAX_MASK (0x0F)
583
584#define ARC_OP1_MUST_BE_IMM (1 << 0)
585#define ARC_OP1_IMM_IMPLIED (1 << 1)
b99747ae
CZ		 586
587#define ARC_SUFFIX_NONE (1 << 0)
588#define ARC_SUFFIX_COND (1 << 1)
589#define ARC_SUFFIX_FLAG (1 << 2)
590
f36e33da
CZ		 591#define ARC_REGISTER_READONLY (1 << 0)
592#define ARC_REGISTER_WRITEONLY (1 << 1)
593#define ARC_REGISTER_NOSHORT_CUT (1 << 2)
b99747ae
CZ		 594
595/* Constants needed to initialize extension instructions. */
596extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
597extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
598extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
599extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
600
601extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
602extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
603extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
604extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
605extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
606extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
607extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
608extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
609extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
610extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
611extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
612extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
613
614extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
615extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
616extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
617
618extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
619extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
620extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
621
622extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
623extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
624extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
625extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
626extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
627extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
628
629extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
630extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
631extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
632extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
633
945e0f82
CZ		 634extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
635extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
636extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
637
db18dbab
GM		 638/* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
639 Instruction Set Reference Manual v2.4 for a description of address types. */
640
641typedef enum
642{
643 /* Addresses in memory. */
644
645 /* Buffer descriptor. */
646 ARC_NPS400_ADDRTYPE_BD,
647
648 /* Job identifier. */
649 ARC_NPS400_ADDRTYPE_JID,
650
651 /* Linked Buffer Descriptor. */
652 ARC_NPS400_ADDRTYPE_LBD,
653
654 /* Multicast Buffer Descriptor. */
655 ARC_NPS400_ADDRTYPE_MBD,
656
657 /* Summarized Address. */
658 ARC_NPS400_ADDRTYPE_SD,
659
660 /* SMEM Security Context Local Memory. */
661 ARC_NPS400_ADDRTYPE_SM,
662
663 /* Extended Address. */
664 ARC_NPS400_ADDRTYPE_XA,
665
666 /* Extended Summarized Address. */
667 ARC_NPS400_ADDRTYPE_XD,
668
669 /* CMEM offset addresses. */
670
671 /* On-demand Counter Descriptor. */
672 ARC_NPS400_ADDRTYPE_CD,
673
674 /* CMEM Buffer Descriptor. */
675 ARC_NPS400_ADDRTYPE_CBD,
676
677 /* CMEM Job Identifier. */
678 ARC_NPS400_ADDRTYPE_CJID,
679
680 /* CMEM Linked Buffer Descriptor. */
681 ARC_NPS400_ADDRTYPE_CLBD,
682
683 /* CMEM Offset. */
684 ARC_NPS400_ADDRTYPE_CM,
685
686 /* CMEM Summarized Address. */
687 ARC_NPS400_ADDRTYPE_CSD,
688
689 /* CMEM Extended Address. */
690 ARC_NPS400_ADDRTYPE_CXA,
691
692 /* CMEM Extended Summarized Address. */
693 ARC_NPS400_ADDRTYPE_CXD
694
695} arc_nps_address_type;
696
697#define ARC_NUM_ADDRTYPES 16
698
6b477896
TS		 699#ifdef __cplusplus
700}
701#endif
702
886a2506 703#endif /* OPCODE_ARC_H */
GDB Binutils - Deliverables
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