[deliverable/binutils-gdb.git] / include / opcode / arm.h

/* ARM assembler/disassembler support.
   Copyright (C) 2004-2015 Free Software Foundation, Inc.

   This file is part of GDB and GAS.

   GDB and GAS are free software; you can redistribute it and/or
   modify it under the terms of the GNU General Public License as
   published by the Free Software Foundation; either version 3, or (at
   your option) any later version.

   GDB and GAS are distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GDB or GAS; see the file COPYING3.  If not, write to the
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

/* The following bitmasks control CPU extensions:  */
#define ARM_EXT_V1	 0x00000001	/* All processors (core set).  */
#define ARM_EXT_V2	 0x00000002	/* Multiply instructions.  */
#define ARM_EXT_V2S	 0x00000004	/* SWP instructions.       */
#define ARM_EXT_V3	 0x00000008	/* MSR MRS.                */
#define ARM_EXT_V3M	 0x00000010	/* Allow long multiplies.  */
#define ARM_EXT_V4	 0x00000020	/* Allow half word loads.  */
#define ARM_EXT_V4T	 0x00000040	/* Thumb.                  */
#define ARM_EXT_V5	 0x00000080	/* Allow CLZ, etc.         */
#define ARM_EXT_V5T	 0x00000100	/* Improved interworking.  */
#define ARM_EXT_V5ExP	 0x00000200	/* DSP core set.           */
#define ARM_EXT_V5E	 0x00000400	/* DSP Double transfers.   */
#define ARM_EXT_V5J	 0x00000800	/* Jazelle extension.	   */
#define ARM_EXT_V6       0x00001000     /* ARM V6.                 */
#define ARM_EXT_V6K      0x00002000     /* ARM V6K.                */
/*			 0x00004000	   Was ARM V6Z.            */
#define ARM_EXT_V8	 0x00004000     /* is now ARMv8.           */
#define ARM_EXT_V6T2	 0x00008000	/* Thumb-2.                */
#define ARM_EXT_DIV	 0x00010000	/* Integer division.       */
/* The 'M' in Arm V7M stands for Microcontroller.
   On earlier architecture variants it stands for Multiply.  */
#define ARM_EXT_V5E_NOTM 0x00020000	/* Arm V5E but not Arm V7M. */
#define ARM_EXT_V6_NOTM	 0x00040000	/* Arm V6 but not Arm V7M. */
#define ARM_EXT_V7	 0x00080000	/* Arm V7.                 */
#define ARM_EXT_V7A	 0x00100000	/* Arm V7A.                */
#define ARM_EXT_V7R	 0x00200000	/* Arm V7R.                */
#define ARM_EXT_V7M	 0x00400000	/* Arm V7M.                */
#define ARM_EXT_V6M	 0x00800000	/* ARM V6M.		    */
#define ARM_EXT_BARRIER	 0x01000000	/* DSB/DMB/ISB.		    */
#define ARM_EXT_THUMB_MSR 0x02000000	/* Thumb MSR/MRS.	    */
#define ARM_EXT_V6_DSP 0x04000000	/* ARM v6 (DSP-related),
					   not in v7-M.  */
#define ARM_EXT_MP       0x08000000     /* Multiprocessing Extensions.  */
#define ARM_EXT_SEC	 0x10000000	/* Security extensions.  */
#define ARM_EXT_OS	 0x20000000	/* OS Extensions.  */
#define ARM_EXT_ADIV	 0x40000000	/* Integer divide extensions in ARM 
					   state.  */
#define ARM_EXT_VIRT	 0x80000000	/* Virtualization extensions.  */

#define ARM_EXT2_PAN	 0x00000001     /* PAN extension.  */
#define ARM_EXT2_V8_2A	 0x00000002     /* ARM V8.2A.  */

/* Co-processor space extensions.  */
#define ARM_CEXT_XSCALE   0x00000001	/* Allow MIA etc.          */
#define ARM_CEXT_MAVERICK 0x00000002	/* Use Cirrus/DSP coprocessor.  */
#define ARM_CEXT_IWMMXT   0x00000004    /* Intel Wireless MMX technology coprocessor.   */
#define ARM_CEXT_IWMMXT2  0x00000008    /* Intel Wireless MMX technology coprocessor version 2.   */

#define FPU_ENDIAN_PURE	 0x80000000	/* Pure-endian doubles.	      */
#define FPU_ENDIAN_BIG	 0		/* Double words-big-endian.   */
#define FPU_FPA_EXT_V1	 0x40000000	/* Base FPA instruction set.  */
#define FPU_FPA_EXT_V2	 0x20000000	/* LFM/SFM.		      */
#define FPU_MAVERICK	 0x10000000	/* Cirrus Maverick.	      */
#define FPU_VFP_EXT_V1xD 0x08000000	/* Base VFP instruction set.  */
#define FPU_VFP_EXT_V1	 0x04000000	/* Double-precision insns.    */
#define FPU_VFP_EXT_V2	 0x02000000	/* ARM10E VFPr1.	      */
#define FPU_VFP_EXT_V3xD 0x01000000	/* VFPv3 single-precision.    */
#define FPU_VFP_EXT_V3	 0x00800000	/* VFPv3 double-precision.    */
#define FPU_NEON_EXT_V1	 0x00400000	/* Neon (SIMD) insns.	      */
#define FPU_VFP_EXT_D32  0x00200000	/* Registers D16-D31.	      */
#define FPU_VFP_EXT_FP16 0x00100000	/* Half-precision extensions. */
#define FPU_NEON_EXT_FMA 0x00080000	/* Neon fused multiply-add    */
#define FPU_VFP_EXT_FMA	 0x00040000	/* VFP fused multiply-add     */
#define FPU_VFP_EXT_ARMV8 0x00020000	/* Double-precision FP for ARMv8.  */
#define FPU_NEON_EXT_ARMV8 0x00010000	/* Neon for ARMv8.  */
#define FPU_CRYPTO_EXT_ARMV8 0x00008000	/* Crypto for ARMv8.  */
#define CRC_EXT_ARMV8	 0x00004000	/* CRC32 for ARMv8.  */
#define FPU_VFP_EXT_ARMV8xD 0x00002000	/* Single-precision FP for ARMv8.  */
#define FPU_NEON_EXT_RDMA 0x00001000     /* v8.1 Adv.SIMD extensions.  */

/* Architectures are the sum of the base and extensions.  The ARM ARM (rev E)
   defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
   ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE.  To these we add
   three more to cover cores prior to ARM6.  Finally, there are cores which
   implement further extensions in the co-processor space.  */
#define ARM_AEXT_V1			  ARM_EXT_V1
#define ARM_AEXT_V2	(ARM_AEXT_V1	| ARM_EXT_V2)
#define ARM_AEXT_V2S	(ARM_AEXT_V2	| ARM_EXT_V2S)
#define ARM_AEXT_V3	(ARM_AEXT_V2S	| ARM_EXT_V3)
#define ARM_AEXT_V3M	(ARM_AEXT_V3	| ARM_EXT_V3M)
#define ARM_AEXT_V4xM	(ARM_AEXT_V3	| ARM_EXT_V4)
#define ARM_AEXT_V4	(ARM_AEXT_V3M	| ARM_EXT_V4)
#define ARM_AEXT_V4TxM	(ARM_AEXT_V4xM	| ARM_EXT_V4T)
#define ARM_AEXT_V4T	(ARM_AEXT_V4	| ARM_EXT_V4T)
#define ARM_AEXT_V5xM	(ARM_AEXT_V4xM	| ARM_EXT_V5)
#define ARM_AEXT_V5	(ARM_AEXT_V4	| ARM_EXT_V5)
#define ARM_AEXT_V5TxM	(ARM_AEXT_V5xM	| ARM_EXT_V4T | ARM_EXT_V5T)
#define ARM_AEXT_V5T	(ARM_AEXT_V5	| ARM_EXT_V4T | ARM_EXT_V5T)
#define ARM_AEXT_V5TExP	(ARM_AEXT_V5T	| ARM_EXT_V5ExP)
#define ARM_AEXT_V5TE	(ARM_AEXT_V5TExP | ARM_EXT_V5E)
#define ARM_AEXT_V5TEJ	(ARM_AEXT_V5TE	| ARM_EXT_V5J)
#define ARM_AEXT_V6     (ARM_AEXT_V5TEJ | ARM_EXT_V6)
#define ARM_AEXT_V6K    (ARM_AEXT_V6    | ARM_EXT_V6K)
#define ARM_AEXT_V6Z    (ARM_AEXT_V6K	| ARM_EXT_SEC)
#define ARM_AEXT_V6KZ   (ARM_AEXT_V6K	| ARM_EXT_SEC)
#define ARM_AEXT_V6T2   (ARM_AEXT_V6 \
    | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \
    | ARM_EXT_V6_DSP )
#define ARM_AEXT_V6KT2  (ARM_AEXT_V6T2 | ARM_EXT_V6K)
#define ARM_AEXT_V6ZT2  (ARM_AEXT_V6T2 | ARM_EXT_SEC)
#define ARM_AEXT_V6KZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
#define ARM_AEXT_V7_ARM	(ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
#define ARM_AEXT_V7A	(ARM_AEXT_V7_ARM | ARM_EXT_V7A)
#define ARM_AEXT_V7VE	(ARM_AEXT_V7A  | ARM_EXT_DIV | ARM_EXT_ADIV \
    | ARM_EXT_VIRT | ARM_EXT_SEC | ARM_EXT_MP)
#define ARM_AEXT_V7R	(ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
#define ARM_AEXT_NOTM \
  (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \
   | ARM_EXT_V6_DSP )
#define ARM_AEXT_V6M_ONLY \
  ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM))
#define ARM_AEXT_V6M \
  ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM))
#define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS)
#define ARM_AEXT_V7M \
  ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \
   & ~(ARM_AEXT_NOTM))
#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
#define ARM_AEXT_V7EM \
  (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP)
#define ARM_AEXT_V8A \
  (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \
   | ARM_EXT_VIRT | ARM_EXT_V8)

/* Processors with specific extensions in the co-processor space.  */
#define ARM_ARCH_XSCALE	ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
#define ARM_ARCH_IWMMXT	\
 ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT)
#define ARM_ARCH_IWMMXT2	\
 ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT \
		  | ARM_CEXT_IWMMXT2)

#define FPU_VFP_V1xD	(FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
#define FPU_VFP_V1	(FPU_VFP_V1xD | FPU_VFP_EXT_V1)
#define FPU_VFP_V2	(FPU_VFP_V1 | FPU_VFP_EXT_V2)
#define FPU_VFP_V3D16	(FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3)
#define FPU_VFP_V3	(FPU_VFP_V3D16 | FPU_VFP_EXT_D32)
#define FPU_VFP_V3xD	(FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD)
#define FPU_VFP_V4D16	(FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
#define FPU_VFP_V4	(FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
#define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
#define FPU_VFP_V5D16	(FPU_VFP_V4D16 | FPU_VFP_EXT_ARMV8xD | FPU_VFP_EXT_ARMV8)
#define FPU_VFP_V5_SP_D16 (FPU_VFP_V4_SP_D16 | FPU_VFP_EXT_ARMV8xD)
#define FPU_VFP_ARMV8	(FPU_VFP_V4 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)
#define FPU_NEON_ARMV8	(FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8)
#define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8)
#define FPU_VFP_HARD	(FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
			 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \
                         | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32)
#define FPU_FPA		(FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)

/* Deprecated.  */
#define FPU_ARCH_VFP	ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)

#define FPU_ARCH_FPE	ARM_FEATURE_COPROC (FPU_FPA_EXT_V1)
#define FPU_ARCH_FPA	ARM_FEATURE_COPROC (FPU_FPA)

#define FPU_ARCH_VFP_V1xD ARM_FEATURE_COPROC (FPU_VFP_V1xD)
#define FPU_ARCH_VFP_V1	  ARM_FEATURE_COPROC (FPU_VFP_V1)
#define FPU_ARCH_VFP_V2	  ARM_FEATURE_COPROC (FPU_VFP_V2)
#define FPU_ARCH_VFP_V3D16	ARM_FEATURE_COPROC (FPU_VFP_V3D16)
#define FPU_ARCH_VFP_V3D16_FP16 \
  ARM_FEATURE_COPROC (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16)
#define FPU_ARCH_VFP_V3	  ARM_FEATURE_COPROC (FPU_VFP_V3)
#define FPU_ARCH_VFP_V3_FP16	ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_VFP_EXT_FP16)
#define FPU_ARCH_VFP_V3xD	ARM_FEATURE_COPROC (FPU_VFP_V3xD)
#define FPU_ARCH_VFP_V3xD_FP16	ARM_FEATURE_COPROC (FPU_VFP_V3xD \
						 | FPU_VFP_EXT_FP16)
#define FPU_ARCH_NEON_V1  ARM_FEATURE_COPROC (FPU_NEON_EXT_V1)
#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
  ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)
#define FPU_ARCH_NEON_FP16 \
  ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16)
#define FPU_ARCH_VFP_HARD ARM_FEATURE_COPROC (FPU_VFP_HARD)
#define FPU_ARCH_VFP_V4 ARM_FEATURE_COPROC (FPU_VFP_V4)
#define FPU_ARCH_VFP_V4D16 ARM_FEATURE_COPROC (FPU_VFP_V4D16)
#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16)
#define FPU_ARCH_VFP_V5D16 ARM_FEATURE_COPROC (FPU_VFP_V5D16)
#define FPU_ARCH_VFP_V5_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16)
#define FPU_ARCH_NEON_VFP_V4 \
  ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)
#define FPU_ARCH_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_VFP_ARMV8)
#define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \
						 | FPU_VFP_ARMV8)
#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \
  ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
#define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8)
#define FPU_ARCH_NEON_VFP_ARMV8_1 \
  ARM_FEATURE_COPROC (FPU_NEON_ARMV8				 \
		      | FPU_VFP_ARMV8				 \
		      | FPU_NEON_EXT_RDMA)
#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1 \
  ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8 \
		      | FPU_NEON_EXT_RDMA)


#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)

#define FPU_ARCH_MAVERICK ARM_FEATURE_COPROC (FPU_MAVERICK)

#define ARM_ARCH_V1	ARM_FEATURE_CORE_LOW (ARM_AEXT_V1)
#define ARM_ARCH_V2	ARM_FEATURE_CORE_LOW (ARM_AEXT_V2)
#define ARM_ARCH_V2S	ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S)
#define ARM_ARCH_V3	ARM_FEATURE_CORE_LOW (ARM_AEXT_V3)
#define ARM_ARCH_V3M	ARM_FEATURE_CORE_LOW (ARM_AEXT_V3M)
#define ARM_ARCH_V4xM	ARM_FEATURE_CORE_LOW (ARM_AEXT_V4xM)
#define ARM_ARCH_V4	ARM_FEATURE_CORE_LOW (ARM_AEXT_V4)
#define ARM_ARCH_V4TxM	ARM_FEATURE_CORE_LOW (ARM_AEXT_V4TxM)
#define ARM_ARCH_V4T	ARM_FEATURE_CORE_LOW (ARM_AEXT_V4T)
#define ARM_ARCH_V5xM	ARM_FEATURE_CORE_LOW (ARM_AEXT_V5xM)
#define ARM_ARCH_V5	ARM_FEATURE_CORE_LOW (ARM_AEXT_V5)
#define ARM_ARCH_V5TxM	ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TxM)
#define ARM_ARCH_V5T	ARM_FEATURE_CORE_LOW (ARM_AEXT_V5T)
#define ARM_ARCH_V5TExP	ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TExP)
#define ARM_ARCH_V5TE	ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TE)
#define ARM_ARCH_V5TEJ	ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TEJ)
#define ARM_ARCH_V6	ARM_FEATURE_CORE_LOW (ARM_AEXT_V6)
#define ARM_ARCH_V6K	ARM_FEATURE_CORE_LOW (ARM_AEXT_V6K)
#define ARM_ARCH_V6Z	ARM_FEATURE_CORE_LOW (ARM_AEXT_V6Z)
#define ARM_ARCH_V6KZ	ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZ)
#define ARM_ARCH_V6T2	ARM_FEATURE_CORE_LOW (ARM_AEXT_V6T2)
#define ARM_ARCH_V6KT2	ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KT2)
#define ARM_ARCH_V6ZT2	ARM_FEATURE_CORE_LOW (ARM_AEXT_V6ZT2)
#define ARM_ARCH_V6KZT2	ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZT2)
#define ARM_ARCH_V6M	ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M)
#define ARM_ARCH_V6SM	ARM_FEATURE_CORE_LOW (ARM_AEXT_V6SM)
#define ARM_ARCH_V7	ARM_FEATURE_CORE_LOW (ARM_AEXT_V7)
#define ARM_ARCH_V7A	ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A)
#define ARM_ARCH_V7VE	ARM_FEATURE_CORE_LOW (ARM_AEXT_V7VE)
#define ARM_ARCH_V7R	ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R)
#define ARM_ARCH_V7M	ARM_FEATURE_CORE_LOW (ARM_AEXT_V7M)
#define ARM_ARCH_V7EM	ARM_FEATURE_CORE_LOW (ARM_AEXT_V7EM)
#define ARM_ARCH_V8A	ARM_FEATURE_CORE_LOW (ARM_AEXT_V8A)
#define ARM_ARCH_V8_1A	ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_EXT2_PAN)
#define ARM_ARCH_V8_2A	ARM_FEATURE_CORE (ARM_AEXT_V8A, \
					  ARM_EXT2_PAN | ARM_EXT2_V8_2A)

/* Some useful combinations:  */
#define ARM_ARCH_NONE	ARM_FEATURE_LOW (0, 0)
#define FPU_NONE	ARM_FEATURE_LOW (0, 0)
#define ARM_ANY		ARM_FEATURE (-1, -1, 0)	/* Any basic core.  */
#define ARM_FEATURE_ALL	ARM_FEATURE (-1, -1, -1)/* All CPU and FPU features.  */
#define FPU_ANY_HARD	ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
#define ARM_ARCH_THUMB2 ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2 | ARM_EXT_V7 \
					      | ARM_EXT_V7A | ARM_EXT_V7R \
					      | ARM_EXT_V7M | ARM_EXT_DIV)
/* v7-a+sec.  */
#define ARM_ARCH_V7A_SEC ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_SEC)
/* v7-a+mp+sec.  */
#define ARM_ARCH_V7A_MP_SEC \
			ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC)
/* v7-r+idiv.  */
#define ARM_ARCH_V7R_IDIV	ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R | ARM_EXT_ADIV)
/* Features that are present in v6M and v6S-M but not other v6 cores.  */
#define ARM_ARCH_V6M_ONLY ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M_ONLY)
/* v8-a+fp.  */
#define ARM_ARCH_V8A_FP	ARM_FEATURE_LOW (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8)
/* v8-a+simd (implies fp).  */
#define ARM_ARCH_V8A_SIMD	ARM_FEATURE_LOW (ARM_AEXT_V8A, \
					     FPU_ARCH_NEON_VFP_ARMV8)
/* v8-a+crypto (implies simd+fp).  */
#define ARM_ARCH_V8A_CRYPTOV1 	ARM_FEATURE_LOW (ARM_AEXT_V8A, \
					     FPU_ARCH_CRYPTO_NEON_VFP_ARMV8)

/* v8.1-a+fp.  */
#define ARM_ARCH_V8_1A_FP	ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \
				     FPU_ARCH_VFP_ARMV8)
/* v8.1-a+simd (implies fp).  */
#define ARM_ARCH_V8_1A_SIMD	ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \
				     FPU_ARCH_NEON_VFP_ARMV8_1)
/* v8.1-a+crypto (implies simd+fp).  */
#define ARM_ARCH_V8_1A_CRYPTOV1   ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \
					       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1)


/* There are too many feature bits to fit in a single word, so use a
   structure.  For simplicity we put all core features in array CORE
   and everything else in the other.  All the bits in element core[0]
   have been occupied, so new feature should use bit in element core[1]
   and use macro ARM_FEATURE to initialize the feature set variable.  */
typedef struct
{
  unsigned long core[2];
  unsigned long coproc;
} arm_feature_set;

#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
  (((CPU).core[0] & (FEAT).core[0]) != 0 \
   || ((CPU).core[1] & (FEAT).core[1]) != 0 \
   || ((CPU).coproc & (FEAT).coproc) != 0)

#define ARM_CPU_IS_ANY(CPU) \
  ((CPU).core[0] == ((arm_feature_set)ARM_ANY).core[0] \
   && (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1])

#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2)	\
  do {						\
    (TARG).core[0] = (F1).core[0] | (F2).core[0];\
    (TARG).core[1] = (F1).core[1] | (F2).core[1];\
    (TARG).coproc = (F1).coproc | (F2).coproc;	\
  } while (0)

#define ARM_CLEAR_FEATURE(TARG,F1,F2)		\
  do {						\
    (TARG).core[0] = (F1).core[0] &~ (F2).core[0];\
    (TARG).core[1] = (F1).core[1] &~ (F2).core[1];\
    (TARG).coproc = (F1).coproc &~ (F2).coproc;	\
  } while (0)

#define ARM_FEATURE_COPY(F1, F2)		\
  do {						\
      (F1).core[0] = (F2).core[0];		\
      (F1).core[1] = (F2).core[1];		\
      (F1).coproc = (F2).coproc;		\
  } while (0)

#define ARM_FEATURE_EQUAL(T1,T2)		\
  ((T1).core[0] == (T2).core[0]			\
   && (T1).core[1] == (T2).core[1]		\
   && (T1).coproc == (T2).coproc)

#define ARM_FEATURE_ZERO(T)			\
  ((T).core[0] == 0 && (T).core[1] == 0 && (T).coproc == 0)

#define ARM_FEATURE_CORE_EQUAL(T1, T2)		\
  ((T1).core[0] == (T2).core[0] && (T1).core[1] == (T2).core[1])

#define ARM_FEATURE_LOW(core, coproc) {{(core), 0}, (coproc)}
#define ARM_FEATURE_CORE(core1, core2) {{(core1), (core2)}, 0}
#define ARM_FEATURE_CORE_LOW(core) {{(core), 0}, 0}
#define ARM_FEATURE_CORE_HIGH(core) {{0, (core)}, 0}
#define ARM_FEATURE_COPROC(coproc) {{0, 0}, (coproc)}
#define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2)}, (coproc)}
Commit	Line	Data
b781e558	1	/* ARM assembler/disassembler support.
b90efa5b	2	Copyright (C) 2004-2015 Free Software Foundation, Inc.
b781e558 RE	3
	4	This file is part of GDB and GAS.
	5
	6	GDB and GAS are free software; you can redistribute it and/or
	7	modify it under the terms of the GNU General Public License as
e4e42b45	8	published by the Free Software Foundation; either version 3, or (at
b781e558 RE	9	your option) any later version.
	10
	11	GDB and GAS are distributed in the hope that it will be useful, but
	12	WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
e4e42b45 NC	17	along with GDB or GAS; see the file COPYING3. If not, write to the
	18	Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
	19	MA 02110-1301, USA. */
b781e558 RE	20
	21	/* The following bitmasks control CPU extensions: */
	22	#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
	23	#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
	24	#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */
	25	#define ARM_EXT_V3 0x00000008 /* MSR MRS. */
	26	#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
	27	#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
0a003adc	28	#define ARM_EXT_V4T 0x00000040 /* Thumb. */
b781e558	29	#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
0a003adc	30	#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */
b781e558 RE	31	#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
	32	#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
	33	#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
	34	#define ARM_EXT_V6 0x00001000 /* ARM V6. */
0dd132b6	35	#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
f4c65163	36	/* 0x00004000 Was ARM V6Z. */
bca38921	37	#define ARM_EXT_V8 0x00004000 /* is now ARMv8. */
0a003adc	38	#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
62b3e311 PB	39	#define ARM_EXT_DIV 0x00010000 /* Integer division. */
	40	/* The 'M' in Arm V7M stands for Microcontroller.
	41	On earlier architecture variants it stands for Multiply. */
	42	#define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */
	43	#define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */
	44	#define ARM_EXT_V7 0x00080000 /* Arm V7. */
	45	#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */
	46	#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */
	47	#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */
7e806470 PB	48	#define ARM_EXT_V6M 0x00800000 /* ARM V6M. */
	49	#define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */
	50	#define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */
9e3c6df6 PB	51	#define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related),
9e3c6df6 PB	52	not in v7-M. */
60e5ef9f	53	#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */
f4c65163	54	#define ARM_EXT_SEC 0x10000000 /* Security extensions. */
b2a5fbdc	55	#define ARM_EXT_OS 0x20000000 /* OS Extensions. */
eea54501 MGD	56	#define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM
eea54501 MGD	57	state. */
90ec0d68	58	#define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */
b781e558	59
ddfded2f	60	#define ARM_EXT2_PAN 0x00000001 /* PAN extension. */
56a1b672	61	#define ARM_EXT2_V8_2A 0x00000002 /* ARM V8.2A. */
ddfded2f	62
b781e558	63	/* Co-processor space extensions. */
e74cfd16 PB	64	#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
	65	#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */
	66	#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */
2d447fca	67	#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */
e74cfd16 PB	68
	69	#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */
	70	#define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */
	71	#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */
	72	#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */
	73	#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */
	74	#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
	75	#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
	76	#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
62f3b8c8 PB	77	#define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */
	78	#define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */
	79	#define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */
	80	#define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */
	81	#define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */
	82	#define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */
	83	#define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */
a715796b	84	#define FPU_VFP_EXT_ARMV8 0x00020000 /* Double-precision FP for ARMv8. */
bca38921 MGD	85	#define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */
bca38921 MGD	86	#define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */
dd5181d5	87	#define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */
a715796b	88	#define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */
d6b4b13e	89	#define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */
b781e558 RE	90
	91	/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
	92	defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
	93	ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
	94	three more to cover cores prior to ARM6. Finally, there are cores which
	95	implement further extensions in the co-processor space. */
e74cfd16 PB	96	#define ARM_AEXT_V1 ARM_EXT_V1
	97	#define ARM_AEXT_V2 (ARM_AEXT_V1 \| ARM_EXT_V2)
	98	#define ARM_AEXT_V2S (ARM_AEXT_V2 \| ARM_EXT_V2S)
	99	#define ARM_AEXT_V3 (ARM_AEXT_V2S \| ARM_EXT_V3)
	100	#define ARM_AEXT_V3M (ARM_AEXT_V3 \| ARM_EXT_V3M)
	101	#define ARM_AEXT_V4xM (ARM_AEXT_V3 \| ARM_EXT_V4)
	102	#define ARM_AEXT_V4 (ARM_AEXT_V3M \| ARM_EXT_V4)
	103	#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM \| ARM_EXT_V4T)
	104	#define ARM_AEXT_V4T (ARM_AEXT_V4 \| ARM_EXT_V4T)
	105	#define ARM_AEXT_V5xM (ARM_AEXT_V4xM \| ARM_EXT_V5)
	106	#define ARM_AEXT_V5 (ARM_AEXT_V4 \| ARM_EXT_V5)
	107	#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM \| ARM_EXT_V4T \| ARM_EXT_V5T)
	108	#define ARM_AEXT_V5T (ARM_AEXT_V5 \| ARM_EXT_V4T \| ARM_EXT_V5T)
	109	#define ARM_AEXT_V5TExP (ARM_AEXT_V5T \| ARM_EXT_V5ExP)
	110	#define ARM_AEXT_V5TE (ARM_AEXT_V5TExP \| ARM_EXT_V5E)
	111	#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE \| ARM_EXT_V5J)
	112	#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ \| ARM_EXT_V6)
	113	#define ARM_AEXT_V6K (ARM_AEXT_V6 \| ARM_EXT_V6K)
f4c65163	114	#define ARM_AEXT_V6Z (ARM_AEXT_V6K \| ARM_EXT_SEC)
f33026a9	115	#define ARM_AEXT_V6KZ (ARM_AEXT_V6K \| ARM_EXT_SEC)
7e806470	116	#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \
9e3c6df6 PB	117	\| ARM_EXT_V6T2 \| ARM_EXT_V6_NOTM \| ARM_EXT_THUMB_MSR \
9e3c6df6 PB	118	\| ARM_EXT_V6_DSP )
62b3e311	119	#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 \| ARM_EXT_V6K)
f4c65163	120	#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 \| ARM_EXT_SEC)
f33026a9	121	#define ARM_AEXT_V6KZT2 (ARM_AEXT_V6T2 \| ARM_EXT_V6K \| ARM_EXT_SEC)
ac7f631b	122	#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 \| ARM_EXT_V7 \| ARM_EXT_BARRIER)
62b3e311	123	#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM \| ARM_EXT_V7A)
c9fb6e58 YZ	124	#define ARM_AEXT_V7VE (ARM_AEXT_V7A \| ARM_EXT_DIV \| ARM_EXT_ADIV \
c9fb6e58 YZ	125	\| ARM_EXT_VIRT \| ARM_EXT_SEC \| ARM_EXT_MP)
62b3e311 PB	126	#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM \| ARM_EXT_V7R \| ARM_EXT_DIV)
62b3e311 PB	127	#define ARM_AEXT_NOTM \
9e3c6df6 PB	128	(ARM_AEXT_V4 \| ARM_EXT_V5ExP \| ARM_EXT_V5J \| ARM_EXT_V6_NOTM \
9e3c6df6 PB	129	\| ARM_EXT_V6_DSP )
251665fc MGD	130	#define ARM_AEXT_V6M_ONLY \
251665fc MGD	131	((ARM_EXT_BARRIER \| ARM_EXT_V6M \| ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM))
7e806470	132	#define ARM_AEXT_V6M \
251665fc	133	((ARM_AEXT_V6K \| ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM))
b2a5fbdc	134	#define ARM_AEXT_V6SM (ARM_AEXT_V6M \| ARM_EXT_OS)
62b3e311	135	#define ARM_AEXT_V7M \
7e806470 PB	136	((ARM_AEXT_V7_ARM \| ARM_EXT_V6M \| ARM_EXT_V7M \| ARM_EXT_DIV) \
7e806470 PB	137	& ~(ARM_AEXT_NOTM))
62b3e311	138	#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
9e3c6df6 PB	139	#define ARM_AEXT_V7EM \
9e3c6df6 PB	140	(ARM_AEXT_V7M \| ARM_EXT_V5ExP \| ARM_EXT_V6_DSP)
bca38921 MGD	141	#define ARM_AEXT_V8A \
	142	(ARM_AEXT_V7A \| ARM_EXT_MP \| ARM_EXT_SEC \| ARM_EXT_DIV \| ARM_EXT_ADIV \
	143	\| ARM_EXT_VIRT \| ARM_EXT_V8)
b781e558 RE	144
b781e558 RE	145	/* Processors with specific extensions in the co-processor space. */
823d2571	146	#define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
e74cfd16	147	#define ARM_ARCH_IWMMXT \
823d2571	148	ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE \| ARM_CEXT_IWMMXT)
2d447fca	149	#define ARM_ARCH_IWMMXT2 \
823d2571 TG	150	ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE \| ARM_CEXT_IWMMXT \
823d2571 TG	151	\| ARM_CEXT_IWMMXT2)
e74cfd16 PB	152
	153	#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD \| FPU_ENDIAN_PURE)
	154	#define FPU_VFP_V1 (FPU_VFP_V1xD \| FPU_VFP_EXT_V1)
	155	#define FPU_VFP_V2 (FPU_VFP_V1 \| FPU_VFP_EXT_V2)
62f3b8c8	156	#define FPU_VFP_V3D16 (FPU_VFP_V2 \| FPU_VFP_EXT_V3xD \| FPU_VFP_EXT_V3)
b1cc4aeb	157	#define FPU_VFP_V3 (FPU_VFP_V3D16 \| FPU_VFP_EXT_D32)
62f3b8c8 PB	158	#define FPU_VFP_V3xD (FPU_VFP_V1xD \| FPU_VFP_EXT_V2 \| FPU_VFP_EXT_V3xD)
	159	#define FPU_VFP_V4D16 (FPU_VFP_V3D16 \| FPU_VFP_EXT_FP16 \| FPU_VFP_EXT_FMA)
	160	#define FPU_VFP_V4 (FPU_VFP_V3 \| FPU_VFP_EXT_FP16 \| FPU_VFP_EXT_FMA)
ada65aa3	161	#define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD \| FPU_VFP_EXT_FP16 \| FPU_VFP_EXT_FMA)
a715796b TG	162	#define FPU_VFP_V5D16 (FPU_VFP_V4D16 \| FPU_VFP_EXT_ARMV8xD \| FPU_VFP_EXT_ARMV8)
	163	#define FPU_VFP_V5_SP_D16 (FPU_VFP_V4_SP_D16 \| FPU_VFP_EXT_ARMV8xD)
	164	#define FPU_VFP_ARMV8 (FPU_VFP_V4 \| FPU_VFP_EXT_ARMV8 \| FPU_VFP_EXT_ARMV8xD)
bca38921 MGD	165	#define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 \| FPU_NEON_EXT_FMA \| FPU_NEON_EXT_ARMV8)
bca38921 MGD	166	#define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8)
9e498214	167	#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD \| FPU_VFP_EXT_V1 \| FPU_VFP_EXT_V2 \
62f3b8c8	168	\| FPU_VFP_EXT_V3xD \| FPU_VFP_EXT_FMA \| FPU_NEON_EXT_FMA \
b1cc4aeb	169	\| FPU_VFP_EXT_V3 \| FPU_NEON_EXT_V1 \| FPU_VFP_EXT_D32)
e74cfd16 PB	170	#define FPU_FPA (FPU_FPA_EXT_V1 \| FPU_FPA_EXT_V2)
e74cfd16 PB	171
84701018	172	/* Deprecated. */
823d2571	173	#define FPU_ARCH_VFP ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
b781e558	174
823d2571 TG	175	#define FPU_ARCH_FPE ARM_FEATURE_COPROC (FPU_FPA_EXT_V1)
823d2571 TG	176	#define FPU_ARCH_FPA ARM_FEATURE_COPROC (FPU_FPA)
b781e558	177
823d2571 TG	178	#define FPU_ARCH_VFP_V1xD ARM_FEATURE_COPROC (FPU_VFP_V1xD)
	179	#define FPU_ARCH_VFP_V1 ARM_FEATURE_COPROC (FPU_VFP_V1)
	180	#define FPU_ARCH_VFP_V2 ARM_FEATURE_COPROC (FPU_VFP_V2)
	181	#define FPU_ARCH_VFP_V3D16 ARM_FEATURE_COPROC (FPU_VFP_V3D16)
62f3b8c8	182	#define FPU_ARCH_VFP_V3D16_FP16 \
823d2571 TG	183	ARM_FEATURE_COPROC (FPU_VFP_V3D16 \| FPU_VFP_EXT_FP16)
	184	#define FPU_ARCH_VFP_V3 ARM_FEATURE_COPROC (FPU_VFP_V3)
	185	#define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3 \| FPU_VFP_EXT_FP16)
	186	#define FPU_ARCH_VFP_V3xD ARM_FEATURE_COPROC (FPU_VFP_V3xD)
	187	#define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3xD \
	188	\| FPU_VFP_EXT_FP16)
	189	#define FPU_ARCH_NEON_V1 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1)
9e498214	190	#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
823d2571	191	ARM_FEATURE_COPROC (FPU_VFP_V3 \| FPU_NEON_EXT_V1)
8e79c3df	192	#define FPU_ARCH_NEON_FP16 \
823d2571 TG	193	ARM_FEATURE_COPROC (FPU_VFP_V3 \| FPU_NEON_EXT_V1 \| FPU_VFP_EXT_FP16)
	194	#define FPU_ARCH_VFP_HARD ARM_FEATURE_COPROC (FPU_VFP_HARD)
	195	#define FPU_ARCH_VFP_V4 ARM_FEATURE_COPROC (FPU_VFP_V4)
	196	#define FPU_ARCH_VFP_V4D16 ARM_FEATURE_COPROC (FPU_VFP_V4D16)
	197	#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16)
	198	#define FPU_ARCH_VFP_V5D16 ARM_FEATURE_COPROC (FPU_VFP_V5D16)
	199	#define FPU_ARCH_VFP_V5_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16)
62f3b8c8	200	#define FPU_ARCH_NEON_VFP_V4 \
823d2571 TG	201	ARM_FEATURE_COPROC (FPU_VFP_V4 \| FPU_NEON_EXT_V1 \| FPU_NEON_EXT_FMA)
	202	#define FPU_ARCH_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_VFP_ARMV8)
	203	#define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \
	204	\| FPU_VFP_ARMV8)
bca38921	205	#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \
823d2571 TG	206	ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 \| FPU_NEON_ARMV8 \| FPU_VFP_ARMV8)
823d2571 TG	207	#define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8)
d6b4b13e MW	208	#define FPU_ARCH_NEON_VFP_ARMV8_1 \
	209	ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \
	210	\| FPU_VFP_ARMV8 \
	211	\| FPU_NEON_EXT_RDMA)
a5932920 MW	212	#define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1 \
	213	ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 \| FPU_NEON_ARMV8 \| FPU_VFP_ARMV8 \
	214	\| FPU_NEON_EXT_RDMA)
d6b4b13e	215
b781e558	216
823d2571	217	#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
b781e558	218
823d2571	219	#define FPU_ARCH_MAVERICK ARM_FEATURE_COPROC (FPU_MAVERICK)
e74cfd16	220
823d2571 TG	221	#define ARM_ARCH_V1 ARM_FEATURE_CORE_LOW (ARM_AEXT_V1)
	222	#define ARM_ARCH_V2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V2)
	223	#define ARM_ARCH_V2S ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S)
	224	#define ARM_ARCH_V3 ARM_FEATURE_CORE_LOW (ARM_AEXT_V3)
	225	#define ARM_ARCH_V3M ARM_FEATURE_CORE_LOW (ARM_AEXT_V3M)
	226	#define ARM_ARCH_V4xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4xM)
	227	#define ARM_ARCH_V4 ARM_FEATURE_CORE_LOW (ARM_AEXT_V4)
	228	#define ARM_ARCH_V4TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4TxM)
	229	#define ARM_ARCH_V4T ARM_FEATURE_CORE_LOW (ARM_AEXT_V4T)
	230	#define ARM_ARCH_V5xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5xM)
	231	#define ARM_ARCH_V5 ARM_FEATURE_CORE_LOW (ARM_AEXT_V5)
	232	#define ARM_ARCH_V5TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TxM)
	233	#define ARM_ARCH_V5T ARM_FEATURE_CORE_LOW (ARM_AEXT_V5T)
	234	#define ARM_ARCH_V5TExP ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TExP)
	235	#define ARM_ARCH_V5TE ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TE)
	236	#define ARM_ARCH_V5TEJ ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TEJ)
	237	#define ARM_ARCH_V6 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6)
	238	#define ARM_ARCH_V6K ARM_FEATURE_CORE_LOW (ARM_AEXT_V6K)
	239	#define ARM_ARCH_V6Z ARM_FEATURE_CORE_LOW (ARM_AEXT_V6Z)
f33026a9	240	#define ARM_ARCH_V6KZ ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZ)
823d2571 TG	241	#define ARM_ARCH_V6T2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6T2)
	242	#define ARM_ARCH_V6KT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KT2)
	243	#define ARM_ARCH_V6ZT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6ZT2)
f33026a9	244	#define ARM_ARCH_V6KZT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZT2)
823d2571 TG	245	#define ARM_ARCH_V6M ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M)
	246	#define ARM_ARCH_V6SM ARM_FEATURE_CORE_LOW (ARM_AEXT_V6SM)
	247	#define ARM_ARCH_V7 ARM_FEATURE_CORE_LOW (ARM_AEXT_V7)
	248	#define ARM_ARCH_V7A ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A)
	249	#define ARM_ARCH_V7VE ARM_FEATURE_CORE_LOW (ARM_AEXT_V7VE)
	250	#define ARM_ARCH_V7R ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R)
	251	#define ARM_ARCH_V7M ARM_FEATURE_CORE_LOW (ARM_AEXT_V7M)
	252	#define ARM_ARCH_V7EM ARM_FEATURE_CORE_LOW (ARM_AEXT_V7EM)
	253	#define ARM_ARCH_V8A ARM_FEATURE_CORE_LOW (ARM_AEXT_V8A)
a5932920	254	#define ARM_ARCH_V8_1A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_EXT2_PAN)
56a1b672 MW	255	#define ARM_ARCH_V8_2A ARM_FEATURE_CORE (ARM_AEXT_V8A, \
56a1b672 MW	256	ARM_EXT2_PAN \| ARM_EXT2_V8_2A)
b781e558 RE	257
b781e558 RE	258	/* Some useful combinations: */
823d2571 TG	259	#define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0)
	260	#define FPU_NONE ARM_FEATURE_LOW (0, 0)
	261	#define ARM_ANY ARM_FEATURE (-1, -1, 0) /* Any basic core. */
1af1dd51	262	#define ARM_FEATURE_ALL ARM_FEATURE (-1, -1, -1)/* All CPU and FPU features. */
823d2571 TG	263	#define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA \| FPU_VFP_HARD \| FPU_MAVERICK)
	264	#define ARM_ARCH_THUMB2 ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2 \| ARM_EXT_V7 \
	265	\| ARM_EXT_V7A \| ARM_EXT_V7R \
	266	\| ARM_EXT_V7M \| ARM_EXT_DIV)
f4c65163	267	/* v7-a+sec. */
823d2571	268	#define ARM_ARCH_V7A_SEC ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A \| ARM_EXT_SEC)
f4c65163 MGD	269	/* v7-a+mp+sec. */
f4c65163 MGD	270	#define ARM_ARCH_V7A_MP_SEC \
823d2571	271	ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A \| ARM_EXT_MP \| ARM_EXT_SEC)
3b2f0793	272	/* v7-r+idiv. */
823d2571	273	#define ARM_ARCH_V7R_IDIV ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R \| ARM_EXT_ADIV)
251665fc	274	/* Features that are present in v6M and v6S-M but not other v6 cores. */
823d2571	275	#define ARM_ARCH_V6M_ONLY ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M_ONLY)
bca38921	276	/* v8-a+fp. */
823d2571	277	#define ARM_ARCH_V8A_FP ARM_FEATURE_LOW (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8)
bca38921	278	/* v8-a+simd (implies fp). */
823d2571	279	#define ARM_ARCH_V8A_SIMD ARM_FEATURE_LOW (ARM_AEXT_V8A, \
bca38921 MGD	280	FPU_ARCH_NEON_VFP_ARMV8)
bca38921 MGD	281	/* v8-a+crypto (implies simd+fp). */
823d2571	282	#define ARM_ARCH_V8A_CRYPTOV1 ARM_FEATURE_LOW (ARM_AEXT_V8A, \
bca38921	283	FPU_ARCH_CRYPTO_NEON_VFP_ARMV8)
e74cfd16	284
a5932920 MW	285	/* v8.1-a+fp. */
	286	#define ARM_ARCH_V8_1A_FP ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \
	287	FPU_ARCH_VFP_ARMV8)
	288	/* v8.1-a+simd (implies fp). */
	289	#define ARM_ARCH_V8_1A_SIMD ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \
	290	FPU_ARCH_NEON_VFP_ARMV8_1)
	291	/* v8.1-a+crypto (implies simd+fp). */
	292	#define ARM_ARCH_V8_1A_CRYPTOV1 ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \
	293	FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1)
	294
	295
e74cfd16	296	/* There are too many feature bits to fit in a single word, so use a
823d2571 TG	297	structure. For simplicity we put all core features in array CORE
	298	and everything else in the other. All the bits in element core[0]
	299	have been occupied, so new feature should use bit in element core[1]
	300	and use macro ARM_FEATURE to initialize the feature set variable. */
e74cfd16 PB	301	typedef struct
e74cfd16 PB	302	{
823d2571	303	unsigned long core[2];
e74cfd16 PB	304	unsigned long coproc;
	305	} arm_feature_set;
	306
	307	#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
823d2571 TG	308	(((CPU).core[0] & (FEAT).core[0]) != 0 \
	309	\|\| ((CPU).core[1] & (FEAT).core[1]) != 0 \
	310	\|\| ((CPU).coproc & (FEAT).coproc) != 0)
e74cfd16	311
59d09be6	312	#define ARM_CPU_IS_ANY(CPU) \
823d2571 TG	313	((CPU).core[0] == ((arm_feature_set)ARM_ANY).core[0] \
823d2571 TG	314	&& (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1])
59d09be6	315
e74cfd16 PB	316	#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \
e74cfd16 PB	317	do { \
823d2571 TG	318	(TARG).core[0] = (F1).core[0] \| (F2).core[0];\
823d2571 TG	319	(TARG).core[1] = (F1).core[1] \| (F2).core[1];\
e74cfd16 PB	320	(TARG).coproc = (F1).coproc \| (F2).coproc; \
	321	} while (0)
	322
	323	#define ARM_CLEAR_FEATURE(TARG,F1,F2) \
	324	do { \
823d2571 TG	325	(TARG).core[0] = (F1).core[0] &~ (F2).core[0];\
823d2571 TG	326	(TARG).core[1] = (F1).core[1] &~ (F2).core[1];\
e74cfd16 PB	327	(TARG).coproc = (F1).coproc &~ (F2).coproc; \
	328	} while (0)
	329
823d2571 TG	330	#define ARM_FEATURE_COPY(F1, F2) \
	331	do { \
	332	(F1).core[0] = (F2).core[0]; \
	333	(F1).core[1] = (F2).core[1]; \
	334	(F1).coproc = (F2).coproc; \
	335	} while (0)
	336
	337	#define ARM_FEATURE_EQUAL(T1,T2) \
	338	((T1).core[0] == (T2).core[0] \
	339	&& (T1).core[1] == (T2).core[1] \
	340	&& (T1).coproc == (T2).coproc)
	341
	342	#define ARM_FEATURE_ZERO(T) \
	343	((T).core[0] == 0 && (T).core[1] == 0 && (T).coproc == 0)
	344
	345	#define ARM_FEATURE_CORE_EQUAL(T1, T2) \
	346	((T1).core[0] == (T2).core[0] && (T1).core[1] == (T2).core[1])
	347
	348	#define ARM_FEATURE_LOW(core, coproc) {{(core), 0}, (coproc)}
a5932920	349	#define ARM_FEATURE_CORE(core1, core2) {{(core1), (core2)}, 0}
823d2571	350	#define ARM_FEATURE_CORE_LOW(core) {{(core), 0}, 0}
ddfded2f	351	#define ARM_FEATURE_CORE_HIGH(core) {{0, (core)}, 0}
823d2571 TG	352	#define ARM_FEATURE_COPROC(coproc) {{0, 0}, (coproc)}
823d2571 TG	353	#define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2)}, (coproc)}