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[deliverable/binutils-gdb.git] / include / opcode / bfin.h
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dc603df5 1/* bfin.h -- Header file for ADI Blackfin opcode table
dd76fcb8 2 Copyright 2005, 2010, 2011 Free Software Foundation, Inc.
dc603df5 3
e4e42b45 4 This file is part of GDB, GAS, and the GNU binutils.
dc603df5 5
e4e42b45
NC		 6 GDB, GAS, and the GNU binutils are free software; you can redistribute
7 them and/or modify them under the terms of the GNU General Public
8 License as published by the Free Software Foundation; either version 3,
9 or (at your option) any later version.
dc603df5 10
e4e42b45
NC		 11 GDB, GAS, and the GNU binutils are distributed in the hope that they
12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
14 the GNU General Public License for more details.
dc603df5 15
e4e42b45
NC		 16 You should have received a copy of the GNU General Public License
17 along with this file; see the file COPYING3. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
dc603df5 20
dd76fcb8
MF		 21#ifndef OPCODE_BFIN_H
22#define OPCODE_BFIN_H
23
dc603df5
CM		 24/* Common to all DSP32 instructions. */
25#define BIT_MULTI_INS 0x0800
26
27/* This just sets the multi instruction bit of a DSP32 instruction. */
28#define SET_MULTI_INSTRUCTION_BIT(x) x->value |= BIT_MULTI_INS;
29
30
31/* DSP instructions (32 bit) */
32
26bb3ddd
MF		 33/* mmod field. */
34#define M_S2RND 1
35#define M_T 2
36#define M_W32 3
37#define M_FU 4
38#define M_TFU 6
39#define M_IS 8
40#define M_ISS2 9
41#define M_IH 11
42#define M_IU 12
43
44static inline int is_macmod_pmove(int x)
45{
46 return (x == 0) || (x == M_IS) || (x == M_FU) || (x == M_S2RND)
47 || (x == M_ISS2) || (x == M_IU);
48}
49
50static inline int is_macmod_hmove(int x)
51{
52 return (x == 0) || (x == M_IS) || (x == M_FU) || (x == M_IU) || (x == M_T)
53 || (x == M_TFU) || (x == M_S2RND) || (x == M_ISS2) || (x == M_IH);
54}
55
dc603df5
CM		 56/* dsp32mac
57+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
58| 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
59|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
60+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
61*/
62
63typedef struct
64{
65 unsigned long opcode;
66 int bits_src1;
67 int mask_src1;
ee99860a 68 int bits_src0;
dc603df5 69 int mask_src0;
ee99860a 70 int bits_dst;
dc603df5 71 int mask_dst;
ee99860a 72 int bits_h10;
dc603df5 73 int mask_h10;
ee99860a 74 int bits_h00;
dc603df5 75 int mask_h00;
ee99860a 76 int bits_op0;
dc603df5 77 int mask_op0;
ee99860a 78 int bits_w0;
dc603df5 79 int mask_w0;
ee99860a 80 int bits_h11;
dc603df5 81 int mask_h11;
ee99860a 82 int bits_h01;
dc603df5 83 int mask_h01;
ee99860a 84 int bits_op1;
dc603df5 85 int mask_op1;
ee99860a 86 int bits_w1;
dc603df5 87 int mask_w1;
ee99860a 88 int bits_P;
dc603df5 89 int mask_P;
ee99860a 90 int bits_MM;
dc603df5 91 int mask_MM;
ee99860a 92 int bits_mmod;
dc603df5 93 int mask_mmod;
ee99860a 94 int bits_code2;
dc603df5 95 int mask_code2;
ee99860a 96 int bits_M;
dc603df5 97 int mask_M;
ee99860a 98 int bits_code;
dc603df5
CM		 99 int mask_code;
100} DSP32Mac;
101
102#define DSP32Mac_opcode 0xc0000000
103#define DSP32Mac_src1_bits 0
104#define DSP32Mac_src1_mask 0x7
105#define DSP32Mac_src0_bits 3
106#define DSP32Mac_src0_mask 0x7
107#define DSP32Mac_dst_bits 6
108#define DSP32Mac_dst_mask 0x7
109#define DSP32Mac_h10_bits 9
110#define DSP32Mac_h10_mask 0x1
111#define DSP32Mac_h00_bits 10
112#define DSP32Mac_h00_mask 0x1
113#define DSP32Mac_op0_bits 11
114#define DSP32Mac_op0_mask 0x3
115#define DSP32Mac_w0_bits 13
116#define DSP32Mac_w0_mask 0x1
117#define DSP32Mac_h11_bits 14
118#define DSP32Mac_h11_mask 0x1
119#define DSP32Mac_h01_bits 15
120#define DSP32Mac_h01_mask 0x1
121#define DSP32Mac_op1_bits 16
122#define DSP32Mac_op1_mask 0x3
123#define DSP32Mac_w1_bits 18
124#define DSP32Mac_w1_mask 0x1
125#define DSP32Mac_p_bits 19
126#define DSP32Mac_p_mask 0x1
ee99860a 127#define DSP32Mac_MM_bits 20
dc603df5
CM		 128#define DSP32Mac_MM_mask 0x1
129#define DSP32Mac_mmod_bits 21
130#define DSP32Mac_mmod_mask 0xf
131#define DSP32Mac_code2_bits 25
132#define DSP32Mac_code2_mask 0x3
133#define DSP32Mac_M_bits 27
134#define DSP32Mac_M_mask 0x1
135#define DSP32Mac_code_bits 28
136#define DSP32Mac_code_mask 0xf
137
138#define init_DSP32Mac \
139{ \
140 DSP32Mac_opcode, \
141 DSP32Mac_src1_bits, DSP32Mac_src1_mask, \
142 DSP32Mac_src0_bits, DSP32Mac_src0_mask, \
143 DSP32Mac_dst_bits, DSP32Mac_dst_mask, \
144 DSP32Mac_h10_bits, DSP32Mac_h10_mask, \
145 DSP32Mac_h00_bits, DSP32Mac_h00_mask, \
146 DSP32Mac_op0_bits, DSP32Mac_op0_mask, \
147 DSP32Mac_w0_bits, DSP32Mac_w0_mask, \
148 DSP32Mac_h11_bits, DSP32Mac_h11_mask, \
149 DSP32Mac_h01_bits, DSP32Mac_h01_mask, \
150 DSP32Mac_op1_bits, DSP32Mac_op1_mask, \
151 DSP32Mac_w1_bits, DSP32Mac_w1_mask, \
152 DSP32Mac_p_bits, DSP32Mac_p_mask, \
153 DSP32Mac_MM_bits, DSP32Mac_MM_mask, \
154 DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \
155 DSP32Mac_code2_bits, DSP32Mac_code2_mask, \
156 DSP32Mac_M_bits, DSP32Mac_M_mask, \
157 DSP32Mac_code_bits, DSP32Mac_code_mask \
158};
159
160/* dsp32mult
161+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
162| 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
163|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
164+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
165*/
166
167typedef DSP32Mac DSP32Mult;
168#define DSP32Mult_opcode 0xc2000000
169
170#define init_DSP32Mult \
171{ \
172 DSP32Mult_opcode, \
173 DSP32Mac_src1_bits, DSP32Mac_src1_mask, \
174 DSP32Mac_src0_bits, DSP32Mac_src0_mask, \
175 DSP32Mac_dst_bits, DSP32Mac_dst_mask, \
176 DSP32Mac_h10_bits, DSP32Mac_h10_mask, \
177 DSP32Mac_h00_bits, DSP32Mac_h00_mask, \
178 DSP32Mac_op0_bits, DSP32Mac_op0_mask, \
179 DSP32Mac_w0_bits, DSP32Mac_w0_mask, \
180 DSP32Mac_h11_bits, DSP32Mac_h11_mask, \
181 DSP32Mac_h01_bits, DSP32Mac_h01_mask, \
182 DSP32Mac_op1_bits, DSP32Mac_op1_mask, \
183 DSP32Mac_w1_bits, DSP32Mac_w1_mask, \
184 DSP32Mac_p_bits, DSP32Mac_p_mask, \
185 DSP32Mac_MM_bits, DSP32Mac_MM_mask, \
186 DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \
187 DSP32Mac_code2_bits, DSP32Mac_code2_mask, \
188 DSP32Mac_M_bits, DSP32Mac_M_mask, \
189 DSP32Mac_code_bits, DSP32Mac_code_mask \
190};
191
192/* dsp32alu
193+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
194| 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
195|.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
196+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
197*/
198
199typedef struct
200{
201 unsigned long opcode;
202 int bits_src1;
203 int mask_src1;
204 int bits_src0;
205 int mask_src0;
206 int bits_dst1;
207 int mask_dst1;
208 int bits_dst0;
209 int mask_dst0;
210 int bits_x;
211 int mask_x;
212 int bits_s;
213 int mask_s;
214 int bits_aop;
215 int mask_aop;
216 int bits_aopcde;
217 int mask_aopcde;
218 int bits_HL;
219 int mask_HL;
220 int bits_dontcare;
221 int mask_dontcare;
222 int bits_code2;
223 int mask_code2;
224 int bits_M;
225 int mask_M;
226 int bits_code;
227 int mask_code;
228} DSP32Alu;
229
230#define DSP32Alu_opcode 0xc4000000
231#define DSP32Alu_src1_bits 0
232#define DSP32Alu_src1_mask 0x7
ee99860a 233#define DSP32Alu_src0_bits 3
dc603df5
CM		 234#define DSP32Alu_src0_mask 0x7
235#define DSP32Alu_dst1_bits 6
236#define DSP32Alu_dst1_mask 0x7
ee99860a 237#define DSP32Alu_dst0_bits 9
dc603df5
CM		 238#define DSP32Alu_dst0_mask 0x7
239#define DSP32Alu_x_bits 12
240#define DSP32Alu_x_mask 0x1
241#define DSP32Alu_s_bits 13
242#define DSP32Alu_s_mask 0x1
243#define DSP32Alu_aop_bits 14
244#define DSP32Alu_aop_mask 0x3
245#define DSP32Alu_aopcde_bits 16
246#define DSP32Alu_aopcde_mask 0x1f
247#define DSP32Alu_HL_bits 21
248#define DSP32Alu_HL_mask 0x1
249#define DSP32Alu_dontcare_bits 22
250#define DSP32Alu_dontcare_mask 0x7
251#define DSP32Alu_code2_bits 25
252#define DSP32Alu_code2_mask 0x3
253#define DSP32Alu_M_bits 27
254#define DSP32Alu_M_mask 0x1
255#define DSP32Alu_code_bits 28
256#define DSP32Alu_code_mask 0xf
257
258#define init_DSP32Alu \
259{ \
260 DSP32Alu_opcode, \
261 DSP32Alu_src1_bits, DSP32Alu_src1_mask, \
262 DSP32Alu_src0_bits, DSP32Alu_src0_mask, \
263 DSP32Alu_dst1_bits, DSP32Alu_dst1_mask, \
264 DSP32Alu_dst0_bits, DSP32Alu_dst0_mask, \
265 DSP32Alu_x_bits, DSP32Alu_x_mask, \
266 DSP32Alu_s_bits, DSP32Alu_s_mask, \
267 DSP32Alu_aop_bits, DSP32Alu_aop_mask, \
268 DSP32Alu_aopcde_bits, DSP32Alu_aopcde_mask, \
269 DSP32Alu_HL_bits, DSP32Alu_HL_mask, \
270 DSP32Alu_dontcare_bits, DSP32Alu_dontcare_mask, \
271 DSP32Alu_code2_bits, DSP32Alu_code2_mask, \
272 DSP32Alu_M_bits, DSP32Alu_M_mask, \
273 DSP32Alu_code_bits, DSP32Alu_code_mask \
274};
275
276/* dsp32shift
277+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
278| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
279|.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
280+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
281*/
282
283typedef struct
284{
285 unsigned long opcode;
286 int bits_src1;
287 int mask_src1;
288 int bits_src0;
289 int mask_src0;
290 int bits_dst1;
291 int mask_dst1;
292 int bits_dst0;
293 int mask_dst0;
294 int bits_HLs;
295 int mask_HLs;
296 int bits_sop;
297 int mask_sop;
298 int bits_sopcde;
299 int mask_sopcde;
300 int bits_dontcare;
301 int mask_dontcare;
302 int bits_code2;
303 int mask_code2;
304 int bits_M;
305 int mask_M;
306 int bits_code;
307 int mask_code;
308} DSP32Shift;
309
310#define DSP32Shift_opcode 0xc6000000
311#define DSP32Shift_src1_bits 0
312#define DSP32Shift_src1_mask 0x7
313#define DSP32Shift_src0_bits 3
314#define DSP32Shift_src0_mask 0x7
315#define DSP32Shift_dst1_bits 6
316#define DSP32Shift_dst1_mask 0x7
317#define DSP32Shift_dst0_bits 9
318#define DSP32Shift_dst0_mask 0x7
319#define DSP32Shift_HLs_bits 12
320#define DSP32Shift_HLs_mask 0x3
321#define DSP32Shift_sop_bits 14
322#define DSP32Shift_sop_mask 0x3
323#define DSP32Shift_sopcde_bits 16
324#define DSP32Shift_sopcde_mask 0x1f
325#define DSP32Shift_dontcare_bits 21
326#define DSP32Shift_dontcare_mask 0x3
327#define DSP32Shift_code2_bits 23
328#define DSP32Shift_code2_mask 0xf
329#define DSP32Shift_M_bits 27
330#define DSP32Shift_M_mask 0x1
331#define DSP32Shift_code_bits 28
332#define DSP32Shift_code_mask 0xf
333
334#define init_DSP32Shift \
335{ \
336 DSP32Shift_opcode, \
337 DSP32Shift_src1_bits, DSP32Shift_src1_mask, \
338 DSP32Shift_src0_bits, DSP32Shift_src0_mask, \
339 DSP32Shift_dst1_bits, DSP32Shift_dst1_mask, \
340 DSP32Shift_dst0_bits, DSP32Shift_dst0_mask, \
341 DSP32Shift_HLs_bits, DSP32Shift_HLs_mask, \
342 DSP32Shift_sop_bits, DSP32Shift_sop_mask, \
343 DSP32Shift_sopcde_bits, DSP32Shift_sopcde_mask, \
344 DSP32Shift_dontcare_bits, DSP32Shift_dontcare_mask, \
345 DSP32Shift_code2_bits, DSP32Shift_code2_mask, \
346 DSP32Shift_M_bits, DSP32Shift_M_mask, \
347 DSP32Shift_code_bits, DSP32Shift_code_mask \
348};
349
350/* dsp32shiftimm
351+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
352| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
353|.sop...|.HLs...|.dst0......|.immag.................|.src1......|
354+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
355*/
356
357typedef struct
358{
359 unsigned long opcode;
360 int bits_src1;
361 int mask_src1;
362 int bits_immag;
363 int mask_immag;
364 int bits_dst0;
365 int mask_dst0;
366 int bits_HLs;
367 int mask_HLs;
368 int bits_sop;
369 int mask_sop;
370 int bits_sopcde;
371 int mask_sopcde;
372 int bits_dontcare;
373 int mask_dontcare;
374 int bits_code2;
375 int mask_code2;
376 int bits_M;
377 int mask_M;
378 int bits_code;
379 int mask_code;
380} DSP32ShiftImm;
381
382#define DSP32ShiftImm_opcode 0xc6800000
383#define DSP32ShiftImm_src1_bits 0
384#define DSP32ShiftImm_src1_mask 0x7
385#define DSP32ShiftImm_immag_bits 3
386#define DSP32ShiftImm_immag_mask 0x3f
387#define DSP32ShiftImm_dst0_bits 9
388#define DSP32ShiftImm_dst0_mask 0x7
389#define DSP32ShiftImm_HLs_bits 12
390#define DSP32ShiftImm_HLs_mask 0x3
391#define DSP32ShiftImm_sop_bits 14
392#define DSP32ShiftImm_sop_mask 0x3
393#define DSP32ShiftImm_sopcde_bits 16
394#define DSP32ShiftImm_sopcde_mask 0x1f
395#define DSP32ShiftImm_dontcare_bits 21
396#define DSP32ShiftImm_dontcare_mask 0x3
397#define DSP32ShiftImm_code2_bits 23
398#define DSP32ShiftImm_code2_mask 0xf
399#define DSP32ShiftImm_M_bits 27
400#define DSP32ShiftImm_M_mask 0x1
ee99860a 401#define DSP32ShiftImm_code_bits 28
dc603df5
CM		 402#define DSP32ShiftImm_code_mask 0xf
403
404#define init_DSP32ShiftImm \
405{ \
406 DSP32ShiftImm_opcode, \
407 DSP32ShiftImm_src1_bits, DSP32ShiftImm_src1_mask, \
408 DSP32ShiftImm_immag_bits, DSP32ShiftImm_immag_mask, \
409 DSP32ShiftImm_dst0_bits, DSP32ShiftImm_dst0_mask, \
410 DSP32ShiftImm_HLs_bits, DSP32ShiftImm_HLs_mask, \
411 DSP32ShiftImm_sop_bits, DSP32ShiftImm_sop_mask, \
412 DSP32ShiftImm_sopcde_bits, DSP32ShiftImm_sopcde_mask, \
413 DSP32ShiftImm_dontcare_bits, DSP32ShiftImm_dontcare_mask, \
414 DSP32ShiftImm_code2_bits, DSP32ShiftImm_code2_mask, \
415 DSP32ShiftImm_M_bits, DSP32ShiftImm_M_mask, \
416 DSP32ShiftImm_code_bits, DSP32ShiftImm_code_mask \
417};
418
419/* LOAD / STORE */
420
421/* LDSTidxI
422+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
423| 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
424|.offset........................................................|
425+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
426*/
427
428typedef struct
429{
430 unsigned long opcode;
431 int bits_offset;
432 int mask_offset;
433 int bits_reg;
434 int mask_reg;
435 int bits_ptr;
436 int mask_ptr;
437 int bits_sz;
438 int mask_sz;
439 int bits_Z;
440 int mask_Z;
441 int bits_W;
442 int mask_W;
443 int bits_code;
444 int mask_code;
445} LDSTidxI;
446
447#define LDSTidxI_opcode 0xe4000000
448#define LDSTidxI_offset_bits 0
449#define LDSTidxI_offset_mask 0xffff
450#define LDSTidxI_reg_bits 16
451#define LDSTidxI_reg_mask 0x7
452#define LDSTidxI_ptr_bits 19
453#define LDSTidxI_ptr_mask 0x7
454#define LDSTidxI_sz_bits 22
455#define LDSTidxI_sz_mask 0x3
456#define LDSTidxI_Z_bits 24
457#define LDSTidxI_Z_mask 0x1
458#define LDSTidxI_W_bits 25
459#define LDSTidxI_W_mask 0x1
460#define LDSTidxI_code_bits 26
461#define LDSTidxI_code_mask 0x3f
462
463#define init_LDSTidxI \
464{ \
465 LDSTidxI_opcode, \
466 LDSTidxI_offset_bits, LDSTidxI_offset_mask, \
467 LDSTidxI_reg_bits, LDSTidxI_reg_mask, \
468 LDSTidxI_ptr_bits, LDSTidxI_ptr_mask, \
469 LDSTidxI_sz_bits, LDSTidxI_sz_mask, \
470 LDSTidxI_Z_bits, LDSTidxI_Z_mask, \
471 LDSTidxI_W_bits, LDSTidxI_W_mask, \
472 LDSTidxI_code_bits, LDSTidxI_code_mask \
473};
474
475
476/* LDST
477+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
478| 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
479+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
480*/
481
482typedef struct
483{
484 unsigned short opcode;
485 int bits_reg;
486 int mask_reg;
487 int bits_ptr;
488 int mask_ptr;
489 int bits_Z;
490 int mask_Z;
491 int bits_aop;
492 int mask_aop;
493 int bits_W;
494 int mask_W;
495 int bits_sz;
496 int mask_sz;
497 int bits_code;
498 int mask_code;
499} LDST;
500
501#define LDST_opcode 0x9000
502#define LDST_reg_bits 0
503#define LDST_reg_mask 0x7
504#define LDST_ptr_bits 3
505#define LDST_ptr_mask 0x7
506#define LDST_Z_bits 6
507#define LDST_Z_mask 0x1
508#define LDST_aop_bits 7
509#define LDST_aop_mask 0x3
510#define LDST_W_bits 9
511#define LDST_W_mask 0x1
512#define LDST_sz_bits 10
513#define LDST_sz_mask 0x3
514#define LDST_code_bits 12
515#define LDST_code_mask 0xf
516
517#define init_LDST \
518{ \
519 LDST_opcode, \
520 LDST_reg_bits, LDST_reg_mask, \
521 LDST_ptr_bits, LDST_ptr_mask, \
522 LDST_Z_bits, LDST_Z_mask, \
523 LDST_aop_bits, LDST_aop_mask, \
524 LDST_W_bits, LDST_W_mask, \
525 LDST_sz_bits, LDST_sz_mask, \
526 LDST_code_bits, LDST_code_mask \
527};
528
529/* LDSTii
530+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
531| 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
532+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
533*/
534
535typedef struct
536{
537 unsigned short opcode;
538 int bits_reg;
539 int mask_reg;
540 int bits_ptr;
541 int mask_ptr;
542 int bits_offset;
543 int mask_offset;
544 int bits_op;
545 int mask_op;
546 int bits_W;
547 int mask_W;
548 int bits_code;
549 int mask_code;
550} LDSTii;
551
552#define LDSTii_opcode 0xa000
553#define LDSTii_reg_bit 0
554#define LDSTii_reg_mask 0x7
555#define LDSTii_ptr_bit 3
556#define LDSTii_ptr_mask 0x7
557#define LDSTii_offset_bit 6
558#define LDSTii_offset_mask 0xf
559#define LDSTii_op_bit 10
560#define LDSTii_op_mask 0x3
561#define LDSTii_W_bit 12
562#define LDSTii_W_mask 0x1
563#define LDSTii_code_bit 13
564#define LDSTii_code_mask 0x7
565
566#define init_LDSTii \
567{ \
568 LDSTii_opcode, \
569 LDSTii_reg_bit, LDSTii_reg_mask, \
570 LDSTii_ptr_bit, LDSTii_ptr_mask, \
571 LDSTii_offset_bit, LDSTii_offset_mask, \
572 LDSTii_op_bit, LDSTii_op_mask, \
573 LDSTii_W_bit, LDSTii_W_mask, \
574 LDSTii_code_bit, LDSTii_code_mask \
575};
576
577
578/* LDSTiiFP
579+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
580| 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
581+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
582*/
583
584typedef struct
585{
586 unsigned short opcode;
587 int bits_reg;
588 int mask_reg;
589 int bits_offset;
590 int mask_offset;
591 int bits_W;
592 int mask_W;
593 int bits_code;
594 int mask_code;
595} LDSTiiFP;
596
597#define LDSTiiFP_opcode 0xb800
598#define LDSTiiFP_reg_bits 0
599#define LDSTiiFP_reg_mask 0xf
600#define LDSTiiFP_offset_bits 4
601#define LDSTiiFP_offset_mask 0x1f
602#define LDSTiiFP_W_bits 9
603#define LDSTiiFP_W_mask 0x1
604#define LDSTiiFP_code_bits 10
605#define LDSTiiFP_code_mask 0x3f
606
607#define init_LDSTiiFP \
608{ \
609 LDSTiiFP_opcode, \
610 LDSTiiFP_reg_bits, LDSTiiFP_reg_mask, \
611 LDSTiiFP_offset_bits, LDSTiiFP_offset_mask, \
612 LDSTiiFP_W_bits, LDSTiiFP_W_mask, \
613 LDSTiiFP_code_bits, LDSTiiFP_code_mask \
614};
615
616/* dspLDST
617+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
618| 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
619+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
620*/
621
622typedef struct
623{
624 unsigned short opcode;
625 int bits_reg;
626 int mask_reg;
627 int bits_i;
628 int mask_i;
629 int bits_m;
630 int mask_m;
631 int bits_aop;
632 int mask_aop;
633 int bits_W;
634 int mask_W;
635 int bits_code;
636 int mask_code;
637} DspLDST;
638
639#define DspLDST_opcode 0x9c00
640#define DspLDST_reg_bits 0
641#define DspLDST_reg_mask 0x7
642#define DspLDST_i_bits 3
643#define DspLDST_i_mask 0x3
644#define DspLDST_m_bits 5
645#define DspLDST_m_mask 0x3
646#define DspLDST_aop_bits 7
647#define DspLDST_aop_mask 0x3
648#define DspLDST_W_bits 9
649#define DspLDST_W_mask 0x1
650#define DspLDST_code_bits 10
651#define DspLDST_code_mask 0x3f
652
653#define init_DspLDST \
654{ \
655 DspLDST_opcode, \
656 DspLDST_reg_bits, DspLDST_reg_mask, \
657 DspLDST_i_bits, DspLDST_i_mask, \
658 DspLDST_m_bits, DspLDST_m_mask, \
659 DspLDST_aop_bits, DspLDST_aop_mask, \
660 DspLDST_W_bits, DspLDST_W_mask, \
661 DspLDST_code_bits, DspLDST_code_mask \
662};
663
664
665/* LDSTpmod
666+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
667| 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
668+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
669*/
670
671typedef struct
672{
673 unsigned short opcode;
674 int bits_ptr;
675 int mask_ptr;
676 int bits_idx;
677 int mask_idx;
678 int bits_reg;
679 int mask_reg;
680 int bits_aop;
681 int mask_aop;
682 int bits_W;
683 int mask_W;
684 int bits_code;
685 int mask_code;
686} LDSTpmod;
687
688#define LDSTpmod_opcode 0x8000
689#define LDSTpmod_ptr_bits 0
690#define LDSTpmod_ptr_mask 0x7
691#define LDSTpmod_idx_bits 3
692#define LDSTpmod_idx_mask 0x7
693#define LDSTpmod_reg_bits 6
694#define LDSTpmod_reg_mask 0x7
695#define LDSTpmod_aop_bits 9
696#define LDSTpmod_aop_mask 0x3
697#define LDSTpmod_W_bits 11
698#define LDSTpmod_W_mask 0x1
699#define LDSTpmod_code_bits 12
700#define LDSTpmod_code_mask 0xf
701
702#define init_LDSTpmod \
703{ \
704 LDSTpmod_opcode, \
705 LDSTpmod_ptr_bits, LDSTpmod_ptr_mask, \
706 LDSTpmod_idx_bits, LDSTpmod_idx_mask, \
707 LDSTpmod_reg_bits, LDSTpmod_reg_mask, \
708 LDSTpmod_aop_bits, LDSTpmod_aop_mask, \
709 LDSTpmod_W_bits, LDSTpmod_W_mask, \
710 LDSTpmod_code_bits, LDSTpmod_code_mask \
711};
712
713
714/* LOGI2op
715+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
716| 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
717+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
718*/
719
720typedef struct
721{
722 unsigned short opcode;
723 int bits_dst;
724 int mask_dst;
725 int bits_src;
726 int mask_src;
727 int bits_opc;
728 int mask_opc;
729 int bits_code;
730 int mask_code;
731} LOGI2op;
732
733#define LOGI2op_opcode 0x4800
734#define LOGI2op_dst_bits 0
735#define LOGI2op_dst_mask 0x7
736#define LOGI2op_src_bits 3
737#define LOGI2op_src_mask 0x1f
738#define LOGI2op_opc_bits 8
739#define LOGI2op_opc_mask 0x7
740#define LOGI2op_code_bits 11
741#define LOGI2op_code_mask 0x1f
742
743#define init_LOGI2op \
744{ \
745 LOGI2op_opcode, \
746 LOGI2op_dst_bits, LOGI2op_dst_mask, \
747 LOGI2op_src_bits, LOGI2op_src_mask, \
748 LOGI2op_opc_bits, LOGI2op_opc_mask, \
749 LOGI2op_code_bits, LOGI2op_code_mask \
750};
751
752
753/* ALU2op
754+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
755| 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
756+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
757*/
758
759typedef struct
760{
761 unsigned short opcode;
762 int bits_dst;
763 int mask_dst;
764 int bits_src;
765 int mask_src;
766 int bits_opc;
767 int mask_opc;
768 int bits_code;
769 int mask_code;
770} ALU2op;
771
772#define ALU2op_opcode 0x4000
773#define ALU2op_dst_bits 0
774#define ALU2op_dst_mask 0x7
775#define ALU2op_src_bits 3
776#define ALU2op_src_mask 0x7
777#define ALU2op_opc_bits 6
778#define ALU2op_opc_mask 0xf
779#define ALU2op_code_bits 10
780#define ALU2op_code_mask 0x3f
781
782#define init_ALU2op \
783{ \
784 ALU2op_opcode, \
785 ALU2op_dst_bits, ALU2op_dst_mask, \
786 ALU2op_src_bits, ALU2op_src_mask, \
787 ALU2op_opc_bits, ALU2op_opc_mask, \
788 ALU2op_code_bits, ALU2op_code_mask \
789};
790
791
792/* BRCC
793+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
794| 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
795+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
796*/
797
798typedef struct
799{
800 unsigned short opcode;
801 int bits_offset;
802 int mask_offset;
803 int bits_B;
804 int mask_B;
805 int bits_T;
806 int mask_T;
807 int bits_code;
808 int mask_code;
809} BRCC;
810
811#define BRCC_opcode 0x1000
812#define BRCC_offset_bits 0
813#define BRCC_offset_mask 0x3ff
814#define BRCC_B_bits 10
815#define BRCC_B_mask 0x1
816#define BRCC_T_bits 11
817#define BRCC_T_mask 0x1
818#define BRCC_code_bits 12
819#define BRCC_code_mask 0xf
820
821#define init_BRCC \
822{ \
823 BRCC_opcode, \
824 BRCC_offset_bits, BRCC_offset_mask, \
825 BRCC_B_bits, BRCC_B_mask, \
826 BRCC_T_bits, BRCC_T_mask, \
827 BRCC_code_bits, BRCC_code_mask \
828};
829
830
831/* UJUMP
832+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
833| 0 | 0 | 1 | 0 |.offset........................................|
834+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
835*/
836
837typedef struct
838{
839 unsigned short opcode;
840 int bits_offset;
841 int mask_offset;
842 int bits_code;
843 int mask_code;
844} UJump;
845
846#define UJump_opcode 0x2000
847#define UJump_offset_bits 0
848#define UJump_offset_mask 0xfff
849#define UJump_code_bits 12
850#define UJump_code_mask 0xf
851
852#define init_UJump \
853{ \
854 UJump_opcode, \
855 UJump_offset_bits, UJump_offset_mask, \
856 UJump_code_bits, UJump_code_mask \
857};
858
859
860/* ProgCtrl
861+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
862| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
863+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
864*/
865
866typedef struct
867{
868 unsigned short opcode;
869 int bits_poprnd;
870 int mask_poprnd;
871 int bits_prgfunc;
872 int mask_prgfunc;
873 int bits_code;
874 int mask_code;
875} ProgCtrl;
876
877#define ProgCtrl_opcode 0x0000
878#define ProgCtrl_poprnd_bits 0
879#define ProgCtrl_poprnd_mask 0xf
880#define ProgCtrl_prgfunc_bits 4
881#define ProgCtrl_prgfunc_mask 0xf
882#define ProgCtrl_code_bits 8
883#define ProgCtrl_code_mask 0xff
884
885#define init_ProgCtrl \
886{ \
887 ProgCtrl_opcode, \
888 ProgCtrl_poprnd_bits, ProgCtrl_poprnd_mask, \
889 ProgCtrl_prgfunc_bits, ProgCtrl_prgfunc_mask, \
890 ProgCtrl_code_bits, ProgCtrl_code_mask \
891};
892
893/* CALLa
894+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
895| 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
896|.lsw...........................................................|
897+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
898*/
899
900
901typedef struct
902{
903 unsigned long opcode;
904 int bits_addr;
905 int mask_addr;
906 int bits_S;
907 int mask_S;
908 int bits_code;
909 int mask_code;
910} CALLa;
911
912#define CALLa_opcode 0xe2000000
913#define CALLa_addr_bits 0
914#define CALLa_addr_mask 0xffffff
915#define CALLa_S_bits 24
916#define CALLa_S_mask 0x1
917#define CALLa_code_bits 25
918#define CALLa_code_mask 0x7f
919
920#define init_CALLa \
921{ \
922 CALLa_opcode, \
923 CALLa_addr_bits, CALLa_addr_mask, \
924 CALLa_S_bits, CALLa_S_mask, \
925 CALLa_code_bits, CALLa_code_mask \
926};
927
928
929/* pseudoDEBUG
930+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
931| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
932+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
933*/
934
935typedef struct
936{
937 unsigned short opcode;
938 int bits_reg;
939 int mask_reg;
940 int bits_grp;
941 int mask_grp;
942 int bits_fn;
943 int mask_fn;
944 int bits_code;
945 int mask_code;
946} PseudoDbg;
947
948#define PseudoDbg_opcode 0xf800
949#define PseudoDbg_reg_bits 0
950#define PseudoDbg_reg_mask 0x7
951#define PseudoDbg_grp_bits 3
952#define PseudoDbg_grp_mask 0x7
953#define PseudoDbg_fn_bits 6
954#define PseudoDbg_fn_mask 0x3
955#define PseudoDbg_code_bits 8
956#define PseudoDbg_code_mask 0xff
957
958#define init_PseudoDbg \
959{ \
960 PseudoDbg_opcode, \
961 PseudoDbg_reg_bits, PseudoDbg_reg_mask, \
962 PseudoDbg_grp_bits, PseudoDbg_grp_mask, \
963 PseudoDbg_fn_bits, PseudoDbg_fn_mask, \
964 PseudoDbg_code_bits, PseudoDbg_code_mask \
965};
966
967/* PseudoDbg_assert
968+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
66a6900a 969| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
dc603df5
CM		 970|.expected......................................................|
971+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
972*/
973
974typedef struct
975{
976 unsigned long opcode;
977 int bits_expected;
978 int mask_expected;
979 int bits_regtest;
980 int mask_regtest;
66a6900a
JZ		 981 int bits_grp;
982 int mask_grp;
dc603df5
CM		 983 int bits_dbgop;
984 int mask_dbgop;
985 int bits_dontcare;
986 int mask_dontcare;
987 int bits_code;
988 int mask_code;
989} PseudoDbg_Assert;
990
991#define PseudoDbg_Assert_opcode 0xf0000000
992#define PseudoDbg_Assert_expected_bits 0
993#define PseudoDbg_Assert_expected_mask 0xffff
994#define PseudoDbg_Assert_regtest_bits 16
995#define PseudoDbg_Assert_regtest_mask 0x7
66a6900a
JZ		 996#define PseudoDbg_Assert_grp_bits 19
997#define PseudoDbg_Assert_grp_mask 0x7
998#define PseudoDbg_Assert_dbgop_bits 22
999#define PseudoDbg_Assert_dbgop_mask 0x3
1000#define PseudoDbg_Assert_dontcare_bits 24
1001#define PseudoDbg_Assert_dontcare_mask 0x7
dc603df5
CM		 1002#define PseudoDbg_Assert_code_bits 27
1003#define PseudoDbg_Assert_code_mask 0x1f
1004
1005#define init_PseudoDbg_Assert \
1006{ \
1007 PseudoDbg_Assert_opcode, \
1008 PseudoDbg_Assert_expected_bits, PseudoDbg_Assert_expected_mask, \
1009 PseudoDbg_Assert_regtest_bits, PseudoDbg_Assert_regtest_mask, \
66a6900a 1010 PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask, \
dc603df5
CM		 1011 PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, \
1012 PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask, \
1013 PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \
1014};
1015
73a63ccf
MF		 1016/* pseudoChr
1017+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1018| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
1019+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1020*/
1021
1022typedef struct
1023{
1024 unsigned short opcode;
1025 int bits_ch;
1026 int mask_ch;
1027 int bits_code;
1028 int mask_code;
1029} PseudoChr;
1030
1031#define PseudoChr_opcode 0xf900
1032#define PseudoChr_ch_bits 0
1033#define PseudoChr_ch_mask 0xff
1034#define PseudoChr_code_bits 8
1035#define PseudoChr_code_mask 0xff
1036
1037#define init_PseudoChr \
1038{ \
1039 PseudoChr_opcode, \
1040 PseudoChr_ch_bits, PseudoChr_ch_mask, \
1041 PseudoChr_code_bits, PseudoChr_code_mask \
1042};
1043
dc603df5
CM		 1044/* CaCTRL
1045+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1046| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
1047+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1048*/
1049
1050typedef struct
1051{
1052 unsigned short opcode;
1053 int bits_reg;
1054 int mask_reg;
1055 int bits_op;
1056 int mask_op;
1057 int bits_a;
1058 int mask_a;
1059 int bits_code;
1060 int mask_code;
1061} CaCTRL;
1062
1063#define CaCTRL_opcode 0x0240
1064#define CaCTRL_reg_bits 0
1065#define CaCTRL_reg_mask 0x7
1066#define CaCTRL_op_bits 3
1067#define CaCTRL_op_mask 0x3
1068#define CaCTRL_a_bits 5
1069#define CaCTRL_a_mask 0x1
1070#define CaCTRL_code_bits 6
1071#define CaCTRL_code_mask 0x3fff
1072
1073#define init_CaCTRL \
1074{ \
1075 CaCTRL_opcode, \
1076 CaCTRL_reg_bits, CaCTRL_reg_mask, \
1077 CaCTRL_op_bits, CaCTRL_op_mask, \
1078 CaCTRL_a_bits, CaCTRL_a_mask, \
1079 CaCTRL_code_bits, CaCTRL_code_mask \
1080};
1081
1082/* PushPopMultiple
1083+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1084| 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
1085+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1086*/
1087
1088typedef struct
1089{
1090 unsigned short opcode;
1091 int bits_pr;
1092 int mask_pr;
1093 int bits_dr;
1094 int mask_dr;
1095 int bits_W;
1096 int mask_W;
1097 int bits_p;
1098 int mask_p;
1099 int bits_d;
1100 int mask_d;
1101 int bits_code;
1102 int mask_code;
1103} PushPopMultiple;
1104
1105#define PushPopMultiple_opcode 0x0400
1106#define PushPopMultiple_pr_bits 0
1107#define PushPopMultiple_pr_mask 0x7
1108#define PushPopMultiple_dr_bits 3
1109#define PushPopMultiple_dr_mask 0x7
1110#define PushPopMultiple_W_bits 6
1111#define PushPopMultiple_W_mask 0x1
1112#define PushPopMultiple_p_bits 7
1113#define PushPopMultiple_p_mask 0x1
1114#define PushPopMultiple_d_bits 8
1115#define PushPopMultiple_d_mask 0x1
1116#define PushPopMultiple_code_bits 8
1117#define PushPopMultiple_code_mask 0x1
1118
1119#define init_PushPopMultiple \
1120{ \
1121 PushPopMultiple_opcode, \
1122 PushPopMultiple_pr_bits, PushPopMultiple_pr_mask, \
1123 PushPopMultiple_dr_bits, PushPopMultiple_dr_mask, \
1124 PushPopMultiple_W_bits, PushPopMultiple_W_mask, \
1125 PushPopMultiple_p_bits, PushPopMultiple_p_mask, \
1126 PushPopMultiple_d_bits, PushPopMultiple_d_mask, \
1127 PushPopMultiple_code_bits, PushPopMultiple_code_mask \
1128};
1129
1130/* PushPopReg
1131+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1132| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
1133+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1134*/
1135
1136typedef struct
1137{
1138 unsigned short opcode;
1139 int bits_reg;
1140 int mask_reg;
1141 int bits_grp;
1142 int mask_grp;
1143 int bits_W;
1144 int mask_W;
1145 int bits_code;
1146 int mask_code;
1147} PushPopReg;
1148
1149#define PushPopReg_opcode 0x0100
1150#define PushPopReg_reg_bits 0
1151#define PushPopReg_reg_mask 0x7
1152#define PushPopReg_grp_bits 3
1153#define PushPopReg_grp_mask 0x7
1154#define PushPopReg_W_bits 6
1155#define PushPopReg_W_mask 0x1
1156#define PushPopReg_code_bits 7
1157#define PushPopReg_code_mask 0x1ff
1158
1159#define init_PushPopReg \
1160{ \
1161 PushPopReg_opcode, \
1162 PushPopReg_reg_bits, PushPopReg_reg_mask, \
1163 PushPopReg_grp_bits, PushPopReg_grp_mask, \
1164 PushPopReg_W_bits, PushPopReg_W_mask, \
1165 PushPopReg_code_bits, PushPopReg_code_mask, \
1166};
1167
1168/* linkage
1169+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1170| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
1171|.framesize.....................................................|
1172+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1173*/
1174
1175typedef struct
1176{
1177 unsigned long opcode;
ee99860a 1178 int bits_framesize;
dc603df5 1179 int mask_framesize;
ee99860a 1180 int bits_R;
dc603df5
CM		 1181 int mask_R;
1182 int bits_code;
1183 int mask_code;
1184} Linkage;
1185
1186#define Linkage_opcode 0xe8000000
1187#define Linkage_framesize_bits 0
1188#define Linkage_framesize_mask 0xffff
1189#define Linkage_R_bits 16
1190#define Linkage_R_mask 0x1
1191#define Linkage_code_bits 17
1192#define Linkage_code_mask 0x7fff
1193
1194#define init_Linkage \
1195{ \
1196 Linkage_opcode, \
1197 Linkage_framesize_bits, Linkage_framesize_mask, \
1198 Linkage_R_bits, Linkage_R_mask, \
1199 Linkage_code_bits, Linkage_code_mask \
1200};
1201
1202/* LoopSetup
1203+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1204| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
1205|.reg...........| - | - |.eoffset...............................|
1206+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1207*/
1208
1209typedef struct
1210{
1211 unsigned long opcode;
1212 int bits_eoffset;
ee99860a
MF		 1213 int mask_eoffset;
1214 int bits_dontcare;
dc603df5 1215 int mask_dontcare;
ee99860a 1216 int bits_reg;
dc603df5 1217 int mask_reg;
ee99860a 1218 int bits_soffset;
dc603df5 1219 int mask_soffset;
ee99860a 1220 int bits_c;
dc603df5 1221 int mask_c;
ee99860a 1222 int bits_rop;
dc603df5 1223 int mask_rop;
ee99860a 1224 int bits_code;
dc603df5
CM		 1225 int mask_code;
1226} LoopSetup;
1227
1228#define LoopSetup_opcode 0xe0800000
1229#define LoopSetup_eoffset_bits 0
1230#define LoopSetup_eoffset_mask 0x3ff
1231#define LoopSetup_dontcare_bits 10
1232#define LoopSetup_dontcare_mask 0x3
1233#define LoopSetup_reg_bits 12
1234#define LoopSetup_reg_mask 0xf
1235#define LoopSetup_soffset_bits 16
1236#define LoopSetup_soffset_mask 0xf
1237#define LoopSetup_c_bits 20
1238#define LoopSetup_c_mask 0x1
1239#define LoopSetup_rop_bits 21
1240#define LoopSetup_rop_mask 0x3
1241#define LoopSetup_code_bits 23
1242#define LoopSetup_code_mask 0x1ff
1243
1244#define init_LoopSetup \
1245{ \
1246 LoopSetup_opcode, \
1247 LoopSetup_eoffset_bits, LoopSetup_eoffset_mask, \
1248 LoopSetup_dontcare_bits, LoopSetup_dontcare_mask, \
1249 LoopSetup_reg_bits, LoopSetup_reg_mask, \
1250 LoopSetup_soffset_bits, LoopSetup_soffset_mask, \
1251 LoopSetup_c_bits, LoopSetup_c_mask, \
1252 LoopSetup_rop_bits, LoopSetup_rop_mask, \
1253 LoopSetup_code_bits, LoopSetup_code_mask \
1254};
1255
1256/* LDIMMhalf
1257+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1258| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
1259|.hword.........................................................|
1260+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1261*/
1262
1263typedef struct
1264{
1265 unsigned long opcode;
1266 int bits_hword;
1267 int mask_hword;
ee99860a 1268 int bits_reg;
dc603df5 1269 int mask_reg;
ee99860a 1270 int bits_grp;
dc603df5 1271 int mask_grp;
ee99860a 1272 int bits_S;
dc603df5 1273 int mask_S;
ee99860a 1274 int bits_H;
dc603df5 1275 int mask_H;
ee99860a 1276 int bits_Z;
dc603df5 1277 int mask_Z;
ee99860a 1278 int bits_code;
dc603df5
CM		 1279 int mask_code;
1280} LDIMMhalf;
1281
1282#define LDIMMhalf_opcode 0xe1000000
1283#define LDIMMhalf_hword_bits 0
1284#define LDIMMhalf_hword_mask 0xffff
1285#define LDIMMhalf_reg_bits 16
1286#define LDIMMhalf_reg_mask 0x7
1287#define LDIMMhalf_grp_bits 19
1288#define LDIMMhalf_grp_mask 0x3
1289#define LDIMMhalf_S_bits 21
1290#define LDIMMhalf_S_mask 0x1
1291#define LDIMMhalf_H_bits 22
1292#define LDIMMhalf_H_mask 0x1
1293#define LDIMMhalf_Z_bits 23
1294#define LDIMMhalf_Z_mask 0x1
1295#define LDIMMhalf_code_bits 24
1296#define LDIMMhalf_code_mask 0xff
1297
1298#define init_LDIMMhalf \
1299{ \
1300 LDIMMhalf_opcode, \
1301 LDIMMhalf_hword_bits, LDIMMhalf_hword_mask, \
1302 LDIMMhalf_reg_bits, LDIMMhalf_reg_mask, \
1303 LDIMMhalf_grp_bits, LDIMMhalf_grp_mask, \
1304 LDIMMhalf_S_bits, LDIMMhalf_S_mask, \
1305 LDIMMhalf_H_bits, LDIMMhalf_H_mask, \
1306 LDIMMhalf_Z_bits, LDIMMhalf_Z_mask, \
1307 LDIMMhalf_code_bits, LDIMMhalf_code_mask \
1308};
1309
1310
1311/* CC2dreg
1312+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1313| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1314+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1315*/
1316
1317typedef struct
1318{
1319 unsigned short opcode;
1320 int bits_reg;
1321 int mask_reg;
ee99860a 1322 int bits_op;
dc603df5 1323 int mask_op;
ee99860a 1324 int bits_code;
dc603df5
CM		 1325 int mask_code;
1326} CC2dreg;
1327
1328#define CC2dreg_opcode 0x0200
1329#define CC2dreg_reg_bits 0
1330#define CC2dreg_reg_mask 0x7
1331#define CC2dreg_op_bits 3
1332#define CC2dreg_op_mask 0x3
1333#define CC2dreg_code_bits 5
1334#define CC2dreg_code_mask 0x7fff
1335
1336#define init_CC2dreg \
1337{ \
1338 CC2dreg_opcode, \
1339 CC2dreg_reg_bits, CC2dreg_reg_mask, \
1340 CC2dreg_op_bits, CC2dreg_op_mask, \
1341 CC2dreg_code_bits, CC2dreg_code_mask \
1342};
1343
1344
1345/* PTR2op
1346+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1347| 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1348+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1349*/
1350
1351typedef struct
1352{
1353 unsigned short opcode;
1354 int bits_dst;
1355 int mask_dst;
ee99860a 1356 int bits_src;
dc603df5 1357 int mask_src;
ee99860a 1358 int bits_opc;
dc603df5 1359 int mask_opc;
ee99860a 1360 int bits_code;
dc603df5
CM		 1361 int mask_code;
1362} PTR2op;
1363
1364#define PTR2op_opcode 0x4400
1365#define PTR2op_dst_bits 0
1366#define PTR2op_dst_mask 0x7
1367#define PTR2op_src_bits 3
1368#define PTR2op_src_mask 0x7
1369#define PTR2op_opc_bits 6
1370#define PTR2op_opc_mask 0x7
ee99860a 1371#define PTR2op_code_bits 9
dc603df5
CM		 1372#define PTR2op_code_mask 0x7f
1373
1374#define init_PTR2op \
1375{ \
1376 PTR2op_opcode, \
1377 PTR2op_dst_bits, PTR2op_dst_mask, \
1378 PTR2op_src_bits, PTR2op_src_mask, \
1379 PTR2op_opc_bits, PTR2op_opc_mask, \
1380 PTR2op_code_bits, PTR2op_code_mask \
1381};
1382
1383
1384/* COMP3op
1385+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1386| 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1387+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1388*/
1389
1390typedef struct
1391{
1392 unsigned short opcode;
1393 int bits_src0;
1394 int mask_src0;
ee99860a 1395 int bits_src1;
dc603df5 1396 int mask_src1;
ee99860a 1397 int bits_dst;
dc603df5 1398 int mask_dst;
ee99860a 1399 int bits_opc;
dc603df5 1400 int mask_opc;
ee99860a 1401 int bits_code;
dc603df5
CM		 1402 int mask_code;
1403} COMP3op;
1404
1405#define COMP3op_opcode 0x5000
1406#define COMP3op_src0_bits 0
1407#define COMP3op_src0_mask 0x7
1408#define COMP3op_src1_bits 3
1409#define COMP3op_src1_mask 0x7
1410#define COMP3op_dst_bits 6
1411#define COMP3op_dst_mask 0x7
1412#define COMP3op_opc_bits 9
1413#define COMP3op_opc_mask 0x7
1414#define COMP3op_code_bits 12
1415#define COMP3op_code_mask 0xf
1416
1417#define init_COMP3op \
1418{ \
1419 COMP3op_opcode, \
1420 COMP3op_src0_bits, COMP3op_src0_mask, \
1421 COMP3op_src1_bits, COMP3op_src1_mask, \
1422 COMP3op_dst_bits, COMP3op_dst_mask, \
1423 COMP3op_opc_bits, COMP3op_opc_mask, \
1424 COMP3op_code_bits, COMP3op_code_mask \
1425};
1426
1427/* ccMV
1428+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1429| 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
1430+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1431*/
1432
1433typedef struct
1434{
1435 unsigned short opcode;
1436 int bits_src;
1437 int mask_src;
ee99860a 1438 int bits_dst;
dc603df5 1439 int mask_dst;
ee99860a 1440 int bits_s;
dc603df5 1441 int mask_s;
ee99860a 1442 int bits_d;
dc603df5 1443 int mask_d;
ee99860a 1444 int bits_T;
dc603df5 1445 int mask_T;
ee99860a 1446 int bits_code;
dc603df5
CM		 1447 int mask_code;
1448} CCmv;
1449
1450#define CCmv_opcode 0x0600
1451#define CCmv_src_bits 0
1452#define CCmv_src_mask 0x7
1453#define CCmv_dst_bits 3
1454#define CCmv_dst_mask 0x7
1455#define CCmv_s_bits 6
1456#define CCmv_s_mask 0x1
ee99860a 1457#define CCmv_d_bits 7
dc603df5
CM		 1458#define CCmv_d_mask 0x1
1459#define CCmv_T_bits 8
1460#define CCmv_T_mask 0x1
1461#define CCmv_code_bits 9
1462#define CCmv_code_mask 0x7f
1463
1464#define init_CCmv \
1465{ \
1466 CCmv_opcode, \
1467 CCmv_src_bits, CCmv_src_mask, \
1468 CCmv_dst_bits, CCmv_dst_mask, \
1469 CCmv_s_bits, CCmv_s_mask, \
1470 CCmv_d_bits, CCmv_d_mask, \
1471 CCmv_T_bits, CCmv_T_mask, \
1472 CCmv_code_bits, CCmv_code_mask \
1473};
1474
1475
1476/* CCflag
1477+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1478| 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1479+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1480*/
1481
1482typedef struct
1483{
1484 unsigned short opcode;
1485 int bits_x;
1486 int mask_x;
ee99860a 1487 int bits_y;
dc603df5 1488 int mask_y;
ee99860a 1489 int bits_G;
dc603df5 1490 int mask_G;
ee99860a 1491 int bits_opc;
dc603df5 1492 int mask_opc;
ee99860a 1493 int bits_I;
dc603df5 1494 int mask_I;
ee99860a 1495 int bits_code;
dc603df5
CM		 1496 int mask_code;
1497} CCflag;
1498
1499#define CCflag_opcode 0x0800
1500#define CCflag_x_bits 0
1501#define CCflag_x_mask 0x7
1502#define CCflag_y_bits 3
1503#define CCflag_y_mask 0x7
1504#define CCflag_G_bits 6
1505#define CCflag_G_mask 0x1
1506#define CCflag_opc_bits 7
1507#define CCflag_opc_mask 0x7
1508#define CCflag_I_bits 10
1509#define CCflag_I_mask 0x1
1510#define CCflag_code_bits 11
1511#define CCflag_code_mask 0x1f
1512
1513#define init_CCflag \
1514{ \
1515 CCflag_opcode, \
1516 CCflag_x_bits, CCflag_x_mask, \
1517 CCflag_y_bits, CCflag_y_mask, \
1518 CCflag_G_bits, CCflag_G_mask, \
1519 CCflag_opc_bits, CCflag_opc_mask, \
1520 CCflag_I_bits, CCflag_I_mask, \
1521 CCflag_code_bits, CCflag_code_mask, \
1522};
1523
1524
1525/* CC2stat
1526+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1527| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1528+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1529*/
1530
1531typedef struct
1532{
1533 unsigned short opcode;
1534 int bits_cbit;
1535 int mask_cbit;
ee99860a 1536 int bits_op;
dc603df5 1537 int mask_op;
ee99860a 1538 int bits_D;
dc603df5 1539 int mask_D;
ee99860a 1540 int bits_code;
dc603df5
CM		 1541 int mask_code;
1542} CC2stat;
1543
1544#define CC2stat_opcode 0x0300
1545#define CC2stat_cbit_bits 0
1546#define CC2stat_cbit_mask 0x1f
1547#define CC2stat_op_bits 5
1548#define CC2stat_op_mask 0x3
1549#define CC2stat_D_bits 7
1550#define CC2stat_D_mask 0x1
1551#define CC2stat_code_bits 8
1552#define CC2stat_code_mask 0xff
1553
1554#define init_CC2stat \
1555{ \
1556 CC2stat_opcode, \
1557 CC2stat_cbit_bits, CC2stat_cbit_mask, \
1558 CC2stat_op_bits, CC2stat_op_mask, \
1559 CC2stat_D_bits, CC2stat_D_mask, \
1560 CC2stat_code_bits, CC2stat_code_mask \
1561};
1562
1563
1564/* REGMV
1565+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1566| 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1567+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1568*/
1569
1570typedef struct
1571{
1572 unsigned short opcode;
1573 int bits_src;
1574 int mask_src;
ee99860a 1575 int bits_dst;
dc603df5 1576 int mask_dst;
ee99860a 1577 int bits_gs;
dc603df5 1578 int mask_gs;
ee99860a 1579 int bits_gd;
dc603df5 1580 int mask_gd;
ee99860a 1581 int bits_code;
dc603df5
CM		 1582 int mask_code;
1583} RegMv;
1584
1585#define RegMv_opcode 0x3000
1586#define RegMv_src_bits 0
1587#define RegMv_src_mask 0x7
1588#define RegMv_dst_bits 3
1589#define RegMv_dst_mask 0x7
1590#define RegMv_gs_bits 6
1591#define RegMv_gs_mask 0x7
1592#define RegMv_gd_bits 9
1593#define RegMv_gd_mask 0x7
1594#define RegMv_code_bits 12
1595#define RegMv_code_mask 0xf
1596
1597#define init_RegMv \
1598{ \
1599 RegMv_opcode, \
1600 RegMv_src_bits, RegMv_src_mask, \
1601 RegMv_dst_bits, RegMv_dst_mask, \
1602 RegMv_gs_bits, RegMv_gs_mask, \
1603 RegMv_gd_bits, RegMv_gd_mask, \
1604 RegMv_code_bits, RegMv_code_mask \
1605};
1606
1607
1608/* COMPI2opD
1609+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1610| 0 | 1 | 1 | 0 | 0 |.op|.isrc......................|.dst.......|
1611+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1612*/
1613
1614typedef struct
1615{
1616 unsigned short opcode;
1617 int bits_dst;
1618 int mask_dst;
ee99860a 1619 int bits_src;
dc603df5 1620 int mask_src;
ee99860a 1621 int bits_op;
dc603df5 1622 int mask_op;
ee99860a 1623 int bits_code;
dc603df5
CM		 1624 int mask_code;
1625} COMPI2opD;
1626
1627#define COMPI2opD_opcode 0x6000
1628#define COMPI2opD_dst_bits 0
1629#define COMPI2opD_dst_mask 0x7
1630#define COMPI2opD_src_bits 3
1631#define COMPI2opD_src_mask 0x7f
1632#define COMPI2opD_op_bits 10
1633#define COMPI2opD_op_mask 0x1
1634#define COMPI2opD_code_bits 11
1635#define COMPI2opD_code_mask 0x1f
1636
1637#define init_COMPI2opD \
1638{ \
1639 COMPI2opD_opcode, \
1640 COMPI2opD_dst_bits, COMPI2opD_dst_mask, \
1641 COMPI2opD_src_bits, COMPI2opD_src_mask, \
1642 COMPI2opD_op_bits, COMPI2opD_op_mask, \
1643 COMPI2opD_code_bits, COMPI2opD_code_mask \
1644};
1645
1646/* COMPI2opP
1647+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1648| 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1649+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1650*/
1651
1652typedef COMPI2opD COMPI2opP;
1653
1654#define COMPI2opP_opcode 0x6800
1655#define COMPI2opP_dst_bits 0
1656#define COMPI2opP_dst_mask 0x7
1657#define COMPI2opP_src_bits 3
1658#define COMPI2opP_src_mask 0x7f
1659#define COMPI2opP_op_bits 10
1660#define COMPI2opP_op_mask 0x1
1661#define COMPI2opP_code_bits 11
1662#define COMPI2opP_code_mask 0x1f
1663
1664#define init_COMPI2opP \
1665{ \
1666 COMPI2opP_opcode, \
1667 COMPI2opP_dst_bits, COMPI2opP_dst_mask, \
1668 COMPI2opP_src_bits, COMPI2opP_src_mask, \
1669 COMPI2opP_op_bits, COMPI2opP_op_mask, \
1670 COMPI2opP_code_bits, COMPI2opP_code_mask \
1671};
1672
1673
1674/* dagMODim
1675+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1676| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1677+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1678*/
1679
1680typedef struct
1681{
1682 unsigned short opcode;
1683 int bits_i;
1684 int mask_i;
ee99860a 1685 int bits_m;
dc603df5 1686 int mask_m;
ee99860a 1687 int bits_op;
dc603df5 1688 int mask_op;
ee99860a 1689 int bits_code2;
dc603df5 1690 int mask_code2;
ee99860a 1691 int bits_br;
dc603df5 1692 int mask_br;
ee99860a 1693 int bits_code;
dc603df5
CM		 1694 int mask_code;
1695} DagMODim;
1696
1697#define DagMODim_opcode 0x9e60
1698#define DagMODim_i_bits 0
1699#define DagMODim_i_mask 0x3
1700#define DagMODim_m_bits 2
1701#define DagMODim_m_mask 0x3
1702#define DagMODim_op_bits 4
1703#define DagMODim_op_mask 0x1
1704#define DagMODim_code2_bits 5
1705#define DagMODim_code2_mask 0x3
1706#define DagMODim_br_bits 7
1707#define DagMODim_br_mask 0x1
1708#define DagMODim_code_bits 8
1709#define DagMODim_code_mask 0xff
1710
1711#define init_DagMODim \
1712{ \
1713 DagMODim_opcode, \
1714 DagMODim_i_bits, DagMODim_i_mask, \
1715 DagMODim_m_bits, DagMODim_m_mask, \
1716 DagMODim_op_bits, DagMODim_op_mask, \
1717 DagMODim_code2_bits, DagMODim_code2_mask, \
1718 DagMODim_br_bits, DagMODim_br_mask, \
1719 DagMODim_code_bits, DagMODim_code_mask \
1720};
1721
1722/* dagMODik
1723+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1724| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
1725+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1726*/
1727
1728typedef struct
1729{
1730 unsigned short opcode;
1731 int bits_i;
1732 int mask_i;
1733 int bits_op;
1734 int mask_op;
1735 int bits_code;
1736 int mask_code;
1737} DagMODik;
1738
1739#define DagMODik_opcode 0x9f60
1740#define DagMODik_i_bits 0
1741#define DagMODik_i_mask 0x3
1742#define DagMODik_op_bits 2
1743#define DagMODik_op_mask 0x3
1744#define DagMODik_code_bits 3
1745#define DagMODik_code_mask 0xfff
1746
1747#define init_DagMODik \
1748{ \
1749 DagMODik_opcode, \
1750 DagMODik_i_bits, DagMODik_i_mask, \
1751 DagMODik_op_bits, DagMODik_op_mask, \
1752 DagMODik_code_bits, DagMODik_code_mask \
1753};
dd76fcb8
MF		 1754
1755#endif
GDB Binutils - Deliverables
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