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[deliverable/binutils-gdb.git] / include / opcode / bfin.h
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CM		 1/* bfin.h -- Header file for ADI Blackfin opcode table
2 Copyright 2005 Free Software Foundation, Inc.
3
4This file is part of GDB, GAS, and the GNU binutils.
5
6GDB, GAS, and the GNU binutils are free software; you can redistribute
7them and/or modify them under the terms of the GNU General Public
8License as published by the Free Software Foundation; either version
91, or (at your option) any later version.
10
11GDB, GAS, and the GNU binutils are distributed in the hope that they
12will be useful, but WITHOUT ANY WARRANTY; without even the implied
13warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
14the GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with this file; see the file COPYING. If not, write to the Free
18Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
19
20/* Common to all DSP32 instructions. */
21#define BIT_MULTI_INS 0x0800
22
23/* This just sets the multi instruction bit of a DSP32 instruction. */
24#define SET_MULTI_INSTRUCTION_BIT(x) x->value |= BIT_MULTI_INS;
25
26
27/* DSP instructions (32 bit) */
28
29/* dsp32mac
30+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
31| 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
32|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
33+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
34*/
35
36typedef struct
37{
38 unsigned long opcode;
39 int bits_src1;
40 int mask_src1;
41 int bits_src0;
42 int mask_src0;
43 int bits_dst;
44 int mask_dst;
45 int bits_h10;
46 int mask_h10;
47 int bits_h00;
48 int mask_h00;
49 int bits_op0;
50 int mask_op0;
51 int bits_w0;
52 int mask_w0;
53 int bits_h11;
54 int mask_h11;
55 int bits_h01;
56 int mask_h01;
57 int bits_op1;
58 int mask_op1;
59 int bits_w1;
60 int mask_w1;
61 int bits_P;
62 int mask_P;
63 int bits_MM;
64 int mask_MM;
65 int bits_mmod;
66 int mask_mmod;
67 int bits_code2;
68 int mask_code2;
69 int bits_M;
70 int mask_M;
71 int bits_code;
72 int mask_code;
73} DSP32Mac;
74
75#define DSP32Mac_opcode 0xc0000000
76#define DSP32Mac_src1_bits 0
77#define DSP32Mac_src1_mask 0x7
78#define DSP32Mac_src0_bits 3
79#define DSP32Mac_src0_mask 0x7
80#define DSP32Mac_dst_bits 6
81#define DSP32Mac_dst_mask 0x7
82#define DSP32Mac_h10_bits 9
83#define DSP32Mac_h10_mask 0x1
84#define DSP32Mac_h00_bits 10
85#define DSP32Mac_h00_mask 0x1
86#define DSP32Mac_op0_bits 11
87#define DSP32Mac_op0_mask 0x3
88#define DSP32Mac_w0_bits 13
89#define DSP32Mac_w0_mask 0x1
90#define DSP32Mac_h11_bits 14
91#define DSP32Mac_h11_mask 0x1
92#define DSP32Mac_h01_bits 15
93#define DSP32Mac_h01_mask 0x1
94#define DSP32Mac_op1_bits 16
95#define DSP32Mac_op1_mask 0x3
96#define DSP32Mac_w1_bits 18
97#define DSP32Mac_w1_mask 0x1
98#define DSP32Mac_p_bits 19
99#define DSP32Mac_p_mask 0x1
100#define DSP32Mac_MM_bits 20
101#define DSP32Mac_MM_mask 0x1
102#define DSP32Mac_mmod_bits 21
103#define DSP32Mac_mmod_mask 0xf
104#define DSP32Mac_code2_bits 25
105#define DSP32Mac_code2_mask 0x3
106#define DSP32Mac_M_bits 27
107#define DSP32Mac_M_mask 0x1
108#define DSP32Mac_code_bits 28
109#define DSP32Mac_code_mask 0xf
110
111#define init_DSP32Mac \
112{ \
113 DSP32Mac_opcode, \
114 DSP32Mac_src1_bits, DSP32Mac_src1_mask, \
115 DSP32Mac_src0_bits, DSP32Mac_src0_mask, \
116 DSP32Mac_dst_bits, DSP32Mac_dst_mask, \
117 DSP32Mac_h10_bits, DSP32Mac_h10_mask, \
118 DSP32Mac_h00_bits, DSP32Mac_h00_mask, \
119 DSP32Mac_op0_bits, DSP32Mac_op0_mask, \
120 DSP32Mac_w0_bits, DSP32Mac_w0_mask, \
121 DSP32Mac_h11_bits, DSP32Mac_h11_mask, \
122 DSP32Mac_h01_bits, DSP32Mac_h01_mask, \
123 DSP32Mac_op1_bits, DSP32Mac_op1_mask, \
124 DSP32Mac_w1_bits, DSP32Mac_w1_mask, \
125 DSP32Mac_p_bits, DSP32Mac_p_mask, \
126 DSP32Mac_MM_bits, DSP32Mac_MM_mask, \
127 DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \
128 DSP32Mac_code2_bits, DSP32Mac_code2_mask, \
129 DSP32Mac_M_bits, DSP32Mac_M_mask, \
130 DSP32Mac_code_bits, DSP32Mac_code_mask \
131};
132
133/* dsp32mult
134+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
135| 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
136|.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
137+----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
138*/
139
140typedef DSP32Mac DSP32Mult;
141#define DSP32Mult_opcode 0xc2000000
142
143#define init_DSP32Mult \
144{ \
145 DSP32Mult_opcode, \
146 DSP32Mac_src1_bits, DSP32Mac_src1_mask, \
147 DSP32Mac_src0_bits, DSP32Mac_src0_mask, \
148 DSP32Mac_dst_bits, DSP32Mac_dst_mask, \
149 DSP32Mac_h10_bits, DSP32Mac_h10_mask, \
150 DSP32Mac_h00_bits, DSP32Mac_h00_mask, \
151 DSP32Mac_op0_bits, DSP32Mac_op0_mask, \
152 DSP32Mac_w0_bits, DSP32Mac_w0_mask, \
153 DSP32Mac_h11_bits, DSP32Mac_h11_mask, \
154 DSP32Mac_h01_bits, DSP32Mac_h01_mask, \
155 DSP32Mac_op1_bits, DSP32Mac_op1_mask, \
156 DSP32Mac_w1_bits, DSP32Mac_w1_mask, \
157 DSP32Mac_p_bits, DSP32Mac_p_mask, \
158 DSP32Mac_MM_bits, DSP32Mac_MM_mask, \
159 DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \
160 DSP32Mac_code2_bits, DSP32Mac_code2_mask, \
161 DSP32Mac_M_bits, DSP32Mac_M_mask, \
162 DSP32Mac_code_bits, DSP32Mac_code_mask \
163};
164
165/* dsp32alu
166+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
167| 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
168|.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
169+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
170*/
171
172typedef struct
173{
174 unsigned long opcode;
175 int bits_src1;
176 int mask_src1;
177 int bits_src0;
178 int mask_src0;
179 int bits_dst1;
180 int mask_dst1;
181 int bits_dst0;
182 int mask_dst0;
183 int bits_x;
184 int mask_x;
185 int bits_s;
186 int mask_s;
187 int bits_aop;
188 int mask_aop;
189 int bits_aopcde;
190 int mask_aopcde;
191 int bits_HL;
192 int mask_HL;
193 int bits_dontcare;
194 int mask_dontcare;
195 int bits_code2;
196 int mask_code2;
197 int bits_M;
198 int mask_M;
199 int bits_code;
200 int mask_code;
201} DSP32Alu;
202
203#define DSP32Alu_opcode 0xc4000000
204#define DSP32Alu_src1_bits 0
205#define DSP32Alu_src1_mask 0x7
206#define DSP32Alu_src0_bits 3
207#define DSP32Alu_src0_mask 0x7
208#define DSP32Alu_dst1_bits 6
209#define DSP32Alu_dst1_mask 0x7
210#define DSP32Alu_dst0_bits 9
211#define DSP32Alu_dst0_mask 0x7
212#define DSP32Alu_x_bits 12
213#define DSP32Alu_x_mask 0x1
214#define DSP32Alu_s_bits 13
215#define DSP32Alu_s_mask 0x1
216#define DSP32Alu_aop_bits 14
217#define DSP32Alu_aop_mask 0x3
218#define DSP32Alu_aopcde_bits 16
219#define DSP32Alu_aopcde_mask 0x1f
220#define DSP32Alu_HL_bits 21
221#define DSP32Alu_HL_mask 0x1
222#define DSP32Alu_dontcare_bits 22
223#define DSP32Alu_dontcare_mask 0x7
224#define DSP32Alu_code2_bits 25
225#define DSP32Alu_code2_mask 0x3
226#define DSP32Alu_M_bits 27
227#define DSP32Alu_M_mask 0x1
228#define DSP32Alu_code_bits 28
229#define DSP32Alu_code_mask 0xf
230
231#define init_DSP32Alu \
232{ \
233 DSP32Alu_opcode, \
234 DSP32Alu_src1_bits, DSP32Alu_src1_mask, \
235 DSP32Alu_src0_bits, DSP32Alu_src0_mask, \
236 DSP32Alu_dst1_bits, DSP32Alu_dst1_mask, \
237 DSP32Alu_dst0_bits, DSP32Alu_dst0_mask, \
238 DSP32Alu_x_bits, DSP32Alu_x_mask, \
239 DSP32Alu_s_bits, DSP32Alu_s_mask, \
240 DSP32Alu_aop_bits, DSP32Alu_aop_mask, \
241 DSP32Alu_aopcde_bits, DSP32Alu_aopcde_mask, \
242 DSP32Alu_HL_bits, DSP32Alu_HL_mask, \
243 DSP32Alu_dontcare_bits, DSP32Alu_dontcare_mask, \
244 DSP32Alu_code2_bits, DSP32Alu_code2_mask, \
245 DSP32Alu_M_bits, DSP32Alu_M_mask, \
246 DSP32Alu_code_bits, DSP32Alu_code_mask \
247};
248
249/* dsp32shift
250+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
251| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
252|.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
253+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
254*/
255
256typedef struct
257{
258 unsigned long opcode;
259 int bits_src1;
260 int mask_src1;
261 int bits_src0;
262 int mask_src0;
263 int bits_dst1;
264 int mask_dst1;
265 int bits_dst0;
266 int mask_dst0;
267 int bits_HLs;
268 int mask_HLs;
269 int bits_sop;
270 int mask_sop;
271 int bits_sopcde;
272 int mask_sopcde;
273 int bits_dontcare;
274 int mask_dontcare;
275 int bits_code2;
276 int mask_code2;
277 int bits_M;
278 int mask_M;
279 int bits_code;
280 int mask_code;
281} DSP32Shift;
282
283#define DSP32Shift_opcode 0xc6000000
284#define DSP32Shift_src1_bits 0
285#define DSP32Shift_src1_mask 0x7
286#define DSP32Shift_src0_bits 3
287#define DSP32Shift_src0_mask 0x7
288#define DSP32Shift_dst1_bits 6
289#define DSP32Shift_dst1_mask 0x7
290#define DSP32Shift_dst0_bits 9
291#define DSP32Shift_dst0_mask 0x7
292#define DSP32Shift_HLs_bits 12
293#define DSP32Shift_HLs_mask 0x3
294#define DSP32Shift_sop_bits 14
295#define DSP32Shift_sop_mask 0x3
296#define DSP32Shift_sopcde_bits 16
297#define DSP32Shift_sopcde_mask 0x1f
298#define DSP32Shift_dontcare_bits 21
299#define DSP32Shift_dontcare_mask 0x3
300#define DSP32Shift_code2_bits 23
301#define DSP32Shift_code2_mask 0xf
302#define DSP32Shift_M_bits 27
303#define DSP32Shift_M_mask 0x1
304#define DSP32Shift_code_bits 28
305#define DSP32Shift_code_mask 0xf
306
307#define init_DSP32Shift \
308{ \
309 DSP32Shift_opcode, \
310 DSP32Shift_src1_bits, DSP32Shift_src1_mask, \
311 DSP32Shift_src0_bits, DSP32Shift_src0_mask, \
312 DSP32Shift_dst1_bits, DSP32Shift_dst1_mask, \
313 DSP32Shift_dst0_bits, DSP32Shift_dst0_mask, \
314 DSP32Shift_HLs_bits, DSP32Shift_HLs_mask, \
315 DSP32Shift_sop_bits, DSP32Shift_sop_mask, \
316 DSP32Shift_sopcde_bits, DSP32Shift_sopcde_mask, \
317 DSP32Shift_dontcare_bits, DSP32Shift_dontcare_mask, \
318 DSP32Shift_code2_bits, DSP32Shift_code2_mask, \
319 DSP32Shift_M_bits, DSP32Shift_M_mask, \
320 DSP32Shift_code_bits, DSP32Shift_code_mask \
321};
322
323/* dsp32shiftimm
324+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
325| 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
326|.sop...|.HLs...|.dst0......|.immag.................|.src1......|
327+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
328*/
329
330typedef struct
331{
332 unsigned long opcode;
333 int bits_src1;
334 int mask_src1;
335 int bits_immag;
336 int mask_immag;
337 int bits_dst0;
338 int mask_dst0;
339 int bits_HLs;
340 int mask_HLs;
341 int bits_sop;
342 int mask_sop;
343 int bits_sopcde;
344 int mask_sopcde;
345 int bits_dontcare;
346 int mask_dontcare;
347 int bits_code2;
348 int mask_code2;
349 int bits_M;
350 int mask_M;
351 int bits_code;
352 int mask_code;
353} DSP32ShiftImm;
354
355#define DSP32ShiftImm_opcode 0xc6800000
356#define DSP32ShiftImm_src1_bits 0
357#define DSP32ShiftImm_src1_mask 0x7
358#define DSP32ShiftImm_immag_bits 3
359#define DSP32ShiftImm_immag_mask 0x3f
360#define DSP32ShiftImm_dst0_bits 9
361#define DSP32ShiftImm_dst0_mask 0x7
362#define DSP32ShiftImm_HLs_bits 12
363#define DSP32ShiftImm_HLs_mask 0x3
364#define DSP32ShiftImm_sop_bits 14
365#define DSP32ShiftImm_sop_mask 0x3
366#define DSP32ShiftImm_sopcde_bits 16
367#define DSP32ShiftImm_sopcde_mask 0x1f
368#define DSP32ShiftImm_dontcare_bits 21
369#define DSP32ShiftImm_dontcare_mask 0x3
370#define DSP32ShiftImm_code2_bits 23
371#define DSP32ShiftImm_code2_mask 0xf
372#define DSP32ShiftImm_M_bits 27
373#define DSP32ShiftImm_M_mask 0x1
374#define DSP32ShiftImm_code_bits 28
375#define DSP32ShiftImm_code_mask 0xf
376
377#define init_DSP32ShiftImm \
378{ \
379 DSP32ShiftImm_opcode, \
380 DSP32ShiftImm_src1_bits, DSP32ShiftImm_src1_mask, \
381 DSP32ShiftImm_immag_bits, DSP32ShiftImm_immag_mask, \
382 DSP32ShiftImm_dst0_bits, DSP32ShiftImm_dst0_mask, \
383 DSP32ShiftImm_HLs_bits, DSP32ShiftImm_HLs_mask, \
384 DSP32ShiftImm_sop_bits, DSP32ShiftImm_sop_mask, \
385 DSP32ShiftImm_sopcde_bits, DSP32ShiftImm_sopcde_mask, \
386 DSP32ShiftImm_dontcare_bits, DSP32ShiftImm_dontcare_mask, \
387 DSP32ShiftImm_code2_bits, DSP32ShiftImm_code2_mask, \
388 DSP32ShiftImm_M_bits, DSP32ShiftImm_M_mask, \
389 DSP32ShiftImm_code_bits, DSP32ShiftImm_code_mask \
390};
391
392/* LOAD / STORE */
393
394/* LDSTidxI
395+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
396| 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
397|.offset........................................................|
398+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
399*/
400
401typedef struct
402{
403 unsigned long opcode;
404 int bits_offset;
405 int mask_offset;
406 int bits_reg;
407 int mask_reg;
408 int bits_ptr;
409 int mask_ptr;
410 int bits_sz;
411 int mask_sz;
412 int bits_Z;
413 int mask_Z;
414 int bits_W;
415 int mask_W;
416 int bits_code;
417 int mask_code;
418} LDSTidxI;
419
420#define LDSTidxI_opcode 0xe4000000
421#define LDSTidxI_offset_bits 0
422#define LDSTidxI_offset_mask 0xffff
423#define LDSTidxI_reg_bits 16
424#define LDSTidxI_reg_mask 0x7
425#define LDSTidxI_ptr_bits 19
426#define LDSTidxI_ptr_mask 0x7
427#define LDSTidxI_sz_bits 22
428#define LDSTidxI_sz_mask 0x3
429#define LDSTidxI_Z_bits 24
430#define LDSTidxI_Z_mask 0x1
431#define LDSTidxI_W_bits 25
432#define LDSTidxI_W_mask 0x1
433#define LDSTidxI_code_bits 26
434#define LDSTidxI_code_mask 0x3f
435
436#define init_LDSTidxI \
437{ \
438 LDSTidxI_opcode, \
439 LDSTidxI_offset_bits, LDSTidxI_offset_mask, \
440 LDSTidxI_reg_bits, LDSTidxI_reg_mask, \
441 LDSTidxI_ptr_bits, LDSTidxI_ptr_mask, \
442 LDSTidxI_sz_bits, LDSTidxI_sz_mask, \
443 LDSTidxI_Z_bits, LDSTidxI_Z_mask, \
444 LDSTidxI_W_bits, LDSTidxI_W_mask, \
445 LDSTidxI_code_bits, LDSTidxI_code_mask \
446};
447
448
449/* LDST
450+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
451| 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
452+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
453*/
454
455typedef struct
456{
457 unsigned short opcode;
458 int bits_reg;
459 int mask_reg;
460 int bits_ptr;
461 int mask_ptr;
462 int bits_Z;
463 int mask_Z;
464 int bits_aop;
465 int mask_aop;
466 int bits_W;
467 int mask_W;
468 int bits_sz;
469 int mask_sz;
470 int bits_code;
471 int mask_code;
472} LDST;
473
474#define LDST_opcode 0x9000
475#define LDST_reg_bits 0
476#define LDST_reg_mask 0x7
477#define LDST_ptr_bits 3
478#define LDST_ptr_mask 0x7
479#define LDST_Z_bits 6
480#define LDST_Z_mask 0x1
481#define LDST_aop_bits 7
482#define LDST_aop_mask 0x3
483#define LDST_W_bits 9
484#define LDST_W_mask 0x1
485#define LDST_sz_bits 10
486#define LDST_sz_mask 0x3
487#define LDST_code_bits 12
488#define LDST_code_mask 0xf
489
490#define init_LDST \
491{ \
492 LDST_opcode, \
493 LDST_reg_bits, LDST_reg_mask, \
494 LDST_ptr_bits, LDST_ptr_mask, \
495 LDST_Z_bits, LDST_Z_mask, \
496 LDST_aop_bits, LDST_aop_mask, \
497 LDST_W_bits, LDST_W_mask, \
498 LDST_sz_bits, LDST_sz_mask, \
499 LDST_code_bits, LDST_code_mask \
500};
501
502/* LDSTii
503+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
504| 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
505+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
506*/
507
508typedef struct
509{
510 unsigned short opcode;
511 int bits_reg;
512 int mask_reg;
513 int bits_ptr;
514 int mask_ptr;
515 int bits_offset;
516 int mask_offset;
517 int bits_op;
518 int mask_op;
519 int bits_W;
520 int mask_W;
521 int bits_code;
522 int mask_code;
523} LDSTii;
524
525#define LDSTii_opcode 0xa000
526#define LDSTii_reg_bit 0
527#define LDSTii_reg_mask 0x7
528#define LDSTii_ptr_bit 3
529#define LDSTii_ptr_mask 0x7
530#define LDSTii_offset_bit 6
531#define LDSTii_offset_mask 0xf
532#define LDSTii_op_bit 10
533#define LDSTii_op_mask 0x3
534#define LDSTii_W_bit 12
535#define LDSTii_W_mask 0x1
536#define LDSTii_code_bit 13
537#define LDSTii_code_mask 0x7
538
539#define init_LDSTii \
540{ \
541 LDSTii_opcode, \
542 LDSTii_reg_bit, LDSTii_reg_mask, \
543 LDSTii_ptr_bit, LDSTii_ptr_mask, \
544 LDSTii_offset_bit, LDSTii_offset_mask, \
545 LDSTii_op_bit, LDSTii_op_mask, \
546 LDSTii_W_bit, LDSTii_W_mask, \
547 LDSTii_code_bit, LDSTii_code_mask \
548};
549
550
551/* LDSTiiFP
552+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
553| 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
554+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
555*/
556
557typedef struct
558{
559 unsigned short opcode;
560 int bits_reg;
561 int mask_reg;
562 int bits_offset;
563 int mask_offset;
564 int bits_W;
565 int mask_W;
566 int bits_code;
567 int mask_code;
568} LDSTiiFP;
569
570#define LDSTiiFP_opcode 0xb800
571#define LDSTiiFP_reg_bits 0
572#define LDSTiiFP_reg_mask 0xf
573#define LDSTiiFP_offset_bits 4
574#define LDSTiiFP_offset_mask 0x1f
575#define LDSTiiFP_W_bits 9
576#define LDSTiiFP_W_mask 0x1
577#define LDSTiiFP_code_bits 10
578#define LDSTiiFP_code_mask 0x3f
579
580#define init_LDSTiiFP \
581{ \
582 LDSTiiFP_opcode, \
583 LDSTiiFP_reg_bits, LDSTiiFP_reg_mask, \
584 LDSTiiFP_offset_bits, LDSTiiFP_offset_mask, \
585 LDSTiiFP_W_bits, LDSTiiFP_W_mask, \
586 LDSTiiFP_code_bits, LDSTiiFP_code_mask \
587};
588
589/* dspLDST
590+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
591| 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
592+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
593*/
594
595typedef struct
596{
597 unsigned short opcode;
598 int bits_reg;
599 int mask_reg;
600 int bits_i;
601 int mask_i;
602 int bits_m;
603 int mask_m;
604 int bits_aop;
605 int mask_aop;
606 int bits_W;
607 int mask_W;
608 int bits_code;
609 int mask_code;
610} DspLDST;
611
612#define DspLDST_opcode 0x9c00
613#define DspLDST_reg_bits 0
614#define DspLDST_reg_mask 0x7
615#define DspLDST_i_bits 3
616#define DspLDST_i_mask 0x3
617#define DspLDST_m_bits 5
618#define DspLDST_m_mask 0x3
619#define DspLDST_aop_bits 7
620#define DspLDST_aop_mask 0x3
621#define DspLDST_W_bits 9
622#define DspLDST_W_mask 0x1
623#define DspLDST_code_bits 10
624#define DspLDST_code_mask 0x3f
625
626#define init_DspLDST \
627{ \
628 DspLDST_opcode, \
629 DspLDST_reg_bits, DspLDST_reg_mask, \
630 DspLDST_i_bits, DspLDST_i_mask, \
631 DspLDST_m_bits, DspLDST_m_mask, \
632 DspLDST_aop_bits, DspLDST_aop_mask, \
633 DspLDST_W_bits, DspLDST_W_mask, \
634 DspLDST_code_bits, DspLDST_code_mask \
635};
636
637
638/* LDSTpmod
639+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
640| 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
641+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
642*/
643
644typedef struct
645{
646 unsigned short opcode;
647 int bits_ptr;
648 int mask_ptr;
649 int bits_idx;
650 int mask_idx;
651 int bits_reg;
652 int mask_reg;
653 int bits_aop;
654 int mask_aop;
655 int bits_W;
656 int mask_W;
657 int bits_code;
658 int mask_code;
659} LDSTpmod;
660
661#define LDSTpmod_opcode 0x8000
662#define LDSTpmod_ptr_bits 0
663#define LDSTpmod_ptr_mask 0x7
664#define LDSTpmod_idx_bits 3
665#define LDSTpmod_idx_mask 0x7
666#define LDSTpmod_reg_bits 6
667#define LDSTpmod_reg_mask 0x7
668#define LDSTpmod_aop_bits 9
669#define LDSTpmod_aop_mask 0x3
670#define LDSTpmod_W_bits 11
671#define LDSTpmod_W_mask 0x1
672#define LDSTpmod_code_bits 12
673#define LDSTpmod_code_mask 0xf
674
675#define init_LDSTpmod \
676{ \
677 LDSTpmod_opcode, \
678 LDSTpmod_ptr_bits, LDSTpmod_ptr_mask, \
679 LDSTpmod_idx_bits, LDSTpmod_idx_mask, \
680 LDSTpmod_reg_bits, LDSTpmod_reg_mask, \
681 LDSTpmod_aop_bits, LDSTpmod_aop_mask, \
682 LDSTpmod_W_bits, LDSTpmod_W_mask, \
683 LDSTpmod_code_bits, LDSTpmod_code_mask \
684};
685
686
687/* LOGI2op
688+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
689| 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
690+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
691*/
692
693typedef struct
694{
695 unsigned short opcode;
696 int bits_dst;
697 int mask_dst;
698 int bits_src;
699 int mask_src;
700 int bits_opc;
701 int mask_opc;
702 int bits_code;
703 int mask_code;
704} LOGI2op;
705
706#define LOGI2op_opcode 0x4800
707#define LOGI2op_dst_bits 0
708#define LOGI2op_dst_mask 0x7
709#define LOGI2op_src_bits 3
710#define LOGI2op_src_mask 0x1f
711#define LOGI2op_opc_bits 8
712#define LOGI2op_opc_mask 0x7
713#define LOGI2op_code_bits 11
714#define LOGI2op_code_mask 0x1f
715
716#define init_LOGI2op \
717{ \
718 LOGI2op_opcode, \
719 LOGI2op_dst_bits, LOGI2op_dst_mask, \
720 LOGI2op_src_bits, LOGI2op_src_mask, \
721 LOGI2op_opc_bits, LOGI2op_opc_mask, \
722 LOGI2op_code_bits, LOGI2op_code_mask \
723};
724
725
726/* ALU2op
727+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
728| 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
729+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
730*/
731
732typedef struct
733{
734 unsigned short opcode;
735 int bits_dst;
736 int mask_dst;
737 int bits_src;
738 int mask_src;
739 int bits_opc;
740 int mask_opc;
741 int bits_code;
742 int mask_code;
743} ALU2op;
744
745#define ALU2op_opcode 0x4000
746#define ALU2op_dst_bits 0
747#define ALU2op_dst_mask 0x7
748#define ALU2op_src_bits 3
749#define ALU2op_src_mask 0x7
750#define ALU2op_opc_bits 6
751#define ALU2op_opc_mask 0xf
752#define ALU2op_code_bits 10
753#define ALU2op_code_mask 0x3f
754
755#define init_ALU2op \
756{ \
757 ALU2op_opcode, \
758 ALU2op_dst_bits, ALU2op_dst_mask, \
759 ALU2op_src_bits, ALU2op_src_mask, \
760 ALU2op_opc_bits, ALU2op_opc_mask, \
761 ALU2op_code_bits, ALU2op_code_mask \
762};
763
764
765/* BRCC
766+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
767| 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
768+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
769*/
770
771typedef struct
772{
773 unsigned short opcode;
774 int bits_offset;
775 int mask_offset;
776 int bits_B;
777 int mask_B;
778 int bits_T;
779 int mask_T;
780 int bits_code;
781 int mask_code;
782} BRCC;
783
784#define BRCC_opcode 0x1000
785#define BRCC_offset_bits 0
786#define BRCC_offset_mask 0x3ff
787#define BRCC_B_bits 10
788#define BRCC_B_mask 0x1
789#define BRCC_T_bits 11
790#define BRCC_T_mask 0x1
791#define BRCC_code_bits 12
792#define BRCC_code_mask 0xf
793
794#define init_BRCC \
795{ \
796 BRCC_opcode, \
797 BRCC_offset_bits, BRCC_offset_mask, \
798 BRCC_B_bits, BRCC_B_mask, \
799 BRCC_T_bits, BRCC_T_mask, \
800 BRCC_code_bits, BRCC_code_mask \
801};
802
803
804/* UJUMP
805+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
806| 0 | 0 | 1 | 0 |.offset........................................|
807+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
808*/
809
810typedef struct
811{
812 unsigned short opcode;
813 int bits_offset;
814 int mask_offset;
815 int bits_code;
816 int mask_code;
817} UJump;
818
819#define UJump_opcode 0x2000
820#define UJump_offset_bits 0
821#define UJump_offset_mask 0xfff
822#define UJump_code_bits 12
823#define UJump_code_mask 0xf
824
825#define init_UJump \
826{ \
827 UJump_opcode, \
828 UJump_offset_bits, UJump_offset_mask, \
829 UJump_code_bits, UJump_code_mask \
830};
831
832
833/* ProgCtrl
834+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
835| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
836+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
837*/
838
839typedef struct
840{
841 unsigned short opcode;
842 int bits_poprnd;
843 int mask_poprnd;
844 int bits_prgfunc;
845 int mask_prgfunc;
846 int bits_code;
847 int mask_code;
848} ProgCtrl;
849
850#define ProgCtrl_opcode 0x0000
851#define ProgCtrl_poprnd_bits 0
852#define ProgCtrl_poprnd_mask 0xf
853#define ProgCtrl_prgfunc_bits 4
854#define ProgCtrl_prgfunc_mask 0xf
855#define ProgCtrl_code_bits 8
856#define ProgCtrl_code_mask 0xff
857
858#define init_ProgCtrl \
859{ \
860 ProgCtrl_opcode, \
861 ProgCtrl_poprnd_bits, ProgCtrl_poprnd_mask, \
862 ProgCtrl_prgfunc_bits, ProgCtrl_prgfunc_mask, \
863 ProgCtrl_code_bits, ProgCtrl_code_mask \
864};
865
866/* CALLa
867+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
868| 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
869|.lsw...........................................................|
870+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
871*/
872
873
874typedef struct
875{
876 unsigned long opcode;
877 int bits_addr;
878 int mask_addr;
879 int bits_S;
880 int mask_S;
881 int bits_code;
882 int mask_code;
883} CALLa;
884
885#define CALLa_opcode 0xe2000000
886#define CALLa_addr_bits 0
887#define CALLa_addr_mask 0xffffff
888#define CALLa_S_bits 24
889#define CALLa_S_mask 0x1
890#define CALLa_code_bits 25
891#define CALLa_code_mask 0x7f
892
893#define init_CALLa \
894{ \
895 CALLa_opcode, \
896 CALLa_addr_bits, CALLa_addr_mask, \
897 CALLa_S_bits, CALLa_S_mask, \
898 CALLa_code_bits, CALLa_code_mask \
899};
900
901
902/* pseudoDEBUG
903+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
904| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
905+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
906*/
907
908typedef struct
909{
910 unsigned short opcode;
911 int bits_reg;
912 int mask_reg;
913 int bits_grp;
914 int mask_grp;
915 int bits_fn;
916 int mask_fn;
917 int bits_code;
918 int mask_code;
919} PseudoDbg;
920
921#define PseudoDbg_opcode 0xf800
922#define PseudoDbg_reg_bits 0
923#define PseudoDbg_reg_mask 0x7
924#define PseudoDbg_grp_bits 3
925#define PseudoDbg_grp_mask 0x7
926#define PseudoDbg_fn_bits 6
927#define PseudoDbg_fn_mask 0x3
928#define PseudoDbg_code_bits 8
929#define PseudoDbg_code_mask 0xff
930
931#define init_PseudoDbg \
932{ \
933 PseudoDbg_opcode, \
934 PseudoDbg_reg_bits, PseudoDbg_reg_mask, \
935 PseudoDbg_grp_bits, PseudoDbg_grp_mask, \
936 PseudoDbg_fn_bits, PseudoDbg_fn_mask, \
937 PseudoDbg_code_bits, PseudoDbg_code_mask \
938};
939
940/* PseudoDbg_assert
941+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
66a6900a 942| 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
dc603df5
CM		 943|.expected......................................................|
944+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
945*/
946
947typedef struct
948{
949 unsigned long opcode;
950 int bits_expected;
951 int mask_expected;
952 int bits_regtest;
953 int mask_regtest;
66a6900a
JZ		 954 int bits_grp;
955 int mask_grp;
dc603df5
CM		 956 int bits_dbgop;
957 int mask_dbgop;
958 int bits_dontcare;
959 int mask_dontcare;
960 int bits_code;
961 int mask_code;
962} PseudoDbg_Assert;
963
964#define PseudoDbg_Assert_opcode 0xf0000000
965#define PseudoDbg_Assert_expected_bits 0
966#define PseudoDbg_Assert_expected_mask 0xffff
967#define PseudoDbg_Assert_regtest_bits 16
968#define PseudoDbg_Assert_regtest_mask 0x7
66a6900a
JZ		 969#define PseudoDbg_Assert_grp_bits 19
970#define PseudoDbg_Assert_grp_mask 0x7
971#define PseudoDbg_Assert_dbgop_bits 22
972#define PseudoDbg_Assert_dbgop_mask 0x3
973#define PseudoDbg_Assert_dontcare_bits 24
974#define PseudoDbg_Assert_dontcare_mask 0x7
dc603df5
CM		 975#define PseudoDbg_Assert_code_bits 27
976#define PseudoDbg_Assert_code_mask 0x1f
977
978#define init_PseudoDbg_Assert \
979{ \
980 PseudoDbg_Assert_opcode, \
981 PseudoDbg_Assert_expected_bits, PseudoDbg_Assert_expected_mask, \
982 PseudoDbg_Assert_regtest_bits, PseudoDbg_Assert_regtest_mask, \
66a6900a 983 PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask, \
dc603df5
CM		 984 PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, \
985 PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask, \
986 PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \
987};
988
989/* CaCTRL
990+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
991| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
992+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
993*/
994
995typedef struct
996{
997 unsigned short opcode;
998 int bits_reg;
999 int mask_reg;
1000 int bits_op;
1001 int mask_op;
1002 int bits_a;
1003 int mask_a;
1004 int bits_code;
1005 int mask_code;
1006} CaCTRL;
1007
1008#define CaCTRL_opcode 0x0240
1009#define CaCTRL_reg_bits 0
1010#define CaCTRL_reg_mask 0x7
1011#define CaCTRL_op_bits 3
1012#define CaCTRL_op_mask 0x3
1013#define CaCTRL_a_bits 5
1014#define CaCTRL_a_mask 0x1
1015#define CaCTRL_code_bits 6
1016#define CaCTRL_code_mask 0x3fff
1017
1018#define init_CaCTRL \
1019{ \
1020 CaCTRL_opcode, \
1021 CaCTRL_reg_bits, CaCTRL_reg_mask, \
1022 CaCTRL_op_bits, CaCTRL_op_mask, \
1023 CaCTRL_a_bits, CaCTRL_a_mask, \
1024 CaCTRL_code_bits, CaCTRL_code_mask \
1025};
1026
1027/* PushPopMultiple
1028+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1029| 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
1030+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1031*/
1032
1033typedef struct
1034{
1035 unsigned short opcode;
1036 int bits_pr;
1037 int mask_pr;
1038 int bits_dr;
1039 int mask_dr;
1040 int bits_W;
1041 int mask_W;
1042 int bits_p;
1043 int mask_p;
1044 int bits_d;
1045 int mask_d;
1046 int bits_code;
1047 int mask_code;
1048} PushPopMultiple;
1049
1050#define PushPopMultiple_opcode 0x0400
1051#define PushPopMultiple_pr_bits 0
1052#define PushPopMultiple_pr_mask 0x7
1053#define PushPopMultiple_dr_bits 3
1054#define PushPopMultiple_dr_mask 0x7
1055#define PushPopMultiple_W_bits 6
1056#define PushPopMultiple_W_mask 0x1
1057#define PushPopMultiple_p_bits 7
1058#define PushPopMultiple_p_mask 0x1
1059#define PushPopMultiple_d_bits 8
1060#define PushPopMultiple_d_mask 0x1
1061#define PushPopMultiple_code_bits 8
1062#define PushPopMultiple_code_mask 0x1
1063
1064#define init_PushPopMultiple \
1065{ \
1066 PushPopMultiple_opcode, \
1067 PushPopMultiple_pr_bits, PushPopMultiple_pr_mask, \
1068 PushPopMultiple_dr_bits, PushPopMultiple_dr_mask, \
1069 PushPopMultiple_W_bits, PushPopMultiple_W_mask, \
1070 PushPopMultiple_p_bits, PushPopMultiple_p_mask, \
1071 PushPopMultiple_d_bits, PushPopMultiple_d_mask, \
1072 PushPopMultiple_code_bits, PushPopMultiple_code_mask \
1073};
1074
1075/* PushPopReg
1076+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1077| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
1078+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1079*/
1080
1081typedef struct
1082{
1083 unsigned short opcode;
1084 int bits_reg;
1085 int mask_reg;
1086 int bits_grp;
1087 int mask_grp;
1088 int bits_W;
1089 int mask_W;
1090 int bits_code;
1091 int mask_code;
1092} PushPopReg;
1093
1094#define PushPopReg_opcode 0x0100
1095#define PushPopReg_reg_bits 0
1096#define PushPopReg_reg_mask 0x7
1097#define PushPopReg_grp_bits 3
1098#define PushPopReg_grp_mask 0x7
1099#define PushPopReg_W_bits 6
1100#define PushPopReg_W_mask 0x1
1101#define PushPopReg_code_bits 7
1102#define PushPopReg_code_mask 0x1ff
1103
1104#define init_PushPopReg \
1105{ \
1106 PushPopReg_opcode, \
1107 PushPopReg_reg_bits, PushPopReg_reg_mask, \
1108 PushPopReg_grp_bits, PushPopReg_grp_mask, \
1109 PushPopReg_W_bits, PushPopReg_W_mask, \
1110 PushPopReg_code_bits, PushPopReg_code_mask, \
1111};
1112
1113/* linkage
1114+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1115| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
1116|.framesize.....................................................|
1117+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1118*/
1119
1120typedef struct
1121{
1122 unsigned long opcode;
1123 int bits_framesize;
1124 int mask_framesize;
1125 int bits_R;
1126 int mask_R;
1127 int bits_code;
1128 int mask_code;
1129} Linkage;
1130
1131#define Linkage_opcode 0xe8000000
1132#define Linkage_framesize_bits 0
1133#define Linkage_framesize_mask 0xffff
1134#define Linkage_R_bits 16
1135#define Linkage_R_mask 0x1
1136#define Linkage_code_bits 17
1137#define Linkage_code_mask 0x7fff
1138
1139#define init_Linkage \
1140{ \
1141 Linkage_opcode, \
1142 Linkage_framesize_bits, Linkage_framesize_mask, \
1143 Linkage_R_bits, Linkage_R_mask, \
1144 Linkage_code_bits, Linkage_code_mask \
1145};
1146
1147/* LoopSetup
1148+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1149| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
1150|.reg...........| - | - |.eoffset...............................|
1151+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1152*/
1153
1154typedef struct
1155{
1156 unsigned long opcode;
1157 int bits_eoffset;
1158 int mask_eoffset;
1159 int bits_dontcare;
1160 int mask_dontcare;
1161 int bits_reg;
1162 int mask_reg;
1163 int bits_soffset;
1164 int mask_soffset;
1165 int bits_c;
1166 int mask_c;
1167 int bits_rop;
1168 int mask_rop;
1169 int bits_code;
1170 int mask_code;
1171} LoopSetup;
1172
1173#define LoopSetup_opcode 0xe0800000
1174#define LoopSetup_eoffset_bits 0
1175#define LoopSetup_eoffset_mask 0x3ff
1176#define LoopSetup_dontcare_bits 10
1177#define LoopSetup_dontcare_mask 0x3
1178#define LoopSetup_reg_bits 12
1179#define LoopSetup_reg_mask 0xf
1180#define LoopSetup_soffset_bits 16
1181#define LoopSetup_soffset_mask 0xf
1182#define LoopSetup_c_bits 20
1183#define LoopSetup_c_mask 0x1
1184#define LoopSetup_rop_bits 21
1185#define LoopSetup_rop_mask 0x3
1186#define LoopSetup_code_bits 23
1187#define LoopSetup_code_mask 0x1ff
1188
1189#define init_LoopSetup \
1190{ \
1191 LoopSetup_opcode, \
1192 LoopSetup_eoffset_bits, LoopSetup_eoffset_mask, \
1193 LoopSetup_dontcare_bits, LoopSetup_dontcare_mask, \
1194 LoopSetup_reg_bits, LoopSetup_reg_mask, \
1195 LoopSetup_soffset_bits, LoopSetup_soffset_mask, \
1196 LoopSetup_c_bits, LoopSetup_c_mask, \
1197 LoopSetup_rop_bits, LoopSetup_rop_mask, \
1198 LoopSetup_code_bits, LoopSetup_code_mask \
1199};
1200
1201/* LDIMMhalf
1202+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1203| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
1204|.hword.........................................................|
1205+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1206*/
1207
1208typedef struct
1209{
1210 unsigned long opcode;
1211 int bits_hword;
1212 int mask_hword;
1213 int bits_reg;
1214 int mask_reg;
1215 int bits_grp;
1216 int mask_grp;
1217 int bits_S;
1218 int mask_S;
1219 int bits_H;
1220 int mask_H;
1221 int bits_Z;
1222 int mask_Z;
1223 int bits_code;
1224 int mask_code;
1225} LDIMMhalf;
1226
1227#define LDIMMhalf_opcode 0xe1000000
1228#define LDIMMhalf_hword_bits 0
1229#define LDIMMhalf_hword_mask 0xffff
1230#define LDIMMhalf_reg_bits 16
1231#define LDIMMhalf_reg_mask 0x7
1232#define LDIMMhalf_grp_bits 19
1233#define LDIMMhalf_grp_mask 0x3
1234#define LDIMMhalf_S_bits 21
1235#define LDIMMhalf_S_mask 0x1
1236#define LDIMMhalf_H_bits 22
1237#define LDIMMhalf_H_mask 0x1
1238#define LDIMMhalf_Z_bits 23
1239#define LDIMMhalf_Z_mask 0x1
1240#define LDIMMhalf_code_bits 24
1241#define LDIMMhalf_code_mask 0xff
1242
1243#define init_LDIMMhalf \
1244{ \
1245 LDIMMhalf_opcode, \
1246 LDIMMhalf_hword_bits, LDIMMhalf_hword_mask, \
1247 LDIMMhalf_reg_bits, LDIMMhalf_reg_mask, \
1248 LDIMMhalf_grp_bits, LDIMMhalf_grp_mask, \
1249 LDIMMhalf_S_bits, LDIMMhalf_S_mask, \
1250 LDIMMhalf_H_bits, LDIMMhalf_H_mask, \
1251 LDIMMhalf_Z_bits, LDIMMhalf_Z_mask, \
1252 LDIMMhalf_code_bits, LDIMMhalf_code_mask \
1253};
1254
1255
1256/* CC2dreg
1257+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1258| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1259+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1260*/
1261
1262typedef struct
1263{
1264 unsigned short opcode;
1265 int bits_reg;
1266 int mask_reg;
1267 int bits_op;
1268 int mask_op;
1269 int bits_code;
1270 int mask_code;
1271} CC2dreg;
1272
1273#define CC2dreg_opcode 0x0200
1274#define CC2dreg_reg_bits 0
1275#define CC2dreg_reg_mask 0x7
1276#define CC2dreg_op_bits 3
1277#define CC2dreg_op_mask 0x3
1278#define CC2dreg_code_bits 5
1279#define CC2dreg_code_mask 0x7fff
1280
1281#define init_CC2dreg \
1282{ \
1283 CC2dreg_opcode, \
1284 CC2dreg_reg_bits, CC2dreg_reg_mask, \
1285 CC2dreg_op_bits, CC2dreg_op_mask, \
1286 CC2dreg_code_bits, CC2dreg_code_mask \
1287};
1288
1289
1290/* PTR2op
1291+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1292| 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1293+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1294*/
1295
1296typedef struct
1297{
1298 unsigned short opcode;
1299 int bits_dst;
1300 int mask_dst;
1301 int bits_src;
1302 int mask_src;
1303 int bits_opc;
1304 int mask_opc;
1305 int bits_code;
1306 int mask_code;
1307} PTR2op;
1308
1309#define PTR2op_opcode 0x4400
1310#define PTR2op_dst_bits 0
1311#define PTR2op_dst_mask 0x7
1312#define PTR2op_src_bits 3
1313#define PTR2op_src_mask 0x7
1314#define PTR2op_opc_bits 6
1315#define PTR2op_opc_mask 0x7
1316#define PTR2op_code_bits 9
1317#define PTR2op_code_mask 0x7f
1318
1319#define init_PTR2op \
1320{ \
1321 PTR2op_opcode, \
1322 PTR2op_dst_bits, PTR2op_dst_mask, \
1323 PTR2op_src_bits, PTR2op_src_mask, \
1324 PTR2op_opc_bits, PTR2op_opc_mask, \
1325 PTR2op_code_bits, PTR2op_code_mask \
1326};
1327
1328
1329/* COMP3op
1330+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1331| 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1332+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1333*/
1334
1335typedef struct
1336{
1337 unsigned short opcode;
1338 int bits_src0;
1339 int mask_src0;
1340 int bits_src1;
1341 int mask_src1;
1342 int bits_dst;
1343 int mask_dst;
1344 int bits_opc;
1345 int mask_opc;
1346 int bits_code;
1347 int mask_code;
1348} COMP3op;
1349
1350#define COMP3op_opcode 0x5000
1351#define COMP3op_src0_bits 0
1352#define COMP3op_src0_mask 0x7
1353#define COMP3op_src1_bits 3
1354#define COMP3op_src1_mask 0x7
1355#define COMP3op_dst_bits 6
1356#define COMP3op_dst_mask 0x7
1357#define COMP3op_opc_bits 9
1358#define COMP3op_opc_mask 0x7
1359#define COMP3op_code_bits 12
1360#define COMP3op_code_mask 0xf
1361
1362#define init_COMP3op \
1363{ \
1364 COMP3op_opcode, \
1365 COMP3op_src0_bits, COMP3op_src0_mask, \
1366 COMP3op_src1_bits, COMP3op_src1_mask, \
1367 COMP3op_dst_bits, COMP3op_dst_mask, \
1368 COMP3op_opc_bits, COMP3op_opc_mask, \
1369 COMP3op_code_bits, COMP3op_code_mask \
1370};
1371
1372/* ccMV
1373+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1374| 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
1375+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1376*/
1377
1378typedef struct
1379{
1380 unsigned short opcode;
1381 int bits_src;
1382 int mask_src;
1383 int bits_dst;
1384 int mask_dst;
1385 int bits_s;
1386 int mask_s;
1387 int bits_d;
1388 int mask_d;
1389 int bits_T;
1390 int mask_T;
1391 int bits_code;
1392 int mask_code;
1393} CCmv;
1394
1395#define CCmv_opcode 0x0600
1396#define CCmv_src_bits 0
1397#define CCmv_src_mask 0x7
1398#define CCmv_dst_bits 3
1399#define CCmv_dst_mask 0x7
1400#define CCmv_s_bits 6
1401#define CCmv_s_mask 0x1
1402#define CCmv_d_bits 7
1403#define CCmv_d_mask 0x1
1404#define CCmv_T_bits 8
1405#define CCmv_T_mask 0x1
1406#define CCmv_code_bits 9
1407#define CCmv_code_mask 0x7f
1408
1409#define init_CCmv \
1410{ \
1411 CCmv_opcode, \
1412 CCmv_src_bits, CCmv_src_mask, \
1413 CCmv_dst_bits, CCmv_dst_mask, \
1414 CCmv_s_bits, CCmv_s_mask, \
1415 CCmv_d_bits, CCmv_d_mask, \
1416 CCmv_T_bits, CCmv_T_mask, \
1417 CCmv_code_bits, CCmv_code_mask \
1418};
1419
1420
1421/* CCflag
1422+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1423| 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1424+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1425*/
1426
1427typedef struct
1428{
1429 unsigned short opcode;
1430 int bits_x;
1431 int mask_x;
1432 int bits_y;
1433 int mask_y;
1434 int bits_G;
1435 int mask_G;
1436 int bits_opc;
1437 int mask_opc;
1438 int bits_I;
1439 int mask_I;
1440 int bits_code;
1441 int mask_code;
1442} CCflag;
1443
1444#define CCflag_opcode 0x0800
1445#define CCflag_x_bits 0
1446#define CCflag_x_mask 0x7
1447#define CCflag_y_bits 3
1448#define CCflag_y_mask 0x7
1449#define CCflag_G_bits 6
1450#define CCflag_G_mask 0x1
1451#define CCflag_opc_bits 7
1452#define CCflag_opc_mask 0x7
1453#define CCflag_I_bits 10
1454#define CCflag_I_mask 0x1
1455#define CCflag_code_bits 11
1456#define CCflag_code_mask 0x1f
1457
1458#define init_CCflag \
1459{ \
1460 CCflag_opcode, \
1461 CCflag_x_bits, CCflag_x_mask, \
1462 CCflag_y_bits, CCflag_y_mask, \
1463 CCflag_G_bits, CCflag_G_mask, \
1464 CCflag_opc_bits, CCflag_opc_mask, \
1465 CCflag_I_bits, CCflag_I_mask, \
1466 CCflag_code_bits, CCflag_code_mask, \
1467};
1468
1469
1470/* CC2stat
1471+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1472| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1473+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1474*/
1475
1476typedef struct
1477{
1478 unsigned short opcode;
1479 int bits_cbit;
1480 int mask_cbit;
1481 int bits_op;
1482 int mask_op;
1483 int bits_D;
1484 int mask_D;
1485 int bits_code;
1486 int mask_code;
1487} CC2stat;
1488
1489#define CC2stat_opcode 0x0300
1490#define CC2stat_cbit_bits 0
1491#define CC2stat_cbit_mask 0x1f
1492#define CC2stat_op_bits 5
1493#define CC2stat_op_mask 0x3
1494#define CC2stat_D_bits 7
1495#define CC2stat_D_mask 0x1
1496#define CC2stat_code_bits 8
1497#define CC2stat_code_mask 0xff
1498
1499#define init_CC2stat \
1500{ \
1501 CC2stat_opcode, \
1502 CC2stat_cbit_bits, CC2stat_cbit_mask, \
1503 CC2stat_op_bits, CC2stat_op_mask, \
1504 CC2stat_D_bits, CC2stat_D_mask, \
1505 CC2stat_code_bits, CC2stat_code_mask \
1506};
1507
1508
1509/* REGMV
1510+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1511| 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1512+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1513*/
1514
1515typedef struct
1516{
1517 unsigned short opcode;
1518 int bits_src;
1519 int mask_src;
1520 int bits_dst;
1521 int mask_dst;
1522 int bits_gs;
1523 int mask_gs;
1524 int bits_gd;
1525 int mask_gd;
1526 int bits_code;
1527 int mask_code;
1528} RegMv;
1529
1530#define RegMv_opcode 0x3000
1531#define RegMv_src_bits 0
1532#define RegMv_src_mask 0x7
1533#define RegMv_dst_bits 3
1534#define RegMv_dst_mask 0x7
1535#define RegMv_gs_bits 6
1536#define RegMv_gs_mask 0x7
1537#define RegMv_gd_bits 9
1538#define RegMv_gd_mask 0x7
1539#define RegMv_code_bits 12
1540#define RegMv_code_mask 0xf
1541
1542#define init_RegMv \
1543{ \
1544 RegMv_opcode, \
1545 RegMv_src_bits, RegMv_src_mask, \
1546 RegMv_dst_bits, RegMv_dst_mask, \
1547 RegMv_gs_bits, RegMv_gs_mask, \
1548 RegMv_gd_bits, RegMv_gd_mask, \
1549 RegMv_code_bits, RegMv_code_mask \
1550};
1551
1552
1553/* COMPI2opD
1554+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1555| 0 | 1 | 1 | 0 | 0 |.op|.isrc......................|.dst.......|
1556+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1557*/
1558
1559typedef struct
1560{
1561 unsigned short opcode;
1562 int bits_dst;
1563 int mask_dst;
1564 int bits_src;
1565 int mask_src;
1566 int bits_op;
1567 int mask_op;
1568 int bits_code;
1569 int mask_code;
1570} COMPI2opD;
1571
1572#define COMPI2opD_opcode 0x6000
1573#define COMPI2opD_dst_bits 0
1574#define COMPI2opD_dst_mask 0x7
1575#define COMPI2opD_src_bits 3
1576#define COMPI2opD_src_mask 0x7f
1577#define COMPI2opD_op_bits 10
1578#define COMPI2opD_op_mask 0x1
1579#define COMPI2opD_code_bits 11
1580#define COMPI2opD_code_mask 0x1f
1581
1582#define init_COMPI2opD \
1583{ \
1584 COMPI2opD_opcode, \
1585 COMPI2opD_dst_bits, COMPI2opD_dst_mask, \
1586 COMPI2opD_src_bits, COMPI2opD_src_mask, \
1587 COMPI2opD_op_bits, COMPI2opD_op_mask, \
1588 COMPI2opD_code_bits, COMPI2opD_code_mask \
1589};
1590
1591/* COMPI2opP
1592+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1593| 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1594+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1595*/
1596
1597typedef COMPI2opD COMPI2opP;
1598
1599#define COMPI2opP_opcode 0x6800
1600#define COMPI2opP_dst_bits 0
1601#define COMPI2opP_dst_mask 0x7
1602#define COMPI2opP_src_bits 3
1603#define COMPI2opP_src_mask 0x7f
1604#define COMPI2opP_op_bits 10
1605#define COMPI2opP_op_mask 0x1
1606#define COMPI2opP_code_bits 11
1607#define COMPI2opP_code_mask 0x1f
1608
1609#define init_COMPI2opP \
1610{ \
1611 COMPI2opP_opcode, \
1612 COMPI2opP_dst_bits, COMPI2opP_dst_mask, \
1613 COMPI2opP_src_bits, COMPI2opP_src_mask, \
1614 COMPI2opP_op_bits, COMPI2opP_op_mask, \
1615 COMPI2opP_code_bits, COMPI2opP_code_mask \
1616};
1617
1618
1619/* dagMODim
1620+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1621| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1622+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1623*/
1624
1625typedef struct
1626{
1627 unsigned short opcode;
1628 int bits_i;
1629 int mask_i;
1630 int bits_m;
1631 int mask_m;
1632 int bits_op;
1633 int mask_op;
1634 int bits_code2;
1635 int mask_code2;
1636 int bits_br;
1637 int mask_br;
1638 int bits_code;
1639 int mask_code;
1640} DagMODim;
1641
1642#define DagMODim_opcode 0x9e60
1643#define DagMODim_i_bits 0
1644#define DagMODim_i_mask 0x3
1645#define DagMODim_m_bits 2
1646#define DagMODim_m_mask 0x3
1647#define DagMODim_op_bits 4
1648#define DagMODim_op_mask 0x1
1649#define DagMODim_code2_bits 5
1650#define DagMODim_code2_mask 0x3
1651#define DagMODim_br_bits 7
1652#define DagMODim_br_mask 0x1
1653#define DagMODim_code_bits 8
1654#define DagMODim_code_mask 0xff
1655
1656#define init_DagMODim \
1657{ \
1658 DagMODim_opcode, \
1659 DagMODim_i_bits, DagMODim_i_mask, \
1660 DagMODim_m_bits, DagMODim_m_mask, \
1661 DagMODim_op_bits, DagMODim_op_mask, \
1662 DagMODim_code2_bits, DagMODim_code2_mask, \
1663 DagMODim_br_bits, DagMODim_br_mask, \
1664 DagMODim_code_bits, DagMODim_code_mask \
1665};
1666
1667/* dagMODik
1668+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1669| 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
1670+---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1671*/
1672
1673typedef struct
1674{
1675 unsigned short opcode;
1676 int bits_i;
1677 int mask_i;
1678 int bits_op;
1679 int mask_op;
1680 int bits_code;
1681 int mask_code;
1682} DagMODik;
1683
1684#define DagMODik_opcode 0x9f60
1685#define DagMODik_i_bits 0
1686#define DagMODik_i_mask 0x3
1687#define DagMODik_op_bits 2
1688#define DagMODik_op_mask 0x3
1689#define DagMODik_code_bits 3
1690#define DagMODik_code_mask 0xfff
1691
1692#define init_DagMODik \
1693{ \
1694 DagMODik_opcode, \
1695 DagMODik_i_bits, DagMODik_i_mask, \
1696 DagMODik_op_bits, DagMODik_op_mask, \
1697 DagMODik_code_bits, DagMODik_code_mask \
1698};
GDB Binutils - Deliverables
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