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3d3d428f | 1 | /* cr16.h -- Header file for CR16 opcode and register tables. |
bab4becb | 2 | Copyright 2007, 2008, 2010, 2013 Free Software Foundation, Inc. |
3d3d428f NC |
3 | Contributed by M R Swami Reddy |
4 | ||
5 | This file is part of GAS, GDB and the GNU binutils. | |
6 | ||
7 | GAS, GDB, and GNU binutils is free software; you can redistribute it | |
8 | and/or modify it under the terms of the GNU General Public License as | |
e4e42b45 | 9 | published by the Free Software Foundation; either version 3, or (at your |
3d3d428f NC |
10 | option) any later version. |
11 | ||
12 | GAS, GDB, and GNU binutils are distributed in the hope that they will be | |
13 | useful, but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software Foundation, | |
19 | Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ | |
20 | ||
21 | #ifndef _CR16_H_ | |
22 | #define _CR16_H_ | |
23 | ||
24 | /* CR16 core Registers : | |
25 | The enums are used as indices to CR16 registers table (cr16_regtab). | |
26 | Therefore, order MUST be preserved. */ | |
27 | ||
28 | typedef enum | |
bab4becb NC |
29 | { |
30 | /* 16-bit general purpose registers. */ | |
31 | r0, r1, r2, r3, | |
32 | r4, r5, r6, r7, | |
33 | r8, r9, r10, r11, | |
34 | r12_L = 12, r13_L = 13, ra = 14, sp_L = 15, | |
35 | ||
36 | /* 32-bit general purpose registers. */ | |
37 | r12 = 12, r13 = 13, r14 = 14, r15 = 15, | |
38 | era = 14, sp = 15, RA, | |
39 | ||
40 | /* Not a register. */ | |
41 | nullregister, | |
42 | MAX_REG | |
43 | } | |
3d3d428f NC |
44 | reg; |
45 | ||
46 | /* CR16 processor registers and special registers : | |
47 | The enums are used as indices to CR16 processor registers table | |
48 | (cr16_pregtab). Therefore, order MUST be preserved. */ | |
49 | ||
50 | typedef enum | |
bab4becb NC |
51 | { |
52 | /* processor registers. */ | |
53 | dbs = MAX_REG, | |
54 | dsr, dcrl, dcrh, | |
55 | car0l, car0h, car1l, car1h, | |
56 | cfg, psr, intbasel, intbaseh, | |
57 | ispl, isph, uspl, usph, | |
58 | dcr = dcrl, | |
59 | car0 = car0l, | |
60 | car1 = car1l, | |
61 | intbase = intbasel, | |
62 | isp = ispl, | |
63 | usp = uspl, | |
64 | /* Not a processor register. */ | |
65 | nullpregister = usph + 1, | |
66 | MAX_PREG | |
67 | } | |
3d3d428f NC |
68 | preg; |
69 | ||
70 | /* CR16 Register types. */ | |
71 | ||
72 | typedef enum | |
bab4becb NC |
73 | { |
74 | CR16_R_REGTYPE, /* r<N> */ | |
75 | CR16_RP_REGTYPE, /* reg pair */ | |
76 | CR16_P_REGTYPE /* Processor register */ | |
77 | } | |
3d3d428f NC |
78 | reg_type; |
79 | ||
80 | /* CR16 argument types : | |
81 | The argument types correspond to instructions operands | |
82 | ||
83 | Argument types : | |
84 | r - register | |
85 | rp - register pair | |
86 | c - constant | |
87 | i - immediate | |
88 | idxr - index with register | |
89 | idxrp - index with register pair | |
90 | rbase - register base | |
91 | rpbase - register pair base | |
bab4becb | 92 | pr - processor register. */ |
3d3d428f NC |
93 | |
94 | typedef enum | |
bab4becb NC |
95 | { |
96 | arg_r, | |
97 | arg_c, | |
98 | arg_cr, | |
99 | arg_crp, | |
100 | arg_ic, | |
101 | arg_icr, | |
102 | arg_idxr, | |
103 | arg_idxrp, | |
104 | arg_rbase, | |
105 | arg_rpbase, | |
106 | arg_rp, | |
107 | arg_pr, | |
108 | arg_prp, | |
109 | arg_cc, | |
110 | arg_ra, | |
111 | /* Not an argument. */ | |
112 | nullargs | |
113 | } | |
3d3d428f NC |
114 | argtype; |
115 | ||
bab4becb | 116 | /* CR16 operand types:The operand types correspond to instructions operands. */ |
3d3d428f NC |
117 | |
118 | typedef enum | |
bab4becb NC |
119 | { |
120 | dummy, | |
121 | /* N-bit signed immediate. */ | |
122 | imm3, imm4, imm5, imm6, imm16, imm20, imm32, | |
123 | /* N-bit unsigned immediate. */ | |
124 | uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32, | |
125 | /* N-bit signed displacement. */ | |
126 | disps5, disps17, disps25, | |
127 | /* N-bit unsigned displacement. */ | |
128 | dispe9, | |
129 | /* N-bit absolute address. */ | |
130 | abs20, abs24, | |
131 | /* Register relative. */ | |
132 | rra, rbase, rbase_disps20, rbase_dispe20, | |
133 | /* Register pair relative. */ | |
134 | rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16, | |
135 | rpbase_disps20, rpbase_dispe20, | |
136 | /* Register index. */ | |
137 | rindex7_abs20, rindex8_abs20, | |
138 | /* Register pair index. */ | |
139 | rpindex_disps0, rpindex_disps14, rpindex_disps20, | |
140 | /* register. */ | |
141 | regr, | |
142 | /* register pair. */ | |
143 | regp, | |
144 | /* processor register. */ | |
145 | pregr, | |
146 | /* processor register 32 bit. */ | |
147 | pregrp, | |
148 | /* condition code - 4 bit. */ | |
149 | cc, | |
150 | /* Not an operand. */ | |
151 | nulloperand, | |
152 | /* Maximum supported operand. */ | |
153 | MAX_OPRD | |
154 | } | |
3d3d428f NC |
155 | operand_type; |
156 | ||
157 | /* CR16 instruction types. */ | |
158 | ||
159 | #define NO_TYPE_INS 0 | |
160 | #define ARITH_INS 1 | |
161 | #define LD_STOR_INS 2 | |
162 | #define BRANCH_INS 3 | |
163 | #define ARITH_BYTE_INS 4 | |
164 | #define SHIFT_INS 5 | |
165 | #define BRANCH_NEQ_INS 6 | |
166 | #define LD_STOR_INS_INC 7 | |
167 | #define STOR_IMM_INS 8 | |
168 | #define CSTBIT_INS 9 | |
169 | ||
170 | /* Maximum value supported for instruction types. */ | |
171 | #define CR16_INS_MAX (1 << 4) | |
172 | /* Mask to record an instruction type. */ | |
173 | #define CR16_INS_MASK (CR16_INS_MAX - 1) | |
174 | /* Return instruction type, given instruction's attributes. */ | |
175 | #define CR16_INS_TYPE(attr) ((attr) & CR16_INS_MASK) | |
176 | ||
177 | /* Indicates whether this instruction has a register list as parameter. */ | |
178 | #define REG_LIST CR16_INS_MAX | |
179 | ||
180 | /* The operands in binary and assembly are placed in reverse order. | |
181 | load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ | |
182 | #define REVERSE_MATCH (1 << 5) | |
183 | ||
184 | /* Printing formats, where the instruction prefix isn't consecutive. */ | |
185 | #define FMT_1 (1 << 9) /* 0xF0F00000 */ | |
186 | #define FMT_2 (1 << 10) /* 0xFFF0FF00 */ | |
187 | #define FMT_3 (1 << 11) /* 0xFFF00F00 */ | |
188 | #define FMT_4 (1 << 12) /* 0xFFF0F000 */ | |
189 | #define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ | |
190 | #define FMT_CR16 (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) | |
191 | ||
192 | /* Indicates whether this instruction can be relaxed. */ | |
193 | #define RELAXABLE (1 << 14) | |
194 | ||
195 | /* Indicates that instruction uses user registers (and not | |
196 | general-purpose registers) as operands. */ | |
197 | #define USER_REG (1 << 15) | |
198 | ||
199 | ||
200 | /* Instruction shouldn't allow 'sp' usage. */ | |
201 | #define NO_SP (1 << 17) | |
202 | ||
203 | /* Instruction shouldn't allow to push a register which is used as a rptr. */ | |
204 | #define NO_RPTR (1 << 18) | |
205 | ||
206 | /* Maximum operands per instruction. */ | |
207 | #define MAX_OPERANDS 5 | |
208 | /* Maximum register name length. */ | |
209 | #define MAX_REGNAME_LEN 10 | |
210 | /* Maximum instruction length. */ | |
211 | #define MAX_INST_LEN 256 | |
212 | ||
213 | ||
214 | /* Values defined for the flags field of a struct operand_entry. */ | |
215 | ||
216 | /* Operand must be an unsigned number. */ | |
217 | #define OP_UNSIGNED (1 << 0) | |
218 | /* Operand must be a signed number. */ | |
219 | #define OP_SIGNED (1 << 1) | |
220 | /* Operand must be a negative number. */ | |
221 | #define OP_NEG (1 << 2) | |
222 | /* A special load/stor 4-bit unsigned displacement operand. */ | |
223 | #define OP_DEC (1 << 3) | |
224 | /* Operand must be an even number. */ | |
225 | #define OP_EVEN (1 << 4) | |
226 | /* Operand is shifted right. */ | |
227 | #define OP_SHIFT (1 << 5) | |
228 | /* Operand is shifted right and decremented. */ | |
229 | #define OP_SHIFT_DEC (1 << 6) | |
230 | /* Operand has reserved escape sequences. */ | |
231 | #define OP_ESC (1 << 7) | |
232 | /* Operand must be a ABS20 number. */ | |
233 | #define OP_ABS20 (1 << 8) | |
234 | /* Operand must be a ABS24 number. */ | |
235 | #define OP_ABS24 (1 << 9) | |
236 | /* Operand has reserved escape sequences type 1. */ | |
237 | #define OP_ESC1 (1 << 10) | |
238 | ||
239 | /* Single operand description. */ | |
240 | ||
241 | typedef struct | |
bab4becb NC |
242 | { |
243 | /* Operand type. */ | |
244 | operand_type op_type; | |
245 | /* Operand location within the opcode. */ | |
246 | unsigned int shift; | |
247 | } | |
3d3d428f NC |
248 | operand_desc; |
249 | ||
250 | /* Instruction data structure used in instruction table. */ | |
251 | ||
252 | typedef struct | |
bab4becb NC |
253 | { |
254 | /* Name. */ | |
255 | const char *mnemonic; | |
256 | /* Size (in words). */ | |
257 | unsigned int size; | |
258 | /* Constant prefix (matched by the disassembler). */ | |
259 | unsigned long match; /* ie opcode */ | |
260 | /* Match size (in bits). */ | |
261 | /* MASK: if( (i & match_bits) == match ) then match */ | |
262 | int match_bits; | |
263 | /* Attributes. */ | |
264 | unsigned int flags; | |
265 | /* Operands (always last, so unreferenced operands are initialized). */ | |
266 | operand_desc operands[MAX_OPERANDS]; | |
267 | } | |
3d3d428f NC |
268 | inst; |
269 | ||
270 | /* Data structure for a single instruction's arguments (Operands). */ | |
271 | ||
272 | typedef struct | |
bab4becb NC |
273 | { |
274 | /* Register or base register. */ | |
275 | reg r; | |
276 | /* Register pair register. */ | |
277 | reg rp; | |
278 | /* Index register. */ | |
279 | reg i_r; | |
280 | /* Processor register. */ | |
281 | preg pr; | |
282 | /* Processor register. 32 bit */ | |
283 | preg prp; | |
284 | /* Constant/immediate/absolute value. */ | |
285 | long constant; | |
286 | /* CC code. */ | |
287 | unsigned int cc; | |
288 | /* Scaled index mode. */ | |
289 | unsigned int scale; | |
290 | /* Argument type. */ | |
291 | argtype type; | |
292 | /* Size of the argument (in bits) required to represent. */ | |
293 | int size; | |
3d3d428f | 294 | /* The type of the expression. */ |
bab4becb NC |
295 | unsigned char X_op; |
296 | } | |
3d3d428f NC |
297 | argument; |
298 | ||
299 | /* Internal structure to hold the various entities | |
300 | corresponding to the current assembling instruction. */ | |
301 | ||
302 | typedef struct | |
bab4becb NC |
303 | { |
304 | /* Number of arguments. */ | |
305 | int nargs; | |
306 | /* The argument data structure for storing args (operands). */ | |
307 | argument arg[MAX_OPERANDS]; | |
3d3d428f NC |
308 | /* The following fields are required only by CR16-assembler. */ |
309 | #ifdef TC_CR16 | |
bab4becb NC |
310 | /* Expression used for setting the fixups (if any). */ |
311 | expressionS exp; | |
312 | bfd_reloc_code_real_type rtype; | |
3d3d428f | 313 | #endif /* TC_CR16 */ |
bab4becb NC |
314 | /* Instruction size (in bytes). */ |
315 | int size; | |
316 | } | |
3d3d428f NC |
317 | ins; |
318 | ||
319 | /* Structure to hold information about predefined operands. */ | |
320 | ||
321 | typedef struct | |
bab4becb NC |
322 | { |
323 | /* Size (in bits). */ | |
324 | unsigned int bit_size; | |
325 | /* Argument type. */ | |
326 | argtype arg_type; | |
327 | /* One bit syntax flags. */ | |
328 | int flags; | |
329 | } | |
3d3d428f NC |
330 | operand_entry; |
331 | ||
332 | /* Structure to hold trap handler information. */ | |
333 | ||
334 | typedef struct | |
bab4becb NC |
335 | { |
336 | /* Trap name. */ | |
337 | char *name; | |
338 | /* Index in dispatch table. */ | |
339 | unsigned int entry; | |
340 | } | |
3d3d428f NC |
341 | trap_entry; |
342 | ||
343 | /* Structure to hold information about predefined registers. */ | |
344 | ||
345 | typedef struct | |
bab4becb NC |
346 | { |
347 | /* Name (string representation). */ | |
348 | char *name; | |
349 | /* Value (enum representation). */ | |
350 | union | |
3d3d428f | 351 | { |
bab4becb NC |
352 | /* Register. */ |
353 | reg reg_val; | |
354 | /* processor register. */ | |
355 | preg preg_val; | |
356 | } value; | |
357 | /* Register image. */ | |
358 | int image; | |
359 | /* Register type. */ | |
360 | reg_type type; | |
361 | } | |
3d3d428f NC |
362 | reg_entry; |
363 | ||
364 | /* CR16 opcode table. */ | |
365 | extern const inst cr16_instruction[]; | |
366 | extern const unsigned int cr16_num_opcodes; | |
367 | #define NUMOPCODES cr16_num_opcodes | |
368 | ||
369 | /* CR16 operands table. */ | |
370 | extern const operand_entry cr16_optab[]; | |
796d5313 | 371 | extern const unsigned int cr16_num_optab; |
3d3d428f NC |
372 | |
373 | /* CR16 registers table. */ | |
374 | extern const reg_entry cr16_regtab[]; | |
375 | extern const unsigned int cr16_num_regs; | |
376 | #define NUMREGS cr16_num_regs | |
377 | ||
378 | /* CR16 register pair table. */ | |
379 | extern const reg_entry cr16_regptab[]; | |
380 | extern const unsigned int cr16_num_regps; | |
381 | #define NUMREGPS cr16_num_regps | |
382 | ||
383 | /* CR16 processor registers table. */ | |
384 | extern const reg_entry cr16_pregtab[]; | |
385 | extern const unsigned int cr16_num_pregs; | |
386 | #define NUMPREGS cr16_num_pregs | |
387 | ||
388 | /* CR16 processor registers - 32 bit table. */ | |
389 | extern const reg_entry cr16_pregptab[]; | |
390 | extern const unsigned int cr16_num_pregps; | |
391 | #define NUMPREGPS cr16_num_pregps | |
392 | ||
393 | /* CR16 trap/interrupt table. */ | |
394 | extern const trap_entry cr16_traps[]; | |
395 | extern const unsigned int cr16_num_traps; | |
396 | #define NUMTRAPS cr16_num_traps | |
397 | ||
398 | /* CR16 CC - codes bit table. */ | |
399 | extern const char * cr16_b_cond_tab[]; | |
400 | extern const unsigned int cr16_num_cc; | |
401 | #define NUMCC cr16_num_cc; | |
402 | ||
403 | ||
404 | /* Table of instructions with no operands. */ | |
405 | extern const char * cr16_no_op_insn[]; | |
406 | ||
407 | /* Current instruction we're assembling. */ | |
408 | extern const inst *instruction; | |
409 | ||
410 | /* A macro for representing the instruction "constant" opcode, that is, | |
411 | the FIXED part of the instruction. The "constant" opcode is represented | |
412 | as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) | |
413 | over that range. */ | |
414 | #define BIN(OPC,SHIFT) (OPC << SHIFT) | |
415 | ||
416 | /* Is the current instruction type is TYPE ? */ | |
417 | #define IS_INSN_TYPE(TYPE) \ | |
418 | (CR16_INS_TYPE (instruction->flags) == TYPE) | |
419 | ||
420 | /* Is the current instruction mnemonic is MNEMONIC ? */ | |
421 | #define IS_INSN_MNEMONIC(MNEMONIC) \ | |
422 | (strcmp (instruction->mnemonic, MNEMONIC) == 0) | |
423 | ||
424 | /* Does the current instruction has register list ? */ | |
425 | #define INST_HAS_REG_LIST \ | |
426 | (instruction->flags & REG_LIST) | |
427 | ||
428 | ||
429 | /* Utility macros for string comparison. */ | |
430 | #define streq(a, b) (strcmp (a, b) == 0) | |
431 | #define strneq(a, b, c) (strncmp (a, b, c) == 0) | |
432 | ||
433 | /* Long long type handling. */ | |
434 | /* Replace all appearances of 'long long int' with LONGLONG. */ | |
435 | typedef long long int LONGLONG; | |
436 | typedef unsigned long long ULONGLONG; | |
437 | ||
bab4becb NC |
438 | /* Data types for opcode handling. */ |
439 | typedef unsigned long dwordU; | |
440 | typedef unsigned short wordU; | |
441 | ||
442 | /* Globals to store opcode data and build the instruction. */ | |
443 | extern wordU cr16_words[3]; | |
444 | extern ULONGLONG cr16_allWords; | |
445 | extern ins cr16_currInsn; | |
446 | ||
447 | /* Prototypes for function in cr16-dis.c. */ | |
73335eae NC |
448 | extern void cr16_make_instruction (void); |
449 | extern int cr16_match_opcode (void); | |
bab4becb | 450 | |
3d3d428f | 451 | #endif /* _CR16_H_ */ |