[deliverable/binutils-gdb.git] / include / opcode / crx.h

/* crx.h -- Header file for CRX opcode and register tables.
   Copyright 2004 Free Software Foundation, Inc.
   Contributed by Tomer Levi, NSC, Israel.
   Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
   Updates, BFDizing, GNUifying and ELF support by Tomer Levi.

   This file is part of GAS, GDB and the GNU binutils.

   GAS, GDB, and GNU binutils is free software; you can redistribute it
   and/or modify it under the terms of the GNU General Public License as
   published by the Free Software Foundation; either version 2, or (at your
   option) any later version.

   GAS, GDB, and GNU binutils are distributed in the hope that they will be
   useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#ifndef _CRX_H_
#define _CRX_H_

/* CRX core/debug Registers :
   The enums are used as indices to CRX registers table (crx_regtab).
   Therefore, order MUST be preserved.  */

typedef enum
  {
    /* 32-bit general purpose registers.  */
    r0, r1, r2, r3, r4, r5, r6, r7, r8, r9,
    r10, r11, r12, r13, r14, r15, ra, sp,
    /* 32-bit user registers.  */
    u0, u1, u2, u3, u4, u5, u6, u7, u8, u9,
    u10, u11, u12, u13, u14, u15, ura, usp,
    /* hi and lo registers.  */
    hi, lo,
    /* hi and lo user registers.  */
    uhi, ulo,
    /* Processor Status Register.  */
    psr,
    /* Interrupt Base Register.  */
    intbase,
    /* Interrupt Stack Pointer Register.  */
    isp,
    /* Configuration Register.  */
    cfg,
    /* Coprocessor Configuration Register.  */
    cpcfg,
    /* Coprocessor Enable Register.  */
    cen,
    /* Not a register.  */
    nullregister,
    MAX_REG
  }
reg;

/* CRX Coprocessor registers and special registers :
   The enums are used as indices to CRX coprocessor registers table
   (crx_copregtab). Therefore, order MUST be preserved.  */

typedef enum
  {
    /* Coprocessor registers.  */
    c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8,
    c9, c10, c11, c12, c13, c14, c15,
    /* Coprocessor special registers.  */
    cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8,
    cs9, cs10, cs11, cs12, cs13, cs14, cs15,
    /* Not a Coprocessor register.  */
    nullcopregister,
    MAX_COPREG
  }
copreg;

/* CRX Register types. */

typedef enum
  {
    CRX_R_REGTYPE,    /*  r<N>	  */
    CRX_U_REGTYPE,    /*  u<N>	  */
    CRX_C_REGTYPE,    /*  c<N>	  */
    CRX_CS_REGTYPE,   /*  cs<N>	  */
    CRX_CFG_REGTYPE   /*  configuration register   */
  }
reg_type;

/* CRX argument types :
   The argument types correspond to instructions operands

   Argument types :
   r - register
   c - constant
   d - displacement
   ic - immediate
   icr - index register
   rbase - register base
   s - star ('*')
   copr - coprocessor register
   copsr - coprocessor special register.  */

typedef enum
  {
    arg_r, arg_c, arg_cr, arg_dc, arg_dcr, arg_sc,
    arg_ic, arg_icr, arg_rbase, arg_copr, arg_copsr,
    /* Not an argument.  */
    nullargs
  }
argtype;

/* CRX operand types :
   The operand types correspond to instructions operands.  */

typedef enum
  {
    dummy,
    /* 4-bit encoded constant.  */
    cst4,
    /* N-bit immediate.  */
    i16, i32,
    /* N-bit unsigned immediate.  */
    ui3, ui4, ui5, ui16,
    /* N-bit signed displacement.  */
    disps9, disps17, disps25, disps32,
    /* N-bit unsigned displacement.  */
    dispu5, 
    /* N-bit escaped displacement.  */
    dispe9,
    /* N-bit absolute address.  */
    abs16, abs32,
    /* Register relative.  */
    rbase, rbase_cst4,
    rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32,
    /* Register index.  */
    rindex_disps6, rindex_disps22,
    /* 4-bit genaral-purpose register specifier.  */
    regr, 
    /* 8-bit register address space.  */
    regr8,
    /* coprocessor register.  */
    copregr, 
    /* coprocessor special register.  */
    copsregr,
    /* Not an operand.  */
    nulloperand,
    /* Maximum supported operand.  */
    MAX_OPRD
  }
operand_type;

/* CRX instruction types.  */

#define NO_TYPE_INS       0
#define ARITH_INS         1
#define LD_STOR_INS       2
#define BRANCH_INS        3
#define ARITH_BYTE_INS    4
#define CMPBR_INS         5
#define SHIFT_INS         6
#define BRANCH_NEQ_INS    7
#define LD_STOR_INS_INC   8
#define STOR_IMM_INS	  9
#define CSTBIT_INS       10
#define SYS_INS		 11
#define JMP_INS		 12
#define MUL_INS		 13
#define DIV_INS		 14
#define COP_BRANCH_INS   15
#define COP_REG_INS      16
#define COPS_REG_INS     17
#define DCR_BRANCH_INS   18
#define MMC_INS          19
#define MMU_INS          20

/* Maximum value supported for instruction types.  */
#define CRX_INS_MAX	(1 << 5)
/* Mask to record an instruction type.  */
#define CRX_INS_MASK	(CRX_INS_MAX - 1)
/* Return instruction type, given instruction's attributes.  */
#define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK)

/* Indicates whether this instruction has a register list as parameter.  */
#define REG_LIST	CRX_INS_MAX
/* The operands in binary and assembly are placed in reverse order.
   load - (REVERSE_MATCH)/store - (! REVERSE_MATCH).  */
#define REVERSE_MATCH  (1 << 6)

/* Kind of displacement map used DISPU[BWD]4.  */
#define DISPUB4	       (1 << 7)
#define DISPUW4	       (1 << 8)
#define DISPUD4	       (1 << 9)
#define DISPU4MAP      (DISPUB4 | DISPUW4 | DISPUD4)

/* Printing formats, where the instruction prefix isn't consecutive.  */
#define FMT_1	       (1 << 10)   /* 0xF0F00000 */
#define FMT_2	       (1 << 11)   /* 0xFFF0FF00 */
#define FMT_3	       (1 << 12)   /* 0xFFF00F00 */
#define FMT_4	       (1 << 13)   /* 0xFFF0F000 */
#define FMT_5	       (1 << 14)   /* 0xFFF0FFF0 */
#define FMT_CRX	       (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)

/* Indicates whether this instruction can be relaxed.  */
#define RELAXABLE      (1 << 15)

/* Indicates that instruction uses user registers (and not 
   general-purpose registers) as operands.  */
#define USER_REG       (1 << 16)

/* Indicates that instruction can perfom a cst4 mapping.  */
#define CST4MAP	       (1 << 17)

/* Instruction shouldn't allow 'sp' usage.  */
#define NO_SP	       (1 << 18)

/* Instruction shouldn't allow to push a register which is used as a rptr.  */
#define NO_RPTR	       (1 << 19)

/* Maximum operands per instruction.  */
#define MAX_OPERANDS	  5
/* Maximum words per instruction.  */
#define MAX_WORDS	  3
/* Maximum register name length. */
#define MAX_REGNAME_LEN	  10
/* Maximum instruction length. */
#define MAX_INST_LEN	  256


/* Values defined for the flags field of a struct operand_entry.  */

/* Operand must be an unsigned number.  */
#define OPERAND_UNSIGNED  (1 << 0)
/* Operand must be a signed number.  */
#define OPERAND_SIGNED	  (1 << 1)
/* A cst4 operand.  */
#define OPERAND_CST4	  (1 << 2)
/* Operand must be an even number.  */
#define OPERAND_EVEN	  (1 << 3)
/* Operand is shifted right.  */
#define OPERAND_SHIFT	  (1 << 4)
/* Operand is shifted right and decremented.  */
#define OPERAND_SHIFT_DEC (1 << 5)
/* Operand has reserved escape sequences.  */
#define OPERAND_ESC	  (1 << 6)

/* Single operand description.  */

typedef struct
  {
    /* Operand type.  */
    operand_type op_type;
    /* Operand location within the opcode.  */
    unsigned int shift;
  }
operand_desc;

/* Instruction data structure used in instruction table.  */

typedef struct
  {
    /* Name.  */
    const char *mnemonic;
    /* Size (in words).  */
    unsigned int size;
    /* Constant prefix (matched by the disassembler).  */
    unsigned long match;
    /* Match size (in bits).  */
    int match_bits;
    /* Attributes.  */
    unsigned int flags;
    /* Operands (always last, so unreferenced operands are initialized).  */
    operand_desc operands[MAX_OPERANDS];
  }
inst;

/* Data structure for a single instruction's arguments (Operands).  */

typedef struct
  {
    /* Register or base register.  */
    reg r;
    /* Index register.  */
    reg i_r;
    /* Coprocessor register.  */
    copreg cr;
    /* Constant/immediate/absolute value.  */
    unsigned long int constant;
    /* Scaled index mode.  */
    unsigned int scale;
    /* Argument type.  */
    argtype type;
    /* Size of the argument (in bits) required to represent.  */
    int size;
    /* Indicates whether a constant is positive or negative.  */
    int signflag;
  }
argument;

/* Internal structure to hold the various entities
   corresponding to the current assembling instruction.  */

typedef struct
  {
    /* Number of arguments.  */
    int nargs;
    /* The argument data structure for storing args (operands).  */
    argument arg[MAX_OPERANDS];
/* The following fields are required only by CRX-assembler.  */
#ifdef TC_CRX
    /* Expression used for setting the fixups (if any).  */
    expressionS exp;
    bfd_reloc_code_real_type rtype;
#endif /* TC_CRX */
    /* Instruction size (in bytes).  */
    int size;
  }
ins;

/* Structure to hold information about predefined operands.  */

typedef struct
  {
    /* Size (in bits).  */
    unsigned int bit_size;
    /* Argument type.  */
    argtype arg_type;
    /* One bit syntax flags.  */
    int flags;
  }
operand_entry;

/* Structure to hold trap handler information.  */

typedef struct
  {
    /* Trap name.  */
    char *name;
    /* Index in dispatch table.  */
    unsigned int entry;
  }
trap_entry;

/* Structure to hold information about predefined registers.  */

typedef struct
  {
    /* Name (string representation).  */
    char *name;
    /* Value (enum representation).  */
    union
    {
      /* Register.  */
      reg reg_val;
      /* Coprocessor register.  */
      copreg copreg_val;
    } value;
    /* Register image.  */
    int image;
    /* Register type.  */
    reg_type type;
  }
reg_entry;

/* Structure to hold a cst4 operand mapping.  */

typedef struct
  {
    /* The binary value which is written to the object file.  */
    int binary;
    /* The value which is mapped.  */
    int value;
  }
cst4_entry;

/* CRX opcode table.  */
extern const inst crx_instruction[];
extern const int crx_num_opcodes;
#define NUMOPCODES crx_num_opcodes

/* CRX operands table.  */
extern const operand_entry crx_optab[];

/* CRX registers table.  */
extern const reg_entry crx_regtab[];
extern const int crx_num_regs;
#define NUMREGS crx_num_regs

/* CRX coprocessor registers table.  */
extern const reg_entry crx_copregtab[];
extern const int crx_num_copregs;
#define NUMCOPREGS crx_num_copregs

/* CRX trap/interrupt table.  */
extern const trap_entry crx_traps[];
extern const int crx_num_traps;
#define NUMTRAPS crx_num_traps

/* cst4 operand mapping.  */
extern const cst4_entry cst4_map[];
extern const int cst4_maps;

/* Current instruction we're assembling.  */
extern const inst *instruction;

/* A macro for representing the instruction "constant" opcode, that is,
   the FIXED part of the instruction. The "constant" opcode is represented
   as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
   over that range.  */
#define BIN(OPC,SHIFT)	(OPC << SHIFT)

/* Is the current instruction type is TYPE ?  */
#define IS_INSN_TYPE(TYPE)	      \
  (CRX_INS_TYPE(instruction->flags) == TYPE)

/* Is the current instruction mnemonic is MNEMONIC ?  */
#define IS_INSN_MNEMONIC(MNEMONIC)    \
  (strcmp(instruction->mnemonic,MNEMONIC) == 0)

/* Does the current instruction has register list ?  */
#define INST_HAS_REG_LIST	      \
  (instruction->flags & REG_LIST)

/* Long long type handling.  */
/* Replace all appearances of 'long long int' with LONGLONG.  */
typedef long long int LONGLONG;
typedef unsigned long long ULONGLONG;

#endif /* _CRX_H_ */
Commit	Line	Data
1fe1f39c NC	1	/* crx.h -- Header file for CRX opcode and register tables.
	2	Copyright 2004 Free Software Foundation, Inc.
	3	Contributed by Tomer Levi, NSC, Israel.
	4	Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
	5	Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
	6
	7	This file is part of GAS, GDB and the GNU binutils.
	8
	9	GAS, GDB, and GNU binutils is free software; you can redistribute it
	10	and/or modify it under the terms of the GNU General Public License as
	11	published by the Free Software Foundation; either version 2, or (at your
	12	option) any later version.
	13
	14	GAS, GDB, and GNU binutils are distributed in the hope that they will be
	15	useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License
	20	along with this program; if not, write to the Free Software
	21	Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	22
	23	#ifndef _CRX_H_
	24	#define _CRX_H_
	25
	26	/* CRX core/debug Registers :
	27	The enums are used as indices to CRX registers table (crx_regtab).
	28	Therefore, order MUST be preserved. */
	29
	30	typedef enum
	31	{
	32	/* 32-bit general purpose registers. */
	33	r0, r1, r2, r3, r4, r5, r6, r7, r8, r9,
	34	r10, r11, r12, r13, r14, r15, ra, sp,
	35	/* 32-bit user registers. */
	36	u0, u1, u2, u3, u4, u5, u6, u7, u8, u9,
	37	u10, u11, u12, u13, u14, u15, ura, usp,
	38	/* hi and lo registers. */
	39	hi, lo,
	40	/* hi and lo user registers. */
	41	uhi, ulo,
	42	/* Processor Status Register. */
	43	psr,
1fe1f39c NC	44	/* Interrupt Base Register. */
	45	intbase,
	46	/* Interrupt Stack Pointer Register. */
	47	isp,
5531e44c TL	48	/* Configuration Register. */
	49	cfg,
	50	/* Coprocessor Configuration Register. */
	51	cpcfg,
1fe1f39c NC	52	/* Coprocessor Enable Register. */
1fe1f39c NC	53	cen,
1fe1f39c NC	54	/* Not a register. */
	55	nullregister,
	56	MAX_REG
	57	}
	58	reg;
	59
	60	/* CRX Coprocessor registers and special registers :
	61	The enums are used as indices to CRX coprocessor registers table
	62	(crx_copregtab). Therefore, order MUST be preserved. */
	63
	64	typedef enum
	65	{
	66	/* Coprocessor registers. */
	67	c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8,
	68	c9, c10, c11, c12, c13, c14, c15,
	69	/* Coprocessor special registers. */
	70	cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8,
	71	cs9, cs10, cs11, cs12, cs13, cs14, cs15,
	72	/* Not a Coprocessor register. */
	73	nullcopregister,
	74	MAX_COPREG
	75	}
	76	copreg;
	77
	78	/* CRX Register types. */
	79
	80	typedef enum
	81	{
1fe1f39c NC	82	CRX_R_REGTYPE, /* r<N> */
	83	CRX_U_REGTYPE, /* u<N> */
	84	CRX_C_REGTYPE, /* c<N> */
	85	CRX_CS_REGTYPE, /* cs<N> */
5531e44c	86	CRX_CFG_REGTYPE /* configuration register */
1fe1f39c NC	87	}
	88	reg_type;
	89
	90	/* CRX argument types :
	91	The argument types correspond to instructions operands
	92
	93	Argument types :
	94	r - register
	95	c - constant
	96	d - displacement
	97	ic - immediate
	98	icr - index register
	99	rbase - register base
	100	s - star ('*')
	101	copr - coprocessor register
	102	copsr - coprocessor special register. */
	103
	104	typedef enum
	105	{
	106	arg_r, arg_c, arg_cr, arg_dc, arg_dcr, arg_sc,
	107	arg_ic, arg_icr, arg_rbase, arg_copr, arg_copsr,
	108	/* Not an argument. */
	109	nullargs
	110	}
	111	argtype;
	112
	113	/* CRX operand types :
5531e44c	114	The operand types correspond to instructions operands. */
1fe1f39c NC	115
	116	typedef enum
	117	{
5531e44c TL	118	dummy,
	119	/* 4-bit encoded constant. */
	120	cst4,
	121	/* N-bit immediate. */
645ea12c	122	i16, i32,
5531e44c TL	123	/* N-bit unsigned immediate. */
	124	ui3, ui4, ui5, ui16,
	125	/* N-bit signed displacement. */
	126	disps9, disps17, disps25, disps32,
	127	/* N-bit unsigned displacement. */
	128	dispu5,
	129	/* N-bit escaped displacement. */
	130	dispe9,
	131	/* N-bit absolute address. */
1fe1f39c	132	abs16, abs32,
5531e44c	133	/* Register relative. */
1fe1f39c	134	rbase, rbase_cst4,
5531e44c TL	135	rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32,
	136	/* Register index. */
	137	rindex_disps6, rindex_disps22,
	138	/* 4-bit genaral-purpose register specifier. */
	139	regr,
	140	/* 8-bit register address space. */
	141	regr8,
	142	/* coprocessor register. */
	143	copregr,
	144	/* coprocessor special register. */
	145	copsregr,
1fe1f39c NC	146	/* Not an operand. */
	147	nulloperand,
	148	/* Maximum supported operand. */
	149	MAX_OPRD
	150	}
	151	operand_type;
	152
	153	/* CRX instruction types. */
	154
5531e44c	155	#define NO_TYPE_INS 0
1fe1f39c NC	156	#define ARITH_INS 1
	157	#define LD_STOR_INS 2
	158	#define BRANCH_INS 3
	159	#define ARITH_BYTE_INS 4
	160	#define CMPBR_INS 5
	161	#define SHIFT_INS 6
	162	#define BRANCH_NEQ_INS 7
	163	#define LD_STOR_INS_INC 8
	164	#define STOR_IMM_INS 9
	165	#define CSTBIT_INS 10
	166	#define SYS_INS 11
	167	#define JMP_INS 12
	168	#define MUL_INS 13
	169	#define DIV_INS 14
	170	#define COP_BRANCH_INS 15
	171	#define COP_REG_INS 16
48c9f030 NC	172	#define COPS_REG_INS 17
	173	#define DCR_BRANCH_INS 18
	174	#define MMC_INS 19
	175	#define MMU_INS 20
1fe1f39c NC	176
	177	/* Maximum value supported for instruction types. */
	178	#define CRX_INS_MAX (1 << 5)
	179	/* Mask to record an instruction type. */
	180	#define CRX_INS_MASK (CRX_INS_MAX - 1)
	181	/* Return instruction type, given instruction's attributes. */
	182	#define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK)
	183
	184	/* Indicates whether this instruction has a register list as parameter. */
	185	#define REG_LIST CRX_INS_MAX
	186	/* The operands in binary and assembly are placed in reverse order.
	187	load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */
5531e44c	188	#define REVERSE_MATCH (1 << 6)
1fe1f39c NC	189
1fe1f39c NC	190	/* Kind of displacement map used DISPU[BWD]4. */
5531e44c TL	191	#define DISPUB4 (1 << 7)
	192	#define DISPUW4 (1 << 8)
	193	#define DISPUD4 (1 << 9)
	194	#define DISPU4MAP (DISPUB4 \| DISPUW4 \| DISPUD4)
1fe1f39c NC	195
1fe1f39c NC	196	/* Printing formats, where the instruction prefix isn't consecutive. */
5531e44c TL	197	#define FMT_1 (1 << 10) /* 0xF0F00000 */
	198	#define FMT_2 (1 << 11) /* 0xFFF0FF00 */
	199	#define FMT_3 (1 << 12) /* 0xFFF00F00 */
	200	#define FMT_4 (1 << 13) /* 0xFFF0F000 */
	201	#define FMT_5 (1 << 14) /* 0xFFF0FFF0 */
1fe1f39c NC	202	#define FMT_CRX (FMT_1 \| FMT_2 \| FMT_3 \| FMT_4 \| FMT_5)
1fe1f39c NC	203
5531e44c TL	204	/* Indicates whether this instruction can be relaxed. */
	205	#define RELAXABLE (1 << 15)
	206
	207	/* Indicates that instruction uses user registers (and not
	208	general-purpose registers) as operands. */
	209	#define USER_REG (1 << 16)
	210
	211	/* Indicates that instruction can perfom a cst4 mapping. */
	212	#define CST4MAP (1 << 17)
	213
	214	/* Instruction shouldn't allow 'sp' usage. */
	215	#define NO_SP (1 << 18)
	216
	217	/* Instruction shouldn't allow to push a register which is used as a rptr. */
	218	#define NO_RPTR (1 << 19)
1fe1f39c NC	219
	220	/* Maximum operands per instruction. */
	221	#define MAX_OPERANDS 5
	222	/* Maximum words per instruction. */
	223	#define MAX_WORDS 3
	224	/* Maximum register name length. */
	225	#define MAX_REGNAME_LEN 10
	226	/* Maximum instruction length. */
	227	#define MAX_INST_LEN 256
	228
5531e44c TL	229
	230	/* Values defined for the flags field of a struct operand_entry. */
	231
	232	/* Operand must be an unsigned number. */
	233	#define OPERAND_UNSIGNED (1 << 0)
	234	/* Operand must be a signed number. */
	235	#define OPERAND_SIGNED (1 << 1)
	236	/* A cst4 operand. */
	237	#define OPERAND_CST4 (1 << 2)
	238	/* Operand must be an even number. */
	239	#define OPERAND_EVEN (1 << 3)
	240	/* Operand is shifted right. */
	241	#define OPERAND_SHIFT (1 << 4)
	242	/* Operand is shifted right and decremented. */
	243	#define OPERAND_SHIFT_DEC (1 << 5)
	244	/* Operand has reserved escape sequences. */
	245	#define OPERAND_ESC (1 << 6)
	246
1fe1f39c NC	247	/* Single operand description. */
	248
	249	typedef struct
	250	{
	251	/* Operand type. */
	252	operand_type op_type;
	253	/* Operand location within the opcode. */
	254	unsigned int shift;
	255	}
	256	operand_desc;
	257
	258	/* Instruction data structure used in instruction table. */
	259
	260	typedef struct
	261	{
	262	/* Name. */
	263	const char *mnemonic;
	264	/* Size (in words). */
	265	unsigned int size;
	266	/* Constant prefix (matched by the disassembler). */
	267	unsigned long match;
	268	/* Match size (in bits). */
	269	int match_bits;
	270	/* Attributes. */
	271	unsigned int flags;
	272	/* Operands (always last, so unreferenced operands are initialized). */
	273	operand_desc operands[MAX_OPERANDS];
	274	}
	275	inst;
	276
	277	/* Data structure for a single instruction's arguments (Operands). */
	278
	279	typedef struct
	280	{
	281	/* Register or base register. */
	282	reg r;
	283	/* Index register. */
	284	reg i_r;
	285	/* Coprocessor register. */
	286	copreg cr;
	287	/* Constant/immediate/absolute value. */
	288	unsigned long int constant;
	289	/* Scaled index mode. */
	290	unsigned int scale;
	291	/* Argument type. */
	292	argtype type;
	293	/* Size of the argument (in bits) required to represent. */
	294	int size;
	295	/* Indicates whether a constant is positive or negative. */
	296	int signflag;
	297	}
	298	argument;
	299
	300	/* Internal structure to hold the various entities
	301	corresponding to the current assembling instruction. */
	302
	303	typedef struct
	304	{
	305	/* Number of arguments. */
	306	int nargs;
	307	/* The argument data structure for storing args (operands). */
	308	argument arg[MAX_OPERANDS];
	309	/* The following fields are required only by CRX-assembler. */
	310	#ifdef TC_CRX
311	/* Expression used for setting the fixups (if any). */
312	expressionS exp;
313	bfd_reloc_code_real_type rtype;
314	#endif /* TC_CRX */
315	/* Instruction size (in bytes). */
316	int size;
317	}
318	ins;
319
320	/* Structure to hold information about predefined operands. */
321
322	typedef struct
323	{
324	/* Size (in bits). */
325	unsigned int bit_size;
326	/* Argument type. */
327	argtype arg_type;
5531e44c TL	328	/* One bit syntax flags. */
5531e44c TL	329	int flags;
1fe1f39c NC	330	}
	331	operand_entry;
	332
	333	/* Structure to hold trap handler information. */
	334
	335	typedef struct
	336	{
	337	/* Trap name. */
	338	char *name;
	339	/* Index in dispatch table. */
	340	unsigned int entry;
	341	}
	342	trap_entry;
	343
	344	/* Structure to hold information about predefined registers. */
	345
	346	typedef struct
	347	{
	348	/* Name (string representation). */
	349	char *name;
	350	/* Value (enum representation). */
	351	union
	352	{
	353	/* Register. */
	354	reg reg_val;
	355	/* Coprocessor register. */
	356	copreg copreg_val;
	357	} value;
	358	/* Register image. */
	359	int image;
	360	/* Register type. */
	361	reg_type type;
	362	}
	363	reg_entry;
	364
	365	/* Structure to hold a cst4 operand mapping. */
	366
	367	typedef struct
	368	{
	369	/* The binary value which is written to the object file. */
	370	int binary;
	371	/* The value which is mapped. */
	372	int value;
	373	}
	374	cst4_entry;
	375
	376	/* CRX opcode table. */
	377	extern const inst crx_instruction[];
	378	extern const int crx_num_opcodes;
	379	#define NUMOPCODES crx_num_opcodes
	380
	381	/* CRX operands table. */
	382	extern const operand_entry crx_optab[];
	383
	384	/* CRX registers table. */
	385	extern const reg_entry crx_regtab[];
	386	extern const int crx_num_regs;
	387	#define NUMREGS crx_num_regs
	388
	389	/* CRX coprocessor registers table. */
	390	extern const reg_entry crx_copregtab[];
	391	extern const int crx_num_copregs;
	392	#define NUMCOPREGS crx_num_copregs
	393
394	/* CRX trap/interrupt table. */
395	extern const trap_entry crx_traps[];
396	extern const int crx_num_traps;
397	#define NUMTRAPS crx_num_traps
398
399	/* cst4 operand mapping. */
400	extern const cst4_entry cst4_map[];
401	extern const int cst4_maps;
402
403	/* Current instruction we're assembling. */
404	extern const inst *instruction;
405
406	/* A macro for representing the instruction "constant" opcode, that is,
407	the FIXED part of the instruction. The "constant" opcode is represented
408	as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
409	over that range. */
410	#define BIN(OPC,SHIFT) (OPC << SHIFT)
411
412	/* Is the current instruction type is TYPE ? */
413	#define IS_INSN_TYPE(TYPE) \
414	(CRX_INS_TYPE(instruction->flags) == TYPE)
415
416	/* Is the current instruction mnemonic is MNEMONIC ? */
417	#define IS_INSN_MNEMONIC(MNEMONIC) \
418	(strcmp(instruction->mnemonic,MNEMONIC) == 0)
419
420	/* Does the current instruction has register list ? */
421	#define INST_HAS_REG_LIST \
422	(instruction->flags & REG_LIST)
423
424	/* Long long type handling. */
425	/* Replace all appearances of 'long long int' with LONGLONG. */
426	typedef long long int LONGLONG;
427	typedef unsigned long long ULONGLONG;
1fe1f39c NC	428
1fe1f39c NC	429	#endif /* _CRX_H_ */