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252b5132 | 1 | /* d10v.h -- Header file for D10V opcode table |
2571583a | 2 | Copyright (C) 1996-2017 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Martin Hunt (hunt@cygnus.com), Cygnus Support |
4 | ||
e4e42b45 | 5 | This file is part of GDB, GAS, and the GNU binutils. |
252b5132 | 6 | |
e4e42b45 NC |
7 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
8 | them and/or modify them under the terms of the GNU General Public | |
9 | License as published by the Free Software Foundation; either version 3, | |
10 | or (at your option) any later version. | |
252b5132 | 11 | |
e4e42b45 NC |
12 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
15 | the GNU General Public License for more details. | |
252b5132 | 16 | |
e4e42b45 NC |
17 | You should have received a copy of the GNU General Public License |
18 | along with this file; see the file COPYING3. If not, write to the Free | |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
20 | MA 02110-1301, USA. */ | |
252b5132 RH |
21 | |
22 | #ifndef D10V_H | |
23 | #define D10V_H | |
24 | ||
1fe0971e TS |
25 | #ifdef __cplusplus |
26 | extern "C" { | |
27 | #endif | |
28 | ||
252b5132 RH |
29 | /* Format Specifier */ |
30 | #define FM00 0 | |
31 | #define FM01 0x40000000 | |
32 | #define FM10 0x80000000 | |
33 | #define FM11 0xC0000000 | |
34 | ||
35 | #define NOP 0x5e00 | |
36 | #define OPCODE_DIVS 0x14002800 | |
37 | ||
38 | /* The opcode table is an array of struct d10v_opcode. */ | |
39 | ||
40 | struct d10v_opcode | |
41 | { | |
42 | /* The opcode name. */ | |
43 | const char *name; | |
44 | ||
45 | /* the opcode format */ | |
46 | int format; | |
47 | ||
48 | /* These numbers were picked so we can do if( i & SHORT_OPCODE) */ | |
49 | #define SHORT_OPCODE 1 | |
50 | #define LONG_OPCODE 8 | |
51 | #define SHORT_2 1 /* short with 2 operands */ | |
52 | #define SHORT_B 3 /* short with 8-bit branch */ | |
53 | #define LONG_B 8 /* long with 16-bit branch */ | |
54 | #define LONG_L 10 /* long with 3 operands */ | |
55 | #define LONG_R 12 /* reserved */ | |
56 | ||
57 | /* just a placeholder for variable-length instructions */ | |
58 | /* for example, "bra" will be a fake for "bra.s" and bra.l" */ | |
59 | /* which will immediately follow in the opcode table. */ | |
60 | #define OPCODE_FAKE 32 | |
61 | ||
62 | /* the number of cycles */ | |
63 | int cycles; | |
64 | ||
65 | /* the execution unit(s) used */ | |
66 | int unit; | |
67 | #define EITHER 0 | |
68 | #define IU 1 | |
69 | #define MU 2 | |
70 | #define BOTH 3 | |
71 | ||
72 | /* execution type; parallel or sequential */ | |
73 | /* this field is used to decide if two instructions */ | |
74 | /* can be executed in parallel */ | |
75 | int exec_type; | |
76 | #define PARONLY 1 /* parallel only */ | |
77 | #define SEQ 2 /* must be sequential */ | |
78 | #define PAR 4 /* may be parallel */ | |
79 | #define BRANCH_LINK 8 /* subroutine call. must be aligned */ | |
80 | #define RMEM 16 /* reads memory */ | |
81 | #define WMEM 32 /* writes memory */ | |
82 | #define RF0 64 /* reads f0 */ | |
83 | #define WF0 128 /* modifies f0 */ | |
84 | #define WCAR 256 /* write Carry */ | |
85 | #define BRANCH 512 /* branch, no link */ | |
f0662e27 | 86 | #define ALONE 1024 /* short but pack with a NOP if on asm line alone */ |
252b5132 RH |
87 | |
88 | /* the opcode */ | |
89 | long opcode; | |
90 | ||
91 | /* mask. if( (i & mask) == opcode ) then match */ | |
92 | long mask; | |
93 | ||
94 | /* An array of operand codes. Each code is an index into the | |
95 | operand table. They appear in the order which the operands must | |
96 | appear in assembly code, and are terminated by a zero. */ | |
97 | unsigned char operands[6]; | |
98 | }; | |
99 | ||
100 | /* The table itself is sorted by major opcode number, and is otherwise | |
101 | in the order in which the disassembler should consider | |
102 | instructions. */ | |
103 | extern const struct d10v_opcode d10v_opcodes[]; | |
104 | extern const int d10v_num_opcodes; | |
105 | ||
106 | /* The operands table is an array of struct d10v_operand. */ | |
107 | struct d10v_operand | |
108 | { | |
109 | /* The number of bits in the operand. */ | |
110 | int bits; | |
111 | ||
112 | /* How far the operand is left shifted in the instruction. */ | |
113 | int shift; | |
114 | ||
115 | /* One bit syntax flags. */ | |
116 | int flags; | |
117 | }; | |
118 | ||
119 | /* Elements in the table are retrieved by indexing with values from | |
120 | the operands field of the d10v_opcodes table. */ | |
121 | ||
122 | extern const struct d10v_operand d10v_operands[]; | |
123 | ||
124 | /* Values defined for the flags field of a struct d10v_operand. */ | |
125 | ||
126 | /* the operand must be an even number */ | |
127 | #define OPERAND_EVEN (1) | |
128 | ||
129 | /* the operand must be an odd number */ | |
130 | #define OPERAND_ODD (2) | |
131 | ||
132 | /* this is the destination register; it will be modified */ | |
133 | /* this is used by the optimizer */ | |
134 | #define OPERAND_DEST (4) | |
135 | ||
136 | /* number or symbol */ | |
137 | #define OPERAND_NUM (8) | |
138 | ||
139 | /* address or label */ | |
140 | #define OPERAND_ADDR (0x10) | |
141 | ||
142 | /* register */ | |
143 | #define OPERAND_REG (0x20) | |
144 | ||
145 | /* postincrement + */ | |
146 | #define OPERAND_PLUS (0x40) | |
147 | ||
148 | /* postdecrement - */ | |
149 | #define OPERAND_MINUS (0x80) | |
150 | ||
151 | /* @ */ | |
152 | #define OPERAND_ATSIGN (0x100) | |
153 | ||
154 | /* @( */ | |
155 | #define OPERAND_ATPAR (0x200) | |
156 | ||
157 | /* accumulator 0 */ | |
158 | #define OPERAND_ACC0 (0x400) | |
159 | ||
160 | /* accumulator 1 */ | |
161 | #define OPERAND_ACC1 (0x800) | |
162 | ||
163 | /* f0 / f1 flag register */ | |
164 | #define OPERAND_FFLAG (0x1000) | |
165 | ||
166 | /* c flag register */ | |
167 | #define OPERAND_CFLAG (0x2000) | |
168 | ||
169 | /* control register */ | |
170 | #define OPERAND_CONTROL (0x4000) | |
171 | ||
172 | /* predecrement mode '@-sp' */ | |
173 | #define OPERAND_ATMINUS (0x8000) | |
174 | ||
175 | /* signed number */ | |
176 | #define OPERAND_SIGNED (0x10000) | |
177 | ||
178 | /* special accumulator shifts need a 4-bit number */ | |
179 | /* 1 <= x <= 16 */ | |
180 | #define OPERAND_SHIFT (0x20000) | |
181 | ||
182 | /* general purpose register */ | |
183 | #define OPERAND_GPR (0x40000) | |
184 | ||
c43185de DN |
185 | /* special imm3 values with range restricted to -2 <= imm3 <= 3 */ |
186 | /* needed for rac/rachi */ | |
187 | #define RESTRICTED_NUM3 (0x80000) | |
188 | ||
9b21d49b AO |
189 | /* Pre-decrement is only supported for SP. */ |
190 | #define OPERAND_SP (0x100000) | |
191 | ||
124ddbb2 AO |
192 | /* Post-decrement is not supported for SP. Like OPERAND_EVEN, and |
193 | unlike OPERAND_SP, this flag doesn't prevent the instruction from | |
194 | matching, it only fails validation later on. */ | |
195 | #define OPERAND_NOSP (0x200000) | |
196 | ||
252b5132 RH |
197 | /* Structure to hold information about predefined registers. */ |
198 | struct pd_reg | |
199 | { | |
200 | char *name; /* name to recognize */ | |
201 | char *pname; /* name to print for this register */ | |
202 | int value; | |
203 | }; | |
204 | ||
205 | extern const struct pd_reg d10v_predefined_registers[]; | |
8cf3f354 | 206 | int d10v_reg_name_cnt (void); |
252b5132 RH |
207 | |
208 | /* an expressionS only has one register type, so we fake it */ | |
209 | /* by setting high bits to indicate type */ | |
210 | #define REGISTER_MASK 0xFF | |
211 | ||
1fe0971e TS |
212 | #ifdef __cplusplus |
213 | } | |
214 | #endif | |
215 | ||
252b5132 | 216 | #endif /* D10V_H */ |