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252b5132 | 1 | /* d10v.h -- Header file for D10V opcode table |
bf9043c5 | 2 | Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Martin Hunt (hunt@cygnus.com), Cygnus Support |
4 | ||
5 | This file is part of GDB, GAS, and the GNU binutils. | |
6 | ||
7 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
8 | them and/or modify them under the terms of the GNU General Public | |
9 | License as published by the Free Software Foundation; either version | |
10 | 1, or (at your option) any later version. | |
11 | ||
12 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
15 | the GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this file; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
21 | #ifndef D10V_H | |
22 | #define D10V_H | |
23 | ||
24 | /* Format Specifier */ | |
25 | #define FM00 0 | |
26 | #define FM01 0x40000000 | |
27 | #define FM10 0x80000000 | |
28 | #define FM11 0xC0000000 | |
29 | ||
30 | #define NOP 0x5e00 | |
31 | #define OPCODE_DIVS 0x14002800 | |
32 | ||
33 | /* The opcode table is an array of struct d10v_opcode. */ | |
34 | ||
35 | struct d10v_opcode | |
36 | { | |
37 | /* The opcode name. */ | |
38 | const char *name; | |
39 | ||
40 | /* the opcode format */ | |
41 | int format; | |
42 | ||
43 | /* These numbers were picked so we can do if( i & SHORT_OPCODE) */ | |
44 | #define SHORT_OPCODE 1 | |
45 | #define LONG_OPCODE 8 | |
46 | #define SHORT_2 1 /* short with 2 operands */ | |
47 | #define SHORT_B 3 /* short with 8-bit branch */ | |
48 | #define LONG_B 8 /* long with 16-bit branch */ | |
49 | #define LONG_L 10 /* long with 3 operands */ | |
50 | #define LONG_R 12 /* reserved */ | |
51 | ||
52 | /* just a placeholder for variable-length instructions */ | |
53 | /* for example, "bra" will be a fake for "bra.s" and bra.l" */ | |
54 | /* which will immediately follow in the opcode table. */ | |
55 | #define OPCODE_FAKE 32 | |
56 | ||
57 | /* the number of cycles */ | |
58 | int cycles; | |
59 | ||
60 | /* the execution unit(s) used */ | |
61 | int unit; | |
62 | #define EITHER 0 | |
63 | #define IU 1 | |
64 | #define MU 2 | |
65 | #define BOTH 3 | |
66 | ||
67 | /* execution type; parallel or sequential */ | |
68 | /* this field is used to decide if two instructions */ | |
69 | /* can be executed in parallel */ | |
70 | int exec_type; | |
71 | #define PARONLY 1 /* parallel only */ | |
72 | #define SEQ 2 /* must be sequential */ | |
73 | #define PAR 4 /* may be parallel */ | |
74 | #define BRANCH_LINK 8 /* subroutine call. must be aligned */ | |
75 | #define RMEM 16 /* reads memory */ | |
76 | #define WMEM 32 /* writes memory */ | |
77 | #define RF0 64 /* reads f0 */ | |
78 | #define WF0 128 /* modifies f0 */ | |
79 | #define WCAR 256 /* write Carry */ | |
80 | #define BRANCH 512 /* branch, no link */ | |
f0662e27 | 81 | #define ALONE 1024 /* short but pack with a NOP if on asm line alone */ |
252b5132 RH |
82 | |
83 | /* the opcode */ | |
84 | long opcode; | |
85 | ||
86 | /* mask. if( (i & mask) == opcode ) then match */ | |
87 | long mask; | |
88 | ||
89 | /* An array of operand codes. Each code is an index into the | |
90 | operand table. They appear in the order which the operands must | |
91 | appear in assembly code, and are terminated by a zero. */ | |
92 | unsigned char operands[6]; | |
93 | }; | |
94 | ||
95 | /* The table itself is sorted by major opcode number, and is otherwise | |
96 | in the order in which the disassembler should consider | |
97 | instructions. */ | |
98 | extern const struct d10v_opcode d10v_opcodes[]; | |
99 | extern const int d10v_num_opcodes; | |
100 | ||
101 | /* The operands table is an array of struct d10v_operand. */ | |
102 | struct d10v_operand | |
103 | { | |
104 | /* The number of bits in the operand. */ | |
105 | int bits; | |
106 | ||
107 | /* How far the operand is left shifted in the instruction. */ | |
108 | int shift; | |
109 | ||
110 | /* One bit syntax flags. */ | |
111 | int flags; | |
112 | }; | |
113 | ||
114 | /* Elements in the table are retrieved by indexing with values from | |
115 | the operands field of the d10v_opcodes table. */ | |
116 | ||
117 | extern const struct d10v_operand d10v_operands[]; | |
118 | ||
119 | /* Values defined for the flags field of a struct d10v_operand. */ | |
120 | ||
121 | /* the operand must be an even number */ | |
122 | #define OPERAND_EVEN (1) | |
123 | ||
124 | /* the operand must be an odd number */ | |
125 | #define OPERAND_ODD (2) | |
126 | ||
127 | /* this is the destination register; it will be modified */ | |
128 | /* this is used by the optimizer */ | |
129 | #define OPERAND_DEST (4) | |
130 | ||
131 | /* number or symbol */ | |
132 | #define OPERAND_NUM (8) | |
133 | ||
134 | /* address or label */ | |
135 | #define OPERAND_ADDR (0x10) | |
136 | ||
137 | /* register */ | |
138 | #define OPERAND_REG (0x20) | |
139 | ||
140 | /* postincrement + */ | |
141 | #define OPERAND_PLUS (0x40) | |
142 | ||
143 | /* postdecrement - */ | |
144 | #define OPERAND_MINUS (0x80) | |
145 | ||
146 | /* @ */ | |
147 | #define OPERAND_ATSIGN (0x100) | |
148 | ||
149 | /* @( */ | |
150 | #define OPERAND_ATPAR (0x200) | |
151 | ||
152 | /* accumulator 0 */ | |
153 | #define OPERAND_ACC0 (0x400) | |
154 | ||
155 | /* accumulator 1 */ | |
156 | #define OPERAND_ACC1 (0x800) | |
157 | ||
158 | /* f0 / f1 flag register */ | |
159 | #define OPERAND_FFLAG (0x1000) | |
160 | ||
161 | /* c flag register */ | |
162 | #define OPERAND_CFLAG (0x2000) | |
163 | ||
164 | /* control register */ | |
165 | #define OPERAND_CONTROL (0x4000) | |
166 | ||
167 | /* predecrement mode '@-sp' */ | |
168 | #define OPERAND_ATMINUS (0x8000) | |
169 | ||
170 | /* signed number */ | |
171 | #define OPERAND_SIGNED (0x10000) | |
172 | ||
173 | /* special accumulator shifts need a 4-bit number */ | |
174 | /* 1 <= x <= 16 */ | |
175 | #define OPERAND_SHIFT (0x20000) | |
176 | ||
177 | /* general purpose register */ | |
178 | #define OPERAND_GPR (0x40000) | |
179 | ||
c43185de DN |
180 | /* special imm3 values with range restricted to -2 <= imm3 <= 3 */ |
181 | /* needed for rac/rachi */ | |
182 | #define RESTRICTED_NUM3 (0x80000) | |
183 | ||
9b21d49b AO |
184 | /* Pre-decrement is only supported for SP. */ |
185 | #define OPERAND_SP (0x100000) | |
186 | ||
124ddbb2 AO |
187 | /* Post-decrement is not supported for SP. Like OPERAND_EVEN, and |
188 | unlike OPERAND_SP, this flag doesn't prevent the instruction from | |
189 | matching, it only fails validation later on. */ | |
190 | #define OPERAND_NOSP (0x200000) | |
191 | ||
252b5132 RH |
192 | /* Structure to hold information about predefined registers. */ |
193 | struct pd_reg | |
194 | { | |
195 | char *name; /* name to recognize */ | |
196 | char *pname; /* name to print for this register */ | |
197 | int value; | |
198 | }; | |
199 | ||
200 | extern const struct pd_reg d10v_predefined_registers[]; | |
d83c6548 | 201 | int d10v_reg_name_cnt PARAMS ((void)); |
252b5132 RH |
202 | |
203 | /* an expressionS only has one register type, so we fake it */ | |
204 | /* by setting high bits to indicate type */ | |
205 | #define REGISTER_MASK 0xFF | |
206 | ||
207 | #endif /* D10V_H */ |