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252b5132 | 1 | /* d30v.h -- Header file for D30V opcode table |
e4e42b45 NC |
2 | Copyright 1997, 1998, 1999, 2000, 2001, 2003, 2010 |
3 | Free Software Foundation, Inc. | |
252b5132 RH |
4 | Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions |
5 | ||
e4e42b45 | 6 | This file is part of GDB, GAS, and the GNU binutils. |
252b5132 | 7 | |
e4e42b45 NC |
8 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
9 | them and/or modify them under the terms of the GNU General Public | |
10 | License as published by the Free Software Foundation; either version 3, | |
11 | or (at your option) any later version. | |
252b5132 | 12 | |
e4e42b45 NC |
13 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
16 | the GNU General Public License for more details. | |
252b5132 | 17 | |
e4e42b45 NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with this file; see the file COPYING3. If not, write to the Free | |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
21 | MA 02110-1301, USA. */ | |
252b5132 RH |
22 | |
23 | #ifndef D30V_H | |
24 | #define D30V_H | |
25 | ||
26 | #define NOP 0x00F00000 | |
27 | ||
28 | /* Structure to hold information about predefined registers. */ | |
29 | struct pd_reg | |
30 | { | |
31 | char *name; /* name to recognize */ | |
32 | char *pname; /* name to print for this register */ | |
33 | int value; | |
34 | }; | |
35 | ||
36 | extern const struct pd_reg pre_defined_registers[]; | |
8cf3f354 | 37 | int reg_name_cnt (void); |
252b5132 RH |
38 | |
39 | /* the number of control registers */ | |
40 | #define MAX_CONTROL_REG 64 | |
41 | ||
42 | /* define the format specifiers */ | |
43 | #define FM00 0 | |
44 | #define FM01 0x80000000 | |
45 | #define FM10 0x8000000000000000LL | |
46 | #define FM11 0x8000000080000000LL | |
47 | ||
48 | /* define the opcode classes */ | |
49 | #define BRA 0 | |
50 | #define LOGIC 1 | |
51 | #define IMEM 2 | |
52 | #define IALU1 4 | |
53 | #define IALU2 5 | |
54 | ||
55 | /* define the execution condition codes */ | |
56 | #define ECC_AL 0 /* ALways (default) */ | |
57 | #define ECC_TX 1 /* F0=True, F1=Don't care */ | |
58 | #define ECC_FX 2 /* F0=False, F1=Don't care */ | |
59 | #define ECC_XT 3 /* F0=Don't care, F1=True */ | |
60 | #define ECC_XF 4 /* F0=Don't care, F1=False */ | |
61 | #define ECC_TT 5 /* F0=True, F1=True */ | |
62 | #define ECC_TF 6 /* F0=True, F1=False */ | |
63 | #define ECC_RESERVED 7 /* reserved */ | |
64 | #define ECC_MAX ECC_RESERVED | |
65 | ||
66 | extern const char *d30v_ecc_names[]; | |
67 | ||
68 | /* condition code table for CMP and CMPU */ | |
69 | extern const char *d30v_cc_names[]; | |
70 | ||
71 | /* The opcode table is an array of struct d30v_opcode. */ | |
72 | struct d30v_opcode | |
73 | { | |
74 | /* The opcode name. */ | |
75 | const char *name; | |
76 | ||
77 | /* the opcode */ | |
78 | int op1; /* first part, "IALU1" for example */ | |
79 | int op2; /* the rest of the opcode */ | |
80 | ||
81 | /* opcode format(s). These numbers correspond to entries */ | |
82 | /* in the d30v_format_table */ | |
83 | unsigned char format[4]; | |
84 | ||
85 | #define SHORT_M 1 | |
86 | #define SHORT_M2 5 /* for ld2w and st2w */ | |
87 | #define SHORT_A 9 | |
88 | #define SHORT_B1 11 | |
89 | #define SHORT_B2 12 | |
866afedc NC |
90 | #define SHORT_B2r 13 |
91 | #define SHORT_B3 14 | |
92 | #define SHORT_B3r 16 | |
93 | #define SHORT_B3b 18 | |
94 | #define SHORT_B3br 20 | |
95 | #define SHORT_D1r 22 | |
96 | #define SHORT_D2 24 | |
97 | #define SHORT_D2r 26 | |
98 | #define SHORT_D2Br 28 | |
99 | #define SHORT_U 30 /* unary SHORT_A. ABS for example */ | |
100 | #define SHORT_F 31 /* SHORT_A with flag registers */ | |
101 | #define SHORT_AF 33 /* SHORT_A with only the first register a flag register */ | |
102 | #define SHORT_T 35 /* for trap instruction */ | |
103 | #define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */ | |
104 | #define SHORT_CMP 38 /* special form for CMPcc */ | |
105 | #define SHORT_CMPU 40 /* special form for CMPUcc */ | |
ba23e138 | 106 | #define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */ |
866afedc NC |
107 | #define SHORT_AA 44 /* SHORT_A with the first register an accumulator */ |
108 | #define SHORT_RA 46 /* SHORT_A with the second register an accumulator */ | |
109 | #define SHORT_MODINC 48 | |
110 | #define SHORT_MODDEC 49 | |
111 | #define SHORT_C1 50 | |
112 | #define SHORT_C2 51 | |
113 | #define SHORT_UF 52 | |
114 | #define SHORT_A2 53 | |
115 | #define SHORT_NONE 55 /* no operands */ | |
ba23e138 NC |
116 | #define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */ |
117 | #define LONG 57 | |
118 | #define LONG_U 58 /* unary LONG */ | |
119 | #define LONG_Ur 59 /* LONG pc-relative */ | |
120 | #define LONG_CMP 60 /* special form for CMPcc and CMPUcc */ | |
121 | #define LONG_M 61 /* Memory long for ldb, stb */ | |
122 | #define LONG_M2 62 /* Memory long for ld2w, st2w */ | |
123 | #define LONG_2 63 /* LONG with 2 operands; jmptnz */ | |
124 | #define LONG_2r 64 /* LONG with 2 operands; bratnz */ | |
125 | #define LONG_2b 65 /* LONG_2 with modifier of 3 */ | |
126 | #define LONG_2br 66 /* LONG_2r with modifier of 3 */ | |
127 | #define LONG_D 67 /* for DJMPI */ | |
128 | #define LONG_Dr 68 /* for DBRAI */ | |
129 | #define LONG_Dbr 69 /* for repeati */ | |
252b5132 RH |
130 | |
131 | /* the execution unit(s) used */ | |
132 | int unit; | |
133 | #define EITHER 0 | |
134 | #define IU 1 | |
135 | #define MU 2 | |
136 | #define EITHER_BUT_PREFER_MU 3 | |
137 | ||
138 | /* this field is used to decide if two instructions */ | |
139 | /* can be executed in parallel */ | |
140 | long flags_used; | |
141 | long flags_set; | |
142 | #define FLAG_0 (1L<<0) | |
143 | #define FLAG_1 (1L<<1) | |
144 | #define FLAG_2 (1L<<2) | |
145 | #define FLAG_3 (1L<<3) | |
146 | #define FLAG_4 (1L<<4) /* S (saturation) */ | |
147 | #define FLAG_5 (1L<<5) /* V (overflow) */ | |
148 | #define FLAG_6 (1L<<6) /* VA (accumulated overflow) */ | |
149 | #define FLAG_7 (1L<<7) /* C (carry/borrow) */ | |
150 | #define FLAG_SM (1L<<8) /* SM (stack mode) */ | |
151 | #define FLAG_RP (1L<<9) /* RP (repeat enable) */ | |
152 | #define FLAG_CONTROL (1L<<10) /* control registers */ | |
153 | #define FLAG_A0 (1L<<11) /* A0 */ | |
154 | #define FLAG_A1 (1L<<12) /* A1 */ | |
155 | #define FLAG_JMP (1L<<13) /* instruction is a branch */ | |
156 | #define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */ | |
157 | #define FLAG_MEM (1L<<15) /* reads/writes memory */ | |
20609ff7 CC |
158 | #define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation |
159 | New meaning: operation cannot be | |
160 | combined in parallel with ADD/SUBppp. */ | |
252b5132 RH |
161 | #define FLAG_MUL16 (1L<<17) /* 16 bit multiply */ |
162 | #define FLAG_MUL32 (1L<<18) /* 32 bit multiply */ | |
163 | #define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */ | |
164 | #define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */ | |
165 | #define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */ | |
166 | #define FLAG_CVVA (FLAG_5|FLAG_6|FLAG_7) | |
167 | #define FLAG_C FLAG_7 | |
168 | #define FLAG_ALL (FLAG_0 | \ | |
169 | FLAG_1 | \ | |
170 | FLAG_2 | \ | |
171 | FLAG_3 | \ | |
172 | FLAG_4 | \ | |
173 | FLAG_5 | \ | |
174 | FLAG_6 | \ | |
175 | FLAG_7 | \ | |
176 | FLAG_SM | \ | |
177 | FLAG_RP | \ | |
178 | FLAG_CONTROL) | |
179 | ||
180 | int reloc_flag; | |
181 | #define RELOC_PCREL 1 | |
182 | #define RELOC_ABS 2 | |
183 | }; | |
184 | ||
185 | extern const struct d30v_opcode d30v_opcode_table[]; | |
186 | extern const int d30v_num_opcodes; | |
187 | ||
188 | /* The operands table is an array of struct d30v_operand. */ | |
189 | struct d30v_operand | |
190 | { | |
191 | /* the length of the field */ | |
192 | int length; | |
193 | ||
194 | /* The number of significant bits in the operand. */ | |
195 | int bits; | |
196 | ||
197 | /* position relative to Ra */ | |
198 | int position; | |
199 | ||
200 | /* syntax flags. */ | |
201 | long flags; | |
202 | }; | |
203 | extern const struct d30v_operand d30v_operand_table[]; | |
204 | ||
205 | /* Values defined for the flags field of a struct d30v_operand. */ | |
206 | ||
207 | /* this is the destination register; it will be modified */ | |
208 | /* this is used by the optimizer */ | |
209 | #define OPERAND_DEST (1) | |
210 | ||
211 | /* number or symbol */ | |
212 | #define OPERAND_NUM (2) | |
213 | ||
214 | /* address or label */ | |
215 | #define OPERAND_ADDR (4) | |
216 | ||
217 | /* register */ | |
218 | #define OPERAND_REG (8) | |
219 | ||
220 | /* postincrement + */ | |
221 | #define OPERAND_PLUS (0x10) | |
222 | ||
223 | /* postdecrement - */ | |
224 | #define OPERAND_MINUS (0x20) | |
225 | ||
226 | /* signed number */ | |
227 | #define OPERAND_SIGNED (0x40) | |
228 | ||
229 | /* this operand must be shifted left by 3 */ | |
230 | #define OPERAND_SHIFT (0x80) | |
231 | ||
232 | /* flag register */ | |
233 | #define OPERAND_FLAG (0x100) | |
234 | ||
235 | /* control register */ | |
236 | #define OPERAND_CONTROL (0x200) | |
237 | ||
238 | /* accumulator */ | |
239 | #define OPERAND_ACC (0x400) | |
240 | ||
241 | /* @ */ | |
242 | #define OPERAND_ATSIGN (0x800) | |
243 | ||
244 | /* @( */ | |
245 | #define OPERAND_ATPAR (0x1000) | |
246 | ||
247 | /* predecrement mode '@-sp' */ | |
248 | #define OPERAND_ATMINUS (0x2000) | |
249 | ||
250 | /* this operand changes the instruction name */ | |
251 | /* for example, CPMcc, CMPUcc */ | |
252 | #define OPERAND_NAME (0x4000) | |
253 | ||
254 | /* fake operand for mvtsys and mvfsys */ | |
255 | #define OPERAND_SPECIAL (0x8000) | |
256 | ||
257 | /* let the optimizer know that two registers are affected */ | |
258 | #define OPERAND_2REG (0x10000) | |
259 | ||
866afedc NC |
260 | /* This operand is pc-relative. Note that repeati can have two immediate |
261 | operands, one of which is pcrel, the other (the IMM6U one) is not. */ | |
262 | #define OPERAND_PCREL (0x20000) | |
263 | ||
252b5132 RH |
264 | /* The format table is an array of struct d30v_format. */ |
265 | struct d30v_format | |
266 | { | |
267 | int form; /* SHORT_A, LONG, etc */ | |
268 | int modifier; /* two bit modifier following opcode */ | |
269 | unsigned char operands[5]; | |
270 | }; | |
271 | extern const struct d30v_format d30v_format_table[]; | |
272 | ||
273 | ||
274 | /* an instruction is defined by an opcode and a format */ | |
275 | /* for example, "add" has one opcode, but three different */ | |
276 | /* formats, 2 SHORT_A forms and a LONG form. */ | |
277 | struct d30v_insn | |
278 | { | |
279 | struct d30v_opcode *op; /* pointer to an entry in the opcode table */ | |
280 | struct d30v_format *form; /* pointer to an entry in the format table */ | |
281 | int ecc; /* execution condition code */ | |
282 | }; | |
283 | ||
284 | /* an expressionS only has one register type, so we fake it */ | |
285 | /* by setting high bits to indicate type */ | |
286 | #define REGISTER_MASK 0xFF | |
287 | ||
288 | #endif /* D30V_H */ |