[deliverable/binutils-gdb.git] / include / opcode / d30v.h

/* d30v.h -- Header file for D30V opcode table
   Copyright 1997 Free Software Foundation, Inc.
   Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions

This file is part of GDB, GAS, and the GNU binutils.

GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.

GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
the GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this file; see the file COPYING.  If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */

#ifndef D30V_H
#define D30V_H

#define NOP 0x00F00000

/* Structure to hold information about predefined registers.  */
struct pd_reg
{
  char *name;		/* name to recognize */
  char *pname;		/* name to print for this register */
  int value;
};

extern const struct pd_reg pre_defined_registers[];
int reg_name_cnt();

/* the number of control registers */
#define MAX_CONTROL_REG	64

/* define the format specifiers */
#define FM00	0
#define FM01	0x80000000
#define FM10	0x8000000000000000LL
#define FM11	0x8000000080000000LL

/* define the opcode classes */
#define BRA	0
#define LOGIC	1
#define IMEM	2
#define IALU1	4
#define IALU2	5

/* define the execution condition codes */
#define ECC_AL	0	/* ALways (default) */
#define ECC_TX	1	/* F0=True, F1=Don't care */
#define ECC_FX	2	/* F0=False, F1=Don't care */
#define ECC_XT	3	/* F0=Don't care, F1=True */
#define ECC_XF	4	/* F0=Don't care, F1=False */
#define ECC_TT	5	/* F0=True, F1=True */
#define ECC_TF	6	/* F0=True, F1=False */
#define ECC_RESERVED	7	/* reserved */
#define ECC_MAX	ECC_RESERVED

extern const char *d30v_ecc_names[];

/* condition code table for CMP and CMPU */
extern const char *d30v_cc_names[];

/* The opcode table is an array of struct d30v_opcode.  */
struct d30v_opcode
{
  /* The opcode name.  */
  const char *name;

  /* the opcode */
  int op1;	/* first part, "IALU1" for example */
  int op2;	/* the rest of the opcode */

  /* opcode format(s).  These numbers correspond to entries */
  /* in the d30v_format_table */
  unsigned char format[4];

#define SHORT_M		1
#define SHORT_M2	5	/* for ld2w and st2w */
#define SHORT_A		9
#define SHORT_B1	11
#define SHORT_B2	12
#define SHORT_B3	13
#define SHORT_B3b	15
#define SHORT_D1	17
#define SHORT_D2	19
#define SHORT_D2B	21
#define SHORT_U		23	/* unary SHORT_A.  ABS for example */
#define SHORT_F		25	/* SHORT_A with flag registers */
#define SHORT_AF	27	/* SHORT_A with only the first register a flag register */
#define SHORT_T		29	/* for trap instruction */
#define SHORT_A5	30	/* SHORT_A with a 5-bit immediate instead of 6 */
#define SHORT_CMP	32	/* special form for CMPcc */
#define SHORT_CMPU	34	/* special form for CMPUcc */
#define SHORT_A1	36	/* special form of SHORT_A for MACa opcodes where a=1 */
#define SHORT_AA	38	/* SHORT_A with the first register an accumulator */
#define SHORT_RA	40	/* SHORT_A with the second register an accumulator */
#define SHORT_MODINC	42	
#define SHORT_MODDEC	43
#define SHORT_C1	44
#define SHORT_C2	45
#define SHORT_UF	46
#define SHORT_A2	47
#define SHORT_A5S	49
#define SHORT_NONE	51	/* no operands */
#define LONG		52
#define LONG_U		53	/* unary LONG */
#define LONG_AF		54	/* LONG with the first register a flag register */
#define LONG_CMP	55	/* special form for CMPcc and CMPUcc */
#define LONG_M		56	/* Memory long for ldb, stb */
#define LONG_M2		57	/* Memory long for ld2w, st2w */
#define LONG_2		58	/* LONG with 2 operands; bratnz */
#define LONG_2b		59	/* LONG_2 with modifier of 3 */
#define LONG_D		60	/* for DBRAI*/
#define LONG_Db		61	/* for repeati*/
#define SHORT_AR	62	/* like SHORT_AA but only accept register as third parameter  */

  /* the execution unit(s) used */
  int unit;
#define EITHER	0
#define IU	1
#define MU	2
#define EITHER_BUT_PREFER_MU 3

  /* this field is used to decide if two instructions */
  /* can be executed in parallel */
  long flags_used;
  long flags_set;
#define FLAG_0		(1L<<0)
#define FLAG_1		(1L<<1)
#define FLAG_2		(1L<<2)
#define FLAG_3		(1L<<3)
#define FLAG_4		(1L<<4)		/* S (saturation) */
#define FLAG_5		(1L<<5)		/* V (overflow) */
#define FLAG_6		(1L<<6)		/* VA (accumulated overflow) */
#define FLAG_7		(1L<<7)		/* C (carry/borrow) */
#define FLAG_SM		(1L<<8)		/* SM (stack mode) */
#define FLAG_RP		(1L<<9)		/* RP (repeat enable) */
#define FLAG_CONTROL	(1L<<10)	/* control registers */
#define FLAG_A0		(1L<<11)	/* A0 */
#define FLAG_A1		(1L<<12)	/* A1 */
#define FLAG_JMP	(1L<<13)	/* instruction is a branch */
#define FLAG_JSR	(1L<<14)	/* subroutine call.  must be aligned */
#define FLAG_MEM	(1L<<15)	/* reads/writes memory */
#define FLAG_NOT_WITH_ADDSUBppp	 (1L<<16) /* Old meaning: a 2 word 4 byter operation
					   New meaning: operation cannot be 
					   combined in parallel with ADD/SUBppp. */
#define FLAG_MUL16	(1L<<17)	/* 16 bit multiply */
#define FLAG_MUL32	(1L<<18)	/* 32 bit multiply */
#define FLAG_ADDSUBppp	(1L<<19)	/* ADDppp or SUBppp */
#define FLAG_DELAY	(1L<<20)	/* This is a delayed branch or jump */
#define FLAG_LKR	(1L<<21)	/* insn in left slot kills right slot */
#define FLAG_CVVA	(FLAG_5|FLAG_6|FLAG_7)
#define FLAG_C		FLAG_7
#define FLAG_ALL	(FLAG_0 | \
			 FLAG_1 | \
			 FLAG_2 | \
			 FLAG_3 | \
			 FLAG_4 | \
			 FLAG_5 | \
			 FLAG_6 | \
			 FLAG_7 | \
			 FLAG_SM | \
			 FLAG_RP | \
			 FLAG_CONTROL)

  int reloc_flag;
#define RELOC_PCREL	1
#define RELOC_ABS	2
};

extern const struct d30v_opcode d30v_opcode_table[];
extern const int d30v_num_opcodes;

/* The operands table is an array of struct d30v_operand.  */
struct d30v_operand
{
  /* the length of the field */
  int length;

  /* The number of significant bits in the operand.  */
  int bits;

  /* position relative to Ra */
  int position;

  /* syntax flags.  */
  long flags;
};
extern const struct d30v_operand d30v_operand_table[];

/* Values defined for the flags field of a struct d30v_operand.  */

/* this is the destination register; it will be modified */
/* this is used by the optimizer */
#define OPERAND_DEST	(1)

/* number or symbol */
#define OPERAND_NUM	(2)

/* address or label */
#define OPERAND_ADDR	(4)

/* register */
#define OPERAND_REG	(8)

/* postincrement +  */
#define OPERAND_PLUS	(0x10)

/* postdecrement -  */
#define OPERAND_MINUS	(0x20)

/* signed number */
#define OPERAND_SIGNED	(0x40)

/* this operand must be shifted left by 3 */
#define OPERAND_SHIFT	(0x80)

/* flag register */
#define OPERAND_FLAG	(0x100)

/* control register  */
#define OPERAND_CONTROL	(0x200)

/* accumulator */
#define OPERAND_ACC	(0x400)

/* @  */
#define OPERAND_ATSIGN	(0x800)

/* @(  */
#define OPERAND_ATPAR	(0x1000)

/* predecrement mode '@-sp'  */
#define OPERAND_ATMINUS	(0x2000)

/* this operand changes the instruction name */
/* for example, CPMcc, CMPUcc */
#define OPERAND_NAME	(0x4000)

/* fake operand for mvtsys and mvfsys */
#define OPERAND_SPECIAL	(0x8000)

/* let the optimizer know that two registers are affected */
#define OPERAND_2REG	(0x10000)

/* The format table is an array of struct d30v_format.  */
struct d30v_format
{
  int	form;		/* SHORT_A, LONG, etc */
  int	modifier;	/* two bit modifier following opcode */
  unsigned char operands[5];
};
extern const struct d30v_format d30v_format_table[];


/* an instruction is defined by an opcode and a format */
/* for example, "add" has one opcode, but three different */
/* formats, 2 SHORT_A forms and a LONG form. */
struct d30v_insn
{
  struct d30v_opcode *op;	/* pointer to an entry in the opcode table */
  struct d30v_format *form;	/* pointer to an entry in the format table */
  int ecc;			/* execution condition code */
};

/* an expressionS only has one register type, so we fake it */
/* by setting high bits to indicate type */
#define REGISTER_MASK	0xFF

#endif /* D30V_H */
Commit	Line	Data
252b5132 RH	1	/* d30v.h -- Header file for D30V opcode table
	2	Copyright 1997 Free Software Foundation, Inc.
	3	Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions
	4
	5	This file is part of GDB, GAS, and the GNU binutils.
	6
	7	GDB, GAS, and the GNU binutils are free software; you can redistribute
	8	them and/or modify them under the terms of the GNU General Public
	9	License as published by the Free Software Foundation; either version
	10	1, or (at your option) any later version.
	11
	12	GDB, GAS, and the GNU binutils are distributed in the hope that they
	13	will be useful, but WITHOUT ANY WARRANTY; without even the implied
	14	warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
	15	the GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this file; see the file COPYING. If not, write to the Free
	19	Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
	20
	21	#ifndef D30V_H
	22	#define D30V_H
	23
	24	#define NOP 0x00F00000
	25
	26	/* Structure to hold information about predefined registers. */
	27	struct pd_reg
	28	{
	29	char name; / name to recognize */
	30	char pname; / name to print for this register */
	31	int value;
	32	};
	33
	34	extern const struct pd_reg pre_defined_registers[];
	35	int reg_name_cnt();
	36
	37	/* the number of control registers */
	38	#define MAX_CONTROL_REG 64
	39
	40	/* define the format specifiers */
	41	#define FM00 0
	42	#define FM01 0x80000000
	43	#define FM10 0x8000000000000000LL
	44	#define FM11 0x8000000080000000LL
	45
	46	/* define the opcode classes */
	47	#define BRA 0
	48	#define LOGIC 1
	49	#define IMEM 2
	50	#define IALU1 4
	51	#define IALU2 5
	52
	53	/* define the execution condition codes */
	54	#define ECC_AL 0 /* ALways (default) */
	55	#define ECC_TX 1 /* F0=True, F1=Don't care */
	56	#define ECC_FX 2 /* F0=False, F1=Don't care */
	57	#define ECC_XT 3 /* F0=Don't care, F1=True */
	58	#define ECC_XF 4 /* F0=Don't care, F1=False */
	59	#define ECC_TT 5 /* F0=True, F1=True */
	60	#define ECC_TF 6 /* F0=True, F1=False */
	61	#define ECC_RESERVED 7 /* reserved */
	62	#define ECC_MAX ECC_RESERVED
	63
	64	extern const char *d30v_ecc_names[];
65
66	/* condition code table for CMP and CMPU */
67	extern const char *d30v_cc_names[];
68
69	/* The opcode table is an array of struct d30v_opcode. */
70	struct d30v_opcode
71	{
72	/* The opcode name. */
73	const char *name;
74
75	/* the opcode */
76	int op1; /* first part, "IALU1" for example */
77	int op2; /* the rest of the opcode */
78
79	/* opcode format(s). These numbers correspond to entries */
80	/* in the d30v_format_table */
81	unsigned char format[4];
82
83	#define SHORT_M 1
84	#define SHORT_M2 5 /* for ld2w and st2w */
85	#define SHORT_A 9
86	#define SHORT_B1 11
87	#define SHORT_B2 12
88	#define SHORT_B3 13
89	#define SHORT_B3b 15
90	#define SHORT_D1 17
91	#define SHORT_D2 19
92	#define SHORT_D2B 21
93	#define SHORT_U 23 /* unary SHORT_A. ABS for example */
94	#define SHORT_F 25 /* SHORT_A with flag registers */
95	#define SHORT_AF 27 /* SHORT_A with only the first register a flag register */
96	#define SHORT_T 29 /* for trap instruction */
97	#define SHORT_A5 30 /* SHORT_A with a 5-bit immediate instead of 6 */
98	#define SHORT_CMP 32 /* special form for CMPcc */
99	#define SHORT_CMPU 34 /* special form for CMPUcc */
100	#define SHORT_A1 36 /* special form of SHORT_A for MACa opcodes where a=1 */
101	#define SHORT_AA 38 /* SHORT_A with the first register an accumulator */
102	#define SHORT_RA 40 /* SHORT_A with the second register an accumulator */
103	#define SHORT_MODINC 42
104	#define SHORT_MODDEC 43
105	#define SHORT_C1 44
106	#define SHORT_C2 45
107	#define SHORT_UF 46
108	#define SHORT_A2 47
109	#define SHORT_A5S 49
110	#define SHORT_NONE 51 /* no operands */
111	#define LONG 52
112	#define LONG_U 53 /* unary LONG */
113	#define LONG_AF 54 /* LONG with the first register a flag register */
114	#define LONG_CMP 55 /* special form for CMPcc and CMPUcc */
115	#define LONG_M 56 /* Memory long for ldb, stb */
116	#define LONG_M2 57 /* Memory long for ld2w, st2w */
117	#define LONG_2 58 /* LONG with 2 operands; bratnz */
118	#define LONG_2b 59 /* LONG_2 with modifier of 3 */
119	#define LONG_D 60 /* for DBRAI*/
120	#define LONG_Db 61 /* for repeati*/
4df2b5c5	121	#define SHORT_AR 62 /* like SHORT_AA but only accept register as third parameter */
252b5132 RH	122
	123	/* the execution unit(s) used */
	124	int unit;
	125	#define EITHER 0
	126	#define IU 1
	127	#define MU 2
	128	#define EITHER_BUT_PREFER_MU 3
	129
	130	/* this field is used to decide if two instructions */
	131	/* can be executed in parallel */
	132	long flags_used;
	133	long flags_set;
	134	#define FLAG_0 (1L<<0)
	135	#define FLAG_1 (1L<<1)
	136	#define FLAG_2 (1L<<2)
	137	#define FLAG_3 (1L<<3)
	138	#define FLAG_4 (1L<<4) /* S (saturation) */
	139	#define FLAG_5 (1L<<5) /* V (overflow) */
	140	#define FLAG_6 (1L<<6) /* VA (accumulated overflow) */
	141	#define FLAG_7 (1L<<7) /* C (carry/borrow) */
	142	#define FLAG_SM (1L<<8) /* SM (stack mode) */
	143	#define FLAG_RP (1L<<9) /* RP (repeat enable) */
	144	#define FLAG_CONTROL (1L<<10) /* control registers */
	145	#define FLAG_A0 (1L<<11) /* A0 */
	146	#define FLAG_A1 (1L<<12) /* A1 */
	147	#define FLAG_JMP (1L<<13) /* instruction is a branch */
	148	#define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */
	149	#define FLAG_MEM (1L<<15) /* reads/writes memory */
20609ff7 CC	150	#define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation
	151	New meaning: operation cannot be
	152	combined in parallel with ADD/SUBppp. */
252b5132 RH	153	#define FLAG_MUL16 (1L<<17) /* 16 bit multiply */
	154	#define FLAG_MUL32 (1L<<18) /* 32 bit multiply */
	155	#define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */
	156	#define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */
	157	#define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */
	158	#define FLAG_CVVA (FLAG_5\|FLAG_6\|FLAG_7)
	159	#define FLAG_C FLAG_7
	160	#define FLAG_ALL (FLAG_0 \| \
	161	FLAG_1 \| \
	162	FLAG_2 \| \
	163	FLAG_3 \| \
	164	FLAG_4 \| \
	165	FLAG_5 \| \
	166	FLAG_6 \| \
	167	FLAG_7 \| \
	168	FLAG_SM \| \
	169	FLAG_RP \| \
	170	FLAG_CONTROL)
	171
	172	int reloc_flag;
	173	#define RELOC_PCREL 1
	174	#define RELOC_ABS 2
	175	};
	176
	177	extern const struct d30v_opcode d30v_opcode_table[];
	178	extern const int d30v_num_opcodes;
	179
	180	/* The operands table is an array of struct d30v_operand. */
	181	struct d30v_operand
	182	{
	183	/* the length of the field */
	184	int length;
	185
	186	/* The number of significant bits in the operand. */
	187	int bits;
	188
	189	/* position relative to Ra */
	190	int position;
	191
	192	/* syntax flags. */
	193	long flags;
	194	};
	195	extern const struct d30v_operand d30v_operand_table[];
	196
	197	/* Values defined for the flags field of a struct d30v_operand. */
	198
	199	/* this is the destination register; it will be modified */
	200	/* this is used by the optimizer */
	201	#define OPERAND_DEST (1)
	202
	203	/* number or symbol */
	204	#define OPERAND_NUM (2)
	205
	206	/* address or label */
	207	#define OPERAND_ADDR (4)
	208
	209	/* register */
	210	#define OPERAND_REG (8)
	211
	212	/* postincrement + */
	213	#define OPERAND_PLUS (0x10)
	214
	215	/* postdecrement - */
	216	#define OPERAND_MINUS (0x20)
217
218	/* signed number */
219	#define OPERAND_SIGNED (0x40)
220
221	/* this operand must be shifted left by 3 */
222	#define OPERAND_SHIFT (0x80)
223
224	/* flag register */
225	#define OPERAND_FLAG (0x100)
226
227	/* control register */
228	#define OPERAND_CONTROL (0x200)
229
230	/* accumulator */
231	#define OPERAND_ACC (0x400)
232
233	/* @ */
234	#define OPERAND_ATSIGN (0x800)
235
236	/* @( */
237	#define OPERAND_ATPAR (0x1000)
238
239	/* predecrement mode '@-sp' */
240	#define OPERAND_ATMINUS (0x2000)
241
242	/* this operand changes the instruction name */
243	/* for example, CPMcc, CMPUcc */
244	#define OPERAND_NAME (0x4000)
245
246	/* fake operand for mvtsys and mvfsys */
247	#define OPERAND_SPECIAL (0x8000)
248
249	/* let the optimizer know that two registers are affected */
250	#define OPERAND_2REG (0x10000)
251
252	/* The format table is an array of struct d30v_format. */
253	struct d30v_format
254	{
255	int form; /* SHORT_A, LONG, etc */
256	int modifier; /* two bit modifier following opcode */
257	unsigned char operands[5];
258	};
259	extern const struct d30v_format d30v_format_table[];
260
261
262	/* an instruction is defined by an opcode and a format */
263	/* for example, "add" has one opcode, but three different */
264	/* formats, 2 SHORT_A forms and a LONG form. */
265	struct d30v_insn
266	{
267	struct d30v_opcode op; / pointer to an entry in the opcode table */
268	struct d30v_format form; / pointer to an entry in the format table */
269	int ecc; /* execution condition code */
270	};
271
272	/* an expressionS only has one register type, so we fake it */
273	/* by setting high bits to indicate type */
274	#define REGISTER_MASK 0xFF
275
276	#endif /* D30V_H */