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d172d4ba NC |
1 | /* Table of opcodes for the DLX microprocess. |
2 | Copyright 2002 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GDB and GAS. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
e172dbf8 | 18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. |
d172d4ba NC |
19 | |
20 | Initially created by Kuang Hwa Lin, 2002. */ | |
21 | ||
22 | /* Following are the function codes for the Special OP (ALU). */ | |
23 | #define ALUOP 0x00000000 | |
24 | #define SPECIALOP 0x00000000 | |
25 | ||
26 | #define NOPF 0x00000000 | |
27 | #define SLLF 0x00000004 | |
28 | #define SRLF 0x00000006 | |
29 | #define SRAF 0x00000007 | |
30 | ||
31 | #define SEQUF 0x00000010 | |
32 | #define SNEUF 0x00000011 | |
33 | #define SLTUF 0x00000012 | |
34 | #define SGTUF 0x00000013 | |
35 | #define SLEUF 0x00000014 | |
36 | #define SGEUF 0x00000015 | |
37 | ||
38 | #define ADDF 0x00000020 | |
39 | #define ADDUF 0x00000021 | |
40 | #define SUBF 0x00000022 | |
41 | #define SUBUF 0x00000023 | |
42 | #define ANDF 0x00000024 | |
43 | #define ORF 0x00000025 | |
44 | #define XORF 0x00000026 | |
45 | ||
46 | #define SEQF 0x00000028 | |
47 | #define SNEF 0x00000029 | |
48 | #define SLTF 0x0000002A | |
49 | #define SGTF 0x0000002B | |
50 | #define SLEF 0x0000002C | |
51 | #define SGEF 0x0000002D | |
52 | /* Following special functions was not mentioned in the | |
53 | Hennessy's book but was implemented in the RTL. */ | |
54 | #define MVTSF 0x00000030 | |
55 | #define MVFSF 0x00000031 | |
56 | #define BSWAPF 0x00000032 | |
57 | #define LUTF 0x00000033 | |
58 | /* Following special functions was mentioned in the | |
59 | Hennessy's book but was not implemented in the RTL. */ | |
60 | #define MULTF 0x00000005 | |
61 | #define MULTUF 0x00000006 | |
62 | #define DIVF 0x00000007 | |
63 | #define DIVUF 0x00000008 | |
64 | ||
65 | ||
66 | /* Following are the rest of the OPcodes: | |
67 | JOP = (0x002 << 26), JALOP = (0x003 << 26), BEQOP = (0x004 << 26), BNEOP = (0x005 << 26) | |
68 | ADDIOP = (0x008 << 26), ADDUIOP= (0x009 << 26), SUBIOP = (0x00A << 26), SUBUIOP= (0x00B << 26) | |
69 | ANDIOP = (0x00C << 26), ORIOP = (0x00D << 26), XORIOP = (0x00E << 26), LHIOP = (0x00F << 26) | |
70 | RFEOP = (0x010 << 26), TRAPOP = (0x011 << 26), JROP = (0x012 << 26), JALROP = (0x013 << 26) | |
71 | BREAKOP= (0x014 << 26) | |
72 | SEQIOP = (0x018 << 26), SNEIOP = (0x019 << 26), SLTIOP = (0x01A << 26), SGTIOP = (0x01B << 26) | |
73 | SLEIOP = (0x01C << 26), SGEIOP = (0x01D << 26) | |
74 | LBOP = (0x020 << 26), LHOP = (0x021 << 26), LWOP = (0x023 << 26), LBUOP = (0x024 << 26) | |
75 | LHUOP = (0x025 << 26), SBOP = (0x028 << 26), SHOP = (0x029 << 26), SWOP = (0x02B << 26) | |
76 | LSBUOP = (0x026 << 26), LSHU = (0x027 << 26), LSW = (0x02C << 26), | |
77 | SEQUIOP= (0x030 << 26), SNEUIOP= (0x031 << 26), SLTUIOP= (0x032 << 26), SGTUIOP= (0x033 << 26) | |
78 | SLEUIOP= (0x034 << 26), SGEUIOP= (0x035 << 26) | |
79 | SLLIOP = (0x036 << 26), SRLIOP = (0x037 << 26), SRAIOP = (0x038 << 26). */ | |
80 | #define JOP 0x08000000 | |
81 | #define JALOP 0x0c000000 | |
82 | #define BEQOP 0x10000000 | |
83 | #define BNEOP 0x14000000 | |
84 | ||
85 | #define ADDIOP 0x20000000 | |
86 | #define ADDUIOP 0x24000000 | |
87 | #define SUBIOP 0x28000000 | |
88 | #define SUBUIOP 0x2c000000 | |
89 | #define ANDIOP 0x30000000 | |
90 | #define ORIOP 0x34000000 | |
91 | #define XORIOP 0x38000000 | |
92 | #define LHIOP 0x3c000000 | |
93 | #define RFEOP 0x40000000 | |
94 | #define TRAPOP 0x44000000 | |
95 | #define JROP 0x48000000 | |
96 | #define JALROP 0x4c000000 | |
97 | #define BREAKOP 0x50000000 | |
98 | ||
99 | #define SEQIOP 0x60000000 | |
100 | #define SNEIOP 0x64000000 | |
101 | #define SLTIOP 0x68000000 | |
102 | #define SGTIOP 0x6c000000 | |
103 | #define SLEIOP 0x70000000 | |
104 | #define SGEIOP 0x74000000 | |
105 | ||
106 | #define LBOP 0x80000000 | |
107 | #define LHOP 0x84000000 | |
108 | #define LWOP 0x8c000000 | |
109 | #define LBUOP 0x90000000 | |
110 | #define LHUOP 0x94000000 | |
111 | #define LDSTBU | |
112 | #define LDSTHU | |
113 | #define SBOP 0xa0000000 | |
114 | #define SHOP 0xa4000000 | |
115 | #define SWOP 0xac000000 | |
116 | #define LDST | |
117 | ||
118 | #define SEQUIOP 0xc0000000 | |
119 | #define SNEUIOP 0xc4000000 | |
120 | #define SLTUIOP 0xc8000000 | |
121 | #define SGTUIOP 0xcc000000 | |
122 | #define SLEUIOP 0xd0000000 | |
123 | #define SGEUIOP 0xd4000000 | |
124 | ||
125 | #define SLLIOP 0xd8000000 | |
126 | #define SRLIOP 0xdc000000 | |
127 | #define SRAIOP 0xe0000000 | |
128 | ||
129 | /* Following 3 ops was added to provide the MP atonmic operation. */ | |
130 | #define LSBUOP 0x98000000 | |
131 | #define LSHUOP 0x9c000000 | |
132 | #define LSWOP 0xb0000000 | |
133 | ||
134 | /* Following opcode was defined in the Hennessy's book as | |
135 | "normal" opcode but was implemented in the RTL as special | |
136 | functions. */ | |
137 | #if 0 | |
138 | #define MVTSOP 0x50000000 | |
139 | #define MVFSOP 0x54000000 | |
140 | #endif | |
141 | ||
142 | struct dlx_opcode | |
143 | { | |
144 | /* Name of the instruction. */ | |
145 | char *name; | |
146 | ||
147 | /* Opcode word. */ | |
148 | unsigned long opcode; | |
149 | ||
150 | /* A string of characters which describe the operands. | |
151 | Valid characters are: | |
152 | , Itself. The character appears in the assembly code. | |
153 | a rs1 The register number is in bits 21-25 of the instruction. | |
154 | b rs2/rd The register number is in bits 16-20 of the instruction. | |
155 | c rd. The register number is in bits 11-15 of the instruction. | |
156 | f FUNC bits 0-10 of the instruction. | |
157 | i An immediate operand is in bits 0-16 of the instruction. 0 extended | |
158 | I An immediate operand is in bits 0-16 of the instruction. sign extended | |
159 | d An 16 bit PC relative displacement. | |
160 | D An immediate operand is in bits 0-25 of the instruction. | |
161 | N No opperands needed, for nops. | |
162 | P it can be a register or a 16 bit operand. */ | |
163 | char *args; | |
164 | }; | |
165 | ||
92007e40 | 166 | static const struct dlx_opcode dlx_opcodes[] = |
d172d4ba NC |
167 | { |
168 | /* Arithmetic and Logic R-TYPE instructions. */ | |
169 | { "nop", (ALUOP|NOPF), "N" }, /* NOP */ | |
170 | { "add", (ALUOP|ADDF), "c,a,b" }, /* Add */ | |
171 | { "addu", (ALUOP|ADDUF), "c,a,b" }, /* Add Unsigned */ | |
172 | { "sub", (ALUOP|SUBF), "c,a,b" }, /* SUB */ | |
173 | { "subu", (ALUOP|SUBUF), "c,a,b" }, /* Sub Unsigned */ | |
174 | { "mult", (ALUOP|MULTF), "c,a,b" }, /* MULTIPLY */ | |
175 | { "multu", (ALUOP|MULTUF), "c,a,b" }, /* MULTIPLY Unsigned */ | |
176 | { "div", (ALUOP|DIVF), "c,a,b" }, /* DIVIDE */ | |
177 | { "divu", (ALUOP|DIVUF), "c,a,b" }, /* DIVIDE Unsigned */ | |
178 | { "and", (ALUOP|ANDF), "c,a,b" }, /* AND */ | |
179 | { "or", (ALUOP|ORF), "c,a,b" }, /* OR */ | |
180 | { "xor", (ALUOP|XORF), "c,a,b" }, /* Exclusive OR */ | |
181 | { "sll", (ALUOP|SLLF), "c,a,b" }, /* SHIFT LEFT LOGICAL */ | |
182 | { "sra", (ALUOP|SRAF), "c,a,b" }, /* SHIFT RIGHT ARITHMETIC */ | |
183 | { "srl", (ALUOP|SRLF), "c,a,b" }, /* SHIFT RIGHT LOGICAL */ | |
184 | { "seq", (ALUOP|SEQF), "c,a,b" }, /* Set if equal */ | |
185 | { "sne", (ALUOP|SNEF), "c,a,b" }, /* Set if not equal */ | |
186 | { "slt", (ALUOP|SLTF), "c,a,b" }, /* Set if less */ | |
187 | { "sgt", (ALUOP|SGTF), "c,a,b" }, /* Set if greater */ | |
188 | { "sle", (ALUOP|SLEF), "c,a,b" }, /* Set if less or equal */ | |
189 | { "sge", (ALUOP|SGEF), "c,a,b" }, /* Set if greater or equal */ | |
190 | { "sequ", (ALUOP|SEQUF), "c,a,b" }, /* Set if equal unsigned */ | |
191 | { "sneu", (ALUOP|SNEUF), "c,a,b" }, /* Set if not equal unsigned */ | |
192 | { "sltu", (ALUOP|SLTUF), "c,a,b" }, /* Set if less unsigned */ | |
193 | { "sgtu", (ALUOP|SGTUF), "c,a,b" }, /* Set if greater unsigned */ | |
194 | { "sleu", (ALUOP|SLEUF), "c,a,b" }, /* Set if less or equal unsigned*/ | |
195 | { "sgeu", (ALUOP|SGEUF), "c,a,b" }, /* Set if greater or equal */ | |
196 | { "mvts", (ALUOP|MVTSF), "c,a" }, /* Move to special register */ | |
197 | { "mvfs", (ALUOP|MVFSF), "c,a" }, /* Move from special register */ | |
198 | { "bswap", (ALUOP|BSWAPF), "c,a,b" }, /* ??? Was not documented */ | |
199 | { "lut", (ALUOP|LUTF), "c,a,b" }, /* ????? same as above */ | |
200 | ||
201 | /* Arithmetic and Logical Immediate I-TYPE instructions. */ | |
202 | { "addi", ADDIOP, "b,a,I" }, /* Add Immediate */ | |
203 | { "addui", ADDUIOP, "b,a,i" }, /* Add Usigned Immediate */ | |
204 | { "subi", SUBIOP, "b,a,I" }, /* Sub Immediate */ | |
205 | { "subui", SUBUIOP, "b,a,i" }, /* Sub Unsigned Immedated */ | |
206 | { "andi", ANDIOP, "b,a,i" }, /* AND Immediate */ | |
207 | { "ori", ORIOP, "b,a,i" }, /* OR Immediate */ | |
208 | { "xori", XORIOP, "b,a,i" }, /* Exclusive OR Immediate */ | |
209 | { "slli", SLLIOP, "b,a,i" }, /* SHIFT LEFT LOCICAL Immediate */ | |
210 | { "srai", SRAIOP, "b,a,i" }, /* SHIFT RIGHT ARITH. Immediate */ | |
211 | { "srli", SRLIOP, "b,a,i" }, /* SHIFT RIGHT LOGICAL Immediate*/ | |
212 | { "seqi", SEQIOP, "b,a,i" }, /* Set if equal */ | |
213 | { "snei", SNEIOP, "b,a,i" }, /* Set if not equal */ | |
214 | { "slti", SLTIOP, "b,a,i" }, /* Set if less */ | |
215 | { "sgti", SGTIOP, "b,a,i" }, /* Set if greater */ | |
216 | { "slei", SLEIOP, "b,a,i" }, /* Set if less or equal */ | |
217 | { "sgei", SGEIOP, "b,a,i" }, /* Set if greater or equal */ | |
218 | { "sequi", SEQUIOP, "b,a,i" }, /* Set if equal */ | |
219 | { "sneui", SNEUIOP, "b,a,i" }, /* Set if not equal */ | |
220 | { "sltui", SLTUIOP, "b,a,i" }, /* Set if less */ | |
221 | { "sgtui", SGTUIOP, "b,a,i" }, /* Set if greater */ | |
222 | { "sleui", SLEUIOP, "b,a,i" }, /* Set if less or equal */ | |
223 | { "sgeui", SGEUIOP, "b,a,i" }, /* Set if greater or equal */ | |
224 | /* Macros for I type instructions. */ | |
225 | { "mov", ADDIOP, "b,P" }, /* a move macro */ | |
226 | { "movu", ADDUIOP, "b,P" }, /* a move macro, unsigned */ | |
227 | ||
228 | #if 0 | |
229 | /* Move special. */ | |
230 | { "mvts", MVTSOP, "b,a" }, /* Move From Integer to Special */ | |
231 | { "mvfs", MVFSOP, "b,a" }, /* Move From Special to Integer */ | |
232 | #endif | |
233 | ||
234 | /* Load high Immediate I-TYPE instruction. */ | |
235 | { "lhi", LHIOP, "b,i" }, /* Load High Immediate */ | |
236 | { "lui", LHIOP, "b,i" }, /* Load High Immediate */ | |
237 | { "sethi", LHIOP, "b,i" }, /* Load High Immediate */ | |
238 | ||
239 | /* LOAD/STORE BYTE 8 bits I-TYPE. */ | |
240 | { "lb", LBOP, "b,a,I" }, /* Load Byte */ | |
241 | { "lbu", LBUOP, "b,a,I" }, /* Load Byte Unsigned */ | |
242 | { "ldstbu", LSBUOP, "b,a,I" }, /* Load store Byte Unsigned */ | |
243 | { "sb", SBOP, "b,a,I" }, /* Store Byte */ | |
244 | ||
245 | /* LOAD/STORE HALFWORD 16 bits. */ | |
246 | { "lh", LHOP, "b,a,I" }, /* Load Halfword */ | |
247 | { "lhu", LHUOP, "b,a,I" }, /* Load Halfword Unsigned */ | |
248 | { "ldsthu", LSHUOP, "b,a,I" }, /* Load Store Halfword Unsigned */ | |
249 | { "sh", SHOP, "b,a,I" }, /* Store Halfword */ | |
250 | ||
251 | /* LOAD/STORE WORD 32 bits. */ | |
252 | { "lw", LWOP, "b,a,I" }, /* Load Word */ | |
253 | { "sw", SWOP, "b,a,I" }, /* Store Word */ | |
254 | { "ldstw", LSWOP, "b,a,I" }, /* Load Store Word */ | |
255 | ||
256 | /* Branch PC-relative, 16 bits offset. */ | |
257 | { "beqz", BEQOP, "a,d" }, /* Branch if a == 0 */ | |
258 | { "bnez", BNEOP, "a,d" }, /* Branch if a != 0 */ | |
259 | { "beq", BEQOP, "a,d" }, /* Branch if a == 0 */ | |
260 | { "bne", BNEOP, "a,d" }, /* Branch if a != 0 */ | |
261 | ||
262 | /* Jumps Trap and RFE J-TYPE. */ | |
263 | { "j", JOP, "D" }, /* Jump, PC-relative 26 bits */ | |
264 | { "jal", JALOP, "D" }, /* JAL, PC-relative 26 bits */ | |
265 | { "break", BREAKOP, "D" }, /* break to OS */ | |
266 | { "trap" , TRAPOP, "D" }, /* TRAP to OS */ | |
267 | { "rfe", RFEOP, "N" }, /* Return From Exception */ | |
268 | /* Macros. */ | |
269 | { "call", JOP, "D" }, /* Jump, PC-relative 26 bits */ | |
270 | ||
271 | /* Jumps Trap and RFE I-TYPE. */ | |
272 | { "jr", JROP, "a" }, /* Jump Register, Abs (32 bits) */ | |
273 | { "jalr", JALROP, "a" }, /* JALR, Abs (32 bits) */ | |
274 | /* Macros. */ | |
275 | { "retr", JROP, "a" }, /* Jump Register, Abs (32 bits) */ | |
276 | ||
277 | { "", 0x0, "" } /* Dummy entry, not included in NUM_OPCODES. | |
278 | This lets code examine entry i + 1 without | |
279 | checking if we've run off the end of the table. */ | |
280 | }; | |
281 | ||
282 | const unsigned int num_dlx_opcodes = (((sizeof dlx_opcodes) / (sizeof dlx_opcodes[0])) - 1); |