Commit | Line | Data |
---|---|---|
252b5132 RH |
1 | /* Table of opcodes for the PA-RISC. |
2 | Copyright (C) 1990, 1991, 1993, 1995, 1999 Free Software Foundation, Inc. | |
3 | ||
4 | Contributed by the Center for Software Science at the | |
5 | University of Utah (pa-gdb-bugs@cs.utah.edu). | |
6 | ||
7 | This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. | |
8 | ||
9 | GAS/GDB is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 1, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GAS/GDB is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GAS or GDB; see the file COPYING. If not, write to | |
21 | the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | #if !defined(__STDC__) && !defined(const) | |
24 | #define const | |
25 | #endif | |
26 | ||
27 | /* | |
28 | * Structure of an opcode table entry. | |
29 | */ | |
30 | ||
31 | /* There are two kinds of delay slot nullification: normal which is | |
32 | * controled by the nullification bit, and conditional, which depends | |
33 | * on the direction of the branch and its success or failure. | |
34 | * | |
35 | * NONE is unfortunately #defined in the hiux system include files. | |
36 | * #undef it away. | |
37 | */ | |
38 | #undef NONE | |
39 | struct pa_opcode | |
40 | { | |
41 | const char *name; | |
42 | unsigned long int match; /* Bits that must be set... */ | |
43 | unsigned long int mask; /* ... in these bits. */ | |
44 | char *args; | |
45 | enum pa_arch arch; | |
73826640 | 46 | char flags; |
252b5132 RH |
47 | }; |
48 | ||
73826640 JL |
49 | /* Enable/disable strict syntax checking. Not currently used, but will |
50 | be necessary for PA2.0 support in the future. */ | |
51 | #define FLAG_STRICT 0x1 | |
252b5132 RH |
52 | |
53 | /* | |
54 | All hppa opcodes are 32 bits. | |
55 | ||
56 | The match component is a mask saying which bits must match a | |
57 | particular opcode in order for an instruction to be an instance | |
58 | of that opcode. | |
59 | ||
c5e52916 JL |
60 | The args component is a string containing one character for each operand of |
61 | the instruction. Characters used as a prefix allow any second character to | |
62 | be used without conflicting with the main operand characters. | |
252b5132 RH |
63 | |
64 | Bit positions in this description follow HP usage of lsb = 31, | |
65 | "at" is lsb of field. | |
66 | ||
67 | In the args field, the following characters must match exactly: | |
68 | ||
69 | '+,() ' | |
70 | ||
71 | In the args field, the following characters are unused: | |
72 | ||
7d8fdb64 | 73 | ' "# & - / 34 6789:;< > @' |
52d836e2 | 74 | ' BC JKLM XY [\] ' |
27bbbb58 | 75 | ' de h m y { } ' |
252b5132 RH |
76 | |
77 | Here are all the characters: | |
78 | ||
79 | ' !"#$%&'()*+-,./0123456789:;<=>?@' | |
80 | 'ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_' | |
81 | 'abcdefghijklmnopqrstuvwxyz{|}~' | |
82 | ||
83 | Kinds of operands: | |
84 | x integer register field at 15. | |
85 | b integer register field at 10. | |
86 | t integer register field at 31. | |
96226a68 | 87 | a integer register field at 10 and 15 (for PERMH) |
252b5132 RH |
88 | 5 5 bit immediate at 15. |
89 | s 2 bit space specifier at 17. | |
90 | S 3 bit space specifier at 18. | |
252b5132 RH |
91 | V 5 bit immediate value at 31 |
92 | i 11 bit immediate value at 31 | |
93 | j 14 bit immediate value at 31 | |
94 | k 21 bit immediate value at 31 | |
95 | n nullification for branch instructions | |
96 | N nullification for spop and copr instructions | |
97 | w 12 bit branch displacement | |
98 | W 17 bit branch displacement (PC relative) | |
99 | z 17 bit branch displacement (just a number, not an address) | |
100 | ||
7d8fdb64 JL |
101 | Also these: |
102 | ||
103 | . 2 bit shift amount at 25 | |
104 | * 4 bit shift amount at 25 | |
105 | p 5 bit shift count at 26 (to support the SHD instruction) encoded as | |
106 | 31-p | |
107 | ~ 6 bit shift count at 20,22:26 encoded as 63-~. | |
108 | P 5 bit bit position at 26 | |
109 | T 5 bit field length at 31 (encoded as 32-T) | |
110 | A 13 bit immediate at 18 (to support the BREAK instruction) | |
111 | ^ like b, but describes a control register | |
112 | ! sar (cr11) register | |
113 | D 26 bit immediate at 31 (to support the DIAG instruction) | |
114 | $ 9 bit immediate at 28 (to support POPBTS) | |
115 | ||
116 | v 3 bit Special Function Unit identifier at 25 | |
117 | O 20 bit Special Function Unit operation split between 15 bits at 20 | |
118 | and 5 bits at 31 | |
119 | o 15 bit Special Function Unit operation at 20 | |
120 | 2 22 bit Special Function Unit operation split between 17 bits at 20 | |
121 | and 5 bits at 31 | |
122 | 1 15 bit Special Function Unit operation split between 10 bits at 20 | |
123 | and 5 bits at 31 | |
124 | 0 10 bit Special Function Unit operation split between 5 bits at 20 | |
125 | and 5 bits at 31 | |
126 | u 3 bit coprocessor unit identifier at 25 | |
127 | F Source Floating Point Operand Format Completer encoded 2 bits at 20 | |
128 | I Source Floating Point Operand Format Completer encoded 1 bits at 20 | |
129 | (for 0xe format FP instructions) | |
130 | G Destination Floating Point Operand Format Completer encoded 2 bits at 18 | |
131 | H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub' | |
132 | (very similar to 'F') | |
133 | ||
134 | r 5 bit immediate value at 31 (for the break instruction) | |
135 | (very similar to V above, except the value is unsigned instead of | |
136 | low_sign_ext) | |
137 | R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions) | |
138 | (same as r above, except the value is in a different location) | |
139 | U 10 bit immediate value at 15 (for SSM, RSM on pa2.0) | |
140 | Q 5 bit immediate value at 10 (a bit position specified in | |
141 | the bb instruction. It's the same as r above, except the | |
142 | value is in a different location) | |
52d836e2 | 143 | Z %r1 -- implicit target of addil instruction. |
c36efdd2 | 144 | g ,gate completer for new syntax branch |
27bbbb58 | 145 | l ,l completer for new syntax branch |
7d8fdb64 | 146 | |
5d4ba527 JL |
147 | Completer operands all have 'c' as the prefix: |
148 | ||
149 | cx indexed load completer. | |
150 | cm short load and store completer. | |
151 | cs store bytes short completer. | |
1d16bf9c JL |
152 | |
153 | cw read/write completer for PROBE | |
154 | cW wide completer for MFCTL | |
155 | cL local processor completer for cache control | |
5d4ba527 | 156 | cZ System Control Completer (to support LPA, LHA, etc.) |
1d16bf9c JL |
157 | |
158 | ci correction completer for DCOR | |
159 | ca add completer | |
160 | cy 32 bit add carry completer | |
161 | cY 64 bit add carry completer | |
162 | cv signed overflow trap completer | |
163 | ct trap on condition completer for ADDI, SUB | |
164 | cT trap on condition completer for UADDCM | |
165 | cb 32 bit borrow completer for SUB | |
166 | cB 64 bit borrow completer for SUB | |
167 | ||
96226a68 JL |
168 | ch left/right half completer |
169 | cH signed/unsigned saturation completer | |
170 | cS signed/unsigned completer at 21 | |
171 | c* permutation completer | |
5d4ba527 | 172 | |
c5e52916 JL |
173 | Condition operands all have '?' as the prefix: |
174 | ||
175 | ?f Floating point compare conditions (encoded as 5 bits at 31) | |
176 | ||
177 | ?a add conditions | |
7d627258 | 178 | ?A 64 bit add conditions |
c5e52916 | 179 | ?@ add branch conditions followed by nullify |
7d627258 JL |
180 | ?d non-negated add branch conditions |
181 | ?D negated add branch conditions | |
182 | ?w wide mode non-negated add branch conditions | |
183 | ?W wide mode negated add branch conditions | |
c5e52916 JL |
184 | |
185 | ?s compare/subtract conditions | |
7d627258 | 186 | ?S 64 bit compare/subtract conditions |
c5e52916 | 187 | ?t non-negated compare conditions |
7d627258 JL |
188 | ?T negated compare conditions |
189 | ?r 64 bit non-negated compare conditions | |
190 | ?R 64 bit negated compare conditions | |
191 | ?Q 64 bit compare conditions for CMPIB instruction | |
c5e52916 JL |
192 | ?n compare conditions followed by nullify |
193 | ||
194 | ?l logical conditions | |
7d627258 JL |
195 | ?L 64 bit logical conditions |
196 | ||
c5e52916 | 197 | ?b branch on bit conditions |
7d627258 | 198 | ?B 64 bit branch on bit conditions |
c5e52916 JL |
199 | |
200 | ?x shift/extract/deposit conditions | |
7d627258 | 201 | ?X 64 bit shift/extract/deposit conditions |
c5e52916 JL |
202 | ?y shift/extract/deposit conditions followed by nullify for conditional |
203 | branches | |
204 | ||
205 | ?u unit conditions | |
7d627258 | 206 | ?U 64 bit unit conditions |
c5e52916 | 207 | |
7d8fdb64 JL |
208 | Floating point registers all have 'f' as a prefix: |
209 | ||
210 | ft target register at 31 | |
211 | fT target register with L/R halves at 31 | |
212 | fa operand 1 register at 10 | |
213 | fA operand 1 register with L/R halves at 10 | |
9392fb11 | 214 | fX Same as fA, except prints a space before register during disasm |
7d8fdb64 JL |
215 | fb operand 2 register at 15 |
216 | fB operand 2 register with L/R halves at 15 | |
217 | fC operand 3 register with L/R halves at 16:18,21:23 | |
218 | ||
219 | Float registers for fmpyadd and fmpysub: | |
220 | ||
221 | fi mult operand 1 register at 10 | |
222 | fj mult operand 2 register at 15 | |
223 | fk mult target register at 20 | |
224 | fl add/sub operand register at 25 | |
225 | fm add/sub target register at 31 | |
252b5132 | 226 | |
7d627258 | 227 | */ |
252b5132 RH |
228 | |
229 | ||
230 | /* List of characters not to put a space after. Note that | |
231 | "," is included, as the "spopN" operations use literal | |
232 | commas in their completer sections. */ | |
233 | static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}"; | |
234 | ||
235 | /* The order of the opcodes in this table is significant: | |
236 | ||
237 | * The assembler requires that all instances of the same mnemonic must be | |
238 | consecutive. If they aren't, the assembler will bomb at runtime. | |
239 | ||
240 | * The disassembler should not care about the order of the opcodes. */ | |
241 | ||
242 | static const struct pa_opcode pa_opcodes[] = | |
243 | { | |
244 | ||
245 | ||
c36efdd2 | 246 | { "b", 0xe8002000, 0xfc00e000, "gnW,b", pa10, FLAG_STRICT}, |
27bbbb58 | 247 | { "b", 0xe8000000, 0xfc00e000, "lnW,b", pa10, FLAG_STRICT}, |
252b5132 RH |
248 | { "b", 0xe8000000, 0xffe0e000, "nW", pa10}, /* bl foo,r0 */ |
249 | { "ldi", 0x34000000, 0xffe0c000, "j,x", pa10}, /* ldo val(r0),r */ | |
c5e52916 | 250 | { "comib", 0x84000000, 0xfc000000, "?nn5,b,w", pa10}, /* comib{tf}*/ |
e26b85f0 JL |
251 | /* This entry is for the disassembler only. It will never be used by |
252 | assembler. */ | |
c5e52916 JL |
253 | { "comib", 0x8c000000, 0xfc000000, "?nn5,b,w", pa10}, /* comib{tf}*/ |
254 | { "comb", 0x80000000, 0xfc000000, "?nnx,b,w", pa10}, /* comb{tf} */ | |
e26b85f0 JL |
255 | /* This entry is for the disassembler only. It will never be used by |
256 | assembler. */ | |
c5e52916 JL |
257 | { "comb", 0x88000000, 0xfc000000, "?nnx,b,w", pa10}, /* comb{tf} */ |
258 | { "addb", 0xa0000000, 0xfc000000, "?@nx,b,w", pa10}, /* addb{tf} */ | |
e26b85f0 JL |
259 | /* This entry is for the disassembler only. It will never be used by |
260 | assembler. */ | |
c5e52916 JL |
261 | { "addb", 0xa8000000, 0xfc000000, "?@nx,b,w", pa10}, |
262 | { "addib", 0xa4000000, 0xfc000000, "?@n5,b,w", pa10}, /* addib{tf}*/ | |
e26b85f0 JL |
263 | /* This entry is for the disassembler only. It will never be used by |
264 | assembler. */ | |
c5e52916 | 265 | { "addib", 0xac000000, 0xfc000000, "?@n5,b,w", pa10}, /* addib{tf}*/ |
252b5132 RH |
266 | { "nop", 0x08000240, 0xffffffff, "", pa10}, /* or 0,0,0 */ |
267 | { "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10}, /* or r,0,t */ | |
268 | { "mtsar", 0x01601840, 0xffe0ffff, "x", pa10}, /* mtctl r,cr11 */ | |
269 | ||
270 | /* Loads and Stores for integer registers. */ | |
90765e3a JL |
271 | { "ldd", 0x0c0000c0, 0xfc001fc0, "cxx(s,b),t", pa20, FLAG_STRICT}, |
272 | { "ldd", 0x0c0000c0, 0xfc001fc0, "cxx(b),t", pa20, FLAG_STRICT}, | |
273 | { "ldd", 0x0c0010c0, 0xfc001fc0, "cm5(s,b),t", pa20, FLAG_STRICT}, | |
274 | { "ldd", 0x0c0010c0, 0xfc001fc0, "cm5(b),t", pa20, FLAG_STRICT}, | |
275 | { "ldw", 0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10, FLAG_STRICT}, | |
276 | { "ldw", 0x0c000080, 0xfc001fc0, "cxx(b),t", pa10, FLAG_STRICT}, | |
277 | { "ldw", 0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10, FLAG_STRICT}, | |
278 | { "ldw", 0x0c001080, 0xfc001fc0, "cm5(b),t", pa10, FLAG_STRICT}, | |
252b5132 RH |
279 | { "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10}, |
280 | { "ldw", 0x48000000, 0xfc000000, "j(b),x", pa10}, | |
90765e3a JL |
281 | { "ldh", 0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10, FLAG_STRICT}, |
282 | { "ldh", 0x0c000040, 0xfc001fc0, "cxx(b),t", pa10, FLAG_STRICT}, | |
283 | { "ldh", 0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10, FLAG_STRICT}, | |
284 | { "ldh", 0x0c001040, 0xfc001fc0, "cm5(b),t", pa10, FLAG_STRICT}, | |
252b5132 RH |
285 | { "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10}, |
286 | { "ldh", 0x44000000, 0xfc000000, "j(b),x", pa10}, | |
90765e3a JL |
287 | { "ldb", 0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10, FLAG_STRICT}, |
288 | { "ldb", 0x0c000000, 0xfc001fc0, "cxx(b),t", pa10, FLAG_STRICT}, | |
289 | { "ldb", 0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10, FLAG_STRICT}, | |
290 | { "ldb", 0x0c001000, 0xfc001fc0, "cm5(b),t", pa10, FLAG_STRICT}, | |
252b5132 RH |
291 | { "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10}, |
292 | { "ldb", 0x40000000, 0xfc000000, "j(b),x", pa10}, | |
90765e3a JL |
293 | { "std", 0x0c0012c0, 0xfc001fc0, "cmx,V(s,b)", pa20, FLAG_STRICT}, |
294 | { "std", 0x0c0012c0, 0xfc001fc0, "cmx,V(b)", pa20, FLAG_STRICT}, | |
295 | { "stw", 0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10, FLAG_STRICT}, | |
296 | { "stw", 0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10, FLAG_STRICT}, | |
252b5132 RH |
297 | { "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10}, |
298 | { "stw", 0x68000000, 0xfc000000, "x,j(b)", pa10}, | |
90765e3a JL |
299 | { "sth", 0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10, FLAG_STRICT}, |
300 | { "sth", 0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10, FLAG_STRICT}, | |
252b5132 RH |
301 | { "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10}, |
302 | { "sth", 0x64000000, 0xfc000000, "x,j(b)", pa10}, | |
90765e3a JL |
303 | { "stb", 0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10, FLAG_STRICT}, |
304 | { "stb", 0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10, FLAG_STRICT}, | |
252b5132 RH |
305 | { "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10}, |
306 | { "stb", 0x60000000, 0xfc000000, "x,j(b)", pa10}, | |
307 | { "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10}, | |
308 | { "ldwm", 0x4c000000, 0xfc000000, "j(b),x", pa10}, | |
309 | { "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10}, | |
310 | { "stwm", 0x6c000000, 0xfc000000, "x,j(b)", pa10}, | |
5d4ba527 JL |
311 | { "ldwx", 0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10}, |
312 | { "ldwx", 0x0c000080, 0xfc001fc0, "cxx(b),t", pa10}, | |
313 | { "ldhx", 0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10}, | |
314 | { "ldhx", 0x0c000040, 0xfc001fc0, "cxx(b),t", pa10}, | |
315 | { "ldbx", 0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10}, | |
316 | { "ldbx", 0x0c000000, 0xfc001fc0, "cxx(b),t", pa10}, | |
90765e3a JL |
317 | { "ldwa", 0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10, FLAG_STRICT}, |
318 | { "ldwa", 0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10, FLAG_STRICT}, | |
319 | { "ldcw", 0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10, FLAG_STRICT}, | |
320 | { "ldcw", 0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10, FLAG_STRICT}, | |
321 | { "ldcw", 0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10, FLAG_STRICT}, | |
322 | { "ldcw", 0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10, FLAG_STRICT}, | |
323 | { "stwa", 0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10, FLAG_STRICT}, | |
324 | { "stby", 0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10, FLAG_STRICT}, | |
325 | { "stby", 0x0c001300, 0xfc001fc0, "csx,V(b)", pa10, FLAG_STRICT}, | |
326 | { "ldda", 0x0c000100, 0xfc00dfc0, "cxx(b),t", pa20, FLAG_STRICT}, | |
327 | { "ldda", 0x0c001100, 0xfc00dfc0, "cm5(b),t", pa20, FLAG_STRICT}, | |
328 | { "ldcd", 0x0c000140, 0xfc001fc0, "cxx(s,b),t", pa20, FLAG_STRICT}, | |
329 | { "ldcd", 0x0c000140, 0xfc001fc0, "cxx(b),t", pa20, FLAG_STRICT}, | |
330 | { "ldcd", 0x0c001140, 0xfc001fc0, "cm5(s,b),t", pa20, FLAG_STRICT}, | |
331 | { "ldcd", 0x0c001140, 0xfc001fc0, "cm5(b),t", pa20, FLAG_STRICT}, | |
332 | { "stda", 0x0c0013c0, 0xfc001fc0, "cmx,V(s,b)", pa20, FLAG_STRICT}, | |
333 | { "stda", 0x0c0013c0, 0xfc001fc0, "cmx,V(b)", pa20, FLAG_STRICT}, | |
5d4ba527 JL |
334 | { "ldwax", 0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10}, |
335 | { "ldcwx", 0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10}, | |
336 | { "ldcwx", 0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10}, | |
337 | { "ldws", 0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10}, | |
338 | { "ldws", 0x0c001080, 0xfc001fc0, "cm5(b),t", pa10}, | |
339 | { "ldhs", 0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10}, | |
340 | { "ldhs", 0x0c001040, 0xfc001fc0, "cm5(b),t", pa10}, | |
341 | { "ldbs", 0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10}, | |
342 | { "ldbs", 0x0c001000, 0xfc001fc0, "cm5(b),t", pa10}, | |
343 | { "ldwas", 0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10}, | |
344 | { "ldcws", 0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10}, | |
345 | { "ldcws", 0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10}, | |
346 | { "stws", 0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10}, | |
347 | { "stws", 0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10}, | |
348 | { "sths", 0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10}, | |
349 | { "sths", 0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10}, | |
350 | { "stbs", 0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10}, | |
351 | { "stbs", 0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10}, | |
352 | { "stwas", 0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10}, | |
90765e3a JL |
353 | { "stdby", 0x0c001340, 0xfc001fc0, "csx,V(s,b)", pa20, FLAG_STRICT}, |
354 | { "stdby", 0x0c001340, 0xfc001fc0, "csx,V(b)", pa20, FLAG_STRICT}, | |
5d4ba527 JL |
355 | { "stbys", 0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10}, |
356 | { "stbys", 0x0c001300, 0xfc001fc0, "csx,V(b)", pa10}, | |
252b5132 RH |
357 | |
358 | /* Immediate instructions. */ | |
359 | { "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10}, | |
360 | { "ldil", 0x20000000, 0xfc000000, "k,b", pa10}, | |
52d836e2 | 361 | { "addil", 0x28000000, 0xfc000000, "k,b,Z", pa10}, |
252b5132 RH |
362 | { "addil", 0x28000000, 0xfc000000, "k,b", pa10}, |
363 | ||
364 | /* Branching instructions. */ | |
365 | { "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10}, | |
366 | { "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10}, | |
367 | { "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10}, | |
368 | { "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10}, | |
369 | { "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10}, | |
370 | { "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10}, | |
371 | { "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10}, | |
c5e52916 JL |
372 | { "movb", 0xc8000000, 0xfc000000, "?ynx,b,w", pa10}, |
373 | { "movib", 0xcc000000, 0xfc000000, "?yn5,b,w", pa10}, | |
374 | { "combt", 0x80000000, 0xfc000000, "?tnx,b,w", pa10}, | |
375 | { "combf", 0x88000000, 0xfc000000, "?tnx,b,w", pa10}, | |
376 | { "comibt", 0x84000000, 0xfc000000, "?tn5,b,w", pa10}, | |
377 | { "comibf", 0x8c000000, 0xfc000000, "?tn5,b,w", pa10}, | |
378 | { "addbt", 0xa0000000, 0xfc000000, "?dnx,b,w", pa10}, | |
379 | { "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10}, | |
380 | { "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10}, | |
381 | { "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10}, | |
e9fc28c6 | 382 | { "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, |
e9fc28c6 | 383 | { "bb", 0xc4006000, 0xfc006000, "?Bnx,Q,w", pa20, FLAG_STRICT}, |
96226a68 | 384 | { "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, |
c5e52916 JL |
385 | { "bb", 0xc4004000, 0xfc004000, "?bnx,Q,w", pa10}, |
386 | { "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10}, | |
88a380f3 | 387 | { "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT}, |
e9fc28c6 | 388 | { "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT}, |
88a380f3 JL |
389 | { "pushnom", 0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT}, |
390 | { "pushbts", 0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT}, | |
252b5132 RH |
391 | |
392 | /* Computation Instructions */ | |
393 | ||
5696871a JL |
394 | { "cmpclr", 0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT}, |
395 | { "cmpclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT}, | |
c5e52916 | 396 | { "comclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10}, |
5696871a | 397 | { "or", 0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, |
c5e52916 | 398 | { "or", 0x08000240, 0xfc000fe0, "?lx,b,t", pa10}, |
5696871a | 399 | { "xor", 0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, |
c5e52916 | 400 | { "xor", 0x08000280, 0xfc000fe0, "?lx,b,t", pa10}, |
5696871a | 401 | { "and", 0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, |
c5e52916 | 402 | { "and", 0x08000200, 0xfc000fe0, "?lx,b,t", pa10}, |
5696871a | 403 | { "andcm", 0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, |
c5e52916 | 404 | { "andcm", 0x08000000, 0xfc000fe0, "?lx,b,t", pa10}, |
1c143202 | 405 | { "uxor", 0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT}, |
c5e52916 | 406 | { "uxor", 0x08000380, 0xfc000fe0, "?ux,b,t", pa10}, |
1d16bf9c JL |
407 | { "uaddcm", 0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT}, |
408 | { "uaddcm", 0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT}, | |
c5e52916 JL |
409 | { "uaddcm", 0x08000980, 0xfc000fe0, "?ux,b,t", pa10}, |
410 | { "uaddcmt", 0x080009c0, 0xfc000fe0, "?ux,b,t", pa10}, | |
1d16bf9c JL |
411 | { "dcor", 0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT}, |
412 | { "dcor", 0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT}, | |
c5e52916 JL |
413 | { "dcor", 0x08000b80, 0xfc1f0fe0, "?ub,t", pa10}, |
414 | { "idcor", 0x08000bc0, 0xfc1f0fe0, "?ub,t", pa10}, | |
1d16bf9c JL |
415 | { "addi", 0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT}, |
416 | { "addi", 0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT}, | |
c5e52916 JL |
417 | { "addi", 0xb4000000, 0xfc000800, "?ai,b,x", pa10}, |
418 | { "addio", 0xb4000800, 0xfc000800, "?ai,b,x", pa10}, | |
419 | { "addit", 0xb0000000, 0xfc000800, "?ai,b,x", pa10}, | |
420 | { "addito", 0xb0000800, 0xfc000800, "?ai,b,x", pa10}, | |
1d16bf9c JL |
421 | { "add", 0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT}, |
422 | { "add", 0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT}, | |
423 | { "add", 0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT}, | |
424 | { "add", 0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT}, | |
c5e52916 JL |
425 | { "add", 0x08000600, 0xfc000fe0, "?ax,b,t", pa10}, |
426 | { "addl", 0x08000a00, 0xfc000fe0, "?ax,b,t", pa10}, | |
427 | { "addo", 0x08000e00, 0xfc000fe0, "?ax,b,t", pa10}, | |
428 | { "addc", 0x08000700, 0xfc000fe0, "?ax,b,t", pa10}, | |
429 | { "addco", 0x08000f00, 0xfc000fe0, "?ax,b,t", pa10}, | |
1d16bf9c JL |
430 | { "sub", 0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT}, |
431 | { "sub", 0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT}, | |
432 | { "sub", 0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT}, | |
433 | { "sub", 0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT}, | |
434 | { "sub", 0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT}, | |
435 | { "sub", 0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT}, | |
c5e52916 JL |
436 | { "sub", 0x08000400, 0xfc000fe0, "?sx,b,t", pa10}, |
437 | { "subo", 0x08000c00, 0xfc000fe0, "?sx,b,t", pa10}, | |
438 | { "subb", 0x08000500, 0xfc000fe0, "?sx,b,t", pa10}, | |
439 | { "subbo", 0x08000d00, 0xfc000fe0, "?sx,b,t", pa10}, | |
440 | { "subt", 0x080004c0, 0xfc000fe0, "?sx,b,t", pa10}, | |
441 | { "subto", 0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10}, | |
442 | { "ds", 0x08000440, 0xfc000fe0, "?sx,b,t", pa10}, | |
1d16bf9c | 443 | { "subi", 0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT}, |
c5e52916 JL |
444 | { "subi", 0x94000000, 0xfc000800, "?si,b,x", pa10}, |
445 | { "subio", 0x94000800, 0xfc000800, "?si,b,x", pa10}, | |
5696871a JL |
446 | { "cmpiclr", 0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT}, |
447 | { "cmpiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT}, | |
c5e52916 | 448 | { "comiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10}, |
1d16bf9c JL |
449 | { "shladd", 0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT}, |
450 | { "shladd", 0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT}, | |
c5e52916 JL |
451 | { "sh1add", 0x08000640, 0xfc000fe0, "?ax,b,t", pa10}, |
452 | { "sh1addl", 0x08000a40, 0xfc000fe0, "?ax,b,t", pa10}, | |
453 | { "sh1addo", 0x08000e40, 0xfc000fe0, "?ax,b,t", pa10}, | |
454 | { "sh2add", 0x08000680, 0xfc000fe0, "?ax,b,t", pa10}, | |
455 | { "sh2addl", 0x08000a80, 0xfc000fe0, "?ax,b,t", pa10}, | |
456 | { "sh2addo", 0x08000e80, 0xfc000fe0, "?ax,b,t", pa10}, | |
457 | { "sh3add", 0x080006c0, 0xfc000fe0, "?ax,b,t", pa10}, | |
458 | { "sh3addl", 0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10}, | |
459 | { "sh3addo", 0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10}, | |
252b5132 | 460 | |
e9fc28c6 JL |
461 | /* Subword Operation Instructions */ |
462 | ||
96226a68 | 463 | { "hadd", 0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, |
e9fc28c6 | 464 | { "havg", 0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT}, |
96226a68 | 465 | { "hshl", 0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT}, |
e9fc28c6 | 466 | { "hshladd", 0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, |
5e6ca421 | 467 | { "hshr", 0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT}, |
e9fc28c6 | 468 | { "hshradd", 0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, |
96226a68 JL |
469 | { "hsub", 0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, |
470 | { "mixh", 0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, | |
471 | { "mixw", 0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, | |
472 | { "permh", 0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT}, | |
e9fc28c6 JL |
473 | |
474 | ||
252b5132 RH |
475 | /* Extract and Deposit Instructions */ |
476 | ||
e9fc28c6 JL |
477 | { "shrpd", 0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT}, |
478 | { "shrpd", 0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT}, | |
479 | { "shrpw", 0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT}, | |
480 | { "shrpw", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT}, | |
c5e52916 JL |
481 | { "vshd", 0xd0000000, 0xfc001fe0, "?xx,b,t", pa10}, |
482 | { "shd", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10}, | |
90927b9c JL |
483 | { "extrd", 0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT}, |
484 | { "extrd", 0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT}, | |
485 | { "extrw", 0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT}, | |
486 | { "extrw", 0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT}, | |
c5e52916 JL |
487 | { "vextru", 0xd0001000, 0xfc001fe0, "?xb,T,x", pa10}, |
488 | { "vextrs", 0xd0001400, 0xfc001fe0, "?xb,T,x", pa10}, | |
489 | { "extru", 0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10}, | |
490 | { "extrs", 0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10}, | |
90927b9c JL |
491 | { "depd", 0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT}, |
492 | { "depd", 0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT}, | |
493 | { "depdi", 0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT}, | |
494 | { "depdi", 0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT}, | |
495 | { "depw", 0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT}, | |
496 | { "depw", 0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT}, | |
497 | { "depwi", 0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT}, | |
f2727d04 | 498 | { "depwi", 0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT}, |
c5e52916 JL |
499 | { "zvdep", 0xd4000000, 0xfc001fe0, "?xx,T,b", pa10}, |
500 | { "vdep", 0xd4000400, 0xfc001fe0, "?xx,T,b", pa10}, | |
501 | { "zdep", 0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10}, | |
502 | { "dep", 0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10}, | |
503 | { "zvdepi", 0xd4001000, 0xfc001fe0, "?x5,T,b", pa10}, | |
504 | { "vdepi", 0xd4001400, 0xfc001fe0, "?x5,T,b", pa10}, | |
505 | { "zdepi", 0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10}, | |
506 | { "depi", 0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10}, | |
252b5132 RH |
507 | |
508 | /* System Control Instructions */ | |
509 | ||
510 | { "break", 0x00000000, 0xfc001fe0, "r,A", pa10}, | |
1d16bf9c | 511 | { "rfi", 0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT}, |
252b5132 RH |
512 | { "rfi", 0x00000c00, 0xffffffff, "", pa10}, |
513 | { "rfir", 0x00000ca0, 0xffffffff, "", pa11}, | |
1d16bf9c | 514 | { "ssm", 0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, |
252b5132 | 515 | { "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10}, |
1d16bf9c | 516 | { "rsm", 0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, |
252b5132 RH |
517 | { "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10}, |
518 | { "mtsm", 0x00001860, 0xffe0ffff, "x", pa10}, | |
519 | { "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10}, | |
520 | { "ldsid", 0x000010a0, 0xfc1f3fe0, "(b),t", pa10}, | |
521 | { "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10}, | |
522 | { "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10}, | |
88a380f3 JL |
523 | { "mtsarcm", 0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT}, |
524 | { "mfia", 0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT}, | |
252b5132 | 525 | { "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10}, |
1d16bf9c | 526 | { "mfctl", 0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT}, |
252b5132 RH |
527 | { "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10}, |
528 | { "sync", 0x00000400, 0xffffffff, "", pa10}, | |
529 | { "syncdma", 0x00100400, 0xffffffff, "", pa10}, | |
e0c52e99 JL |
530 | { "probe", 0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT}, |
531 | { "probe", 0x04001180, 0xfc003fa0, "cw(b),x,t", pa10, FLAG_STRICT}, | |
532 | { "probei", 0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT}, | |
533 | { "probei", 0x04003180, 0xfc003fa0, "cw(b),R,t", pa10, FLAG_STRICT}, | |
252b5132 RH |
534 | { "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10}, |
535 | { "prober", 0x04001180, 0xfc003fe0, "(b),x,t", pa10}, | |
536 | { "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10}, | |
537 | { "proberi", 0x04003180, 0xfc003fe0, "(b),R,t", pa10}, | |
538 | { "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10}, | |
539 | { "probew", 0x040011c0, 0xfc003fe0, "(b),x,t", pa10}, | |
540 | { "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10}, | |
541 | { "probewi", 0x040031c0, 0xfc003fe0, "(b),R,t", pa10}, | |
5d4ba527 JL |
542 | { "lpa", 0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10}, |
543 | { "lpa", 0x04001340, 0xfc003fc0, "cZx(b),t", pa10}, | |
544 | { "lha", 0x04001300, 0xfc003fc0, "cZx(s,b),t", pa10}, | |
545 | { "lha", 0x04001300, 0xfc003fc0, "cZx(b),t", pa10}, | |
252b5132 RH |
546 | { "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa10}, |
547 | { "lci", 0x04001300, 0xfc003fe0, "x(b),t", pa10}, | |
1d16bf9c JL |
548 | { "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT}, |
549 | { "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(b)", pa20, FLAG_STRICT}, | |
5d4ba527 JL |
550 | { "pdtlb", 0x04001200, 0xfc003fdf, "cZx(s,b)", pa10}, |
551 | { "pdtlb", 0x04001200, 0xfc003fdf, "cZx(b)", pa10}, | |
1d16bf9c JL |
552 | { "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT}, |
553 | { "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(b)", pa20, FLAG_STRICT}, | |
5d4ba527 JL |
554 | { "pitlb", 0x04000200, 0xfc001fdf, "cZx(S,b)", pa10}, |
555 | { "pitlb", 0x04000200, 0xfc001fdf, "cZx(b)", pa10}, | |
556 | { "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(s,b)", pa10}, | |
557 | { "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(b)", pa10}, | |
558 | { "pitlbe", 0x04000240, 0xfc001fdf, "cZx(S,b)", pa10}, | |
559 | { "pitlbe", 0x04000240, 0xfc001fdf, "cZx(b)", pa10}, | |
252b5132 RH |
560 | { "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10}, |
561 | { "idtlba", 0x04001040, 0xfc003fff, "x,(b)", pa10}, | |
562 | { "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10}, | |
563 | { "iitlba", 0x04000040, 0xfc001fff, "x,(b)", pa10}, | |
564 | { "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10}, | |
565 | { "idtlbp", 0x04001000, 0xfc003fff, "x,(b)", pa10}, | |
566 | { "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10}, | |
567 | { "iitlbp", 0x04000000, 0xfc001fff, "x,(b)", pa10}, | |
5d4ba527 JL |
568 | { "pdc", 0x04001380, 0xfc003fdf, "cZx(s,b)", pa10}, |
569 | { "pdc", 0x04001380, 0xfc003fdf, "cZx(b)", pa10}, | |
570 | { "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10}, | |
571 | { "fdc", 0x04001280, 0xfc003fdf, "cZx(b)", pa10}, | |
572 | { "fic", 0x04000280, 0xfc001fdf, "cZx(S,b)", pa10}, | |
573 | { "fic", 0x04000280, 0xfc001fdf, "cZx(b)", pa10}, | |
574 | { "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10}, | |
575 | { "fdce", 0x040012c0, 0xfc003fdf, "cZx(b)", pa10}, | |
576 | { "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10}, | |
577 | { "fice", 0x040002c0, 0xfc001fdf, "cZx(b)", pa10}, | |
252b5132 | 578 | { "diag", 0x14000000, 0xfc000000, "D", pa10}, |
90765e3a JL |
579 | { "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, |
580 | { "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, | |
252b5132 | 581 | |
aa008907 JL |
582 | /* These may be specific to certain versions of the PA. Joel claimed |
583 | they were 72000 (7200?) specific. However, I'm almost certain the | |
584 | mtcpu/mfcpu were undocumented, but available in the older 700 machines. */ | |
585 | { "mtcpu", 0x14001600, 0xfc00ffff, "x,^"}, | |
586 | { "mfcpu", 0x14001A00, 0xfc00ffff, "^,x"}, | |
587 | { "tocen", 0x14403600, 0xffffffff, ""}, | |
588 | { "tocdis", 0x14401620, 0xffffffff, ""}, | |
589 | { "shdwgr", 0x14402600, 0xffffffff, ""}, | |
590 | { "grshdw", 0x14400620, 0xffffffff, ""}, | |
591 | ||
252b5132 RH |
592 | /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either |
593 | the Timex FPU or the Mustang ERS (not sure which) manual. */ | |
5d4ba527 JL |
594 | { "gfw", 0x04001680, 0xfc003fdf, "cZx(s,b)", pa11}, |
595 | { "gfw", 0x04001680, 0xfc003fdf, "cZx(b)", pa11}, | |
596 | { "gfr", 0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11}, | |
597 | { "gfr", 0x04001a80, 0xfc003fdf, "cZx(b)", pa11}, | |
252b5132 RH |
598 | |
599 | /* Floating Point Coprocessor Instructions */ | |
600 | ||
7d8fdb64 JL |
601 | { "fldwx", 0x24000000, 0xfc001f80, "cxx(s,b),fT", pa10}, |
602 | { "fldwx", 0x24000000, 0xfc001f80, "cxx(b),fT", pa10}, | |
603 | { "flddx", 0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10}, | |
604 | { "flddx", 0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10}, | |
605 | { "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10}, | |
606 | { "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(b)", pa10}, | |
607 | { "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10}, | |
608 | { "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10}, | |
609 | { "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10}, | |
610 | { "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(b)", pa10}, | |
611 | { "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10}, | |
612 | { "fldws", 0x24001000, 0xfc001f80, "cm5(b),fT", pa10}, | |
613 | { "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10}, | |
614 | { "fldds", 0x2c001000, 0xfc001fc0, "cm5(b),ft", pa10}, | |
615 | { "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10}, | |
616 | { "fstws", 0x24001200, 0xfc001f80, "cmfT,5(b)", pa10}, | |
617 | { "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10}, | |
618 | { "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(b)", pa10}, | |
619 | { "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10}, | |
620 | { "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(b)", pa10}, | |
621 | { "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10}, | |
622 | { "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10}, | |
623 | { "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10}, | |
624 | { "fsub", 0x38002600, 0xfc00e720, "IfA,fB,fT", pa10}, | |
625 | { "fmpy", 0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10}, | |
626 | { "fmpy", 0x38004600, 0xfc00e720, "IfA,fB,fT", pa10}, | |
627 | { "fdiv", 0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10}, | |
628 | { "fdiv", 0x38006600, 0xfc00e720, "IfA,fB,fT", pa10}, | |
629 | { "fsqrt", 0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10}, | |
630 | { "fsqrt", 0x38008000, 0xfc1fe720, "FfA,fT", pa10}, | |
631 | { "fabs", 0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10}, | |
632 | { "fabs", 0x38006000, 0xfc1fe720, "FfA,fT", pa10}, | |
633 | { "frem", 0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10}, | |
634 | { "frem", 0x38008600, 0xfc00e720, "FfA,fB,fT", pa10}, | |
635 | { "frnd", 0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10}, | |
636 | { "frnd", 0x3800a000, 0xfc1fe720, "FfA,fT", pa10}, | |
637 | { "fcpy", 0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10}, | |
638 | { "fcpy", 0x38004000, 0xfc1fe720, "FfA,fT", pa10}, | |
639 | { "fcnvff", 0x30000200, 0xfc1f87e0, "FGfa,fT", pa10}, | |
640 | { "fcnvff", 0x38000200, 0xfc1f8720, "FGfA,fT", pa10}, | |
641 | { "fcnvxf", 0x30008200, 0xfc1f87e0, "FGfa,fT", pa10}, | |
642 | { "fcnvxf", 0x38008200, 0xfc1f8720, "FGfA,fT", pa10}, | |
643 | { "fcnvfx", 0x30010200, 0xfc1f87e0, "FGfa,fT", pa10}, | |
644 | { "fcnvfx", 0x38010200, 0xfc1f8720, "FGfA,fT", pa10}, | |
645 | { "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGfa,fT", pa10}, | |
646 | { "fcnvfxt", 0x38018200, 0xfc1f8720, "FGfA,fT", pa10}, | |
647 | { "fmpyfadd", 0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, | |
648 | { "fmpynfadd", 0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, | |
649 | { "fneg", 0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, | |
650 | { "fneg", 0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, | |
651 | { "fnegabs", 0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, | |
652 | { "fnegabs", 0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, | |
653 | { "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10}, | |
654 | { "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10}, | |
9392fb11 | 655 | { "xmpyu", 0x38004700, 0xfc00e720, "fX,fB,fT", pa11}, |
7d8fdb64 JL |
656 | { "fmpyadd", 0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11}, |
657 | { "fmpysub", 0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11}, | |
252b5132 RH |
658 | { "ftest", 0x30002420, 0xffffffff, "", pa10}, |
659 | { "fid", 0x30000000, 0xffffffff, "", pa11}, | |
660 | ||
1d16bf9c JL |
661 | /* Performance Monitor Instructions */ |
662 | ||
663 | { "pmdis", 0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT}, | |
664 | { "pmenb", 0x30000680, 0xffffffff, "", pa20, FLAG_STRICT}, | |
252b5132 RH |
665 | |
666 | /* Assist Instructions */ | |
667 | ||
7d8fdb64 JL |
668 | { "spop0", 0x10000000, 0xfc000600, "v,ON", pa10}, |
669 | { "spop1", 0x10000200, 0xfc000600, "v,oNt", pa10}, | |
670 | { "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10}, | |
671 | { "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10}, | |
252b5132 | 672 | { "copr", 0x30000000, 0xfc000000, "u,2N", pa10}, |
5d4ba527 JL |
673 | { "cldwx", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10}, |
674 | { "cldwx", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10}, | |
675 | { "clddx", 0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10}, | |
676 | { "clddx", 0x2c000000, 0xfc001e00, "ucxx(b),t", pa10}, | |
677 | { "cstwx", 0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10}, | |
678 | { "cstwx", 0x24000200, 0xfc001e00, "ucxt,x(b)", pa10}, | |
679 | { "cstdx", 0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10}, | |
680 | { "cstdx", 0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10}, | |
681 | { "cldws", 0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10}, | |
682 | { "cldws", 0x24001000, 0xfc001e00, "ucm5(b),t", pa10}, | |
683 | { "cldds", 0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10}, | |
684 | { "cldds", 0x2c001000, 0xfc001e00, "ucm5(b),t", pa10}, | |
685 | { "cstws", 0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10}, | |
686 | { "cstws", 0x24001200, 0xfc001e00, "ucmt,5(b)", pa10}, | |
687 | { "cstds", 0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10}, | |
688 | { "cstds", 0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10}, | |
90765e3a JL |
689 | { "cldw", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT}, |
690 | { "cldw", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT}, | |
691 | { "cldw", 0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT}, | |
692 | { "cldw", 0x24001000, 0xfc001e00, "ucm5(b),t", pa10, FLAG_STRICT}, | |
693 | { "cldd", 0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT}, | |
694 | { "cldd", 0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT}, | |
695 | { "cldd", 0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT}, | |
696 | { "cldd", 0x2c001000, 0xfc001e00, "ucm5(b),t", pa20, FLAG_STRICT}, | |
697 | { "cstw", 0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT}, | |
698 | { "cstw", 0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT}, | |
699 | { "cstw", 0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT}, | |
700 | { "cstw", 0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT}, | |
701 | { "cstd", 0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT}, | |
702 | { "cstd", 0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT}, | |
703 | { "cstd", 0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT}, | |
704 | { "cstd", 0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT}, | |
252b5132 RH |
705 | }; |
706 | ||
707 | #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0])) | |
708 | ||
709 | /* SKV 12/18/92. Added some denotations for various operands. */ | |
710 | ||
711 | #define PA_IMM11_AT_31 'i' | |
712 | #define PA_IMM14_AT_31 'j' | |
713 | #define PA_IMM21_AT_31 'k' | |
714 | #define PA_DISP12 'w' | |
715 | #define PA_DISP17 'W' | |
716 | ||
717 | #define N_HPPA_OPERAND_FORMATS 5 |