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1 | /* i370.h -- Header file for S/390 opcode table |
2 | Copyright 1994, 95, 98, 99, 2000 Free Software Foundation, Inc. | |
3 | PowerPC version written by Ian Lance Taylor, Cygnus Support | |
4 | Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org> | |
5 | ||
6 | This file is part of GDB, GAS, and the GNU binutils. | |
7 | ||
8 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
9 | them and/or modify them under the terms of the GNU General Public | |
10 | License as published by the Free Software Foundation; either version | |
11 | 1, or (at your option) any later version. | |
12 | ||
13 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
16 | the GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this file; see the file COPYING. If not, write to the Free | |
20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #ifndef I370_H | |
23 | #define I370_H | |
24 | ||
25 | /* The opcode table is an array of struct i370_opcode. */ | |
26 | typedef union | |
27 | { | |
28 | unsigned int i[2]; | |
29 | unsigned short s[4]; | |
30 | unsigned char b[8]; | |
31 | } i370_insn_t; | |
32 | ||
33 | struct i370_opcode | |
34 | { | |
35 | /* The opcode name. */ | |
36 | const char *name; | |
37 | ||
38 | /* the length of the instruction */ | |
39 | char len; | |
40 | ||
41 | /* The opcode itself. Those bits which will be filled in with | |
42 | operands are zeroes. */ | |
43 | i370_insn_t opcode; | |
44 | ||
45 | /* The opcode mask. This is used by the disassembler. This is a | |
46 | mask containing ones indicating those bits which must match the | |
47 | opcode field, and zeroes indicating those bits which need not | |
48 | match (and are presumably filled in by operands). */ | |
49 | i370_insn_t mask; | |
50 | ||
51 | /* One bit flags for the opcode. These are used to indicate which | |
52 | specific processors support the instructions. The defined values | |
53 | are listed below. */ | |
54 | unsigned long flags; | |
55 | ||
56 | /* An array of operand codes. Each code is an index into the | |
57 | operand table. They appear in the order which the operands must | |
58 | appear in assembly code, and are terminated by a zero. */ | |
59 | unsigned char operands[8]; | |
60 | }; | |
61 | ||
62 | /* The table itself is sorted by major opcode number, and is otherwise | |
63 | in the order in which the disassembler should consider | |
64 | instructions. */ | |
65 | extern const struct i370_opcode i370_opcodes[]; | |
66 | extern const int i370_num_opcodes; | |
67 | ||
68 | /* Values defined for the flags field of a struct i370_opcode. */ | |
69 | ||
70 | /* Opcode is defined for the original 360 architecture. */ | |
71 | #define I370_OPCODE_360 (0x01) | |
72 | ||
73 | /* Opcode is defined for the 370 architecture. */ | |
74 | #define I370_OPCODE_370 (0x02) | |
75 | ||
76 | /* Opcode is defined for the 370-XA architecture. */ | |
77 | #define I370_OPCODE_370_XA (0x04) | |
78 | ||
79 | /* Opcode is defined for the ESA/370 architecture. */ | |
80 | #define I370_OPCODE_ESA370 (0x08) | |
81 | ||
82 | /* Opcode is defined for the ESA/390 architecture. */ | |
83 | #define I370_OPCODE_ESA390 (0x10) | |
84 | ||
85 | /* Opcode is defined for the ESA/390 w/ BFP facility. */ | |
86 | #define I370_OPCODE_ESA390_BF (0x20) | |
87 | ||
88 | /* Opcode is defined for the ESA/390 w/ branch & set authority facility. */ | |
89 | #define I370_OPCODE_ESA390_BS (0x40) | |
90 | ||
91 | /* Opcode is defined for the ESA/390 w/ checksum facility. */ | |
92 | #define I370_OPCODE_ESA390_CK (0x80) | |
93 | ||
94 | /* Opcode is defined for the ESA/390 w/ compare & move extended facility. */ | |
95 | #define I370_OPCODE_ESA390_CM (0x100) | |
96 | ||
97 | /* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */ | |
98 | #define I370_OPCODE_ESA390_FX (0x200) | |
99 | ||
100 | /* Opcode is defined for the ESA/390 w/ HFP facility. */ | |
101 | #define I370_OPCODE_ESA390_HX (0x400) | |
102 | ||
103 | /* Opcode is defined for the ESA/390 w/ immediate & relative facility. */ | |
104 | #define I370_OPCODE_ESA390_IR (0x800) | |
105 | ||
106 | /* Opcode is defined for the ESA/390 w/ move-inverse facility. */ | |
107 | #define I370_OPCODE_ESA390_MI (0x1000) | |
108 | ||
109 | /* Opcode is defined for the ESA/390 w/ program-call-fast facility. */ | |
110 | #define I370_OPCODE_ESA390_PC (0x2000) | |
111 | ||
112 | /* Opcode is defined for the ESA/390 w/ perform-locked-op facility. */ | |
113 | #define I370_OPCODE_ESA390_PL (0x4000) | |
114 | ||
115 | /* Opcode is defined for the ESA/390 w/ square-root facility. */ | |
116 | #define I370_OPCODE_ESA390_QR (0x8000) | |
117 | ||
118 | /* Opcode is defined for the ESA/390 w/ resume-program facility. */ | |
119 | #define I370_OPCODE_ESA390_RP (0x10000) | |
120 | ||
121 | /* Opcode is defined for the ESA/390 w/ set-address-space-fast facility. */ | |
122 | #define I370_OPCODE_ESA390_SA (0x20000) | |
123 | ||
124 | /* Opcode is defined for the ESA/390 w/ subspace group facility. */ | |
125 | #define I370_OPCODE_ESA390_SG (0x40000) | |
126 | ||
127 | /* Opcode is defined for the ESA/390 w/ string facility. */ | |
128 | #define I370_OPCODE_ESA390_SR (0x80000) | |
129 | ||
130 | /* Opcode is defined for the ESA/390 w/ trap facility. */ | |
131 | #define I370_OPCODE_ESA390_TR (0x100000) | |
132 | ||
133 | #define I370_OPCODE_ESA390_SUPERSET (0x1fffff) | |
134 | ||
135 | \f | |
136 | /* The operands table is an array of struct i370_operand. */ | |
137 | ||
138 | struct i370_operand | |
139 | { | |
140 | /* The number of bits in the operand. */ | |
141 | int bits; | |
142 | ||
143 | /* How far the operand is left shifted in the instruction. */ | |
144 | int shift; | |
145 | ||
146 | /* Insertion function. This is used by the assembler. To insert an | |
147 | operand value into an instruction, check this field. | |
148 | ||
149 | If it is NULL, execute | |
150 | i |= (op & ((1 << o->bits) - 1)) << o->shift; | |
151 | (i is the instruction which we are filling in, o is a pointer to | |
152 | this structure, and op is the opcode value; this assumes twos | |
153 | complement arithmetic). | |
154 | ||
155 | If this field is not NULL, then simply call it with the | |
156 | instruction and the operand value. It will return the new value | |
157 | of the instruction. If the ERRMSG argument is not NULL, then if | |
158 | the operand value is illegal, *ERRMSG will be set to a warning | |
159 | string (the operand will be inserted in any case). If the | |
160 | operand value is legal, *ERRMSG will be unchanged (most operands | |
161 | can accept any value). */ | |
162 | i370_insn_t (*insert) PARAMS ((i370_insn_t instruction, long op, | |
163 | const char **errmsg)); | |
164 | ||
165 | /* Extraction function. This is used by the disassembler. To | |
166 | extract this operand type from an instruction, check this field. | |
167 | ||
168 | If it is NULL, compute | |
169 | op = ((i) >> o->shift) & ((1 << o->bits) - 1); | |
170 | if ((o->flags & I370_OPERAND_SIGNED) != 0 | |
171 | && (op & (1 << (o->bits - 1))) != 0) | |
172 | op -= 1 << o->bits; | |
173 | (i is the instruction, o is a pointer to this structure, and op | |
174 | is the result; this assumes twos complement arithmetic). | |
175 | ||
176 | If this field is not NULL, then simply call it with the | |
177 | instruction value. It will return the value of the operand. If | |
178 | the INVALID argument is not NULL, *INVALID will be set to | |
179 | non-zero if this operand type can not actually be extracted from | |
180 | this operand (i.e., the instruction does not match). If the | |
181 | operand is valid, *INVALID will not be changed. */ | |
182 | long (*extract) PARAMS ((i370_insn_t instruction, int *invalid)); | |
183 | ||
184 | /* One bit syntax flags. */ | |
185 | unsigned long flags; | |
186 | ||
187 | /* name -- handy for debugging, otherwise pointless */ | |
188 | char * name; | |
189 | }; | |
190 | ||
191 | /* Elements in the table are retrieved by indexing with values from | |
192 | the operands field of the i370_opcodes table. */ | |
193 | ||
194 | extern const struct i370_operand i370_operands[]; | |
195 | ||
196 | /* Values defined for the flags field of a struct i370_operand. */ | |
197 | ||
198 | /* This operand should be wrapped in parentheses rather than | |
199 | separated from the previous by a comma. This is used for S, RS and | |
200 | SS form instructions which want their operands to look like | |
201 | reg,displacement(basereg) */ | |
202 | #define I370_OPERAND_SBASE (0x01) | |
203 | ||
204 | /* This operand is a base register. It may or may not appear next | |
205 | to an index register, i.e. either of the two forms | |
206 | reg,displacement(basereg) | |
207 | reg,displacement(index,basereg) */ | |
208 | #define I370_OPERAND_BASE (0x02) | |
209 | ||
210 | /* This pair of operands should be wrapped in parentheses rather than | |
211 | separated from the last by a comma. This is used for the RX form | |
212 | instructions which want their operands to look like | |
213 | reg,displacement(index,basereg) */ | |
214 | #define I370_OPERAND_INDEX (0x04) | |
215 | ||
216 | /* This operand names a register. The disassembler uses this to print | |
217 | register names with a leading 'r'. */ | |
218 | #define I370_OPERAND_GPR (0x08) | |
219 | ||
220 | /* This operand names a floating point register. The disassembler | |
221 | prints these with a leading 'f'. */ | |
222 | #define I370_OPERAND_FPR (0x10) | |
223 | ||
224 | /* This operand is a displacement. */ | |
225 | #define I370_OPERAND_RELATIVE (0x20) | |
226 | ||
227 | /* This operand is a length, such as that in SS form instructions. */ | |
228 | #define I370_OPERAND_LENGTH (0x40) | |
229 | ||
230 | /* This operand is optional, and is zero if omitted. This is used for | |
231 | the optional B2 field in the shift-left, shift-right instructions. The | |
232 | assembler must count the number of operands remaining on the line, | |
233 | and the number of operands remaining for the opcode, and decide | |
234 | whether this operand is present or not. The disassembler should | |
235 | print this operand out only if it is not zero. */ | |
236 | #define I370_OPERAND_OPTIONAL (0x80) | |
237 | ||
238 | \f | |
239 | /* Define some misc macros. We keep them with the operands table | |
240 | for simplicity. The macro table is an array of struct i370_macro. */ | |
241 | ||
242 | struct i370_macro | |
243 | { | |
244 | /* The macro name. */ | |
245 | const char *name; | |
246 | ||
247 | /* The number of operands the macro takes. */ | |
248 | unsigned int operands; | |
249 | ||
250 | /* One bit flags for the opcode. These are used to indicate which | |
251 | specific processors support the instructions. The values are the | |
252 | same as those for the struct i370_opcode flags field. */ | |
253 | unsigned long flags; | |
254 | ||
255 | /* A format string to turn the macro into a normal instruction. | |
256 | Each %N in the string is replaced with operand number N (zero | |
257 | based). */ | |
258 | const char *format; | |
259 | }; | |
260 | ||
261 | extern const struct i370_macro i370_macros[]; | |
262 | extern const int i370_num_macros; | |
263 | ||
264 | ||
265 | #endif /* I370_H */ |