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2002-08-27 Elena Zannoni <ezannoni@redhat.com>
[deliverable/binutils-gdb.git] / include / opcode / i386.h
CommitLineData
252b5132 1/* opcode/i386.h -- Intel 80386 opcode table
4f1d9bd8
NC		 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001
4 Free Software Foundation, Inc.
252b5132
RH		 5
6This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
7
8This program is free software; you can redistribute it and/or modify
9it under the terms of the GNU General Public License as published by
10the Free Software Foundation; either version 2 of the License, or
11(at your option) any later version.
12
13This program is distributed in the hope that it will be useful,
14but WITHOUT ANY WARRANTY; without even the implied warranty of
15MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with this program; if not, write to the Free Software
20Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21
d0b47220
AM		 22/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
23 ix86 Unix assemblers, generate floating point instructions with
24 reversed source and destination registers in certain cases.
25 Unfortunately, gcc and possibly many other programs use this
26 reversed syntax, so we're stuck with it.
252b5132 27
7f3f1ea2
AM		 28 eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
29 `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
30 the expected st(3) = st(3) - st
252b5132
RH		 31
32 This happens with all the non-commutative arithmetic floating point
33 operations with two register operands, where the source register is
7f3f1ea2
AM		 34 %st, and destination register is %st(i). See FloatDR below.
35
36 The affected opcode map is dceX, dcfX, deeX, defX. */
252b5132 37
d0b47220 38#ifndef SYSV386_COMPAT
252b5132 39/* Set non-zero for broken, compatible instructions. Set to zero for
d0b47220 40 non-broken opcodes at your peril. gcc generates SystemV/386
252b5132 41 compatible instructions. */
d0b47220
AM		 42#define SYSV386_COMPAT 1
43#endif
44#ifndef OLDGCC_COMPAT
45/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
46 generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
47 reversed. */
48#define OLDGCC_COMPAT SYSV386_COMPAT
252b5132 49#endif
252b5132
RH		 50
51static const template i386_optab[] = {
52
53#define X None
c0d8940f
JH		 54#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
55#define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
56#define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
57#define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf|No_qSuf)
58#define q_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf)
59#define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_qSuf)
60#define bw_Suf (No_lSuf|No_sSuf|No_xSuf|No_qSuf)
61#define bl_Suf (No_wSuf|No_sSuf|No_xSuf|No_qSuf)
62#define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf)
63#define wlq_Suf (No_bSuf|No_sSuf|No_xSuf)
64#define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf)
85a33fe2 65#define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf)
c0d8940f
JH		 66#define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf)
67#define sldx_Suf (No_bSuf|No_wSuf|No_qSuf)
68#define bwl_Suf (No_sSuf|No_xSuf|No_qSuf)
69#define bwlq_Suf (No_sSuf|No_xSuf)
252b5132
RH		 70#define FP (NoSuf|IgnoreSize)
71#define l_FP (l_Suf|IgnoreSize)
252b5132
RH		 72#define x_FP (x_Suf|IgnoreSize)
73#define sl_FP (sl_Suf|IgnoreSize)
d0b47220 74#if SYSV386_COMPAT
7f3f1ea2
AM		 75/* Someone forgot that the FloatR bit reverses the operation when not
76 equal to the FloatD bit. ie. Changing only FloatD results in the
77 destination being swapped *and* the direction being reversed. */
252b5132
RH		 78#define FloatDR FloatD
79#else
80#define FloatDR (FloatD|FloatR)
81#endif
82
d0b47220 83/* Move instructions. */
252b5132 84#define MOV_AX_DISP32 0xa0
c0d8940f
JH		 85/* In the 64bit mode the short form mov immediate is redefined to have
86 64bit displacement value. */
87{ "mov", 2, 0xa0, X, CpuNo64,bwlq_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
88{ "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
89/* In the 64bit mode the short form mov immediate is redefined to have
90 64bit displacement value. */
91{ "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { EncImm, Reg8|Reg16|Reg32, 0 } },
92{ "mov", 2, 0xc6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0 } },
93{ "mov", 2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } },
e413e4e9 94/* The segment register moves accept WordReg so that a segment register
252b5132
RH		 95 can be copied to a 32 bit register, and vice versa, without using a
96 size prefix. When moving to a 32 bit register, the upper 16 bits
97 are set to an implementation defined value (on the Pentium Pro,
98 the implementation defined value is zero). */
e413e4e9
AM		 99{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|WordMem, 0 } },
100{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|WordMem, 0 } },
101{ "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg2, 0 } },
102{ "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3, 0 } },
c0d8940f
JH		 103/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit
104 mode they are 64bit.*/
105{ "mov", 2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|InvMem, 0} },
106{ "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} },
107{ "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} },
108{ "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} },
e413e4e9 109{ "mov", 2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} },
c0d8940f
JH		 110{ "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } },
111{ "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } },
252b5132 112
d0b47220 113/* Move with sign extend. */
252b5132
RH		 114/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
115 conflict with the "movs" string move instruction. */
e413e4e9
AM		 116{"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} },
117{"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} },
c0d8940f
JH		 118{"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem,Reg32, 0} },
119{"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
120{"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} },
121{"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} },
122/* Intel Syntax next 5 insns */
e413e4e9 123{"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
cd61ebfe 124{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} },
c0d8940f 125{"movsx", 2, 0x0fbe, X, Cpu64, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
cd61ebfe 126{"movsx", 2, 0x0fbf, X, Cpu64, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} },
c0d8940f 127{"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} },
252b5132 128
d0b47220 129/* Move with zero extend. */
e413e4e9
AM		 130{"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
131{"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} },
c0d8940f
JH		 132/* These instructions are not particulary usefull, since the zero extend
133 32->64 is implicit, but we can encode them. */
134{"movzbq", 2, 0x0fb6, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
135{"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} },
136/* Intel Syntax next 4 insns */
e413e4e9 137{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
cd61ebfe 138{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} },
c0d8940f
JH		 139/* These instructions are not particulary usefull, since the zero extend
140 32->64 is implicit, but we can encode them. */
141{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
cd61ebfe 142{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} },
252b5132 143
d0b47220 144/* Push instructions. */
c0d8940f
JH		 145{"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
146{"push", 1, 0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
147{"push", 1, 0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm8S, 0, 0} },
148{"push", 1, 0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} },
149{"push", 1, 0x06, X, 0|CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
150{"push", 1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
151/* In 64bit mode, the operand size is implicitly 64bit. */
5a8b245c
JH		 152{"push", 1, 0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } },
153{"push", 1, 0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } },
85a33fe2 154{"push", 1, 0x6a, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },
5a8b245c 155{"push", 1, 0x68, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} },
85a33fe2
JH		 156{"push", 1, 0x06, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
157{"push", 1, 0x0fa0, X, Cpu386|Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
c0d8940f 158
e2914f48 159{"pusha", 0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } },
252b5132 160
d0b47220 161/* Pop instructions. */
c0d8940f
JH		 162{"pop", 1, 0x58, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
163{"pop", 1, 0x8f, 0, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
252b5132 164#define POP_SEG_SHORT 0x07
c0d8940f
JH		 165{"pop", 1, 0x07, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
166{"pop", 1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
167/* In 64bit mode, the operand size is implicitly 64bit. */
5a8b245c
JH		 168{"pop", 1, 0x58, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } },
169{"pop", 1, 0x8f, 0, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } },
85a33fe2
JH		 170{"pop", 1, 0x07, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
171{"pop", 1, 0x0fa1, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
c0d8940f
JH		 172
173{"popa", 0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } },
252b5132 174
d0b47220 175/* Exchange instructions.
c0d8940f
JH		 176 xchg commutes: we allow both operand orders.
177
178 In the 64bit code, xchg eax, eax is reused for new nop instruction.
179 */
85a33fe2
JH		 180{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { WordReg, Acc, 0 } },
181{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { Acc, WordReg, 0 } },
c0d8940f
JH		 182{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
183{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } },
252b5132 184
d0b47220 185/* In/out from ports. */
85a33fe2
JH		 186{"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } },
187{"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } },
188{"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } },
189{"in", 1, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } },
190{"out", 2, 0xe6, X, 0, bwl_Suf|W, { Acc, Imm8, 0 } },
191{"out", 2, 0xee, X, 0, bwl_Suf|W, { Acc, InOutPortReg, 0 } },
192{"out", 1, 0xe6, X, 0, bwl_Suf|W, { Imm8, 0, 0 } },
193{"out", 1, 0xee, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } },
252b5132 194
d0b47220 195/* Load effective address. */
c0d8940f 196{"lea", 2, 0x8d, X, 0, wlq_Suf|Modrm, { WordMem, WordReg, 0 } },
252b5132 197
d0b47220 198/* Load segment registers from memory. */
c0d8940f
JH		 199{"lds", 2, 0xc5, X, CpuNo64, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
200{"les", 2, 0xc4, X, CpuNo64, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
201{"lfs", 2, 0x0fb4, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
202{"lgs", 2, 0x0fb5, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
203{"lss", 2, 0x0fb2, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} },
252b5132 204
d0b47220 205/* Flags register instructions. */
e413e4e9
AM		 206{"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} },
207{"cld", 0, 0xfc, X, 0, NoSuf, { 0, 0, 0} },
208{"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} },
209{"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} },
210{"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} },
c0d8940f
JH		 211{"lahf", 0, 0x9f, X, CpuNo64,NoSuf, { 0, 0, 0} },
212{"sahf", 0, 0x9e, X, CpuNo64,NoSuf, { 0, 0, 0} },
6f8c0c4c 213{"pushf", 0, 0x9c, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} },
85a33fe2 214{"pushf", 0, 0x9c, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
6f8c0c4c 215{"popf", 0, 0x9d, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} },
85a33fe2 216{"popf", 0, 0x9d, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
e413e4e9
AM		 217{"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} },
218{"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} },
219{"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} },
252b5132 220
d0b47220 221/* Arithmetic. */
c0d8940f
JH		 222{"add", 2, 0x00, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
223{"add", 2, 0x83, 0, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
224{"add", 2, 0x04, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
225{"add", 2, 0x80, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
226
227{"inc", 1, 0x40, X, CpuNo64,wl_Suf|ShortForm, { WordReg, 0, 0} },
228{"inc", 1, 0xfe, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
229
230{"sub", 2, 0x28, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
231{"sub", 2, 0x83, 5, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
232{"sub", 2, 0x2c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
233{"sub", 2, 0x80, 5, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
234
235{"dec", 1, 0x48, X, CpuNo64, wl_Suf|ShortForm, { WordReg, 0, 0} },
236{"dec", 1, 0xfe, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
237
238{"sbb", 2, 0x18, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
239{"sbb", 2, 0x83, 3, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
240{"sbb", 2, 0x1c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
241{"sbb", 2, 0x80, 3, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
242
243{"cmp", 2, 0x38, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
244{"cmp", 2, 0x83, 7, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
245{"cmp", 2, 0x3c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
246{"cmp", 2, 0x80, 7, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
247
248{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} },
249{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} },
250{"test", 2, 0xa8, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
251{"test", 2, 0xf6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
252
253{"and", 2, 0x20, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
254{"and", 2, 0x83, 4, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
255{"and", 2, 0x24, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
256{"and", 2, 0x80, 4, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
257
258{"or", 2, 0x08, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
259{"or", 2, 0x83, 1, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
260{"or", 2, 0x0c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
261{"or", 2, 0x80, 1, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
262
263{"xor", 2, 0x30, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
264{"xor", 2, 0x83, 6, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
265{"xor", 2, 0x34, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
266{"xor", 2, 0x80, 6, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
e413e4e9
AM		 267
268/* clr with 1 operand is really xor with 2 operands. */
c0d8940f 269{"clr", 1, 0x30, X, 0, bwlq_Suf|W|Modrm|regKludge, { Reg, 0, 0 } },
e413e4e9 270
c0d8940f
JH		 271{"adc", 2, 0x10, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
272{"adc", 2, 0x83, 2, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
273{"adc", 2, 0x14, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} },
274{"adc", 2, 0x80, 2, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} },
e413e4e9 275
c0d8940f
JH		 276{"neg", 1, 0xf6, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
277{"not", 1, 0xf6, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
e413e4e9
AM		 278
279{"aaa", 0, 0x37, X, 0, NoSuf, { 0, 0, 0} },
280{"aas", 0, 0x3f, X, 0, NoSuf, { 0, 0, 0} },
281{"daa", 0, 0x27, X, 0, NoSuf, { 0, 0, 0} },
282{"das", 0, 0x2f, X, 0, NoSuf, { 0, 0, 0} },
283{"aad", 0, 0xd50a, X, 0, NoSuf, { 0, 0, 0} },
284{"aad", 1, 0xd5, X, 0, NoSuf, { Imm8S, 0, 0} },
285{"aam", 0, 0xd40a, X, 0, NoSuf, { 0, 0, 0} },
286{"aam", 1, 0xd4, X, 0, NoSuf, { Imm8S, 0, 0} },
252b5132 287
d0b47220
AM		 288/* Conversion insns. */
289/* Intel naming */
e413e4e9 290{"cbw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} },
c0d8940f 291{"cdqe", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} },
e413e4e9
AM		 292{"cwde", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} },
293{"cwd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} },
294{"cdq", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} },
c0d8940f 295{"cqo", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} },
d0b47220 296/* AT&T naming */
e413e4e9 297{"cbtw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} },
c0d8940f 298{"cltq", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} },
e413e4e9
AM		 299{"cwtl", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} },
300{"cwtd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} },
301{"cltd", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} },
c0d8940f 302{"cqto", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} },
252b5132
RH		 303
304/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
305 expanding 64-bit multiplies, and *cannot* be selected to accomplish
306 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
307 These multiplies can only be selected with single operand forms. */
c0d8940f
JH		 308{"mul", 1, 0xf6, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
309{"imul", 1, 0xf6, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
310{"imul", 2, 0x0faf, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
311{"imul", 3, 0x6b, X, Cpu186, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} },
312{"imul", 3, 0x69, X, Cpu186, wlq_Suf|Modrm, { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} },
252b5132
RH		 313/* imul with 2 operands mimics imul with 3 by putting the register in
314 both i.rm.reg & i.rm.regmem fields. regKludge enables this
315 transformation. */
c0d8940f
JH		 316{"imul", 2, 0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
317{"imul", 2, 0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} },
318
319{"div", 1, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
320{"div", 2, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
321{"idiv", 1, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
322{"idiv", 2, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
323
324{"rol", 2, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
325{"rol", 2, 0xc0, 0, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
326{"rol", 2, 0xd2, 0, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
327{"rol", 1, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
328
329{"ror", 2, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
330{"ror", 2, 0xc0, 1, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
331{"ror", 2, 0xd2, 1, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
332{"ror", 1, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
333
334{"rcl", 2, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
335{"rcl", 2, 0xc0, 2, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
336{"rcl", 2, 0xd2, 2, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
337{"rcl", 1, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
338
339{"rcr", 2, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
340{"rcr", 2, 0xc0, 3, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
341{"rcr", 2, 0xd2, 3, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
342{"rcr", 1, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
343
344{"sal", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
345{"sal", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
346{"sal", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
347{"sal", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
348
349{"shl", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
350{"shl", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
351{"shl", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
352{"shl", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
353
354{"shr", 2, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
355{"shr", 2, 0xc0, 5, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
356{"shr", 2, 0xd2, 5, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
357{"shr", 1, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
358
359{"sar", 2, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
360{"sar", 2, 0xc0, 7, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
361{"sar", 2, 0xd2, 7, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
362{"sar", 1, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
363
364{"shld", 3, 0x0fa4, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
365{"shld", 3, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
366{"shld", 2, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
367
368{"shrd", 3, 0x0fac, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
369{"shrd", 3, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
370{"shrd", 2, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
252b5132 371
d0b47220 372/* Control transfer instructions. */
c0d8940f 373{"call", 1, 0xe8, X, 0, wlq_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },
85a33fe2
JH		 374{"call", 1, 0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} },
375{"call", 1, 0xff, 2, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64,{ WordReg|WordMem|JumpAbsolute, 0, 0} },
252b5132 376/* Intel Syntax */
c0d8940f 377{"call", 2, 0x9a, X, CpuNo64,wlq_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
3138f287 378/* Intel Syntax */
e413e4e9 379{"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} },
c0d8940f
JH		 380{"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
381{"lcall", 1, 0xff, 3, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} },
382{"lcall", 1, 0xff, 3, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64,{ WordMem|JumpAbsolute, 0, 0} },
252b5132
RH		 383
384#define JUMP_PC_RELATIVE 0xeb
e413e4e9 385{"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp, 0, 0} },
85a33fe2
JH		 386{"jmp", 1, 0xff, 4, CpuNo64, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
387{"jmp", 1, 0xff, 4, Cpu64, wq_Suf|Modrm|NoRex64, { WordReg|WordMem|JumpAbsolute, 0, 0} },
252b5132 388/* Intel Syntax */
c0d8940f 389{"jmp", 2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
3138f287 390/* Intel Syntax */
e413e4e9 391{"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem, 0, 0} },
c0d8940f
JH		 392{"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
393{"ljmp", 1, 0xff, 5, CpuNo64, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} },
394{"ljmp", 1, 0xff, 5, Cpu64, q_Suf|Modrm|NoRex64, { WordMem|JumpAbsolute, 0, 0} },
252b5132 395
e2914f48
JH		 396{"ret", 0, 0xc3, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} },
397{"ret", 1, 0xc2, X, CpuNo64,wlq_Suf|DefaultSize, { Imm16, 0, 0} },
398{"ret", 0, 0xc3, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
399{"ret", 1, 0xc2, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} },
c0d8940f
JH		 400{"lret", 0, 0xcb, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} },
401{"lret", 1, 0xca, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} },
402{"enter", 2, 0xc8, X, Cpu186, wlq_Suf|DefaultSize, { Imm16, Imm8, 0} },
403{"leave", 0, 0xc9, X, Cpu186, wlq_Suf|DefaultSize, { 0, 0, 0} },
252b5132 404
d0b47220 405/* Conditional jumps. */
e413e4e9
AM		 406{"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} },
407{"jno", 1, 0x71, X, 0, NoSuf|Jump, { Disp, 0, 0} },
408{"jb", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
409{"jc", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
410{"jnae", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
411{"jnb", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
412{"jnc", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
413{"jae", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
414{"je", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} },
415{"jz", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} },
416{"jne", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} },
417{"jnz", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} },
418{"jbe", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} },
419{"jna", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} },
420{"jnbe", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} },
421{"ja", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} },
422{"js", 1, 0x78, X, 0, NoSuf|Jump, { Disp, 0, 0} },
423{"jns", 1, 0x79, X, 0, NoSuf|Jump, { Disp, 0, 0} },
424{"jp", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} },
425{"jpe", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} },
426{"jnp", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} },
427{"jpo", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} },
428{"jl", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} },
429{"jnge", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} },
430{"jnl", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} },
431{"jge", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} },
432{"jle", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} },
433{"jng", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} },
434{"jnle", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} },
435{"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} },
252b5132
RH		 436
437/* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
85a33fe2
JH		 438{"jcxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} },
439{"jecxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} },
440{"jecxz", 1, 0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} },
441{"jrcxz", 1, 0xe3, X, Cpu64, NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} },
252b5132
RH		 442
443/* The loop instructions also use the address size prefix to select
444 %cx rather than %ecx for the loop count, so the `w' form of these
445 instructions emit an address size prefix rather than a data size
446 prefix. */
85a33fe2
JH		 447{"loop", 1, 0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
448{"loop", 1, 0xe2, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
449{"loopz", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
450{"loopz", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
451{"loope", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
452{"loope", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
453{"loopnz", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
454{"loopnz", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
455{"loopne", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
456{"loopne", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
252b5132 457
d0b47220 458/* Set byte on flag instructions. */
e413e4e9
AM		 459{"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
460{"setno", 1, 0x0f91, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
461{"setb", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
462{"setc", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
463{"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
464{"setnb", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
465{"setnc", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
466{"setae", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
467{"sete", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
468{"setz", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
469{"setne", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
470{"setnz", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
471{"setbe", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
472{"setna", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
473{"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
474{"seta", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
475{"sets", 1, 0x0f98, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
476{"setns", 1, 0x0f99, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
477{"setp", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
478{"setpe", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
479{"setnp", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
480{"setpo", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
481{"setl", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
482{"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
483{"setnl", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
484{"setge", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
485{"setle", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
486{"setng", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
487{"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
488{"setg", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
252b5132 489
d0b47220 490/* String manipulation. */
c0d8940f
JH		 491{"cmps", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
492{"cmps", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
493{"scmp", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
494{"scmp", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
85a33fe2
JH		 495{"ins", 0, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} },
496{"ins", 2, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} },
497{"outs", 0, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} },
498{"outs", 2, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { AnyMem, InOutPortReg, 0} },
c0d8940f
JH		 499{"lods", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
500{"lods", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} },
501{"lods", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} },
502{"slod", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
503{"slod", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} },
504{"slod", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} },
505{"movs", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
506{"movs", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
507{"smov", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
508{"smov", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
509{"scas", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
510{"scas", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
511{"scas", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
512{"ssca", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
513{"ssca", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
514{"ssca", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
515{"stos", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
516{"stos", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
517{"stos", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
518{"ssto", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} },
519{"ssto", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
520{"ssto", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
e413e4e9
AM		 521{"xlat", 0, 0xd7, X, 0, b_Suf|IsString, { 0, 0, 0} },
522{"xlat", 1, 0xd7, X, 0, b_Suf|IsString, { AnyMem, 0, 0} },
252b5132 523
d0b47220 524/* Bit manipulation. */
c0d8940f
JH		 525{"bsf", 2, 0x0fbc, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
526{"bsr", 2, 0x0fbd, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
527{"bt", 2, 0x0fa3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
528{"bt", 2, 0x0fba, 4, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
529{"btc", 2, 0x0fbb, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
530{"btc", 2, 0x0fba, 7, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
531{"btr", 2, 0x0fb3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
532{"btr", 2, 0x0fba, 6, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
533{"bts", 2, 0x0fab, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
534{"bts", 2, 0x0fba, 5, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
252b5132 535
d0b47220 536/* Interrupts & op. sys insns. */
252b5132 537/* See gas/config/tc-i386.c for conversion of 'int $3' into the special
d0b47220 538 int 3 insn. */
252b5132
RH		 539#define INT_OPCODE 0xcd
540#define INT3_OPCODE 0xcc
e413e4e9
AM		 541{"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} },
542{"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} },
543{"into", 0, 0xce, X, 0, NoSuf, { 0, 0, 0} },
c0d8940f 544{"iret", 0, 0xcf, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} },
d0b47220 545/* i386sl, i486sl, later 486, and Pentium. */
e413e4e9 546{"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} },
252b5132 547
c0d8940f 548{"bound", 2, 0x62, X, Cpu186, wlq_Suf|Modrm, { WordReg, WordMem, 0} },
252b5132 549
e413e4e9 550{"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} },
d0b47220 551/* nop is actually 'xchgl %eax, %eax'. */
e413e4e9 552{"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} },
252b5132 553
d0b47220 554/* Protection control. */
e413e4e9 555{"arpl", 2, 0x63, X, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
c0d8940f
JH		 556{"lar", 2, 0x0f02, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
557{"lgdt", 1, 0x0f01, 2, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} },
558{"lidt", 1, 0x0f01, 3, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} },
e413e4e9
AM		 559{"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
560{"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
c0d8940f 561{"lsl", 2, 0x0f03, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
e413e4e9
AM		 562{"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
563
c0d8940f
JH		 564{"sgdt", 1, 0x0f01, 0, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} },
565{"sidt", 1, 0x0f01, 1, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} },
e5470cdc
AM		 566{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} },
567{"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
568{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} },
569{"smsw", 1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
570{"str", 1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} },
571{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
e413e4e9
AM		 572
573{"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
574{"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
252b5132 575
d0b47220 576/* Floating point instructions. */
252b5132
RH		 577
578/* load */
e413e4e9 579{"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
f16b83df 580{"fld", 1, 0xd9, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9 581{"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
252b5132 582/* Intel Syntax */
e413e4e9 583{"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} },
f9e0cf0b 584{"fild", 1, 0xdf, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 585/* Intel Syntax */
e413e4e9
AM		 586{"fildd", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
587{"fildq", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
588{"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
589{"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
590{"fbld", 1, 0xdf, 4, 0, FP|Modrm, { LLongMem, 0, 0} },
252b5132
RH		 591
592/* store (no pop) */
e413e4e9 593{"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
f16b83df 594{"fst", 1, 0xd9, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9 595{"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
f16b83df 596{"fist", 1, 0xdf, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132
RH		 597
598/* store (with pop) */
e413e4e9 599{"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
f16b83df 600{"fstp", 1, 0xd9, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9 601{"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
252b5132 602/* Intel Syntax */
e413e4e9
AM		 603{"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} },
604{"fistp", 1, 0xdf, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 605/* Intel Syntax */
e413e4e9
AM		 606{"fistpd", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
607{"fistpq", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
608{"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
609{"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
610{"fbstp", 1, 0xdf, 6, 0, FP|Modrm, { LLongMem, 0, 0} },
252b5132
RH		 611
612/* exchange %st<n> with %st0 */
e413e4e9
AM		 613{"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
614/* alias for fxch %st(1) */
615{"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 616
617/* comparison (without pop) */
e413e4e9
AM		 618{"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
619/* alias for fcom %st(1) */
620{"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} },
f16b83df 621{"fcom", 1, 0xd8, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9
AM		 622{"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
623{"ficom", 1, 0xde, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132
RH		 624
625/* comparison (with pop) */
e413e4e9
AM		 626{"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
627/* alias for fcomp %st(1) */
628{"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} },
f16b83df 629{"fcomp", 1, 0xd8, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9
AM		 630{"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
631{"ficomp", 1, 0xde, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
632{"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 633
634/* unordered comparison (with pop) */
e413e4e9
AM		 635{"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} },
636/* alias for fucom %st(1) */
637{"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} },
638{"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} },
639/* alias for fucomp %st(1) */
640{"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} },
641{"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} },
252b5132 642
e413e4e9
AM		 643{"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} },
644{"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 645
646/* load constants into %st0 */
e413e4e9
AM		 647{"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} },
648{"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} },
649{"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} },
650{"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} },
651{"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} },
652{"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} },
653{"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 654
655/* arithmetic */
656
657/* add */
e413e4e9
AM		 658{"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
659/* alias for fadd %st(i), %st */
660{"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 661#if SYSV386_COMPAT
e413e4e9
AM		 662/* alias for faddp */
663{"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 664#endif
f16b83df
JH		 665{"fadd", 1, 0xd8, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
666{"fiadd", 1, 0xde, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 667
e413e4e9
AM		 668{"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
669{"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
670/* alias for faddp %st, %st(1) */
671{"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} },
672{"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
252b5132
RH		 673
674/* subtract */
e413e4e9
AM		 675{"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
676{"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 677#if SYSV386_COMPAT
e413e4e9
AM		 678/* alias for fsubp */
679{"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 680#endif
f16b83df 681{"fsub", 1, 0xd8, 4, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9 682{"fisub", 1, 0xde, 4, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 683
d0b47220 684#if SYSV386_COMPAT
e413e4e9
AM		 685{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
686{"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
687{"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },
d0b47220 688#if OLDGCC_COMPAT
e413e4e9 689{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 690#endif
252b5132 691#else
e413e4e9
AM		 692{"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
693{"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
694{"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 695#endif
696
697/* subtract reverse */
e413e4e9
AM		 698{"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
699{"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 700#if SYSV386_COMPAT
e413e4e9
AM		 701/* alias for fsubrp */
702{"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 703#endif
f16b83df 704{"fsubr", 1, 0xd8, 5, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9 705{"fisubr", 1, 0xde, 5, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 706
d0b47220 707#if SYSV386_COMPAT
e413e4e9
AM		 708{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
709{"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
710{"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },
d0b47220 711#if OLDGCC_COMPAT
e413e4e9 712{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 713#endif
252b5132 714#else
e413e4e9
AM		 715{"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
716{"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
717{"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 718#endif
719
720/* multiply */
e413e4e9
AM		 721{"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
722{"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 723#if SYSV386_COMPAT
e413e4e9
AM		 724/* alias for fmulp */
725{"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 726#endif
f16b83df
JH		 727{"fmul", 1, 0xd8, 1, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
728{"fimul", 1, 0xde, 1, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 729
e413e4e9
AM		 730{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
731{"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
732{"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} },
733{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
252b5132
RH		 734
735/* divide */
e413e4e9
AM		 736{"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
737{"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 738#if SYSV386_COMPAT
e413e4e9
AM		 739/* alias for fdivp */
740{"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 741#endif
f16b83df
JH		 742{"fdiv", 1, 0xd8, 6, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
743{"fidiv", 1, 0xde, 6, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 744
d0b47220 745#if SYSV386_COMPAT
e413e4e9
AM		 746{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
747{"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
748{"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },
d0b47220 749#if OLDGCC_COMPAT
e413e4e9 750{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 751#endif
252b5132 752#else
e413e4e9
AM		 753{"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
754{"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
755{"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 756#endif
757
758/* divide reverse */
e413e4e9
AM		 759{"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
760{"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 761#if SYSV386_COMPAT
e413e4e9
AM		 762/* alias for fdivrp */
763{"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 764#endif
f16b83df 765{"fdivr", 1, 0xd8, 7, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9 766{"fidivr", 1, 0xde, 7, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 767
d0b47220 768#if SYSV386_COMPAT
e413e4e9
AM		 769{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
770{"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
771{"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },
d0b47220 772#if OLDGCC_COMPAT
e413e4e9 773{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 774#endif
252b5132 775#else
e413e4e9
AM		 776{"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
777{"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
778{"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 779#endif
780
e413e4e9
AM		 781{"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} },
782{"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} },
783{"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} },
784{"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} },
785{"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} },
786{"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} },
787{"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} },
788{"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} },
789{"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} },
790{"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} },
791{"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} },
792{"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} },
793{"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} },
794{"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} },
795{"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} },
796{"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} },
797{"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} },
798{"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 799
800/* processor control */
e413e4e9
AM		 801{"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} },
802{"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} },
803{"fldcw", 1, 0xd9, 5, 0, FP|Modrm, { ShortMem, 0, 0} },
804{"fnstcw", 1, 0xd9, 7, 0, FP|Modrm, { ShortMem, 0, 0} },
805{"fstcw", 1, 0xd9, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} },
806{"fnstsw", 1, 0xdfe0, X, 0, FP, { Acc, 0, 0} },
807{"fnstsw", 1, 0xdd, 7, 0, FP|Modrm, { ShortMem, 0, 0} },
808{"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} },
809{"fstsw", 1, 0xdfe0, X, 0, FP|FWait, { Acc, 0, 0} },
810{"fstsw", 1, 0xdd, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} },
811{"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} },
812{"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} },
813{"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} },
d0b47220 814/* Short forms of fldenv, fstenv use data size prefix. */
e413e4e9
AM		 815{"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
816{"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
817{"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
818{"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
819{"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
820{"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
821
822{"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
252b5132 823/* P6:free st(i), pop st */
e413e4e9
AM		 824{"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
825{"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} },
252b5132 826#define FWAIT_OPCODE 0x9b
e413e4e9 827{"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} },
252b5132 828
d0b47220
AM		 829/* Opcode prefixes; we allow them as separate insns too. */
830
252b5132 831#define ADDR_PREFIX_OPCODE 0x67
e413e4e9
AM		 832{"addr16", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
833{"addr32", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
834{"aword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
835{"adword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
252b5132 836#define DATA_PREFIX_OPCODE 0x66
e413e4e9
AM		 837{"data16", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
838{"data32", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
839{"word", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
840{"dword", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
252b5132 841#define LOCK_PREFIX_OPCODE 0xf0
e413e4e9
AM		 842{"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
843{"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 844#define CS_PREFIX_OPCODE 0x2e
e413e4e9 845{"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 846#define DS_PREFIX_OPCODE 0x3e
e413e4e9 847{"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 848#define ES_PREFIX_OPCODE 0x26
e413e4e9 849{"es", 0, 0x26, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 850#define FS_PREFIX_OPCODE 0x64
e413e4e9 851{"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 852#define GS_PREFIX_OPCODE 0x65
e413e4e9 853{"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 854#define SS_PREFIX_OPCODE 0x36
e413e4e9 855{"ss", 0, 0x36, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132
RH		 856#define REPNE_PREFIX_OPCODE 0xf2
857#define REPE_PREFIX_OPCODE 0xf3
e413e4e9
AM		 858{"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
859{"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
860{"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
861{"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
862{"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
c0d8940f
JH		 863{"rex", 0, 0x40, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
864{"rexz", 0, 0x41, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
865{"rexy", 0, 0x42, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
866{"rexyz", 0, 0x43, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
867{"rexx", 0, 0x44, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
868{"rexxz", 0, 0x45, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
869{"rexxy", 0, 0x46, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
870{"rexxyz", 0, 0x47, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
871{"rex64", 0, 0x48, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
872{"rex64z", 0, 0x49, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
873{"rex64y", 0, 0x4a, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
874{"rex64yz",0, 0x4b, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
875{"rex64x", 0, 0x4c, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
876{"rex64xz",0, 0x4d, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
877{"rex64xy",0, 0x4e, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
878{"rex64xyz",0, 0x4f, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 879
d0b47220 880/* 486 extensions. */
252b5132 881
c0d8940f
JH		 882{"bswap", 1, 0x0fc8, X, Cpu486, lq_Suf|ShortForm, { Reg32|Reg64, 0, 0 } },
883{"xadd", 2, 0x0fc0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
884{"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
e413e4e9
AM		 885{"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} },
886{"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} },
887{"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm, { AnyMem, 0, 0} },
252b5132 888
d0b47220 889/* 586 and late 486 extensions. */
e413e4e9 890{"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} },
252b5132 891
d0b47220 892/* Pentium extensions. */
e413e4e9
AM		 893{"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} },
894{"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} },
895{"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} },
896{"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm, { LLongMem, 0, 0} },
252b5132 897
558b0a60 898/* Pentium II/Pentium Pro extensions. */
c0d8940f
JH		 899{"sysenter",0, 0x0f34, X, Cpu686|CpuNo64, NoSuf, { 0, 0, 0} },
900{"sysexit", 0, 0x0f35, X, Cpu686|CpuNo64, NoSuf, { 0, 0, 0} },
558b0a60
AM		 901{"fxsave", 1, 0x0fae, 0, Cpu686, FP|Modrm, { LLongMem, 0, 0} },
902{"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm, { LLongMem, 0, 0} },
e413e4e9
AM		 903{"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} },
904/* official undefined instr. */
905{"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} },
906/* alias for ud2 */
907{"ud2a", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} },
908/* 2nd. official undefined instr. */
909{"ud2b", 0, 0x0fb9, X, Cpu686, NoSuf, { 0, 0, 0} },
910
c0d8940f
JH		 911{"cmovo", 2, 0x0f40, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
912{"cmovno", 2, 0x0f41, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
913{"cmovb", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
914{"cmovc", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
915{"cmovnae", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
916{"cmovae", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
917{"cmovnc", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
918{"cmovnb", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
919{"cmove", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
920{"cmovz", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
921{"cmovne", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
922{"cmovnz", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
923{"cmovbe", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
924{"cmovna", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
925{"cmova", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
926{"cmovnbe", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
927{"cmovs", 2, 0x0f48, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
928{"cmovns", 2, 0x0f49, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
929{"cmovp", 2, 0x0f4a, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
930{"cmovnp", 2, 0x0f4b, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
931{"cmovl", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
932{"cmovnge", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
933{"cmovge", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
934{"cmovnl", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
935{"cmovle", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
936{"cmovng", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
937{"cmovg", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
938{"cmovnle", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
e413e4e9
AM		 939
940{"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
941{"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
942{"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
943{"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
944{"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
945{"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
946{"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
947{"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
948{"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
949{"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
950{"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
951{"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
952
953{"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
954{"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
955{"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
956{"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
957{"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
958{"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
959{"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
960{"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
961{"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
962{"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
963{"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
964{"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
965{"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
966{"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
252b5132 967
6f8c0c4c
JH		 968/* Pentium4 extensions. */
969
079966a8
AM		 970{"movnti", 2, 0x0fc3, X, CpuP4, FP|Modrm, { WordReg, WordMem, 0 } },
971{"clflush", 1, 0x0fae, 7, CpuP4, FP|Modrm, { ByteMem, 0, 0 } },
972{"lfence", 0, 0x0fae, 0xe8, CpuP4, FP|ImmExt, { 0, 0, 0 } },
973{"mfence", 0, 0x0fae, 0xf0, CpuP4, FP|ImmExt, { 0, 0, 0 } },
974{"pause", 0, 0xf390, X, CpuP4, FP, { 0, 0, 0 } },
6f8c0c4c
JH		 975
976/* MMX/SSE2 instructions. */
252b5132 977
e413e4e9
AM		 978{"emms", 0, 0x0f77, X, CpuMMX, FP, { 0, 0, 0 } },
979{"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } },
980{"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } },
6f8c0c4c
JH		 981{"movd", 2, 0x660f6e,X,CpuSSE2,FP|Modrm, { Reg32|LLongMem, RegXMM, 0 } },
982{"movd", 2, 0x660f7e,X,CpuSSE2,FP|Modrm, { RegXMM, Reg32|LLongMem, 0 } },
c0d8940f 983/* Real MMX instructions. */
85a33fe2
JH		 984{"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg64|LLongMem, RegMMX, 0 } },
985{"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg64|LLongMem, 0 } },
986{"movd", 2, 0x660f6e,X,CpuSSE2,FP|Modrm, { Reg64|LLongMem, RegXMM, 0 } },
987{"movd", 2, 0x660f7e,X,CpuSSE2,FP|Modrm, { RegXMM, Reg64|LLongMem, 0 } },
988/* In the 64bit mode the short form mov immediate is redefined to have
989 64bit displacement value. */
e413e4e9
AM		 990{"movq", 2, 0x0f6f, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
991{"movq", 2, 0x0f7f, X, CpuMMX, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } },
6f8c0c4c
JH		 992{"movq", 2, 0xf30f7e,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
993{"movq", 2, 0x660fd6,X,CpuSSE2,FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
c0d8940f
JH		 994{"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } },
995{"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } },
996{"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } },
997/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit
998 mode they are 64bit.*/
999{"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} },
1000{"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} },
e413e4e9 1001{"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1002{"packssdw", 2, 0x660f6b,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1003{"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1004{"packsswb", 2, 0x660f63,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1005{"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1006{"packuswb", 2, 0x660f67,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1007{"paddb", 2, 0x0ffc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1008{"paddb", 2, 0x660ffc,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1009{"paddw", 2, 0x0ffd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1010{"paddw", 2, 0x660ffd,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1011{"paddd", 2, 0x0ffe, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1012{"paddd", 2, 0x660ffe,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
87890af0
AM		 1013{"paddq", 2, 0x0fd4, X, CpuMMX, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1014{"paddq", 2, 0x660fd4,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1015{"paddsb", 2, 0x0fec, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1016{"paddsb", 2, 0x660fec,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1017{"paddsw", 2, 0x0fed, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1018{"paddsw", 2, 0x660fed,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1019{"paddusb", 2, 0x0fdc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1020{"paddusb", 2, 0x660fdc,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1021{"paddusw", 2, 0x0fdd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1022{"paddusw", 2, 0x660fdd,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1023{"pand", 2, 0x0fdb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1024{"pand", 2, 0x660fdb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1025{"pandn", 2, 0x0fdf, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1026{"pandn", 2, 0x660fdf,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1027{"pcmpeqb", 2, 0x0f74, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1028{"pcmpeqb", 2, 0x660f74,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1029{"pcmpeqw", 2, 0x0f75, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1030{"pcmpeqw", 2, 0x660f75,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1031{"pcmpeqd", 2, 0x0f76, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1032{"pcmpeqd", 2, 0x660f76,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1033{"pcmpgtb", 2, 0x0f64, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1034{"pcmpgtb", 2, 0x660f64,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1035{"pcmpgtw", 2, 0x0f65, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1036{"pcmpgtw", 2, 0x660f65,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1037{"pcmpgtd", 2, 0x0f66, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1038{"pcmpgtd", 2, 0x660f66,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1039{"pmaddwd", 2, 0x0ff5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1040{"pmaddwd", 2, 0x660ff5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1041{"pmulhw", 2, 0x0fe5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1042{"pmulhw", 2, 0x660fe5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1043{"pmullw", 2, 0x0fd5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1044{"pmullw", 2, 0x660fd5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1045{"por", 2, 0x0feb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1046{"por", 2, 0x660feb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1047{"psllw", 2, 0x0ff1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1048{"psllw", 2, 0x660ff1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1049{"psllw", 2, 0x0f71, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
6f8c0c4c 1050{"psllw", 2, 0x660f71,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
e413e4e9 1051{"pslld", 2, 0x0ff2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1052{"pslld", 2, 0x660ff2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1053{"pslld", 2, 0x0f72, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
6f8c0c4c 1054{"pslld", 2, 0x660f72,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
e413e4e9 1055{"psllq", 2, 0x0ff3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1056{"psllq", 2, 0x660ff3,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1057{"psllq", 2, 0x0f73, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
6f8c0c4c 1058{"psllq", 2, 0x660f73,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
e413e4e9 1059{"psraw", 2, 0x0fe1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1060{"psraw", 2, 0x660fe1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1061{"psraw", 2, 0x0f71, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
6f8c0c4c 1062{"psraw", 2, 0x660f71,4,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
e413e4e9 1063{"psrad", 2, 0x0fe2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1064{"psrad", 2, 0x660fe2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1065{"psrad", 2, 0x0f72, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
6f8c0c4c 1066{"psrad", 2, 0x660f72,4,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
e413e4e9 1067{"psrlw", 2, 0x0fd1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1068{"psrlw", 2, 0x660fd1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1069{"psrlw", 2, 0x0f71, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
6f8c0c4c 1070{"psrlw", 2, 0x660f71,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
e413e4e9 1071{"psrld", 2, 0x0fd2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1072{"psrld", 2, 0x660fd2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1073{"psrld", 2, 0x0f72, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
6f8c0c4c 1074{"psrld", 2, 0x660f72,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
e413e4e9 1075{"psrlq", 2, 0x0fd3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1076{"psrlq", 2, 0x660fd3,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1077{"psrlq", 2, 0x0f73, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
6f8c0c4c 1078{"psrlq", 2, 0x660f73,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } },
e413e4e9 1079{"psubb", 2, 0x0ff8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1080{"psubb", 2, 0x660ff8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1081{"psubw", 2, 0x0ff9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1082{"psubw", 2, 0x660ff9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1083{"psubd", 2, 0x0ffa, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1084{"psubd", 2, 0x660ffa,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
87890af0
AM		 1085{"psubq", 2, 0x0ffb, X, CpuMMX, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1086{"psubq", 2, 0x660ffb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1087{"psubsb", 2, 0x0fe8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1088{"psubsb", 2, 0x660fe8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1089{"psubsw", 2, 0x0fe9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1090{"psubsw", 2, 0x660fe9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1091{"psubusb", 2, 0x0fd8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1092{"psubusb", 2, 0x660fd8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1093{"psubusw", 2, 0x0fd9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1094{"psubusw", 2, 0x660fd9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1095{"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1096{"punpckhbw",2, 0x660f68,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1097{"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1098{"punpckhwd",2, 0x660f69,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1099{"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1100{"punpckhdq",2, 0x660f6a,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1101{"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1102{"punpcklbw",2, 0x660f60,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1103{"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1104{"punpcklwd",2, 0x660f61,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1105{"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1106{"punpckldq",2, 0x660f62,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1107{"pxor", 2, 0x0fef, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
6f8c0c4c 1108{"pxor", 2, 0x660fef,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
c608c12e 1109
d0b47220 1110/* PIII Katmai New Instructions / SIMD instructions. */
c608c12e 1111
e413e4e9
AM		 1112{"addps", 2, 0x0f58, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1113{"addss", 2, 0xf30f58, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1114{"andnps", 2, 0x0f55, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1115{"andps", 2, 0x0f54, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1116{"cmpeqps", 2, 0x0fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1117{"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1118{"cmpleps", 2, 0x0fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1119{"cmpless", 2, 0xf30fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1120{"cmpltps", 2, 0x0fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1121{"cmpltss", 2, 0xf30fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1122{"cmpneqps", 2, 0x0fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1123{"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1124{"cmpnleps", 2, 0x0fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1125{"cmpnless", 2, 0xf30fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1126{"cmpnltps", 2, 0x0fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1127{"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1128{"cmpordps", 2, 0x0fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1129{"cmpordss", 2, 0xf30fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1130{"cmpunordps",2, 0x0fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
1131{"cmpunordss",2, 0xf30fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
1132{"cmpps", 3, 0x0fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1133{"cmpss", 3, 0xf30fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } },
1134{"comiss", 2, 0x0f2f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1135{"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
1136{"cvtps2pi", 2, 0x0f2d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
76f227a5
JH		 1137{"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
1138{"cvtss2si", 2, 0xf30f2d, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
e413e4e9 1139{"cvttps2pi", 2, 0x0f2c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
76f227a5 1140{"cvttss2si", 2, 0xf30f2c, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } },
e413e4e9
AM		 1141{"divps", 2, 0x0f5e, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1142{"divss", 2, 0xf30f5e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1143{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, FP|Modrm, { WordMem, 0, 0 } },
1144{"maskmovq", 2, 0x0ff7, X, CpuSSE, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } },
1145{"maxps", 2, 0x0f5f, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1146{"maxss", 2, 0xf30f5f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1147{"minps", 2, 0x0f5d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1148{"minss", 2, 0xf30f5d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1149{"movaps", 2, 0x0f28, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1150{"movaps", 2, 0x0f29, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1151{"movhlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
1152{"movhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } },
1153{"movhps", 2, 0x0f17, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
1154{"movlhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
1155{"movlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } },
1156{"movlps", 2, 0x0f13, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
85a33fe2 1157{"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
e413e4e9
AM		 1158{"movntps", 2, 0x0f2b, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
1159{"movntq", 2, 0x0fe7, X, CpuSSE, FP|Modrm, { RegMMX, LLongMem, 0 } },
0f17484f 1160{"movntdq", 2, 0x660fe7, X, CpuSSE2,FP|Modrm, { RegXMM, LLongMem, 0 } },
e413e4e9
AM		 1161{"movss", 2, 0xf30f10, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1162{"movss", 2, 0xf30f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } },
1163{"movups", 2, 0x0f10, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1164{"movups", 2, 0x0f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1165{"mulps", 2, 0x0f59, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1166{"mulss", 2, 0xf30f59, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1167{"orps", 2, 0x0f56, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1168{"pavgb", 2, 0x0fe0, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
6f8c0c4c 1169{"pavgb", 2, 0x660fe0, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1170{"pavgw", 2, 0x0fe3, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
6f8c0c4c 1171{"pavgw", 2, 0x660fe3, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
85a33fe2
JH		 1172{"pextrw", 3, 0x0fc5, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } },
1173{"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } },
1174{"pinsrw", 3, 0x0fc4, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } },
1175{"pinsrw", 3, 0x660fc4, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } },
e413e4e9 1176{"pmaxsw", 2, 0x0fee, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
6f8c0c4c 1177{"pmaxsw", 2, 0x660fee, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1178{"pmaxub", 2, 0x0fde, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
6f8c0c4c 1179{"pmaxub", 2, 0x660fde, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1180{"pminsw", 2, 0x0fea, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
6f8c0c4c 1181{"pminsw", 2, 0x660fea, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9 1182{"pminub", 2, 0x0fda, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
6f8c0c4c 1183{"pminub", 2, 0x660fda, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
85a33fe2
JH		 1184{"pmovmskb", 2, 0x0fd7, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } },
1185{"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
e413e4e9 1186{"pmulhuw", 2, 0x0fe4, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
6f8c0c4c 1187{"pmulhuw", 2, 0x660fe4, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9
AM		 1188{"prefetchnta", 1, 0x0f18, 0, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1189{"prefetcht0", 1, 0x0f18, 1, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1190{"prefetcht1", 1, 0x0f18, 2, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1191{"prefetcht2", 1, 0x0f18, 3, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1192{"psadbw", 2, 0x0ff6, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
6f8c0c4c 1193{"psadbw", 2, 0x660ff6, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
e413e4e9
AM		 1194{"pshufw", 3, 0x0f70, X, CpuSSE, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } },
1195{"rcpps", 2, 0x0f53, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1196{"rcpss", 2, 0xf30f53, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1197{"rsqrtps", 2, 0x0f52, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1198{"rsqrtss", 2, 0xf30f52, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
7bc70a8e 1199{"sfence", 0, 0x0fae, 0xf8, CpuSSE, FP|ImmExt, { 0, 0, 0 } },
e413e4e9
AM		 1200{"shufps", 3, 0x0fc6, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1201{"sqrtps", 2, 0x0f51, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1202{"sqrtss", 2, 0xf30f51, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1203{"stmxcsr", 1, 0x0fae, 3, CpuSSE, FP|Modrm, { WordMem, 0, 0 } },
1204{"subps", 2, 0x0f5c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1205{"subss", 2, 0xf30f5c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1206{"ucomiss", 2, 0x0f2e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1207{"unpckhps", 2, 0x0f15, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1208{"unpcklps", 2, 0x0f14, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1209{"xorps", 2, 0x0f57, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
c608c12e 1210
6f8c0c4c
JH		 1211/* SSE-2 instructions. */
1212
1213{"addpd", 2, 0x660f58, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1214{"addsd", 2, 0xf20f58, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1215{"andnpd", 2, 0x660f55, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1216{"andpd", 2, 0x660f54, X, CpuSSE2, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1217{"cmpeqpd", 2, 0x660fc2, 0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1218{"cmpeqsd", 2, 0xf20fc2, 0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1219{"cmplepd", 2, 0x660fc2, 2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1220{"cmplesd", 2, 0xf20fc2, 2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1221{"cmpltpd", 2, 0x660fc2, 1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1222{"cmpltsd", 2, 0xf20fc2, 1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1223{"cmpneqpd", 2, 0x660fc2, 4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1224{"cmpneqsd", 2, 0xf20fc2, 4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1225{"cmpnlepd", 2, 0x660fc2, 6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1226{"cmpnlesd", 2, 0xf20fc2, 6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1227{"cmpnltpd", 2, 0x660fc2, 5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1228{"cmpnltsd", 2, 0xf20fc2, 5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1229{"cmpordpd", 2, 0x660fc2, 7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1230{"cmpordsd", 2, 0xf20fc2, 7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1231{"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
1232{"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
1233{"cmppd", 3, 0x660fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
cd47f4f1
AM		 1234/* Intel mode string compare. */
1235{"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
1236{"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
b9612d14 1237{"cmpsd", 3, 0xf20fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LongMem, RegXMM } },
6f8c0c4c
JH		 1238{"comisd", 2, 0x660f2f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1239{"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
76f227a5 1240{"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
6f8c0c4c
JH		 1241{"divpd", 2, 0x660f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1242{"divsd", 2, 0xf20f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1243{"maxpd", 2, 0x660f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1244{"maxsd", 2, 0xf20f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1245{"minpd", 2, 0x660f5d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1246{"minsd", 2, 0xf20f5d, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1247{"movapd", 2, 0x660f28, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1248{"movapd", 2, 0x660f29, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1249{"movhpd", 2, 0x660f16, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } },
1250{"movhpd", 2, 0x660f17, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } },
1251{"movlpd", 2, 0x660f12, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } },
1252{"movlpd", 2, 0x660f13, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } },
85a33fe2 1253{"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
6f8c0c4c 1254{"movntpd", 2, 0x660f2b, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } },
cd47f4f1
AM		 1255/* Intel mode string move. */
1256{"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
1257{"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
b9612d14
AM		 1258{"movsd", 2, 0xf20f10, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1259{"movsd", 2, 0xf20f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LongMem, 0 } },
6f8c0c4c
JH		 1260{"movupd", 2, 0x660f10, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1261{"movupd", 2, 0x660f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1262{"mulpd", 2, 0x660f59, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1263{"mulsd", 2, 0xf20f59, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1264{"orpd", 2, 0x660f56, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1265{"shufpd", 3, 0x660fc6, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1266{"sqrtpd", 2, 0x660f51, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1267{"sqrtsd", 2, 0xf20f51, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1268{"subpd", 2, 0x660f5c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1269{"subsd", 2, 0xf20f5c, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1270{"ucomisd", 2, 0x660f2e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1271{"unpckhpd", 2, 0x660f15, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1272{"unpcklpd", 2, 0x660f14, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1273{"xorpd", 2, 0x660f57, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1274{"cvtdq2pd", 2, 0xf30fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1275{"cvtpd2dq", 2, 0xf20fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1276{"cvtdq2ps", 2, 0x0f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1277{"cvtpd2pi", 2, 0x660f2d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
1278{"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1279{"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
67d6227d 1280{"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
76f227a5 1281{"cvtsd2si", 2, 0xf20f2d, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } },
6f8c0c4c
JH		 1282{"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1283{"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1284{"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
76f227a5 1285{"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
7c2b079e
JH		 1286{"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1287{"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
0f17484f 1288{"maskmovdqu",2, 0x660ff7, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
6f8c0c4c
JH		 1289{"movdqa", 2, 0x660f6f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1290{"movdqa", 2, 0x660f7f, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1291{"movdqu", 2, 0xf30f6f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1292{"movdqu", 2, 0xf30f7f, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
67d6227d
AM		 1293{"movdq2q", 2, 0xf20fd6, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, RegMMX, 0 } },
1294{"movq2dq", 2, 0xf30fd6, X, CpuSSE2, FP|Modrm, { RegMMX|InvMem, RegXMM, 0 } },
6f8c0c4c
JH		 1295{"pmuludq", 2, 0x0ff4, X, CpuSSE2, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
1296{"pmuludq", 2, 0x660ff4, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } },
1297{"pshufd", 3, 0x660f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1298{"pshufhw", 3, 0xf30f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1299{"pshuflw", 3, 0xf20f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1300{"pslldq", 2, 0x660f73, 7, CpuSSE2, FP|Modrm, { Imm8, RegXMM, 0 } },
1301{"psrldq", 2, 0x660f73, 3, CpuSSE2, FP|Modrm, { Imm8, RegXMM, 0 } },
1302{"punpckhqdq",2, 0x660f6d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
0f17484f 1303{"punpcklqdq",2, 0x660f6c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
6f8c0c4c 1304
d0b47220 1305/* AMD 3DNow! instructions. */
c608c12e 1306
e413e4e9
AM		 1307{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } },
1308{"prefetchw",1, 0x0f0d, 1, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } },
1309{"femms", 0, 0x0f0e, X, Cpu3dnow, FP, { 0, 0, 0 } },
1310{"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1311{"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1312{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1313{"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1314{"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1315{"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1316{"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1317{"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1318{"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1319{"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1320{"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1321{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1322{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1323{"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1324{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1325{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1326{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1327{"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1328{"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1329{"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1330{"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1331{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1332{"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1333{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1334
c0d8940f 1335/* AMD extensions. */
296bc568
AM		 1336{"syscall", 0, 0x0f05, X, CpuK6, NoSuf, { 0, 0, 0} },
1337{"sysret", 0, 0x0f07, X, CpuK6, lq_Suf|DefaultSize, { 0, 0, 0} },
1338{"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} },
c0d8940f 1339
e413e4e9
AM		 1340/* sentinel */
1341{NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
252b5132
RH		 1342};
1343#undef X
252b5132
RH		 1344#undef NoSuf
1345#undef b_Suf
1346#undef w_Suf
1347#undef l_Suf
c0d8940f 1348#undef q_Suf
eecb386c 1349#undef x_Suf
252b5132
RH		 1350#undef bw_Suf
1351#undef bl_Suf
1352#undef wl_Suf
c0d8940f 1353#undef wlq_Suf
252b5132
RH		 1354#undef sl_Suf
1355#undef bwl_Suf
c0d8940f 1356#undef bwlq_Suf
252b5132
RH		 1357#undef FP
1358#undef l_FP
eecb386c 1359#undef x_FP
252b5132
RH		 1360#undef sl_FP
1361
1362#define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */
1363
1364
d0b47220 1365/* 386 register table. */
252b5132
RH		 1366
1367static const reg_entry i386_regtab[] = {
5f47d35b 1368 /* make %st first as we test for it */
3e73aa7c 1369 {"st", FloatReg|FloatAcc, 0, 0},
252b5132 1370 /* 8 bit regs */
2e98d2de 1371#define REGNAM_AL 1 /* Entry in i386_regtab. */
3e73aa7c
JH		 1372 {"al", Reg8|Acc, 0, 0},
1373 {"cl", Reg8|ShiftCount, 0, 1},
1374 {"dl", Reg8, 0, 2},
1375 {"bl", Reg8, 0, 3},
1376 {"ah", Reg8, 0, 4},
1377 {"ch", Reg8, 0, 5},
1378 {"dh", Reg8, 0, 6},
1379 {"bh", Reg8, 0, 7},
c0d8940f
JH		 1380 {"axl", Reg8|Acc, RegRex64, 0}, /* Must be in the "al + 8" slot. */
1381 {"cxl", Reg8, RegRex64, 1},
1382 {"dxl", Reg8, RegRex64, 2},
1383 {"bxl", Reg8, RegRex64, 3},
1384 {"spl", Reg8, RegRex64, 4},
1385 {"bpl", Reg8, RegRex64, 5},
1386 {"sil", Reg8, RegRex64, 6},
1387 {"dil", Reg8, RegRex64, 7},
1388 {"r8b", Reg8, RegRex64|RegRex, 0},
1389 {"r9b", Reg8, RegRex64|RegRex, 1},
1390 {"r10b", Reg8, RegRex64|RegRex, 2},
1391 {"r11b", Reg8, RegRex64|RegRex, 3},
1392 {"r12b", Reg8, RegRex64|RegRex, 4},
1393 {"r13b", Reg8, RegRex64|RegRex, 5},
1394 {"r14b", Reg8, RegRex64|RegRex, 6},
1395 {"r15b", Reg8, RegRex64|RegRex, 7},
252b5132 1396 /* 16 bit regs */
2e98d2de 1397#define REGNAM_AX 25
3e73aa7c
JH		 1398 {"ax", Reg16|Acc, 0, 0},
1399 {"cx", Reg16, 0, 1},
1400 {"dx", Reg16|InOutPortReg, 0, 2},
1401 {"bx", Reg16|BaseIndex, 0, 3},
1402 {"sp", Reg16, 0, 4},
1403 {"bp", Reg16|BaseIndex, 0, 5},
1404 {"si", Reg16|BaseIndex, 0, 6},
1405 {"di", Reg16|BaseIndex, 0, 7},
c0d8940f
JH		 1406 {"r8w", Reg16, RegRex, 0},
1407 {"r9w", Reg16, RegRex, 1},
1408 {"r10w", Reg16, RegRex, 2},
1409 {"r11w", Reg16, RegRex, 3},
1410 {"r12w", Reg16, RegRex, 4},
1411 {"r13w", Reg16, RegRex, 5},
1412 {"r14w", Reg16, RegRex, 6},
1413 {"r15w", Reg16, RegRex, 7},
252b5132 1414 /* 32 bit regs */
2e98d2de 1415#define REGNAM_EAX 41
c0d8940f 1416 {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot */
3e73aa7c
JH		 1417 {"ecx", Reg32|BaseIndex, 0, 1},
1418 {"edx", Reg32|BaseIndex, 0, 2},
1419 {"ebx", Reg32|BaseIndex, 0, 3},
1420 {"esp", Reg32, 0, 4},
1421 {"ebp", Reg32|BaseIndex, 0, 5},
1422 {"esi", Reg32|BaseIndex, 0, 6},
1423 {"edi", Reg32|BaseIndex, 0, 7},
c0d8940f
JH		 1424 {"r8d", Reg32|BaseIndex, RegRex, 0},
1425 {"r9d", Reg32|BaseIndex, RegRex, 1},
1426 {"r10d", Reg32|BaseIndex, RegRex, 2},
1427 {"r11d", Reg32|BaseIndex, RegRex, 3},
1428 {"r12d", Reg32|BaseIndex, RegRex, 4},
1429 {"r13d", Reg32|BaseIndex, RegRex, 5},
1430 {"r14d", Reg32|BaseIndex, RegRex, 6},
1431 {"r15d", Reg32|BaseIndex, RegRex, 7},
1432 {"rax", Reg64|BaseIndex|Acc, 0, 0},
1433 {"rcx", Reg64|BaseIndex, 0, 1},
1434 {"rdx", Reg64|BaseIndex, 0, 2},
1435 {"rbx", Reg64|BaseIndex, 0, 3},
1436 {"rsp", Reg64, 0, 4},
1437 {"rbp", Reg64|BaseIndex, 0, 5},
1438 {"rsi", Reg64|BaseIndex, 0, 6},
1439 {"rdi", Reg64|BaseIndex, 0, 7},
1440 {"r8", Reg64|BaseIndex, RegRex, 0},
1441 {"r9", Reg64|BaseIndex, RegRex, 1},
1442 {"r10", Reg64|BaseIndex, RegRex, 2},
1443 {"r11", Reg64|BaseIndex, RegRex, 3},
1444 {"r12", Reg64|BaseIndex, RegRex, 4},
1445 {"r13", Reg64|BaseIndex, RegRex, 5},
1446 {"r14", Reg64|BaseIndex, RegRex, 6},
1447 {"r15", Reg64|BaseIndex, RegRex, 7},
252b5132 1448 /* segment registers */
3e73aa7c
JH		 1449 {"es", SReg2, 0, 0},
1450 {"cs", SReg2, 0, 1},
1451 {"ss", SReg2, 0, 2},
1452 {"ds", SReg2, 0, 3},
1453 {"fs", SReg3, 0, 4},
1454 {"gs", SReg3, 0, 5},
252b5132 1455 /* control registers */
3e73aa7c
JH		 1456 {"cr0", Control, 0, 0},
1457 {"cr1", Control, 0, 1},
1458 {"cr2", Control, 0, 2},
1459 {"cr3", Control, 0, 3},
1460 {"cr4", Control, 0, 4},
1461 {"cr5", Control, 0, 5},
1462 {"cr6", Control, 0, 6},
1463 {"cr7", Control, 0, 7},
c0d8940f
JH		 1464 {"cr8", Control, RegRex, 0},
1465 {"cr9", Control, RegRex, 1},
1466 {"cr10", Control, RegRex, 2},
1467 {"cr11", Control, RegRex, 3},
1468 {"cr12", Control, RegRex, 4},
1469 {"cr13", Control, RegRex, 5},
1470 {"cr14", Control, RegRex, 6},
1471 {"cr15", Control, RegRex, 7},
252b5132 1472 /* debug registers */
3e73aa7c
JH		 1473 {"db0", Debug, 0, 0},
1474 {"db1", Debug, 0, 1},
1475 {"db2", Debug, 0, 2},
1476 {"db3", Debug, 0, 3},
1477 {"db4", Debug, 0, 4},
1478 {"db5", Debug, 0, 5},
1479 {"db6", Debug, 0, 6},
1480 {"db7", Debug, 0, 7},
c0d8940f
JH		 1481 {"db8", Debug, RegRex, 0},
1482 {"db9", Debug, RegRex, 1},
1483 {"db10", Debug, RegRex, 2},
1484 {"db11", Debug, RegRex, 3},
1485 {"db12", Debug, RegRex, 4},
1486 {"db13", Debug, RegRex, 5},
1487 {"db14", Debug, RegRex, 6},
1488 {"db15", Debug, RegRex, 7},
3e73aa7c
JH		 1489 {"dr0", Debug, 0, 0},
1490 {"dr1", Debug, 0, 1},
1491 {"dr2", Debug, 0, 2},
1492 {"dr3", Debug, 0, 3},
1493 {"dr4", Debug, 0, 4},
1494 {"dr5", Debug, 0, 5},
1495 {"dr6", Debug, 0, 6},
1496 {"dr7", Debug, 0, 7},
c0d8940f
JH		 1497 {"dr8", Debug, RegRex, 0},
1498 {"dr9", Debug, RegRex, 1},
1499 {"dr10", Debug, RegRex, 2},
1500 {"dr11", Debug, RegRex, 3},
1501 {"dr12", Debug, RegRex, 4},
1502 {"dr13", Debug, RegRex, 5},
1503 {"dr14", Debug, RegRex, 6},
1504 {"dr15", Debug, RegRex, 7},
252b5132 1505 /* test registers */
3e73aa7c
JH		 1506 {"tr0", Test, 0, 0},
1507 {"tr1", Test, 0, 1},
1508 {"tr2", Test, 0, 2},
1509 {"tr3", Test, 0, 3},
1510 {"tr4", Test, 0, 4},
1511 {"tr5", Test, 0, 5},
1512 {"tr6", Test, 0, 6},
1513 {"tr7", Test, 0, 7},
5f47d35b 1514 /* mmx and simd registers */
3e73aa7c
JH		 1515 {"mm0", RegMMX, 0, 0},
1516 {"mm1", RegMMX, 0, 1},
1517 {"mm2", RegMMX, 0, 2},
1518 {"mm3", RegMMX, 0, 3},
1519 {"mm4", RegMMX, 0, 4},
1520 {"mm5", RegMMX, 0, 5},
1521 {"mm6", RegMMX, 0, 6},
1522 {"mm7", RegMMX, 0, 7},
1523 {"xmm0", RegXMM, 0, 0},
1524 {"xmm1", RegXMM, 0, 1},
1525 {"xmm2", RegXMM, 0, 2},
1526 {"xmm3", RegXMM, 0, 3},
1527 {"xmm4", RegXMM, 0, 4},
1528 {"xmm5", RegXMM, 0, 5},
1529 {"xmm6", RegXMM, 0, 6},
c0d8940f
JH		 1530 {"xmm7", RegXMM, 0, 7},
1531 {"xmm8", RegXMM, RegRex, 0},
1532 {"xmm9", RegXMM, RegRex, 1},
1533 {"xmm10", RegXMM, RegRex, 2},
1534 {"xmm11", RegXMM, RegRex, 3},
1535 {"xmm12", RegXMM, RegRex, 4},
1536 {"xmm13", RegXMM, RegRex, 5},
1537 {"xmm14", RegXMM, RegRex, 6},
1538 {"xmm15", RegXMM, RegRex, 7},
1539 /* no type will make this register rejected for all purposes except
1540 for addressing. This saves creating one extra type for RIP. */
1541 {"rip", BaseIndex, 0, 0}
252b5132
RH		 1542};
1543
5f47d35b 1544static const reg_entry i386_float_regtab[] = {
3e73aa7c
JH		 1545 {"st(0)", FloatReg|FloatAcc, 0, 0},
1546 {"st(1)", FloatReg, 0, 1},
1547 {"st(2)", FloatReg, 0, 2},
1548 {"st(3)", FloatReg, 0, 3},
1549 {"st(4)", FloatReg, 0, 4},
1550 {"st(5)", FloatReg, 0, 5},
1551 {"st(6)", FloatReg, 0, 6},
1552 {"st(7)", FloatReg, 0, 7}
5f47d35b
AM		 1553};
1554
252b5132
RH		 1555#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
1556
1557/* segment stuff */
1558static const seg_entry cs = { "cs", 0x2e };
1559static const seg_entry ds = { "ds", 0x3e };
1560static const seg_entry ss = { "ss", 0x36 };
1561static const seg_entry es = { "es", 0x26 };
1562static const seg_entry fs = { "fs", 0x64 };
1563static const seg_entry gs = { "gs", 0x65 };
1564
1565/* end of opcode/i386.h */
GDB Binutils - Deliverables
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