Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* opcode/i386.h -- Intel 80386 opcode table |
b722f2be AM |
2 | Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000 |
3 | Free Software Foundation. | |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
20 | ||
d0b47220 AM |
21 | /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived |
22 | ix86 Unix assemblers, generate floating point instructions with | |
23 | reversed source and destination registers in certain cases. | |
24 | Unfortunately, gcc and possibly many other programs use this | |
25 | reversed syntax, so we're stuck with it. | |
252b5132 | 26 | |
7f3f1ea2 AM |
27 | eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but |
28 | `fsub %st,%st(3)' results in st(3) = st - st(3), rather than | |
29 | the expected st(3) = st(3) - st | |
252b5132 RH |
30 | |
31 | This happens with all the non-commutative arithmetic floating point | |
32 | operations with two register operands, where the source register is | |
7f3f1ea2 AM |
33 | %st, and destination register is %st(i). See FloatDR below. |
34 | ||
35 | The affected opcode map is dceX, dcfX, deeX, defX. */ | |
252b5132 | 36 | |
d0b47220 | 37 | #ifndef SYSV386_COMPAT |
252b5132 | 38 | /* Set non-zero for broken, compatible instructions. Set to zero for |
d0b47220 | 39 | non-broken opcodes at your peril. gcc generates SystemV/386 |
252b5132 | 40 | compatible instructions. */ |
d0b47220 AM |
41 | #define SYSV386_COMPAT 1 |
42 | #endif | |
43 | #ifndef OLDGCC_COMPAT | |
44 | /* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could | |
45 | generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands | |
46 | reversed. */ | |
47 | #define OLDGCC_COMPAT SYSV386_COMPAT | |
252b5132 | 48 | #endif |
252b5132 RH |
49 | |
50 | static const template i386_optab[] = { | |
51 | ||
52 | #define X None | |
252b5132 RH |
53 | #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) |
54 | #define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) | |
55 | #define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) | |
56 | #define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_dSuf|No_xSuf) | |
57 | #define d_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf) | |
58 | #define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_dSuf) | |
59 | #define bw_Suf (No_lSuf|No_sSuf|No_dSuf|No_xSuf) | |
60 | #define bl_Suf (No_wSuf|No_sSuf|No_dSuf|No_xSuf) | |
61 | #define wl_Suf (No_bSuf|No_sSuf|No_dSuf|No_xSuf) | |
e413e4e9 | 62 | #define wld_Suf (No_bSuf|No_sSuf|No_xSuf) |
252b5132 RH |
63 | #define sl_Suf (No_bSuf|No_wSuf|No_dSuf|No_xSuf) |
64 | #define sld_Suf (No_bSuf|No_wSuf|No_xSuf) | |
65 | #define sldx_Suf (No_bSuf|No_wSuf) | |
66 | #define bwl_Suf (No_sSuf|No_dSuf|No_xSuf) | |
67 | #define bwld_Suf (No_sSuf|No_xSuf) | |
68 | #define FP (NoSuf|IgnoreSize) | |
69 | #define l_FP (l_Suf|IgnoreSize) | |
70 | #define d_FP (d_Suf|IgnoreSize) | |
71 | #define x_FP (x_Suf|IgnoreSize) | |
72 | #define sl_FP (sl_Suf|IgnoreSize) | |
73 | #define sld_FP (sld_Suf|IgnoreSize) | |
74 | #define sldx_FP (sldx_Suf|IgnoreSize) | |
d0b47220 | 75 | #if SYSV386_COMPAT |
7f3f1ea2 AM |
76 | /* Someone forgot that the FloatR bit reverses the operation when not |
77 | equal to the FloatD bit. ie. Changing only FloatD results in the | |
78 | destination being swapped *and* the direction being reversed. */ | |
252b5132 RH |
79 | #define FloatDR FloatD |
80 | #else | |
81 | #define FloatDR (FloatD|FloatR) | |
82 | #endif | |
83 | ||
d0b47220 | 84 | /* Move instructions. */ |
252b5132 | 85 | #define MOV_AX_DISP32 0xa0 |
e413e4e9 AM |
86 | { "mov", 2, 0xa0, X, 0, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, |
87 | { "mov", 2, 0x88, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } }, | |
88 | { "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { Imm, Reg, 0 } }, | |
89 | { "mov", 2, 0xc6, X, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0 } }, | |
90 | /* The segment register moves accept WordReg so that a segment register | |
252b5132 RH |
91 | can be copied to a 32 bit register, and vice versa, without using a |
92 | size prefix. When moving to a 32 bit register, the upper 16 bits | |
93 | are set to an implementation defined value (on the Pentium Pro, | |
94 | the implementation defined value is zero). */ | |
e413e4e9 AM |
95 | { "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|WordMem, 0 } }, |
96 | { "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|WordMem, 0 } }, | |
97 | { "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg2, 0 } }, | |
98 | { "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3, 0 } }, | |
d0b47220 | 99 | /* Move to/from control debug registers. */ |
e413e4e9 AM |
100 | { "mov", 2, 0x0f20, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32|InvMem, 0} }, |
101 | { "mov", 2, 0x0f21, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32|InvMem, 0} }, | |
102 | { "mov", 2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, | |
252b5132 | 103 | |
d0b47220 | 104 | /* Move with sign extend. */ |
252b5132 RH |
105 | /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid |
106 | conflict with the "movs" string move instruction. */ | |
e413e4e9 AM |
107 | {"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, |
108 | {"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, | |
109 | {"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, | |
f9e0cf0b | 110 | /* Intel Syntax next 2 insns */ |
e413e4e9 | 111 | {"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, |
fc29466d | 112 | {"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, |
252b5132 | 113 | |
d0b47220 | 114 | /* Move with zero extend. */ |
e413e4e9 AM |
115 | {"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, |
116 | {"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, | |
f9e0cf0b | 117 | /* Intel Syntax next 2 insns */ |
e413e4e9 | 118 | {"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, |
fc29466d | 119 | {"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, |
252b5132 | 120 | |
d0b47220 | 121 | /* Push instructions. */ |
e413e4e9 AM |
122 | {"push", 1, 0x50, X, 0, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, |
123 | {"push", 1, 0xff, 6, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, | |
124 | {"push", 1, 0x6a, X, Cpu186, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, | |
125 | {"push", 1, 0x68, X, Cpu186, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, | |
126 | {"push", 1, 0x06, X, 0, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, | |
127 | {"push", 1, 0x0fa0, X, Cpu386, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, | |
128 | {"pusha", 0, 0x60, X, Cpu186, wld_Suf|DefaultSize, { 0, 0, 0 } }, | |
252b5132 | 129 | |
d0b47220 | 130 | /* Pop instructions. */ |
e413e4e9 AM |
131 | {"pop", 1, 0x58, X, 0, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, |
132 | {"pop", 1, 0x8f, 0, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, | |
252b5132 | 133 | #define POP_SEG_SHORT 0x07 |
e413e4e9 AM |
134 | {"pop", 1, 0x07, X, 0, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, |
135 | {"pop", 1, 0x0fa1, X, Cpu386, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, | |
136 | {"popa", 0, 0x61, X, Cpu186, wld_Suf|DefaultSize, { 0, 0, 0 } }, | |
252b5132 | 137 | |
d0b47220 AM |
138 | /* Exchange instructions. |
139 | xchg commutes: we allow both operand orders. */ | |
e413e4e9 AM |
140 | {"xchg", 2, 0x90, X, 0, wl_Suf|ShortForm, { WordReg, Acc, 0 } }, |
141 | {"xchg", 2, 0x90, X, 0, wl_Suf|ShortForm, { Acc, WordReg, 0 } }, | |
142 | {"xchg", 2, 0x86, X, 0, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, | |
143 | {"xchg", 2, 0x86, X, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, | |
252b5132 | 144 | |
d0b47220 | 145 | /* In/out from ports. */ |
e413e4e9 AM |
146 | {"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } }, |
147 | {"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, | |
148 | {"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, | |
149 | {"in", 1, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, | |
150 | {"out", 2, 0xe6, X, 0, bwl_Suf|W, { Acc, Imm8, 0 } }, | |
151 | {"out", 2, 0xee, X, 0, bwl_Suf|W, { Acc, InOutPortReg, 0 } }, | |
152 | {"out", 1, 0xe6, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, | |
153 | {"out", 1, 0xee, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, | |
252b5132 | 154 | |
d0b47220 | 155 | /* Load effective address. */ |
e413e4e9 | 156 | {"lea", 2, 0x8d, X, 0, wl_Suf|Modrm, { WordMem, WordReg, 0 } }, |
252b5132 | 157 | |
d0b47220 | 158 | /* Load segment registers from memory. */ |
e413e4e9 AM |
159 | {"lds", 2, 0xc5, X, 0, wl_Suf|Modrm, { WordMem, WordReg, 0} }, |
160 | {"les", 2, 0xc4, X, 0, wl_Suf|Modrm, { WordMem, WordReg, 0} }, | |
161 | {"lfs", 2, 0x0fb4, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, | |
162 | {"lgs", 2, 0x0fb5, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, | |
163 | {"lss", 2, 0x0fb2, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, | |
252b5132 | 164 | |
d0b47220 | 165 | /* Flags register instructions. */ |
e413e4e9 AM |
166 | {"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} }, |
167 | {"cld", 0, 0xfc, X, 0, NoSuf, { 0, 0, 0} }, | |
168 | {"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} }, | |
169 | {"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} }, | |
170 | {"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} }, | |
171 | {"lahf", 0, 0x9f, X, 0, NoSuf, { 0, 0, 0} }, | |
172 | {"sahf", 0, 0x9e, X, 0, NoSuf, { 0, 0, 0} }, | |
173 | {"pushf", 0, 0x9c, X, 0, wld_Suf|DefaultSize, { 0, 0, 0} }, | |
174 | {"popf", 0, 0x9d, X, 0, wld_Suf|DefaultSize, { 0, 0, 0} }, | |
175 | {"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} }, | |
176 | {"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} }, | |
177 | {"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} }, | |
252b5132 | 178 | |
d0b47220 | 179 | /* Arithmetic. */ |
e413e4e9 AM |
180 | {"add", 2, 0x00, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, |
181 | {"add", 2, 0x83, 0, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
182 | {"add", 2, 0x04, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, | |
183 | {"add", 2, 0x80, 0, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, | |
184 | ||
185 | {"inc", 1, 0x40, X, 0, wl_Suf|ShortForm, { WordReg, 0, 0} }, | |
186 | {"inc", 1, 0xfe, 0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
187 | ||
188 | {"sub", 2, 0x28, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, | |
189 | {"sub", 2, 0x83, 5, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
190 | {"sub", 2, 0x2c, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, | |
191 | {"sub", 2, 0x80, 5, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, | |
192 | ||
193 | {"dec", 1, 0x48, X, 0, wl_Suf|ShortForm, { WordReg, 0, 0} }, | |
194 | {"dec", 1, 0xfe, 1, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
195 | ||
196 | {"sbb", 2, 0x18, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, | |
197 | {"sbb", 2, 0x83, 3, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
198 | {"sbb", 2, 0x1c, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, | |
199 | {"sbb", 2, 0x80, 3, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, | |
200 | ||
201 | {"cmp", 2, 0x38, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, | |
202 | {"cmp", 2, 0x83, 7, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
203 | {"cmp", 2, 0x3c, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, | |
204 | {"cmp", 2, 0x80, 7, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, | |
205 | ||
206 | {"test", 2, 0x84, X, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} }, | |
207 | {"test", 2, 0x84, X, 0, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} }, | |
208 | {"test", 2, 0xa8, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, | |
209 | {"test", 2, 0xf6, 0, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, | |
210 | ||
211 | {"and", 2, 0x20, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, | |
212 | {"and", 2, 0x83, 4, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
213 | {"and", 2, 0x24, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, | |
214 | {"and", 2, 0x80, 4, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, | |
215 | ||
216 | {"or", 2, 0x08, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, | |
217 | {"or", 2, 0x83, 1, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
218 | {"or", 2, 0x0c, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, | |
219 | {"or", 2, 0x80, 1, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, | |
220 | ||
221 | {"xor", 2, 0x30, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, | |
222 | {"xor", 2, 0x83, 6, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
223 | {"xor", 2, 0x34, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, | |
224 | {"xor", 2, 0x80, 6, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, | |
225 | ||
226 | /* clr with 1 operand is really xor with 2 operands. */ | |
227 | {"clr", 1, 0x30, X, 0, bwl_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, | |
228 | ||
229 | {"adc", 2, 0x10, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, | |
230 | {"adc", 2, 0x83, 2, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
231 | {"adc", 2, 0x14, X, 0, bwl_Suf|W, { Imm, Acc, 0} }, | |
232 | {"adc", 2, 0x80, 2, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, | |
233 | ||
234 | {"neg", 1, 0xf6, 3, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
235 | {"not", 1, 0xf6, 2, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
236 | ||
237 | {"aaa", 0, 0x37, X, 0, NoSuf, { 0, 0, 0} }, | |
238 | {"aas", 0, 0x3f, X, 0, NoSuf, { 0, 0, 0} }, | |
239 | {"daa", 0, 0x27, X, 0, NoSuf, { 0, 0, 0} }, | |
240 | {"das", 0, 0x2f, X, 0, NoSuf, { 0, 0, 0} }, | |
241 | {"aad", 0, 0xd50a, X, 0, NoSuf, { 0, 0, 0} }, | |
242 | {"aad", 1, 0xd5, X, 0, NoSuf, { Imm8S, 0, 0} }, | |
243 | {"aam", 0, 0xd40a, X, 0, NoSuf, { 0, 0, 0} }, | |
244 | {"aam", 1, 0xd4, X, 0, NoSuf, { Imm8S, 0, 0} }, | |
252b5132 | 245 | |
d0b47220 AM |
246 | /* Conversion insns. */ |
247 | /* Intel naming */ | |
e413e4e9 AM |
248 | {"cbw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, |
249 | {"cwde", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, | |
250 | {"cwd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, | |
251 | {"cdq", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, | |
d0b47220 | 252 | /* AT&T naming */ |
e413e4e9 AM |
253 | {"cbtw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, |
254 | {"cwtl", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, | |
255 | {"cwtd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, | |
256 | {"cltd", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, | |
252b5132 RH |
257 | |
258 | /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are | |
259 | expanding 64-bit multiplies, and *cannot* be selected to accomplish | |
260 | 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) | |
261 | These multiplies can only be selected with single operand forms. */ | |
e413e4e9 AM |
262 | {"mul", 1, 0xf6, 4, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, |
263 | {"imul", 1, 0xf6, 5, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
264 | {"imul", 2, 0x0faf, X, Cpu386, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
265 | {"imul", 3, 0x6b, X, Cpu186, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, | |
266 | {"imul", 3, 0x69, X, Cpu186, wl_Suf|Modrm, { Imm16|Imm32, WordReg|WordMem, WordReg} }, | |
252b5132 RH |
267 | /* imul with 2 operands mimics imul with 3 by putting the register in |
268 | both i.rm.reg & i.rm.regmem fields. regKludge enables this | |
269 | transformation. */ | |
e413e4e9 AM |
270 | {"imul", 2, 0x6b, X, Cpu186, wl_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} }, |
271 | {"imul", 2, 0x69, X, Cpu186, wl_Suf|Modrm|regKludge,{ Imm16|Imm32, WordReg, 0} }, | |
272 | ||
273 | {"div", 1, 0xf6, 6, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
274 | {"div", 2, 0xf6, 6, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, | |
275 | {"idiv", 1, 0xf6, 7, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
276 | {"idiv", 2, 0xf6, 7, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, | |
277 | ||
278 | {"rol", 2, 0xd0, 0, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
279 | {"rol", 2, 0xc0, 0, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
280 | {"rol", 2, 0xd2, 0, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
281 | {"rol", 1, 0xd0, 0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
282 | ||
283 | {"ror", 2, 0xd0, 1, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
284 | {"ror", 2, 0xc0, 1, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
285 | {"ror", 2, 0xd2, 1, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
286 | {"ror", 1, 0xd0, 1, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
287 | ||
288 | {"rcl", 2, 0xd0, 2, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
289 | {"rcl", 2, 0xc0, 2, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
290 | {"rcl", 2, 0xd2, 2, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
291 | {"rcl", 1, 0xd0, 2, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
292 | ||
293 | {"rcr", 2, 0xd0, 3, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
294 | {"rcr", 2, 0xc0, 3, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
295 | {"rcr", 2, 0xd2, 3, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
296 | {"rcr", 1, 0xd0, 3, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
297 | ||
298 | {"sal", 2, 0xd0, 4, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
299 | {"sal", 2, 0xc0, 4, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
300 | {"sal", 2, 0xd2, 4, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
301 | {"sal", 1, 0xd0, 4, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
302 | ||
303 | {"shl", 2, 0xd0, 4, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
304 | {"shl", 2, 0xc0, 4, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
305 | {"shl", 2, 0xd2, 4, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
306 | {"shl", 1, 0xd0, 4, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
307 | ||
308 | {"shr", 2, 0xd0, 5, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
309 | {"shr", 2, 0xc0, 5, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
310 | {"shr", 2, 0xd2, 5, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
311 | {"shr", 1, 0xd0, 5, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
312 | ||
313 | {"sar", 2, 0xd0, 7, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
314 | {"sar", 2, 0xc0, 7, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
315 | {"sar", 2, 0xd2, 7, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
316 | {"sar", 1, 0xd0, 7, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
317 | ||
318 | {"shld", 3, 0x0fa4, X, Cpu386, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, | |
319 | {"shld", 3, 0x0fa5, X, Cpu386, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, | |
320 | {"shld", 2, 0x0fa5, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, | |
321 | ||
322 | {"shrd", 3, 0x0fac, X, Cpu386, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, | |
323 | {"shrd", 3, 0x0fad, X, Cpu386, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, | |
324 | {"shrd", 2, 0x0fad, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, | |
252b5132 | 325 | |
d0b47220 | 326 | /* Control transfer instructions. */ |
e413e4e9 AM |
327 | {"call", 1, 0xe8, X, 0, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, |
328 | {"call", 1, 0xff, 2, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, | |
252b5132 | 329 | /* Intel Syntax */ |
e413e4e9 | 330 | {"call", 2, 0x9a, X, 0, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, |
3138f287 | 331 | /* Intel Syntax */ |
e413e4e9 AM |
332 | {"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} }, |
333 | {"lcall", 2, 0x9a, X, 0, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, | |
334 | {"lcall", 1, 0xff, 3, 0, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} }, | |
252b5132 RH |
335 | |
336 | #define JUMP_PC_RELATIVE 0xeb | |
e413e4e9 AM |
337 | {"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp, 0, 0} }, |
338 | {"jmp", 1, 0xff, 4, 0, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, | |
252b5132 | 339 | /* Intel Syntax */ |
e413e4e9 | 340 | {"jmp", 2, 0xea, X, 0, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, |
3138f287 | 341 | /* Intel Syntax */ |
e413e4e9 AM |
342 | {"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem, 0, 0} }, |
343 | {"ljmp", 2, 0xea, X, 0, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, | |
344 | {"ljmp", 1, 0xff, 5, 0, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, | |
252b5132 | 345 | |
e413e4e9 AM |
346 | {"ret", 0, 0xc3, X, 0, wl_Suf|DefaultSize, { 0, 0, 0} }, |
347 | {"ret", 1, 0xc2, X, 0, wl_Suf|DefaultSize, { Imm16, 0, 0} }, | |
348 | {"lret", 0, 0xcb, X, 0, wl_Suf|DefaultSize, { 0, 0, 0} }, | |
349 | {"lret", 1, 0xca, X, 0, wl_Suf|DefaultSize, { Imm16, 0, 0} }, | |
350 | {"enter", 2, 0xc8, X, Cpu186, wl_Suf|DefaultSize, { Imm16, Imm8, 0} }, | |
351 | {"leave", 0, 0xc9, X, Cpu186, wl_Suf|DefaultSize, { 0, 0, 0} }, | |
252b5132 | 352 | |
d0b47220 | 353 | /* Conditional jumps. */ |
e413e4e9 AM |
354 | {"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} }, |
355 | {"jno", 1, 0x71, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
356 | {"jb", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
357 | {"jc", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
358 | {"jnae", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
359 | {"jnb", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
360 | {"jnc", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
361 | {"jae", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
362 | {"je", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
363 | {"jz", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
364 | {"jne", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
365 | {"jnz", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
366 | {"jbe", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
367 | {"jna", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
368 | {"jnbe", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
369 | {"ja", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
370 | {"js", 1, 0x78, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
371 | {"jns", 1, 0x79, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
372 | {"jp", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
373 | {"jpe", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
374 | {"jnp", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
375 | {"jpo", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
376 | {"jl", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
377 | {"jnge", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
378 | {"jnl", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
379 | {"jge", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
380 | {"jle", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
381 | {"jng", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
382 | {"jnle", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
383 | {"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
252b5132 RH |
384 | |
385 | /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ | |
e413e4e9 AM |
386 | {"jcxz", 1, 0xe3, X, 0, NoSuf|JumpByte|Size16, { Disp, 0, 0} }, |
387 | {"jecxz", 1, 0xe3, X, 0, NoSuf|JumpByte|Size32, { Disp, 0, 0} }, | |
252b5132 RH |
388 | |
389 | /* The loop instructions also use the address size prefix to select | |
390 | %cx rather than %ecx for the loop count, so the `w' form of these | |
391 | instructions emit an address size prefix rather than a data size | |
392 | prefix. */ | |
e413e4e9 AM |
393 | {"loop", 1, 0xe2, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} }, |
394 | {"loopz", 1, 0xe1, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} }, | |
395 | {"loope", 1, 0xe1, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} }, | |
396 | {"loopnz", 1, 0xe0, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} }, | |
397 | {"loopne", 1, 0xe0, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} }, | |
252b5132 | 398 | |
d0b47220 | 399 | /* Set byte on flag instructions. */ |
e413e4e9 AM |
400 | {"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, |
401 | {"setno", 1, 0x0f91, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
402 | {"setb", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
403 | {"setc", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
404 | {"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
405 | {"setnb", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
406 | {"setnc", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
407 | {"setae", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
408 | {"sete", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
409 | {"setz", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
410 | {"setne", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
411 | {"setnz", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
412 | {"setbe", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
413 | {"setna", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
414 | {"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
415 | {"seta", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
416 | {"sets", 1, 0x0f98, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
417 | {"setns", 1, 0x0f99, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
418 | {"setp", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
419 | {"setpe", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
420 | {"setnp", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
421 | {"setpo", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
422 | {"setl", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
423 | {"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
424 | {"setnl", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
425 | {"setge", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
426 | {"setle", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
427 | {"setng", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
428 | {"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
429 | {"setg", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
252b5132 | 430 | |
d0b47220 | 431 | /* String manipulation. */ |
e413e4e9 AM |
432 | {"cmps", 0, 0xa6, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} }, |
433 | {"cmps", 2, 0xa6, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, | |
434 | {"scmp", 0, 0xa6, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} }, | |
435 | {"scmp", 2, 0xa6, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, | |
436 | {"ins", 0, 0x6c, X, Cpu186, bwld_Suf|W|IsString, { 0, 0, 0} }, | |
437 | {"ins", 2, 0x6c, X, Cpu186, bwld_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} }, | |
438 | {"outs", 0, 0x6e, X, Cpu186, bwld_Suf|W|IsString, { 0, 0, 0} }, | |
439 | {"outs", 2, 0x6e, X, Cpu186, bwld_Suf|W|IsString, { AnyMem, InOutPortReg, 0} }, | |
440 | {"lods", 0, 0xac, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} }, | |
441 | {"lods", 1, 0xac, X, 0, bwld_Suf|W|IsString, { AnyMem, 0, 0} }, | |
442 | {"lods", 2, 0xac, X, 0, bwld_Suf|W|IsString, { AnyMem, Acc, 0} }, | |
443 | {"slod", 0, 0xac, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} }, | |
444 | {"slod", 1, 0xac, X, 0, bwld_Suf|W|IsString, { AnyMem, 0, 0} }, | |
445 | {"slod", 2, 0xac, X, 0, bwld_Suf|W|IsString, { AnyMem, Acc, 0} }, | |
446 | {"movs", 0, 0xa4, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} }, | |
447 | {"movs", 2, 0xa4, X, 0, bwld_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, | |
448 | {"smov", 0, 0xa4, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} }, | |
449 | {"smov", 2, 0xa4, X, 0, bwld_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, | |
450 | {"scas", 0, 0xae, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} }, | |
451 | {"scas", 1, 0xae, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, | |
452 | {"scas", 2, 0xae, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, | |
453 | {"ssca", 0, 0xae, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} }, | |
454 | {"ssca", 1, 0xae, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, | |
455 | {"ssca", 2, 0xae, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, | |
456 | {"stos", 0, 0xaa, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} }, | |
457 | {"stos", 1, 0xaa, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, | |
458 | {"stos", 2, 0xaa, X, 0, bwld_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, | |
459 | {"ssto", 0, 0xaa, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} }, | |
460 | {"ssto", 1, 0xaa, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, | |
461 | {"ssto", 2, 0xaa, X, 0, bwld_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, | |
462 | {"xlat", 0, 0xd7, X, 0, b_Suf|IsString, { 0, 0, 0} }, | |
463 | {"xlat", 1, 0xd7, X, 0, b_Suf|IsString, { AnyMem, 0, 0} }, | |
252b5132 | 464 | |
d0b47220 | 465 | /* Bit manipulation. */ |
e413e4e9 AM |
466 | {"bsf", 2, 0x0fbc, X, Cpu386, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, |
467 | {"bsr", 2, 0x0fbd, X, Cpu386, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
468 | {"bt", 2, 0x0fa3, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, | |
469 | {"bt", 2, 0x0fba, 4, Cpu386, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, | |
470 | {"btc", 2, 0x0fbb, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, | |
471 | {"btc", 2, 0x0fba, 7, Cpu386, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, | |
472 | {"btr", 2, 0x0fb3, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, | |
473 | {"btr", 2, 0x0fba, 6, Cpu386, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, | |
474 | {"bts", 2, 0x0fab, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, | |
475 | {"bts", 2, 0x0fba, 5, Cpu386, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, | |
252b5132 | 476 | |
d0b47220 | 477 | /* Interrupts & op. sys insns. */ |
252b5132 | 478 | /* See gas/config/tc-i386.c for conversion of 'int $3' into the special |
d0b47220 | 479 | int 3 insn. */ |
252b5132 RH |
480 | #define INT_OPCODE 0xcd |
481 | #define INT3_OPCODE 0xcc | |
e413e4e9 AM |
482 | {"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} }, |
483 | {"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} }, | |
484 | {"into", 0, 0xce, X, 0, NoSuf, { 0, 0, 0} }, | |
b722f2be | 485 | {"iret", 0, 0xcf, X, 0, wld_Suf|DefaultSize, { 0, 0, 0} }, |
d0b47220 | 486 | /* i386sl, i486sl, later 486, and Pentium. */ |
e413e4e9 | 487 | {"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} }, |
252b5132 | 488 | |
e413e4e9 | 489 | {"bound", 2, 0x62, X, Cpu186, wl_Suf|Modrm, { WordReg, WordMem, 0} }, |
252b5132 | 490 | |
e413e4e9 | 491 | {"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} }, |
d0b47220 | 492 | /* nop is actually 'xchgl %eax, %eax'. */ |
e413e4e9 | 493 | {"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} }, |
252b5132 | 494 | |
d0b47220 | 495 | /* Protection control. */ |
e413e4e9 AM |
496 | {"arpl", 2, 0x63, X, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, |
497 | {"lar", 2, 0x0f02, X, Cpu286, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
498 | {"lgdt", 1, 0x0f01, 2, Cpu286, wl_Suf|Modrm, { WordMem, 0, 0} }, | |
499 | {"lidt", 1, 0x0f01, 3, Cpu286, wl_Suf|Modrm, { WordMem, 0, 0} }, | |
500 | {"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, | |
501 | {"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, | |
502 | {"lsl", 2, 0x0f03, X, Cpu286, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
503 | {"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, | |
504 | ||
505 | {"sgdt", 1, 0x0f01, 0, Cpu286, wl_Suf|Modrm, { WordMem, 0, 0} }, | |
506 | {"sidt", 1, 0x0f01, 1, Cpu286, wl_Suf|Modrm, { WordMem, 0, 0} }, | |
507 | {"sldt", 1, 0x0f00, 0, Cpu286, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} }, | |
508 | {"smsw", 1, 0x0f01, 4, Cpu286, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} }, | |
509 | {"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, | |
510 | ||
511 | {"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, | |
512 | {"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, | |
252b5132 | 513 | |
d0b47220 | 514 | /* Floating point instructions. */ |
252b5132 RH |
515 | |
516 | /* load */ | |
e413e4e9 AM |
517 | {"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, |
518 | {"fld", 1, 0xd9, 0, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, | |
519 | {"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, | |
252b5132 | 520 | /* Intel Syntax */ |
e413e4e9 | 521 | {"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} }, |
f9e0cf0b | 522 | {"fild", 1, 0xdf, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, |
252b5132 | 523 | /* Intel Syntax */ |
e413e4e9 AM |
524 | {"fildd", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, |
525 | {"fildq", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, | |
526 | {"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, | |
527 | {"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, | |
528 | {"fbld", 1, 0xdf, 4, 0, FP|Modrm, { LLongMem, 0, 0} }, | |
252b5132 RH |
529 | |
530 | /* store (no pop) */ | |
e413e4e9 AM |
531 | {"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, |
532 | {"fst", 1, 0xd9, 2, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, | |
533 | {"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, | |
534 | {"fist", 1, 0xdf, 2, 0, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 RH |
535 | |
536 | /* store (with pop) */ | |
e413e4e9 AM |
537 | {"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, |
538 | {"fstp", 1, 0xd9, 3, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, | |
539 | {"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, | |
252b5132 | 540 | /* Intel Syntax */ |
e413e4e9 AM |
541 | {"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} }, |
542 | {"fistp", 1, 0xdf, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 | 543 | /* Intel Syntax */ |
e413e4e9 AM |
544 | {"fistpd", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, |
545 | {"fistpq", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, | |
546 | {"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, | |
547 | {"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, | |
548 | {"fbstp", 1, 0xdf, 6, 0, FP|Modrm, { LLongMem, 0, 0} }, | |
252b5132 RH |
549 | |
550 | /* exchange %st<n> with %st0 */ | |
e413e4e9 AM |
551 | {"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, |
552 | /* alias for fxch %st(1) */ | |
553 | {"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
554 | |
555 | /* comparison (without pop) */ | |
e413e4e9 AM |
556 | {"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, |
557 | /* alias for fcom %st(1) */ | |
558 | {"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} }, | |
559 | {"fcom", 1, 0xd8, 2, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, | |
560 | {"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, | |
561 | {"ficom", 1, 0xde, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 RH |
562 | |
563 | /* comparison (with pop) */ | |
e413e4e9 AM |
564 | {"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, |
565 | /* alias for fcomp %st(1) */ | |
566 | {"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} }, | |
567 | {"fcomp", 1, 0xd8, 3, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, | |
568 | {"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, | |
569 | {"ficomp", 1, 0xde, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, | |
570 | {"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
571 | |
572 | /* unordered comparison (with pop) */ | |
e413e4e9 AM |
573 | {"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, |
574 | /* alias for fucom %st(1) */ | |
575 | {"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} }, | |
576 | {"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, | |
577 | /* alias for fucomp %st(1) */ | |
578 | {"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} }, | |
579 | {"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} }, | |
252b5132 | 580 | |
e413e4e9 AM |
581 | {"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} }, |
582 | {"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
583 | |
584 | /* load constants into %st0 */ | |
e413e4e9 AM |
585 | {"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} }, |
586 | {"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} }, | |
587 | {"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} }, | |
588 | {"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} }, | |
589 | {"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} }, | |
590 | {"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} }, | |
591 | {"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
592 | |
593 | /* arithmetic */ | |
594 | ||
595 | /* add */ | |
e413e4e9 AM |
596 | {"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, |
597 | /* alias for fadd %st(i), %st */ | |
598 | {"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
d0b47220 | 599 | #if SYSV386_COMPAT |
e413e4e9 AM |
600 | /* alias for faddp */ |
601 | {"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} }, | |
252b5132 | 602 | #endif |
e413e4e9 AM |
603 | {"fadd", 1, 0xd8, 0, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, |
604 | {"fiadd", 1, 0xde, 0, 0, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 | 605 | |
e413e4e9 AM |
606 | {"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
607 | {"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
608 | /* alias for faddp %st, %st(1) */ | |
609 | {"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} }, | |
610 | {"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, | |
252b5132 RH |
611 | |
612 | /* subtract */ | |
e413e4e9 AM |
613 | {"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, |
614 | {"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
d0b47220 | 615 | #if SYSV386_COMPAT |
e413e4e9 AM |
616 | /* alias for fsubp */ |
617 | {"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} }, | |
252b5132 | 618 | #endif |
e413e4e9 AM |
619 | {"fsub", 1, 0xd8, 4, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, |
620 | {"fisub", 1, 0xde, 4, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 | 621 | |
d0b47220 | 622 | #if SYSV386_COMPAT |
e413e4e9 AM |
623 | {"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
624 | {"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
625 | {"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, | |
d0b47220 | 626 | #if OLDGCC_COMPAT |
e413e4e9 | 627 | {"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, |
d0b47220 | 628 | #endif |
252b5132 | 629 | #else |
e413e4e9 AM |
630 | {"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
631 | {"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
632 | {"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
633 | #endif |
634 | ||
635 | /* subtract reverse */ | |
e413e4e9 AM |
636 | {"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, |
637 | {"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
d0b47220 | 638 | #if SYSV386_COMPAT |
e413e4e9 AM |
639 | /* alias for fsubrp */ |
640 | {"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} }, | |
252b5132 | 641 | #endif |
e413e4e9 AM |
642 | {"fsubr", 1, 0xd8, 5, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, |
643 | {"fisubr", 1, 0xde, 5, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 | 644 | |
d0b47220 | 645 | #if SYSV386_COMPAT |
e413e4e9 AM |
646 | {"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
647 | {"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
648 | {"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, | |
d0b47220 | 649 | #if OLDGCC_COMPAT |
e413e4e9 | 650 | {"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, |
d0b47220 | 651 | #endif |
252b5132 | 652 | #else |
e413e4e9 AM |
653 | {"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
654 | {"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
655 | {"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
656 | #endif |
657 | ||
658 | /* multiply */ | |
e413e4e9 AM |
659 | {"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, |
660 | {"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
d0b47220 | 661 | #if SYSV386_COMPAT |
e413e4e9 AM |
662 | /* alias for fmulp */ |
663 | {"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} }, | |
252b5132 | 664 | #endif |
e413e4e9 AM |
665 | {"fmul", 1, 0xd8, 1, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, |
666 | {"fimul", 1, 0xde, 1, 0, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 | 667 | |
e413e4e9 AM |
668 | {"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
669 | {"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
670 | {"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} }, | |
671 | {"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, | |
252b5132 RH |
672 | |
673 | /* divide */ | |
e413e4e9 AM |
674 | {"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, |
675 | {"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
d0b47220 | 676 | #if SYSV386_COMPAT |
e413e4e9 AM |
677 | /* alias for fdivp */ |
678 | {"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} }, | |
252b5132 | 679 | #endif |
e413e4e9 AM |
680 | {"fdiv", 1, 0xd8, 6, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, |
681 | {"fidiv", 1, 0xde, 6, 0, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 | 682 | |
d0b47220 | 683 | #if SYSV386_COMPAT |
e413e4e9 AM |
684 | {"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
685 | {"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
686 | {"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, | |
d0b47220 | 687 | #if OLDGCC_COMPAT |
e413e4e9 | 688 | {"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, |
d0b47220 | 689 | #endif |
252b5132 | 690 | #else |
e413e4e9 AM |
691 | {"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
692 | {"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
693 | {"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
694 | #endif |
695 | ||
696 | /* divide reverse */ | |
e413e4e9 AM |
697 | {"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, |
698 | {"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
d0b47220 | 699 | #if SYSV386_COMPAT |
e413e4e9 AM |
700 | /* alias for fdivrp */ |
701 | {"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} }, | |
252b5132 | 702 | #endif |
e413e4e9 AM |
703 | {"fdivr", 1, 0xd8, 7, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, |
704 | {"fidivr", 1, 0xde, 7, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 | 705 | |
d0b47220 | 706 | #if SYSV386_COMPAT |
e413e4e9 AM |
707 | {"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
708 | {"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
709 | {"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, | |
d0b47220 | 710 | #if OLDGCC_COMPAT |
e413e4e9 | 711 | {"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, |
d0b47220 | 712 | #endif |
252b5132 | 713 | #else |
e413e4e9 AM |
714 | {"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
715 | {"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
716 | {"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
717 | #endif |
718 | ||
e413e4e9 AM |
719 | {"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} }, |
720 | {"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} }, | |
721 | {"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} }, | |
722 | {"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} }, | |
723 | {"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} }, | |
724 | {"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} }, | |
725 | {"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} }, | |
726 | {"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} }, | |
727 | {"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} }, | |
728 | {"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} }, | |
729 | {"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} }, | |
730 | {"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} }, | |
731 | {"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} }, | |
732 | {"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} }, | |
733 | {"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} }, | |
734 | {"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} }, | |
735 | {"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} }, | |
736 | {"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
737 | |
738 | /* processor control */ | |
e413e4e9 AM |
739 | {"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} }, |
740 | {"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} }, | |
741 | {"fldcw", 1, 0xd9, 5, 0, FP|Modrm, { ShortMem, 0, 0} }, | |
742 | {"fnstcw", 1, 0xd9, 7, 0, FP|Modrm, { ShortMem, 0, 0} }, | |
743 | {"fstcw", 1, 0xd9, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} }, | |
744 | {"fnstsw", 1, 0xdfe0, X, 0, FP, { Acc, 0, 0} }, | |
745 | {"fnstsw", 1, 0xdd, 7, 0, FP|Modrm, { ShortMem, 0, 0} }, | |
746 | {"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} }, | |
747 | {"fstsw", 1, 0xdfe0, X, 0, FP|FWait, { Acc, 0, 0} }, | |
748 | {"fstsw", 1, 0xdd, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} }, | |
749 | {"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} }, | |
750 | {"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} }, | |
751 | {"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} }, | |
d0b47220 | 752 | /* Short forms of fldenv, fstenv use data size prefix. */ |
e413e4e9 AM |
753 | {"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, |
754 | {"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, | |
755 | {"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, | |
756 | {"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, | |
757 | {"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, | |
758 | {"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, | |
759 | ||
760 | {"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
252b5132 | 761 | /* P6:free st(i), pop st */ |
e413e4e9 AM |
762 | {"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, |
763 | {"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} }, | |
252b5132 | 764 | #define FWAIT_OPCODE 0x9b |
e413e4e9 | 765 | {"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} }, |
252b5132 | 766 | |
d0b47220 AM |
767 | /* Opcode prefixes; we allow them as separate insns too. */ |
768 | ||
252b5132 | 769 | #define ADDR_PREFIX_OPCODE 0x67 |
e413e4e9 AM |
770 | {"addr16", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, |
771 | {"addr32", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, | |
772 | {"aword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, | |
773 | {"adword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, | |
252b5132 | 774 | #define DATA_PREFIX_OPCODE 0x66 |
e413e4e9 AM |
775 | {"data16", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, |
776 | {"data32", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, | |
777 | {"word", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, | |
778 | {"dword", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, | |
252b5132 | 779 | #define LOCK_PREFIX_OPCODE 0xf0 |
e413e4e9 AM |
780 | {"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, |
781 | {"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, | |
252b5132 | 782 | #define CS_PREFIX_OPCODE 0x2e |
e413e4e9 | 783 | {"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, |
252b5132 | 784 | #define DS_PREFIX_OPCODE 0x3e |
e413e4e9 | 785 | {"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, |
252b5132 | 786 | #define ES_PREFIX_OPCODE 0x26 |
e413e4e9 | 787 | {"es", 0, 0x26, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, |
252b5132 | 788 | #define FS_PREFIX_OPCODE 0x64 |
e413e4e9 | 789 | {"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, |
252b5132 | 790 | #define GS_PREFIX_OPCODE 0x65 |
e413e4e9 | 791 | {"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, |
252b5132 | 792 | #define SS_PREFIX_OPCODE 0x36 |
e413e4e9 | 793 | {"ss", 0, 0x36, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, |
252b5132 RH |
794 | #define REPNE_PREFIX_OPCODE 0xf2 |
795 | #define REPE_PREFIX_OPCODE 0xf3 | |
e413e4e9 AM |
796 | {"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, |
797 | {"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, | |
798 | {"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, | |
799 | {"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, | |
800 | {"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, | |
252b5132 | 801 | |
d0b47220 | 802 | /* 486 extensions. */ |
252b5132 | 803 | |
e413e4e9 AM |
804 | {"bswap", 1, 0x0fc8, X, Cpu486, l_Suf|ShortForm, { Reg32, 0, 0 } }, |
805 | {"xadd", 2, 0x0fc0, X, Cpu486, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, | |
806 | {"cmpxchg", 2, 0x0fb0, X, Cpu486, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, | |
807 | {"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} }, | |
808 | {"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} }, | |
809 | {"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm, { AnyMem, 0, 0} }, | |
252b5132 | 810 | |
d0b47220 | 811 | /* 586 and late 486 extensions. */ |
e413e4e9 | 812 | {"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} }, |
252b5132 | 813 | |
d0b47220 | 814 | /* Pentium extensions. */ |
e413e4e9 AM |
815 | {"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} }, |
816 | {"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} }, | |
817 | {"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} }, | |
818 | {"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm, { LLongMem, 0, 0} }, | |
252b5132 | 819 | |
558b0a60 AM |
820 | /* Pentium II/Pentium Pro extensions. */ |
821 | {"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} }, | |
822 | {"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} }, | |
823 | {"fxsave", 1, 0x0fae, 0, Cpu686, FP|Modrm, { LLongMem, 0, 0} }, | |
824 | {"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm, { LLongMem, 0, 0} }, | |
e413e4e9 AM |
825 | {"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} }, |
826 | /* official undefined instr. */ | |
827 | {"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, | |
828 | /* alias for ud2 */ | |
829 | {"ud2a", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, | |
830 | /* 2nd. official undefined instr. */ | |
831 | {"ud2b", 0, 0x0fb9, X, Cpu686, NoSuf, { 0, 0, 0} }, | |
832 | ||
833 | {"cmovo", 2, 0x0f40, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
834 | {"cmovno", 2, 0x0f41, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
835 | {"cmovb", 2, 0x0f42, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
836 | {"cmovc", 2, 0x0f42, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
837 | {"cmovnae", 2, 0x0f42, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
838 | {"cmovae", 2, 0x0f43, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
839 | {"cmovnc", 2, 0x0f43, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
840 | {"cmovnb", 2, 0x0f43, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
841 | {"cmove", 2, 0x0f44, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
842 | {"cmovz", 2, 0x0f44, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
843 | {"cmovne", 2, 0x0f45, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
844 | {"cmovnz", 2, 0x0f45, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
845 | {"cmovbe", 2, 0x0f46, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
846 | {"cmovna", 2, 0x0f46, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
847 | {"cmova", 2, 0x0f47, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
848 | {"cmovnbe", 2, 0x0f47, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
849 | {"cmovs", 2, 0x0f48, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
850 | {"cmovns", 2, 0x0f49, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
851 | {"cmovp", 2, 0x0f4a, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
852 | {"cmovnp", 2, 0x0f4b, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
853 | {"cmovl", 2, 0x0f4c, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
854 | {"cmovnge", 2, 0x0f4c, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
855 | {"cmovge", 2, 0x0f4d, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
856 | {"cmovnl", 2, 0x0f4d, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
857 | {"cmovle", 2, 0x0f4e, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
858 | {"cmovng", 2, 0x0f4e, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
859 | {"cmovg", 2, 0x0f4f, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
860 | {"cmovnle", 2, 0x0f4f, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
861 | ||
862 | {"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
863 | {"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
864 | {"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
865 | {"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
866 | {"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
867 | {"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
868 | {"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
869 | {"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
870 | {"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
871 | {"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
872 | {"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
873 | {"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
874 | ||
875 | {"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
876 | {"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, | |
877 | {"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, | |
878 | {"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
879 | {"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, | |
880 | {"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, | |
881 | {"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
882 | {"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
883 | {"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, | |
884 | {"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, | |
885 | {"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
886 | {"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
887 | {"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, | |
888 | {"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, | |
252b5132 RH |
889 | |
890 | /* MMX instructions. */ | |
891 | ||
e413e4e9 AM |
892 | {"emms", 0, 0x0f77, X, CpuMMX, FP, { 0, 0, 0 } }, |
893 | {"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } }, | |
894 | {"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } }, | |
895 | {"movq", 2, 0x0f6f, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
896 | {"movq", 2, 0x0f7f, X, CpuMMX, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, | |
897 | {"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
898 | {"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
899 | {"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
900 | {"paddb", 2, 0x0ffc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
901 | {"paddw", 2, 0x0ffd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
902 | {"paddd", 2, 0x0ffe, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
903 | {"paddsb", 2, 0x0fec, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
904 | {"paddsw", 2, 0x0fed, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
905 | {"paddusb", 2, 0x0fdc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
906 | {"paddusw", 2, 0x0fdd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
907 | {"pand", 2, 0x0fdb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
908 | {"pandn", 2, 0x0fdf, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
909 | {"pcmpeqb", 2, 0x0f74, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
910 | {"pcmpeqw", 2, 0x0f75, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
911 | {"pcmpeqd", 2, 0x0f76, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
912 | {"pcmpgtb", 2, 0x0f64, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
913 | {"pcmpgtw", 2, 0x0f65, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
914 | {"pcmpgtd", 2, 0x0f66, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
915 | {"pmaddwd", 2, 0x0ff5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
916 | {"pmulhw", 2, 0x0fe5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
917 | {"pmullw", 2, 0x0fd5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
918 | {"por", 2, 0x0feb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
919 | {"psllw", 2, 0x0ff1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
920 | {"psllw", 2, 0x0f71, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, | |
921 | {"pslld", 2, 0x0ff2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
922 | {"pslld", 2, 0x0f72, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, | |
923 | {"psllq", 2, 0x0ff3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
924 | {"psllq", 2, 0x0f73, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, | |
925 | {"psraw", 2, 0x0fe1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
926 | {"psraw", 2, 0x0f71, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, | |
927 | {"psrad", 2, 0x0fe2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
928 | {"psrad", 2, 0x0f72, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, | |
929 | {"psrlw", 2, 0x0fd1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
930 | {"psrlw", 2, 0x0f71, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, | |
931 | {"psrld", 2, 0x0fd2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
932 | {"psrld", 2, 0x0f72, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, | |
933 | {"psrlq", 2, 0x0fd3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
934 | {"psrlq", 2, 0x0f73, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, | |
935 | {"psubb", 2, 0x0ff8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
936 | {"psubw", 2, 0x0ff9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
937 | {"psubd", 2, 0x0ffa, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
938 | {"psubsb", 2, 0x0fe8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
939 | {"psubsw", 2, 0x0fe9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
940 | {"psubusb", 2, 0x0fd8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
941 | {"psubusw", 2, 0x0fd9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
942 | {"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
943 | {"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
944 | {"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
945 | {"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
946 | {"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
947 | {"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
948 | {"pxor", 2, 0x0fef, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
c608c12e AM |
949 | |
950 | ||
d0b47220 | 951 | /* PIII Katmai New Instructions / SIMD instructions. */ |
c608c12e | 952 | |
e413e4e9 AM |
953 | {"addps", 2, 0x0f58, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
954 | {"addss", 2, 0xf30f58, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
955 | {"andnps", 2, 0x0f55, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
956 | {"andps", 2, 0x0f54, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
957 | {"cmpeqps", 2, 0x0fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
958 | {"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
959 | {"cmpleps", 2, 0x0fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
960 | {"cmpless", 2, 0xf30fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
961 | {"cmpltps", 2, 0x0fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
962 | {"cmpltss", 2, 0xf30fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
963 | {"cmpneqps", 2, 0x0fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
964 | {"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
965 | {"cmpnleps", 2, 0x0fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
966 | {"cmpnless", 2, 0xf30fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
967 | {"cmpnltps", 2, 0x0fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
968 | {"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
969 | {"cmpordps", 2, 0x0fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
970 | {"cmpordss", 2, 0xf30fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
971 | {"cmpunordps",2, 0x0fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
972 | {"cmpunordss",2, 0xf30fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
973 | {"cmpps", 3, 0x0fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, | |
974 | {"cmpss", 3, 0xf30fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, | |
975 | {"comiss", 2, 0x0f2f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
976 | {"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, | |
977 | {"cvtps2pi", 2, 0x0f2d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, | |
978 | {"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, FP|Modrm, { Reg32|WordMem, RegXMM, 0 } }, | |
979 | {"cvtss2si", 2, 0xf30f2d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, | |
980 | {"cvttps2pi", 2, 0x0f2c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, | |
981 | {"cvttss2si", 2, 0xf30f2c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, | |
982 | {"divps", 2, 0x0f5e, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
983 | {"divss", 2, 0xf30f5e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
984 | {"ldmxcsr", 1, 0x0fae, 2, CpuSSE, FP|Modrm, { WordMem, 0, 0 } }, | |
985 | {"maskmovq", 2, 0x0ff7, X, CpuSSE, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, | |
986 | {"maxps", 2, 0x0f5f, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
987 | {"maxss", 2, 0xf30f5f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
988 | {"minps", 2, 0x0f5d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
989 | {"minss", 2, 0xf30f5d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
990 | {"movaps", 2, 0x0f28, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
991 | {"movaps", 2, 0x0f29, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, | |
992 | {"movhlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, | |
993 | {"movhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } }, | |
994 | {"movhps", 2, 0x0f17, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, | |
995 | {"movlhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, | |
996 | {"movlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } }, | |
997 | {"movlps", 2, 0x0f13, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, | |
998 | {"movmskps", 2, 0x0f50, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } }, | |
999 | {"movntps", 2, 0x0f2b, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, | |
1000 | {"movntq", 2, 0x0fe7, X, CpuSSE, FP|Modrm, { RegMMX, LLongMem, 0 } }, | |
1001 | {"movss", 2, 0xf30f10, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1002 | {"movss", 2, 0xf30f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, | |
1003 | {"movups", 2, 0x0f10, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1004 | {"movups", 2, 0x0f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, | |
1005 | {"mulps", 2, 0x0f59, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1006 | {"mulss", 2, 0xf30f59, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1007 | {"orps", 2, 0x0f56, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1008 | {"pavgb", 2, 0x0fe0, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, | |
1009 | {"pavgw", 2, 0x0fe3, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, | |
1010 | {"pextrw", 3, 0x0fc5, X, CpuSSE, FP|Modrm, { Imm8, RegMMX, Reg32|InvMem } }, | |
1011 | {"pinsrw", 3, 0x0fc4, X, CpuSSE, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } }, | |
1012 | {"pmaxsw", 2, 0x0fee, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, | |
1013 | {"pmaxub", 2, 0x0fde, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, | |
1014 | {"pminsw", 2, 0x0fea, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, | |
1015 | {"pminub", 2, 0x0fda, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, | |
1016 | {"pmovmskb", 2, 0x0fd7, X, CpuSSE, FP|Modrm, { RegMMX, Reg32|InvMem, 0 } }, | |
1017 | {"pmulhuw", 2, 0x0fe4, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, | |
1018 | {"prefetchnta", 1, 0x0f18, 0, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, | |
1019 | {"prefetcht0", 1, 0x0f18, 1, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, | |
1020 | {"prefetcht1", 1, 0x0f18, 2, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, | |
1021 | {"prefetcht2", 1, 0x0f18, 3, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, | |
1022 | {"psadbw", 2, 0x0ff6, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, | |
1023 | {"pshufw", 3, 0x0f70, X, CpuSSE, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, | |
1024 | {"rcpps", 2, 0x0f53, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1025 | {"rcpss", 2, 0xf30f53, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1026 | {"rsqrtps", 2, 0x0f52, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1027 | {"rsqrtss", 2, 0xf30f52, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1028 | {"sfence", 0, 0x0faef8, X, CpuSSE, FP, { 0, 0, 0 } }, | |
1029 | {"shufps", 3, 0x0fc6, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, | |
1030 | {"sqrtps", 2, 0x0f51, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1031 | {"sqrtss", 2, 0xf30f51, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1032 | {"stmxcsr", 1, 0x0fae, 3, CpuSSE, FP|Modrm, { WordMem, 0, 0 } }, | |
1033 | {"subps", 2, 0x0f5c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1034 | {"subss", 2, 0xf30f5c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1035 | {"ucomiss", 2, 0x0f2e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1036 | {"unpckhps", 2, 0x0f15, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1037 | {"unpcklps", 2, 0x0f14, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1038 | {"xorps", 2, 0x0f57, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
c608c12e | 1039 | |
d0b47220 | 1040 | /* AMD 3DNow! instructions. */ |
c608c12e | 1041 | |
e413e4e9 AM |
1042 | {"prefetch", 1, 0x0f0d, 0, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } }, |
1043 | {"prefetchw",1, 0x0f0d, 1, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } }, | |
1044 | {"femms", 0, 0x0f0e, X, Cpu3dnow, FP, { 0, 0, 0 } }, | |
1045 | {"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1046 | {"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1047 | {"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1048 | {"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1049 | {"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1050 | {"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1051 | {"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1052 | {"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1053 | {"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1054 | {"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1055 | {"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1056 | {"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1057 | {"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1058 | {"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1059 | {"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1060 | {"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1061 | {"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1062 | {"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1063 | {"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1064 | {"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1065 | {"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1066 | {"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1067 | {"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1068 | {"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1069 | ||
1070 | /* sentinel */ | |
1071 | {NULL, 0, 0, 0, 0, 0, { 0, 0, 0} } | |
252b5132 RH |
1072 | }; |
1073 | #undef X | |
252b5132 RH |
1074 | #undef NoSuf |
1075 | #undef b_Suf | |
1076 | #undef w_Suf | |
1077 | #undef l_Suf | |
eecb386c AM |
1078 | #undef d_Suf |
1079 | #undef x_Suf | |
252b5132 RH |
1080 | #undef bw_Suf |
1081 | #undef bl_Suf | |
1082 | #undef wl_Suf | |
e413e4e9 | 1083 | #undef wld_Suf |
252b5132 | 1084 | #undef sl_Suf |
eecb386c AM |
1085 | #undef sld_Suf |
1086 | #undef sldx_Suf | |
252b5132 | 1087 | #undef bwl_Suf |
eecb386c | 1088 | #undef bwld_Suf |
252b5132 RH |
1089 | #undef FP |
1090 | #undef l_FP | |
eecb386c AM |
1091 | #undef d_FP |
1092 | #undef x_FP | |
252b5132 | 1093 | #undef sl_FP |
eecb386c AM |
1094 | #undef sld_FP |
1095 | #undef sldx_FP | |
252b5132 RH |
1096 | |
1097 | #define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */ | |
1098 | ||
1099 | ||
d0b47220 | 1100 | /* 386 register table. */ |
252b5132 RH |
1101 | |
1102 | static const reg_entry i386_regtab[] = { | |
5f47d35b AM |
1103 | /* make %st first as we test for it */ |
1104 | {"st", FloatReg|FloatAcc, 0}, | |
252b5132 RH |
1105 | /* 8 bit regs */ |
1106 | {"al", Reg8|Acc, 0}, | |
1107 | {"cl", Reg8|ShiftCount, 1}, | |
1108 | {"dl", Reg8, 2}, | |
1109 | {"bl", Reg8, 3}, | |
1110 | {"ah", Reg8, 4}, | |
1111 | {"ch", Reg8, 5}, | |
1112 | {"dh", Reg8, 6}, | |
1113 | {"bh", Reg8, 7}, | |
1114 | /* 16 bit regs */ | |
1115 | {"ax", Reg16|Acc, 0}, | |
1116 | {"cx", Reg16, 1}, | |
1117 | {"dx", Reg16|InOutPortReg, 2}, | |
1118 | {"bx", Reg16|BaseIndex, 3}, | |
1119 | {"sp", Reg16, 4}, | |
1120 | {"bp", Reg16|BaseIndex, 5}, | |
1121 | {"si", Reg16|BaseIndex, 6}, | |
1122 | {"di", Reg16|BaseIndex, 7}, | |
1123 | /* 32 bit regs */ | |
1124 | {"eax", Reg32|BaseIndex|Acc, 0}, | |
1125 | {"ecx", Reg32|BaseIndex, 1}, | |
1126 | {"edx", Reg32|BaseIndex, 2}, | |
1127 | {"ebx", Reg32|BaseIndex, 3}, | |
1128 | {"esp", Reg32, 4}, | |
1129 | {"ebp", Reg32|BaseIndex, 5}, | |
1130 | {"esi", Reg32|BaseIndex, 6}, | |
1131 | {"edi", Reg32|BaseIndex, 7}, | |
1132 | /* segment registers */ | |
1133 | {"es", SReg2, 0}, | |
1134 | {"cs", SReg2, 1}, | |
1135 | {"ss", SReg2, 2}, | |
1136 | {"ds", SReg2, 3}, | |
1137 | {"fs", SReg3, 4}, | |
1138 | {"gs", SReg3, 5}, | |
1139 | /* control registers */ | |
1140 | {"cr0", Control, 0}, | |
1141 | {"cr1", Control, 1}, | |
1142 | {"cr2", Control, 2}, | |
1143 | {"cr3", Control, 3}, | |
1144 | {"cr4", Control, 4}, | |
1145 | {"cr5", Control, 5}, | |
1146 | {"cr6", Control, 6}, | |
1147 | {"cr7", Control, 7}, | |
1148 | /* debug registers */ | |
1149 | {"db0", Debug, 0}, | |
1150 | {"db1", Debug, 1}, | |
1151 | {"db2", Debug, 2}, | |
1152 | {"db3", Debug, 3}, | |
1153 | {"db4", Debug, 4}, | |
1154 | {"db5", Debug, 5}, | |
1155 | {"db6", Debug, 6}, | |
1156 | {"db7", Debug, 7}, | |
1157 | {"dr0", Debug, 0}, | |
1158 | {"dr1", Debug, 1}, | |
1159 | {"dr2", Debug, 2}, | |
1160 | {"dr3", Debug, 3}, | |
1161 | {"dr4", Debug, 4}, | |
1162 | {"dr5", Debug, 5}, | |
1163 | {"dr6", Debug, 6}, | |
1164 | {"dr7", Debug, 7}, | |
1165 | /* test registers */ | |
1166 | {"tr0", Test, 0}, | |
1167 | {"tr1", Test, 1}, | |
1168 | {"tr2", Test, 2}, | |
1169 | {"tr3", Test, 3}, | |
1170 | {"tr4", Test, 4}, | |
1171 | {"tr5", Test, 5}, | |
1172 | {"tr6", Test, 6}, | |
1173 | {"tr7", Test, 7}, | |
5f47d35b | 1174 | /* mmx and simd registers */ |
252b5132 RH |
1175 | {"mm0", RegMMX, 0}, |
1176 | {"mm1", RegMMX, 1}, | |
1177 | {"mm2", RegMMX, 2}, | |
1178 | {"mm3", RegMMX, 3}, | |
1179 | {"mm4", RegMMX, 4}, | |
1180 | {"mm5", RegMMX, 5}, | |
1181 | {"mm6", RegMMX, 6}, | |
c608c12e AM |
1182 | {"mm7", RegMMX, 7}, |
1183 | {"xmm0", RegXMM, 0}, | |
1184 | {"xmm1", RegXMM, 1}, | |
1185 | {"xmm2", RegXMM, 2}, | |
1186 | {"xmm3", RegXMM, 3}, | |
1187 | {"xmm4", RegXMM, 4}, | |
1188 | {"xmm5", RegXMM, 5}, | |
1189 | {"xmm6", RegXMM, 6}, | |
1190 | {"xmm7", RegXMM, 7} | |
252b5132 RH |
1191 | }; |
1192 | ||
5f47d35b AM |
1193 | static const reg_entry i386_float_regtab[] = { |
1194 | {"st(0)", FloatReg|FloatAcc, 0}, | |
1195 | {"st(1)", FloatReg, 1}, | |
1196 | {"st(2)", FloatReg, 2}, | |
1197 | {"st(3)", FloatReg, 3}, | |
1198 | {"st(4)", FloatReg, 4}, | |
1199 | {"st(5)", FloatReg, 5}, | |
1200 | {"st(6)", FloatReg, 6}, | |
1201 | {"st(7)", FloatReg, 7} | |
1202 | }; | |
1203 | ||
252b5132 RH |
1204 | #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ |
1205 | ||
1206 | /* segment stuff */ | |
1207 | static const seg_entry cs = { "cs", 0x2e }; | |
1208 | static const seg_entry ds = { "ds", 0x3e }; | |
1209 | static const seg_entry ss = { "ss", 0x36 }; | |
1210 | static const seg_entry es = { "es", 0x26 }; | |
1211 | static const seg_entry fs = { "fs", 0x64 }; | |
1212 | static const seg_entry gs = { "gs", 0x65 }; | |
1213 | ||
1214 | /* end of opcode/i386.h */ |