Commit | Line | Data |
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ce868e5c | 1 | /* i386-opcode.h -- Intel 80386 opcode table |
ffd42166 | 2 | Copyright 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation. |
ce868e5c JG |
3 | |
4 | This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
cd22144a | 18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
ce868e5c | 19 | |
c0d7b534 ILT |
20 | /* The NON_BROKEN_OPCODES cases use the operands in the reverse order |
21 | from that documented in the Intel manuals. The opcode values are | |
22 | such that they actually generate different instructions. These | |
654b0845 ILT |
23 | values must not be changed, as they are the values generated by the |
24 | UnixWare assembler, and possibly other ix86 assemblers. */ | |
c0d7b534 | 25 | |
ce868e5c JG |
26 | static const template i386_optab[] = { |
27 | ||
28 | #define _ None | |
29 | /* move instructions */ | |
a43022bd | 30 | #define MOV_AX_DISP32 0xa0 |
fc0d7441 ILT |
31 | { "mov", 2, 0xa0, _, DW|NoModrm, { Disp32, Acc, 0 } }, |
32 | { "mov", 2, 0x88, _, DW|Modrm, { Reg, Reg|Mem, 0 } }, | |
33 | { "mov", 2, 0xb0, _, ShortFormW, { Imm, Reg, 0 } }, | |
34 | { "mov", 2, 0xc6, _, W|Modrm, { Imm, Reg|Mem, 0 } }, | |
eff2a090 ILT |
35 | /* The next instruction accepts WordReg so that `movl %gs,%esi' can be |
36 | used to move a segment register to a 32 bit register without using | |
37 | a size prefix, which works although Intel does not document it. I | |
86bdd00e | 38 | think it zeroes the upper 16 bits in the 32 bit register. */ |
eff2a090 | 39 | { "mov", 2, 0x8c, _, D|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } }, |
ce868e5c | 40 | /* move to/from control debug registers */ |
fc0d7441 ILT |
41 | { "mov", 2, 0x0f20, _, D|Modrm, { Control, Reg32, 0} }, |
42 | { "mov", 2, 0x0f21, _, D|Modrm, { Debug, Reg32, 0} }, | |
43 | { "mov", 2, 0x0f24, _, D|Modrm, { Test, Reg32, 0} }, | |
ce868e5c JG |
44 | |
45 | /* move with sign extend */ | |
46 | /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid | |
47 | conflict with the "movs" string move instruction. Thus, | |
fc0d7441 | 48 | {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} }, |
ce868e5c | 49 | is not kosher; we must seperate the two instructions. */ |
a43022bd KR |
50 | {"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data32, { Reg8|Mem, Reg32, 0} }, |
51 | {"movsbw", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data16, { Reg8|Mem, Reg16, 0} }, | |
fc0d7441 | 52 | {"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} }, |
ce868e5c JG |
53 | |
54 | /* move with zero extend */ | |
fc0d7441 ILT |
55 | {"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} }, |
56 | {"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} }, | |
ce868e5c JG |
57 | |
58 | /* push instructions */ | |
fc0d7441 ILT |
59 | {"push", 1, 0x50, _, ShortForm, { WordReg,0,0 } }, |
60 | {"push", 1, 0xff, 0x6, Modrm, { WordReg|WordMem, 0, 0 } }, | |
61 | {"push", 1, 0x6a, _, NoModrm, { Imm8S, 0, 0} }, | |
a43022bd | 62 | {"push", 1, 0x68, _, NoModrm, { Imm16|Imm32, 0, 0} }, |
fc0d7441 ILT |
63 | {"push", 1, 0x06, _, Seg2ShortForm, { SReg2,0,0 } }, |
64 | {"push", 1, 0x0fa0, _, Seg3ShortForm, { SReg3,0,0 } }, | |
ce868e5c | 65 | /* push all */ |
fc0d7441 | 66 | {"pusha", 0, 0x60, _, NoModrm, { 0, 0, 0 } }, |
ce868e5c JG |
67 | |
68 | /* pop instructions */ | |
fc0d7441 ILT |
69 | {"pop", 1, 0x58, _, ShortForm, { WordReg,0,0 } }, |
70 | {"pop", 1, 0x8f, 0x0, Modrm, { WordReg|WordMem, 0, 0 } }, | |
ce868e5c | 71 | #define POP_SEG_SHORT 0x7 |
fc0d7441 ILT |
72 | {"pop", 1, 0x07, _, Seg2ShortForm, { SReg2,0,0 } }, |
73 | {"pop", 1, 0x0fa1, _, Seg3ShortForm, { SReg3,0,0 } }, | |
ce868e5c | 74 | /* pop all */ |
fc0d7441 | 75 | {"popa", 0, 0x61, _, NoModrm, { 0, 0, 0 } }, |
ce868e5c JG |
76 | |
77 | /* xchg exchange instructions | |
78 | xchg commutes: we allow both operand orders */ | |
fc0d7441 ILT |
79 | {"xchg", 2, 0x90, _, ShortForm, { WordReg, Acc, 0 } }, |
80 | {"xchg", 2, 0x90, _, ShortForm, { Acc, WordReg, 0 } }, | |
81 | {"xchg", 2, 0x86, _, W|Modrm, { Reg, Reg|Mem, 0 } }, | |
82 | {"xchg", 2, 0x86, _, W|Modrm, { Reg|Mem, Reg, 0 } }, | |
ce868e5c JG |
83 | |
84 | /* in/out from ports */ | |
fc0d7441 ILT |
85 | {"in", 2, 0xe4, _, W|NoModrm, { Imm8, Acc, 0 } }, |
86 | {"in", 2, 0xec, _, W|NoModrm, { InOutPortReg, Acc, 0 } }, | |
87 | {"in", 1, 0xe4, _, W|NoModrm, { Imm8, 0, 0 } }, | |
88 | {"in", 1, 0xec, _, W|NoModrm, { InOutPortReg, 0, 0 } }, | |
89 | {"out", 2, 0xe6, _, W|NoModrm, { Acc, Imm8, 0 } }, | |
90 | {"out", 2, 0xee, _, W|NoModrm, { Acc, InOutPortReg, 0 } }, | |
91 | {"out", 1, 0xe6, _, W|NoModrm, { Imm8, 0, 0 } }, | |
92 | {"out", 1, 0xee, _, W|NoModrm, { InOutPortReg, 0, 0 } }, | |
93 | ||
ce868e5c | 94 | /* load effective address */ |
fc0d7441 | 95 | {"lea", 2, 0x8d, _, Modrm, { WordMem, WordReg, 0 } }, |
ce868e5c JG |
96 | |
97 | /* load segment registers from memory */ | |
fc0d7441 ILT |
98 | {"lds", 2, 0xc5, _, Modrm, { Mem, Reg32, 0} }, |
99 | {"les", 2, 0xc4, _, Modrm, { Mem, Reg32, 0} }, | |
100 | {"lfs", 2, 0x0fb4, _, Modrm, { Mem, Reg32, 0} }, | |
101 | {"lgs", 2, 0x0fb5, _, Modrm, { Mem, Reg32, 0} }, | |
102 | {"lss", 2, 0x0fb2, _, Modrm, { Mem, Reg32, 0} }, | |
ce868e5c JG |
103 | |
104 | /* flags register instructions */ | |
fc0d7441 ILT |
105 | {"clc", 0, 0xf8, _, NoModrm, { 0, 0, 0} }, |
106 | {"cld", 0, 0xfc, _, NoModrm, { 0, 0, 0} }, | |
107 | {"cli", 0, 0xfa, _, NoModrm, { 0, 0, 0} }, | |
108 | {"clts", 0, 0x0f06, _, NoModrm, { 0, 0, 0} }, | |
109 | {"cmc", 0, 0xf5, _, NoModrm, { 0, 0, 0} }, | |
110 | {"lahf", 0, 0x9f, _, NoModrm, { 0, 0, 0} }, | |
111 | {"sahf", 0, 0x9e, _, NoModrm, { 0, 0, 0} }, | |
cd22144a KR |
112 | {"pushfl", 0, 0x9c, _, NoModrm|Data32, { 0, 0, 0} }, |
113 | {"popfl", 0, 0x9d, _, NoModrm|Data32, { 0, 0, 0} }, | |
a43022bd KR |
114 | {"pushfw", 0, 0x9c, _, NoModrm|Data16, { 0, 0, 0} }, |
115 | {"popfw", 0, 0x9d, _, NoModrm|Data16, { 0, 0, 0} }, | |
527cabaf ILT |
116 | {"pushf", 0, 0x9c, _, NoModrm, { 0, 0, 0} }, |
117 | {"popf", 0, 0x9d, _, NoModrm, { 0, 0, 0} }, | |
fc0d7441 ILT |
118 | {"stc", 0, 0xf9, _, NoModrm, { 0, 0, 0} }, |
119 | {"std", 0, 0xfd, _, NoModrm, { 0, 0, 0} }, | |
120 | {"sti", 0, 0xfb, _, NoModrm, { 0, 0, 0} }, | |
121 | ||
122 | {"add", 2, 0x0, _, DW|Modrm, { Reg, Reg|Mem, 0} }, | |
123 | {"add", 2, 0x83, 0, Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
124 | {"add", 2, 0x4, _, W|NoModrm, { Imm, Acc, 0} }, | |
125 | {"add", 2, 0x80, 0, W|Modrm, { Imm, Reg|Mem, 0} }, | |
126 | ||
127 | {"inc", 1, 0x40, _, ShortForm, { WordReg, 0, 0} }, | |
128 | {"inc", 1, 0xfe, 0, W|Modrm, { Reg|Mem, 0, 0} }, | |
129 | ||
130 | {"sub", 2, 0x28, _, DW|Modrm, { Reg, Reg|Mem, 0} }, | |
131 | {"sub", 2, 0x83, 5, Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
132 | {"sub", 2, 0x2c, _, W|NoModrm, { Imm, Acc, 0} }, | |
133 | {"sub", 2, 0x80, 5, W|Modrm, { Imm, Reg|Mem, 0} }, | |
134 | ||
135 | {"dec", 1, 0x48, _, ShortForm, { WordReg, 0, 0} }, | |
136 | {"dec", 1, 0xfe, 1, W|Modrm, { Reg|Mem, 0, 0} }, | |
137 | ||
138 | {"sbb", 2, 0x18, _, DW|Modrm, { Reg, Reg|Mem, 0} }, | |
139 | {"sbb", 2, 0x83, 3, Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
140 | {"sbb", 2, 0x1c, _, W|NoModrm, { Imm, Acc, 0} }, | |
141 | {"sbb", 2, 0x80, 3, W|Modrm, { Imm, Reg|Mem, 0} }, | |
142 | ||
143 | {"cmp", 2, 0x38, _, DW|Modrm, { Reg, Reg|Mem, 0} }, | |
144 | {"cmp", 2, 0x83, 7, Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
145 | {"cmp", 2, 0x3c, _, W|NoModrm, { Imm, Acc, 0} }, | |
146 | {"cmp", 2, 0x80, 7, W|Modrm, { Imm, Reg|Mem, 0} }, | |
147 | ||
148 | {"test", 2, 0x84, _, W|Modrm, { Reg|Mem, Reg, 0} }, | |
149 | {"test", 2, 0x84, _, W|Modrm, { Reg, Reg|Mem, 0} }, | |
150 | {"test", 2, 0xa8, _, W|NoModrm, { Imm, Acc, 0} }, | |
151 | {"test", 2, 0xf6, 0, W|Modrm, { Imm, Reg|Mem, 0} }, | |
152 | ||
153 | {"and", 2, 0x20, _, DW|Modrm, { Reg, Reg|Mem, 0} }, | |
154 | {"and", 2, 0x83, 4, Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
155 | {"and", 2, 0x24, _, W|NoModrm, { Imm, Acc, 0} }, | |
156 | {"and", 2, 0x80, 4, W|Modrm, { Imm, Reg|Mem, 0} }, | |
157 | ||
158 | {"or", 2, 0x08, _, DW|Modrm, { Reg, Reg|Mem, 0} }, | |
159 | {"or", 2, 0x83, 1, Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
160 | {"or", 2, 0x0c, _, W|NoModrm, { Imm, Acc, 0} }, | |
161 | {"or", 2, 0x80, 1, W|Modrm, { Imm, Reg|Mem, 0} }, | |
162 | ||
163 | {"xor", 2, 0x30, _, DW|Modrm, { Reg, Reg|Mem, 0} }, | |
164 | {"xor", 2, 0x83, 6, Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
165 | {"xor", 2, 0x34, _, W|NoModrm, { Imm, Acc, 0} }, | |
166 | {"xor", 2, 0x80, 6, W|Modrm, { Imm, Reg|Mem, 0} }, | |
167 | ||
c00435ed ILT |
168 | /* iclr with 1 operand is really xor with 2 operands. */ |
169 | {"clr", 1, 0x30, _, W|Modrm|iclrKludge, { Reg } }, | |
170 | ||
fc0d7441 ILT |
171 | {"adc", 2, 0x10, _, DW|Modrm, { Reg, Reg|Mem, 0} }, |
172 | {"adc", 2, 0x83, 2, Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
173 | {"adc", 2, 0x14, _, W|NoModrm, { Imm, Acc, 0} }, | |
174 | {"adc", 2, 0x80, 2, W|Modrm, { Imm, Reg|Mem, 0} }, | |
175 | ||
176 | {"neg", 1, 0xf6, 3, W|Modrm, { Reg|Mem, 0, 0} }, | |
177 | {"not", 1, 0xf6, 2, W|Modrm, { Reg|Mem, 0, 0} }, | |
178 | ||
179 | {"aaa", 0, 0x37, _, NoModrm, { 0, 0, 0} }, | |
180 | {"aas", 0, 0x3f, _, NoModrm, { 0, 0, 0} }, | |
181 | {"daa", 0, 0x27, _, NoModrm, { 0, 0, 0} }, | |
182 | {"das", 0, 0x2f, _, NoModrm, { 0, 0, 0} }, | |
183 | {"aad", 0, 0xd50a, _, NoModrm, { 0, 0, 0} }, | |
184 | {"aam", 0, 0xd40a, _, NoModrm, { 0, 0, 0} }, | |
ce868e5c JG |
185 | |
186 | /* conversion insns */ | |
187 | /* conversion: intel naming */ | |
a43022bd KR |
188 | {"cbw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} }, |
189 | {"cwd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} }, | |
190 | {"cwde", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} }, | |
191 | {"cdq", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} }, | |
ce868e5c | 192 | /* att naming */ |
a43022bd KR |
193 | {"cbtw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} }, |
194 | {"cwtl", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} }, | |
195 | {"cwtd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} }, | |
196 | {"cltd", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} }, | |
ce868e5c JG |
197 | |
198 | /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are | |
199 | expanding 64-bit multiplies, and *cannot* be selected to accomplish | |
200 | 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) | |
a43022bd | 201 | These multiplies can only be selected with single operand forms. */ |
fc0d7441 ILT |
202 | {"mul", 1, 0xf6, 4, W|Modrm, { Reg|Mem, 0, 0} }, |
203 | {"imul", 1, 0xf6, 5, W|Modrm, { Reg|Mem, 0, 0} }, | |
ce868e5c JG |
204 | |
205 | ||
206 | ||
207 | ||
208 | /* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields. | |
209 | These instructions are exceptions: 'imul $2, %eax, %ecx' would put | |
210 | '%eax' in the reg field and '%ecx' in the regmem field if we did not | |
211 | switch them. */ | |
fc0d7441 ILT |
212 | {"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, |
213 | {"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, { Imm8S, WordReg|Mem, WordReg} }, | |
214 | {"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, { Imm16|Imm32, WordReg|Mem, WordReg} }, | |
ce868e5c JG |
215 | /* |
216 | imul with 2 operands mimicks imul with 3 by puting register both | |
217 | in i.rm.reg & i.rm.regmem fields | |
218 | */ | |
fc0d7441 ILT |
219 | {"imul", 2, 0x6b, _, Modrm|imulKludge, { Imm8S, WordReg, 0} }, |
220 | {"imul", 2, 0x69, _, Modrm|imulKludge, { Imm16|Imm32, WordReg, 0} }, | |
221 | {"div", 1, 0xf6, 6, W|Modrm, { Reg|Mem, 0, 0} }, | |
222 | {"div", 2, 0xf6, 6, W|Modrm, { Reg|Mem, Acc, 0} }, | |
223 | {"idiv", 1, 0xf6, 7, W|Modrm, { Reg|Mem, 0, 0} }, | |
224 | {"idiv", 2, 0xf6, 7, W|Modrm, { Reg|Mem, Acc, 0} }, | |
225 | ||
226 | {"rol", 2, 0xd0, 0, W|Modrm, { Imm1, Reg|Mem, 0} }, | |
227 | {"rol", 2, 0xc0, 0, W|Modrm, { Imm8, Reg|Mem, 0} }, | |
228 | {"rol", 2, 0xd2, 0, W|Modrm, { ShiftCount, Reg|Mem, 0} }, | |
229 | {"rol", 1, 0xd0, 0, W|Modrm, { Reg|Mem, 0, 0} }, | |
230 | ||
231 | {"ror", 2, 0xd0, 1, W|Modrm, { Imm1, Reg|Mem, 0} }, | |
232 | {"ror", 2, 0xc0, 1, W|Modrm, { Imm8, Reg|Mem, 0} }, | |
233 | {"ror", 2, 0xd2, 1, W|Modrm, { ShiftCount, Reg|Mem, 0} }, | |
234 | {"ror", 1, 0xd0, 1, W|Modrm, { Reg|Mem, 0, 0} }, | |
235 | ||
236 | {"rcl", 2, 0xd0, 2, W|Modrm, { Imm1, Reg|Mem, 0} }, | |
237 | {"rcl", 2, 0xc0, 2, W|Modrm, { Imm8, Reg|Mem, 0} }, | |
238 | {"rcl", 2, 0xd2, 2, W|Modrm, { ShiftCount, Reg|Mem, 0} }, | |
239 | {"rcl", 1, 0xd0, 2, W|Modrm, { Reg|Mem, 0, 0} }, | |
240 | ||
241 | {"rcr", 2, 0xd0, 3, W|Modrm, { Imm1, Reg|Mem, 0} }, | |
242 | {"rcr", 2, 0xc0, 3, W|Modrm, { Imm8, Reg|Mem, 0} }, | |
243 | {"rcr", 2, 0xd2, 3, W|Modrm, { ShiftCount, Reg|Mem, 0} }, | |
244 | {"rcr", 1, 0xd0, 3, W|Modrm, { Reg|Mem, 0, 0} }, | |
245 | ||
246 | {"sal", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} }, | |
247 | {"sal", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} }, | |
248 | {"sal", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} }, | |
249 | {"sal", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} }, | |
250 | {"shl", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} }, | |
251 | {"shl", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} }, | |
252 | {"shl", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} }, | |
253 | {"shl", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} }, | |
254 | ||
255 | {"shld", 3, 0x0fa4, _, Modrm, { Imm8, WordReg, WordReg|Mem} }, | |
256 | {"shld", 3, 0x0fa5, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} }, | |
257 | {"shld", 2, 0x0fa5, _, Modrm, { WordReg, WordReg|Mem, 0} }, | |
258 | ||
259 | {"shr", 2, 0xd0, 5, W|Modrm, { Imm1, Reg|Mem, 0} }, | |
260 | {"shr", 2, 0xc0, 5, W|Modrm, { Imm8, Reg|Mem, 0} }, | |
261 | {"shr", 2, 0xd2, 5, W|Modrm, { ShiftCount, Reg|Mem, 0} }, | |
262 | {"shr", 1, 0xd0, 5, W|Modrm, { Reg|Mem, 0, 0} }, | |
263 | ||
264 | {"shrd", 3, 0x0fac, _, Modrm, { Imm8, WordReg, WordReg|Mem} }, | |
265 | {"shrd", 3, 0x0fad, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} }, | |
266 | {"shrd", 2, 0x0fad, _, Modrm, { WordReg, WordReg|Mem, 0} }, | |
267 | ||
268 | {"sar", 2, 0xd0, 7, W|Modrm, { Imm1, Reg|Mem, 0} }, | |
269 | {"sar", 2, 0xc0, 7, W|Modrm, { Imm8, Reg|Mem, 0} }, | |
270 | {"sar", 2, 0xd2, 7, W|Modrm, { ShiftCount, Reg|Mem, 0} }, | |
271 | {"sar", 1, 0xd0, 7, W|Modrm, { Reg|Mem, 0, 0} }, | |
ce868e5c JG |
272 | |
273 | /* control transfer instructions */ | |
274 | #define CALL_PC_RELATIVE 0xe8 | |
fc0d7441 | 275 | {"call", 1, 0xe8, _, JumpDword, { Disp32, 0, 0} }, |
a43022bd KR |
276 | {"call", 1, 0xff, 2, Modrm|Data32, { Reg|Mem|JumpAbsolute, 0, 0} }, |
277 | {"callw", 1, 0xff, 2, Modrm|Data16, { Reg|Mem|JumpAbsolute, 0, 0} }, | |
ce868e5c | 278 | #define CALL_FAR_IMMEDIATE 0x9a |
527cabaf | 279 | {"lcall", 2, 0x9a, _, JumpInterSegment, { Imm16, Imm32, 0} }, |
a43022bd KR |
280 | {"lcall", 1, 0xff, 3, Modrm|Data32, { Mem, 0, 0} }, |
281 | {"lcallw", 1, 0xff, 3, Modrm|Data16, { Mem, 0, 0} }, | |
ce868e5c JG |
282 | |
283 | #define JUMP_PC_RELATIVE 0xeb | |
fc0d7441 ILT |
284 | {"jmp", 1, 0xeb, _, Jump, { Disp, 0, 0} }, |
285 | {"jmp", 1, 0xff, 4, Modrm, { Reg32|Mem|JumpAbsolute, 0, 0} }, | |
ce868e5c | 286 | #define JUMP_FAR_IMMEDIATE 0xea |
fc0d7441 | 287 | {"ljmp", 2, 0xea, _, JumpInterSegment, { Imm16, Imm32, 0} }, |
a43022bd KR |
288 | {"ljmp", 1, 0xff, 5, Modrm|Data32, { Mem, 0, 0} }, |
289 | ||
290 | {"ret", 0, 0xc3, _, NoModrm|Data32, { 0, 0, 0} }, | |
291 | {"ret", 1, 0xc2, _, NoModrm|Data32, { Imm16, 0, 0} }, | |
292 | {"retw", 0, 0xc3, _, NoModrm|Data16, { 0, 0, 0} }, | |
293 | {"retw", 1, 0xc2, _, NoModrm|Data16, { Imm16, 0, 0} }, | |
294 | {"lret", 0, 0xcb, _, NoModrm|Data32, { 0, 0, 0} }, | |
295 | {"lret", 1, 0xca, _, NoModrm|Data32, { Imm16, 0, 0} }, | |
296 | {"lretw", 0, 0xcb, _, NoModrm|Data16, { 0, 0, 0} }, | |
297 | {"lretw", 1, 0xca, _, NoModrm|Data16, { Imm16, 0, 0} }, | |
cd22144a KR |
298 | {"enter", 2, 0xc8, _, NoModrm|Data32, { Imm16, Imm8, 0} }, |
299 | {"leave", 0, 0xc9, _, NoModrm|Data32, { 0, 0, 0} }, | |
300 | {"enterw", 2, 0xc8, _, NoModrm|Data16, { Imm16, Imm8, 0} }, | |
301 | {"leavew", 0, 0xc9, _, NoModrm|Data16, { 0, 0, 0} }, | |
ce868e5c JG |
302 | |
303 | /* conditional jumps */ | |
fc0d7441 | 304 | {"jo", 1, 0x70, _, Jump, { Disp, 0, 0} }, |
ce868e5c | 305 | |
fc0d7441 | 306 | {"jno", 1, 0x71, _, Jump, { Disp, 0, 0} }, |
ce868e5c | 307 | |
fc0d7441 ILT |
308 | {"jb", 1, 0x72, _, Jump, { Disp, 0, 0} }, |
309 | {"jc", 1, 0x72, _, Jump, { Disp, 0, 0} }, | |
310 | {"jnae", 1, 0x72, _, Jump, { Disp, 0, 0} }, | |
ce868e5c | 311 | |
fc0d7441 ILT |
312 | {"jnb", 1, 0x73, _, Jump, { Disp, 0, 0} }, |
313 | {"jnc", 1, 0x73, _, Jump, { Disp, 0, 0} }, | |
314 | {"jae", 1, 0x73, _, Jump, { Disp, 0, 0} }, | |
ce868e5c | 315 | |
fc0d7441 ILT |
316 | {"je", 1, 0x74, _, Jump, { Disp, 0, 0} }, |
317 | {"jz", 1, 0x74, _, Jump, { Disp, 0, 0} }, | |
ce868e5c | 318 | |
fc0d7441 ILT |
319 | {"jne", 1, 0x75, _, Jump, { Disp, 0, 0} }, |
320 | {"jnz", 1, 0x75, _, Jump, { Disp, 0, 0} }, | |
ce868e5c | 321 | |
fc0d7441 ILT |
322 | {"jbe", 1, 0x76, _, Jump, { Disp, 0, 0} }, |
323 | {"jna", 1, 0x76, _, Jump, { Disp, 0, 0} }, | |
ce868e5c | 324 | |
fc0d7441 ILT |
325 | {"jnbe", 1, 0x77, _, Jump, { Disp, 0, 0} }, |
326 | {"ja", 1, 0x77, _, Jump, { Disp, 0, 0} }, | |
ce868e5c | 327 | |
fc0d7441 | 328 | {"js", 1, 0x78, _, Jump, { Disp, 0, 0} }, |
ce868e5c | 329 | |
fc0d7441 | 330 | {"jns", 1, 0x79, _, Jump, { Disp, 0, 0} }, |
ce868e5c | 331 | |
fc0d7441 ILT |
332 | {"jp", 1, 0x7a, _, Jump, { Disp, 0, 0} }, |
333 | {"jpe", 1, 0x7a, _, Jump, { Disp, 0, 0} }, | |
ce868e5c | 334 | |
fc0d7441 ILT |
335 | {"jnp", 1, 0x7b, _, Jump, { Disp, 0, 0} }, |
336 | {"jpo", 1, 0x7b, _, Jump, { Disp, 0, 0} }, | |
ce868e5c | 337 | |
fc0d7441 ILT |
338 | {"jl", 1, 0x7c, _, Jump, { Disp, 0, 0} }, |
339 | {"jnge", 1, 0x7c, _, Jump, { Disp, 0, 0} }, | |
ce868e5c | 340 | |
fc0d7441 ILT |
341 | {"jnl", 1, 0x7d, _, Jump, { Disp, 0, 0} }, |
342 | {"jge", 1, 0x7d, _, Jump, { Disp, 0, 0} }, | |
ce868e5c | 343 | |
fc0d7441 ILT |
344 | {"jle", 1, 0x7e, _, Jump, { Disp, 0, 0} }, |
345 | {"jng", 1, 0x7e, _, Jump, { Disp, 0, 0} }, | |
ce868e5c | 346 | |
fc0d7441 ILT |
347 | {"jnle", 1, 0x7f, _, Jump, { Disp, 0, 0} }, |
348 | {"jg", 1, 0x7f, _, Jump, { Disp, 0, 0} }, | |
ce868e5c | 349 | |
ce868e5c | 350 | #define IS_JUMP_ON_CX_ZERO(o) \ |
ce868e5c JG |
351 | (o == 0xe3) |
352 | ||
c2367582 | 353 | /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ |
a43022bd KR |
354 | {"jcxz", 1, 0xe3, _, JumpByte|Data16, { Disp, 0, 0} }, |
355 | {"jecxz", 1, 0xe3, _, JumpByte|Data32, { Disp, 0, 0} }, | |
ce868e5c JG |
356 | |
357 | #define IS_LOOP_ECX_TIMES(o) \ | |
358 | (o == 0xe2 || o == 0xe1 || o == 0xe0) | |
359 | ||
fc0d7441 | 360 | {"loop", 1, 0xe2, _, JumpByte, { Disp, 0, 0} }, |
ce868e5c | 361 | |
fc0d7441 ILT |
362 | {"loopz", 1, 0xe1, _, JumpByte, { Disp, 0, 0} }, |
363 | {"loope", 1, 0xe1, _, JumpByte, { Disp, 0, 0} }, | |
ce868e5c | 364 | |
fc0d7441 ILT |
365 | {"loopnz", 1, 0xe0, _, JumpByte, { Disp, 0, 0} }, |
366 | {"loopne", 1, 0xe0, _, JumpByte, { Disp, 0, 0} }, | |
ce868e5c JG |
367 | |
368 | /* set byte on flag instructions */ | |
fc0d7441 | 369 | {"seto", 1, 0x0f90, 0, Modrm, { Reg8|Mem, 0, 0} }, |
ce868e5c | 370 | |
fc0d7441 | 371 | {"setno", 1, 0x0f91, 0, Modrm, { Reg8|Mem, 0, 0} }, |
ce868e5c | 372 | |
fc0d7441 ILT |
373 | {"setb", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, |
374 | {"setc", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, | |
375 | {"setnae", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, | |
ce868e5c | 376 | |
fc0d7441 ILT |
377 | {"setnb", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, |
378 | {"setnc", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, | |
379 | {"setae", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, | |
ce868e5c | 380 | |
fc0d7441 ILT |
381 | {"sete", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} }, |
382 | {"setz", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} }, | |
ce868e5c | 383 | |
fc0d7441 ILT |
384 | {"setne", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} }, |
385 | {"setnz", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} }, | |
ce868e5c | 386 | |
fc0d7441 ILT |
387 | {"setbe", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} }, |
388 | {"setna", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} }, | |
ce868e5c | 389 | |
fc0d7441 ILT |
390 | {"setnbe", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} }, |
391 | {"seta", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} }, | |
ce868e5c | 392 | |
fc0d7441 | 393 | {"sets", 1, 0x0f98, 0, Modrm, { Reg8|Mem, 0, 0} }, |
ce868e5c | 394 | |
fc0d7441 | 395 | {"setns", 1, 0x0f99, 0, Modrm, { Reg8|Mem, 0, 0} }, |
ce868e5c | 396 | |
fc0d7441 ILT |
397 | {"setp", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} }, |
398 | {"setpe", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} }, | |
ce868e5c | 399 | |
fc0d7441 ILT |
400 | {"setnp", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} }, |
401 | {"setpo", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} }, | |
ce868e5c | 402 | |
fc0d7441 ILT |
403 | {"setl", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} }, |
404 | {"setnge", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} }, | |
ce868e5c | 405 | |
fc0d7441 ILT |
406 | {"setnl", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} }, |
407 | {"setge", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} }, | |
ce868e5c | 408 | |
fc0d7441 ILT |
409 | {"setle", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} }, |
410 | {"setng", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} }, | |
ce868e5c | 411 | |
fc0d7441 ILT |
412 | {"setnle", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} }, |
413 | {"setg", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} }, | |
ce868e5c JG |
414 | |
415 | #define IS_STRING_INSTRUCTION(o) \ | |
416 | ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \ | |
417 | (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \ | |
418 | (o) == 0xd7) | |
419 | ||
420 | /* string manipulation */ | |
fc0d7441 ILT |
421 | {"cmps", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} }, |
422 | {"scmp", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} }, | |
423 | {"ins", 0, 0x6c, _, W|NoModrm, { 0, 0, 0} }, | |
424 | {"outs", 0, 0x6e, _, W|NoModrm, { 0, 0, 0} }, | |
425 | {"lods", 0, 0xac, _, W|NoModrm, { 0, 0, 0} }, | |
426 | {"slod", 0, 0xac, _, W|NoModrm, { 0, 0, 0} }, | |
427 | {"movs", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} }, | |
428 | {"smov", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} }, | |
429 | {"scas", 0, 0xae, _, W|NoModrm, { 0, 0, 0} }, | |
430 | {"ssca", 0, 0xae, _, W|NoModrm, { 0, 0, 0} }, | |
431 | {"stos", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} }, | |
432 | {"ssto", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} }, | |
433 | {"xlat", 0, 0xd7, _, NoModrm, { 0, 0, 0} }, | |
ce868e5c JG |
434 | |
435 | /* bit manipulation */ | |
fc0d7441 ILT |
436 | {"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} }, |
437 | {"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} }, | |
438 | {"bt", 2, 0x0fa3, _, Modrm, { Reg, Reg|Mem, 0} }, | |
439 | {"bt", 2, 0x0fba, 4, Modrm, { Imm8, Reg|Mem, 0} }, | |
440 | {"btc", 2, 0x0fbb, _, Modrm, { Reg, Reg|Mem, 0} }, | |
441 | {"btc", 2, 0x0fba, 7, Modrm, { Imm8, Reg|Mem, 0} }, | |
442 | {"btr", 2, 0x0fb3, _, Modrm, { Reg, Reg|Mem, 0} }, | |
443 | {"btr", 2, 0x0fba, 6, Modrm, { Imm8, Reg|Mem, 0} }, | |
444 | {"bts", 2, 0x0fab, _, Modrm, { Reg, Reg|Mem, 0} }, | |
445 | {"bts", 2, 0x0fba, 5, Modrm, { Imm8, Reg|Mem, 0} }, | |
ce868e5c JG |
446 | |
447 | /* interrupts & op. sys insns */ | |
a43022bd KR |
448 | /* See gas/config/tc-i386.c for conversion of 'int $3' into the special |
449 | int 3 insn. */ | |
ce868e5c JG |
450 | #define INT_OPCODE 0xcd |
451 | #define INT3_OPCODE 0xcc | |
fc0d7441 ILT |
452 | {"int", 1, 0xcd, _, NoModrm, { Imm8, 0, 0} }, |
453 | {"int3", 0, 0xcc, _, NoModrm, { 0, 0, 0} }, | |
454 | {"into", 0, 0xce, _, NoModrm, { 0, 0, 0} }, | |
a43022bd KR |
455 | {"iret", 0, 0xcf, _, NoModrm|Data32, { 0, 0, 0} }, |
456 | {"iretw", 0, 0xcf, _, NoModrm|Data16, { 0, 0, 0} }, | |
cd22144a | 457 | /* i386sl, i486sl, later 486, and Pentium */ |
a43022bd | 458 | {"rsm", 0, 0x0faa, _, NoModrm,{ 0, 0, 0} }, |
ce868e5c | 459 | |
a43022bd KR |
460 | {"boundl", 2, 0x62, _, Modrm|Data32, { Reg32, Mem, 0} }, |
461 | {"boundw", 2, 0x62, _, Modrm|Data16, { Reg16, Mem, 0} }, | |
ce868e5c | 462 | |
fc0d7441 ILT |
463 | {"hlt", 0, 0xf4, _, NoModrm, { 0, 0, 0} }, |
464 | {"wait", 0, 0x9b, _, NoModrm, { 0, 0, 0} }, | |
ce868e5c | 465 | /* nop is actually 'xchgl %eax, %eax' */ |
fc0d7441 | 466 | {"nop", 0, 0x90, _, NoModrm, { 0, 0, 0} }, |
ce868e5c JG |
467 | |
468 | /* protection control */ | |
fc0d7441 ILT |
469 | {"arpl", 2, 0x63, _, Modrm, { Reg16, Reg16|Mem, 0} }, |
470 | {"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, | |
ffd42166 ILT |
471 | {"lgdt", 1, 0x0f01, 2, Modrm, { Mem, 0, 0} }, |
472 | {"lidt", 1, 0x0f01, 3, Modrm, { Mem, 0, 0} }, | |
fc0d7441 ILT |
473 | {"lldt", 1, 0x0f00, 2, Modrm, { WordReg|Mem, 0, 0} }, |
474 | {"lmsw", 1, 0x0f01, 6, Modrm, { WordReg|Mem, 0, 0} }, | |
475 | {"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, | |
476 | {"ltr", 1, 0x0f00, 3, Modrm, { WordReg|Mem, 0, 0} }, | |
477 | ||
478 | {"sgdt", 1, 0x0f01, 0, Modrm, { Mem, 0, 0} }, | |
479 | {"sidt", 1, 0x0f01, 1, Modrm, { Mem, 0, 0} }, | |
480 | {"sldt", 1, 0x0f00, 0, Modrm, { WordReg|Mem, 0, 0} }, | |
481 | {"smsw", 1, 0x0f01, 4, Modrm, { WordReg|Mem, 0, 0} }, | |
482 | {"str", 1, 0x0f00, 1, Modrm, { Reg16|Mem, 0, 0} }, | |
483 | ||
484 | {"verr", 1, 0x0f00, 4, Modrm, { WordReg|Mem, 0, 0} }, | |
485 | {"verw", 1, 0x0f00, 5, Modrm, { WordReg|Mem, 0, 0} }, | |
ce868e5c JG |
486 | |
487 | /* floating point instructions */ | |
488 | ||
489 | /* load */ | |
fc0d7441 ILT |
490 | {"fld", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ |
491 | {"flds", 1, 0xd9, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem float */ | |
492 | {"fldl", 1, 0xdd, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem double */ | |
493 | {"fldl", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ | |
494 | {"fild", 1, 0xdf, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem word (16) */ | |
495 | {"fildl", 1, 0xdb, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem dword (32) */ | |
496 | {"fildq",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */ | |
497 | {"fildll",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */ | |
498 | {"fldt", 1, 0xdb, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem efloat */ | |
499 | {"fbld", 1, 0xdf, 4, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem bcd */ | |
ce868e5c JG |
500 | |
501 | /* store (no pop) */ | |
fc0d7441 ILT |
502 | {"fst", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ |
503 | {"fsts", 1, 0xd9, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */ | |
504 | {"fstl", 1, 0xdd, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */ | |
505 | {"fstl", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ | |
506 | {"fist", 1, 0xdf, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */ | |
507 | {"fistl", 1, 0xdb, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */ | |
ce868e5c JG |
508 | |
509 | /* store (with pop) */ | |
fc0d7441 ILT |
510 | {"fstp", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */ |
511 | {"fstps", 1, 0xd9, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */ | |
512 | {"fstpl", 1, 0xdd, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */ | |
513 | {"fstpl", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */ | |
514 | {"fistp", 1, 0xdf, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */ | |
515 | {"fistpl",1, 0xdb, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */ | |
516 | {"fistpq",1, 0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */ | |
517 | {"fistpll",1,0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */ | |
518 | {"fstpt", 1, 0xdb, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem efloat */ | |
519 | {"fbstp", 1, 0xdf, 6, Modrm, { Mem, 0, 0} }, /* %st0 --> mem bcd */ | |
ce868e5c JG |
520 | |
521 | /* exchange %st<n> with %st0 */ | |
fc0d7441 | 522 | {"fxch", 1, 0xd9c8, _, ShortForm, { FloatReg, 0, 0} }, |
a43022bd | 523 | {"fxch", 0, 0xd9c9, _, NoModrm, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */ |
ce868e5c JG |
524 | |
525 | /* comparison (without pop) */ | |
fc0d7441 ILT |
526 | {"fcom", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} }, |
527 | {"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */ | |
9df6ca2f | 528 | {"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */ |
fc0d7441 ILT |
529 | {"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */ |
530 | {"fcoml", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} }, | |
9df6ca2f | 531 | {"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */ |
ce868e5c JG |
532 | |
533 | /* comparison (with pop) */ | |
fc0d7441 | 534 | {"fcomp", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} }, |
c2367582 | 535 | {"fcomp", 0, 0xd8d9, _, NoModrm, {0, 0, 0} }, /* fcomp %st, %st(1) */ |
fc0d7441 | 536 | {"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */ |
9df6ca2f | 537 | {"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */ |
fc0d7441 ILT |
538 | {"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */ |
539 | {"fcompl", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} }, | |
9df6ca2f | 540 | {"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */ |
fc0d7441 | 541 | {"fcompp", 0, 0xded9, _, NoModrm, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */ |
ce868e5c JG |
542 | |
543 | /* unordered comparison (with pop) */ | |
fc0d7441 ILT |
544 | {"fucom", 1, 0xdde0, _, ShortForm, { FloatReg, 0, 0} }, |
545 | {"fucomp", 1, 0xdde8, _, ShortForm, { FloatReg, 0, 0} }, | |
546 | {"fucompp", 0, 0xdae9, _, NoModrm, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */ | |
ce868e5c | 547 | |
fc0d7441 ILT |
548 | {"ftst", 0, 0xd9e4, _, NoModrm, { 0, 0, 0} }, /* test %st0 */ |
549 | {"fxam", 0, 0xd9e5, _, NoModrm, { 0, 0, 0} }, /* examine %st0 */ | |
ce868e5c JG |
550 | |
551 | /* load constants into %st0 */ | |
fc0d7441 ILT |
552 | {"fld1", 0, 0xd9e8, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 1.0 */ |
553 | {"fldl2t", 0, 0xd9e9, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(10) */ | |
554 | {"fldl2e", 0, 0xd9ea, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(e) */ | |
555 | {"fldpi", 0, 0xd9eb, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- pi */ | |
556 | {"fldlg2", 0, 0xd9ec, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log10(2) */ | |
557 | {"fldln2", 0, 0xd9ed, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- ln(2) */ | |
558 | {"fldz", 0, 0xd9ee, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 0.0 */ | |
ce868e5c JG |
559 | |
560 | /* arithmetic */ | |
561 | ||
562 | /* add */ | |
fc0d7441 ILT |
563 | {"fadd", 1, 0xd8c0, _, ShortForm, { FloatReg, 0, 0} }, |
564 | {"fadd", 2, 0xd8c0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, | |
565 | {"fadd", 0, 0xdcc1, _, NoModrm, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */ | |
527cabaf ILT |
566 | {"faddp", 1, 0xdec0, _, ShortForm, { FloatReg, 0, 0} }, |
567 | {"faddp", 2, 0xdec0, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
568 | {"faddp", 2, 0xdec0, _, ShortForm, { FloatAcc, FloatReg, 0} }, | |
fc0d7441 ILT |
569 | {"faddp", 0, 0xdec1, _, NoModrm, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */ |
570 | {"fadds", 1, 0xd8, 0, Modrm, { Mem, 0, 0} }, | |
571 | {"fiaddl", 1, 0xda, 0, Modrm, { Mem, 0, 0} }, | |
572 | {"faddl", 1, 0xdc, 0, Modrm, { Mem, 0, 0} }, | |
573 | {"fiadds", 1, 0xde, 0, Modrm, { Mem, 0, 0} }, | |
ce868e5c JG |
574 | |
575 | /* sub */ | |
576 | /* Note: intel has decided that certain of these operations are reversed | |
577 | in assembler syntax. */ | |
fc0d7441 ILT |
578 | {"fsub", 1, 0xd8e0, _, ShortForm, { FloatReg, 0, 0} }, |
579 | {"fsub", 2, 0xd8e0, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
ce868e5c | 580 | #ifdef NON_BROKEN_OPCODES |
fc0d7441 | 581 | {"fsub", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
ce868e5c | 582 | #else |
fc0d7441 | 583 | {"fsub", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
ce868e5c | 584 | #endif |
fc0d7441 | 585 | {"fsub", 0, 0xdce1, _, NoModrm, { 0, 0, 0} }, |
c00435ed ILT |
586 | {"fsubp", 1, 0xdee8, _, ShortForm, { FloatReg, 0, 0} }, |
587 | {"fsubp", 2, 0xdee8, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
ce868e5c | 588 | #ifdef NON_BROKEN_OPCODES |
fc0d7441 | 589 | {"fsubp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
654b0845 | 590 | {"fsubp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} }, |
ce868e5c | 591 | #else |
c0d7b534 | 592 | {"fsubp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
654b0845 | 593 | {"fsubp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} }, |
ce868e5c | 594 | #endif |
fc0d7441 ILT |
595 | {"fsubs", 1, 0xd8, 4, Modrm, { Mem, 0, 0} }, |
596 | {"fisubl", 1, 0xda, 4, Modrm, { Mem, 0, 0} }, | |
597 | {"fsubl", 1, 0xdc, 4, Modrm, { Mem, 0, 0} }, | |
598 | {"fisubs", 1, 0xde, 4, Modrm, { Mem, 0, 0} }, | |
ce868e5c JG |
599 | |
600 | /* sub reverse */ | |
fc0d7441 ILT |
601 | {"fsubr", 1, 0xd8e8, _, ShortForm, { FloatReg, 0, 0} }, |
602 | {"fsubr", 2, 0xd8e8, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
ce868e5c | 603 | #ifdef NON_BROKEN_OPCODES |
fc0d7441 | 604 | {"fsubr", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
ce868e5c | 605 | #else |
fc0d7441 | 606 | {"fsubr", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
ce868e5c | 607 | #endif |
fc0d7441 | 608 | {"fsubr", 0, 0xdce9, _, NoModrm, { 0, 0, 0} }, |
c00435ed ILT |
609 | {"fsubrp", 1, 0xdee0, _, ShortForm, { FloatReg, 0, 0} }, |
610 | {"fsubrp", 2, 0xdee0, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
ce868e5c | 611 | #ifdef NON_BROKEN_OPCODES |
fc0d7441 | 612 | {"fsubrp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
654b0845 | 613 | {"fsubrp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} }, |
ce868e5c | 614 | #else |
c0d7b534 | 615 | {"fsubrp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
654b0845 | 616 | {"fsubrp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} }, |
ce868e5c | 617 | #endif |
fc0d7441 ILT |
618 | {"fsubrs", 1, 0xd8, 5, Modrm, { Mem, 0, 0} }, |
619 | {"fisubrl", 1, 0xda, 5, Modrm, { Mem, 0, 0} }, | |
620 | {"fsubrl", 1, 0xdc, 5, Modrm, { Mem, 0, 0} }, | |
621 | {"fisubrs", 1, 0xde, 5, Modrm, { Mem, 0, 0} }, | |
ce868e5c JG |
622 | |
623 | /* mul */ | |
fc0d7441 ILT |
624 | {"fmul", 1, 0xd8c8, _, ShortForm, { FloatReg, 0, 0} }, |
625 | {"fmul", 2, 0xd8c8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, | |
626 | {"fmul", 0, 0xdcc9, _, NoModrm, { 0, 0, 0} }, | |
527cabaf ILT |
627 | {"fmulp", 1, 0xdec8, _, ShortForm, { FloatReg, 0, 0} }, |
628 | {"fmulp", 2, 0xdec8, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
629 | {"fmulp", 2, 0xdec8, _, ShortForm, { FloatAcc, FloatReg, 0} }, | |
fc0d7441 ILT |
630 | {"fmulp", 0, 0xdec9, _, NoModrm, { 0, 0, 0} }, |
631 | {"fmuls", 1, 0xd8, 1, Modrm, { Mem, 0, 0} }, | |
632 | {"fimull", 1, 0xda, 1, Modrm, { Mem, 0, 0} }, | |
633 | {"fmull", 1, 0xdc, 1, Modrm, { Mem, 0, 0} }, | |
634 | {"fimuls", 1, 0xde, 1, Modrm, { Mem, 0, 0} }, | |
ce868e5c JG |
635 | |
636 | /* div */ | |
637 | /* Note: intel has decided that certain of these operations are reversed | |
638 | in assembler syntax. */ | |
fc0d7441 ILT |
639 | {"fdiv", 1, 0xd8f0, _, ShortForm, { FloatReg, 0, 0} }, |
640 | {"fdiv", 2, 0xd8f0, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
ce868e5c | 641 | #ifdef NON_BROKEN_OPCODES |
fc0d7441 | 642 | {"fdiv", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
ce868e5c | 643 | #else |
fc0d7441 | 644 | {"fdiv", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
ce868e5c | 645 | #endif |
fc0d7441 | 646 | {"fdiv", 0, 0xdcf1, _, NoModrm, { 0, 0, 0} }, |
c00435ed ILT |
647 | {"fdivp", 1, 0xdef8, _, ShortForm, { FloatReg, 0, 0} }, |
648 | {"fdivp", 2, 0xdef8, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
ce868e5c | 649 | #ifdef NON_BROKEN_OPCODES |
fc0d7441 | 650 | {"fdivp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
654b0845 | 651 | {"fdivp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} }, |
ce868e5c | 652 | #else |
c0d7b534 | 653 | {"fdivp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
654b0845 | 654 | {"fdivp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} }, |
ce868e5c | 655 | #endif |
fc0d7441 ILT |
656 | {"fdivs", 1, 0xd8, 6, Modrm, { Mem, 0, 0} }, |
657 | {"fidivl", 1, 0xda, 6, Modrm, { Mem, 0, 0} }, | |
658 | {"fdivl", 1, 0xdc, 6, Modrm, { Mem, 0, 0} }, | |
659 | {"fidivs", 1, 0xde, 6, Modrm, { Mem, 0, 0} }, | |
ce868e5c JG |
660 | |
661 | /* div reverse */ | |
fc0d7441 ILT |
662 | {"fdivr", 1, 0xd8f8, _, ShortForm, { FloatReg, 0, 0} }, |
663 | {"fdivr", 2, 0xd8f8, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
ce868e5c | 664 | #ifdef NON_BROKEN_OPCODES |
fc0d7441 | 665 | {"fdivr", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
ce868e5c | 666 | #else |
fc0d7441 | 667 | {"fdivr", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
ce868e5c | 668 | #endif |
fc0d7441 | 669 | {"fdivr", 0, 0xdcf9, _, NoModrm, { 0, 0, 0} }, |
c00435ed ILT |
670 | {"fdivrp", 1, 0xdef0, _, ShortForm, { FloatReg, 0, 0} }, |
671 | {"fdivrp", 2, 0xdef0, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
ce868e5c | 672 | #ifdef NON_BROKEN_OPCODES |
fc0d7441 | 673 | {"fdivrp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
654b0845 | 674 | {"fdivrp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} }, |
ce868e5c | 675 | #else |
c0d7b534 | 676 | {"fdivrp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} }, |
654b0845 | 677 | {"fdivrp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} }, |
ce868e5c | 678 | #endif |
fc0d7441 ILT |
679 | {"fdivrs", 1, 0xd8, 7, Modrm, { Mem, 0, 0} }, |
680 | {"fidivrl", 1, 0xda, 7, Modrm, { Mem, 0, 0} }, | |
681 | {"fdivrl", 1, 0xdc, 7, Modrm, { Mem, 0, 0} }, | |
682 | {"fidivrs", 1, 0xde, 7, Modrm, { Mem, 0, 0} }, | |
683 | ||
684 | {"f2xm1", 0, 0xd9f0, _, NoModrm, { 0, 0, 0} }, | |
685 | {"fyl2x", 0, 0xd9f1, _, NoModrm, { 0, 0, 0} }, | |
686 | {"fptan", 0, 0xd9f2, _, NoModrm, { 0, 0, 0} }, | |
687 | {"fpatan", 0, 0xd9f3, _, NoModrm, { 0, 0, 0} }, | |
688 | {"fxtract", 0, 0xd9f4, _, NoModrm, { 0, 0, 0} }, | |
689 | {"fprem1", 0, 0xd9f5, _, NoModrm, { 0, 0, 0} }, | |
690 | {"fdecstp", 0, 0xd9f6, _, NoModrm, { 0, 0, 0} }, | |
691 | {"fincstp", 0, 0xd9f7, _, NoModrm, { 0, 0, 0} }, | |
692 | {"fprem", 0, 0xd9f8, _, NoModrm, { 0, 0, 0} }, | |
693 | {"fyl2xp1", 0, 0xd9f9, _, NoModrm, { 0, 0, 0} }, | |
694 | {"fsqrt", 0, 0xd9fa, _, NoModrm, { 0, 0, 0} }, | |
695 | {"fsincos", 0, 0xd9fb, _, NoModrm, { 0, 0, 0} }, | |
696 | {"frndint", 0, 0xd9fc, _, NoModrm, { 0, 0, 0} }, | |
697 | {"fscale", 0, 0xd9fd, _, NoModrm, { 0, 0, 0} }, | |
698 | {"fsin", 0, 0xd9fe, _, NoModrm, { 0, 0, 0} }, | |
699 | {"fcos", 0, 0xd9ff, _, NoModrm, { 0, 0, 0} }, | |
700 | ||
701 | {"fchs", 0, 0xd9e0, _, NoModrm, { 0, 0, 0} }, | |
702 | {"fabs", 0, 0xd9e1, _, NoModrm, { 0, 0, 0} }, | |
ce868e5c JG |
703 | |
704 | /* processor control */ | |
ffd42166 ILT |
705 | {"fninit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} }, |
706 | {"finit", 0, 0xdbe3, _, FWait|NoModrm, { 0, 0, 0} }, | |
707 | {"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} }, | |
708 | {"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} }, | |
709 | {"fstcw", 1, 0xd9, 7, FWait|Modrm, { Mem, 0, 0} }, | |
710 | {"fnstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} }, | |
711 | {"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} }, | |
712 | {"fnstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} }, | |
713 | {"fstsw", 1, 0xdfe0, _, FWait|NoModrm, { Acc, 0, 0} }, | |
714 | {"fstsw", 1, 0xdd, 7, FWait|Modrm, { Mem, 0, 0} }, | |
715 | {"fstsw", 0, 0xdfe0, _, FWait|NoModrm, { 0, 0, 0} }, | |
716 | {"fnclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} }, | |
717 | {"fclex", 0, 0xdbe2, _, FWait|NoModrm, { 0, 0, 0} }, | |
718 | {"fnstenv",1, 0xd9, 6, Modrm, { Mem, 0, 0} }, | |
719 | {"fstenv", 1, 0xd9, 6, FWait|Modrm, { Mem, 0, 0} }, | |
720 | {"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} }, | |
721 | {"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} }, | |
722 | {"fsave", 1, 0xdd, 6, FWait|Modrm, { Mem, 0, 0} }, | |
723 | {"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} }, | |
724 | /* Short forms of fldenv, fstenv use data size prefix. (At least I | |
725 | think so. The PentPro prog ref I have says address size in one | |
726 | place, operand size elsewhere). FIXME: Are these the right names? */ | |
727 | {"fnstenvs",1, 0xd9, 6, Modrm|Data16, { Mem, 0, 0} }, | |
728 | {"fstenvs", 1, 0xd9, 6, FWait|Modrm|Data16, { Mem, 0, 0} }, | |
729 | {"fldenvs", 1, 0xd9, 4, Modrm|Data16, { Mem, 0, 0} }, | |
730 | ||
731 | {"ffree", 1, 0xddc0, _, ShortForm, { FloatReg, 0, 0} }, | |
527cabaf | 732 | /* P6:free st(i), pop st */ |
ffd42166 ILT |
733 | {"ffreep", 1, 0xdfc0, _, ShortForm, { FloatReg, 0, 0} }, |
734 | {"fnop", 0, 0xd9d0, _, NoModrm, { 0, 0, 0} }, | |
735 | #define FWAIT_OPCODE 0x9b | |
736 | {"fwait", 0, 0x9b, _, NoModrm, { 0, 0, 0} }, | |
ce868e5c JG |
737 | |
738 | /* | |
739 | opcode prefixes; we allow them as seperate insns too | |
740 | (see prefix table below) | |
741 | */ | |
fc0d7441 ILT |
742 | {"aword", 0, 0x67, _, NoModrm, { 0, 0, 0} }, |
743 | {"addr16", 0, 0x67, _, NoModrm, { 0, 0, 0} }, | |
744 | {"word", 0, 0x66, _, NoModrm, { 0, 0, 0} }, | |
745 | {"data16", 0, 0x66, _, NoModrm, { 0, 0, 0} }, | |
746 | {"lock", 0, 0xf0, _, NoModrm, { 0, 0, 0} }, | |
747 | {"cs", 0, 0x2e, _, NoModrm, { 0, 0, 0} }, | |
748 | {"ds", 0, 0x3e, _, NoModrm, { 0, 0, 0} }, | |
749 | {"es", 0, 0x26, _, NoModrm, { 0, 0, 0} }, | |
750 | {"fs", 0, 0x64, _, NoModrm, { 0, 0, 0} }, | |
751 | {"gs", 0, 0x65, _, NoModrm, { 0, 0, 0} }, | |
752 | {"ss", 0, 0x36, _, NoModrm, { 0, 0, 0} }, | |
753 | {"rep", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, | |
754 | {"repe", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, | |
755 | {"repz", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, | |
756 | {"repne", 0, 0xf2, _, NoModrm, { 0, 0, 0} }, | |
757 | {"repnz", 0, 0xf2, _, NoModrm, { 0, 0, 0} }, | |
758 | ||
759 | /* 486 extensions */ | |
760 | ||
761 | {"bswap", 1, 0x0fc8, _, ShortForm, { Reg32,0,0 } }, | |
527cabaf ILT |
762 | {"xadd", 2, 0x0fc0, _, W|Modrm, { Reg, Reg|Mem, 0 } }, |
763 | {"cmpxchg", 2, 0x0fb0, _, W|Modrm, { Reg, Reg|Mem, 0 } }, | |
fc0d7441 ILT |
764 | {"invd", 0, 0x0f08, _, NoModrm, { 0, 0, 0} }, |
765 | {"wbinvd", 0, 0x0f09, _, NoModrm, { 0, 0, 0} }, | |
766 | {"invlpg", 1, 0x0f01, 7, Modrm, { Mem, 0, 0} }, | |
767 | ||
cd22144a KR |
768 | /* 586 and late 486 extensions */ |
769 | {"cpuid", 0, 0x0fa2, _, NoModrm, { 0, 0, 0} }, | |
770 | ||
771 | /* Pentium extensions */ | |
772 | {"wrmsr", 0, 0x0f30, _, NoModrm, { 0, 0, 0} }, | |
773 | {"rdtsc", 0, 0x0f31, _, NoModrm, { 0, 0, 0} }, | |
774 | {"rdmsr", 0, 0x0f32, _, NoModrm, { 0, 0, 0} }, | |
527cabaf ILT |
775 | {"cmpxchg8b", 1, 0x0fc7, 1, Modrm, { Mem, 0, 0} }, |
776 | ||
777 | /* Pentium Pro extensions */ | |
778 | {"rdpmc", 0, 0x0f33, _, NoModrm, { 0, 0, 0} }, | |
779 | ||
19f080ab | 780 | {"ud2", 0, 0x0f0b, _, NoModrm, {0, 0, 0} }, /* official undefined instr. */ |
c2367582 | 781 | |
654b0845 ILT |
782 | {"cmovo", 2, 0x0f40, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, |
783 | {"cmovno", 2, 0x0f41, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
784 | {"cmovb", 2, 0x0f42, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
785 | {"cmovae", 2, 0x0f43, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
786 | {"cmove", 2, 0x0f44, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
787 | {"cmovne", 2, 0x0f45, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
788 | {"cmovbe", 2, 0x0f46, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
789 | {"cmova", 2, 0x0f47, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
790 | {"cmovs", 2, 0x0f48, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
791 | {"cmovns", 2, 0x0f49, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
792 | {"cmovp", 2, 0x0f4a, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
793 | {"cmovnp", 2, 0x0f4b, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
794 | {"cmovl", 2, 0x0f4c, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
795 | {"cmovge", 2, 0x0f4d, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
796 | {"cmovle", 2, 0x0f4e, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
797 | {"cmovg", 2, 0x0f4f, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, | |
527cabaf ILT |
798 | |
799 | {"fcmovb", 2, 0xdac0, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
800 | {"fcmove", 2, 0xdac8, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
801 | {"fcmovbe",2, 0xdad0, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
802 | {"fcmovu", 2, 0xdad8, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
803 | {"fcmovnb", 2, 0xdbc0, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
804 | {"fcmovne", 2, 0xdbc8, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
805 | {"fcmovnbe",2, 0xdbd0, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
806 | {"fcmovnu", 2, 0xdbd8, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
807 | ||
808 | {"fcomi", 2, 0xdbf0, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
809 | {"fucomi", 2, 0xdbe8, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
810 | {"fcomip", 2, 0xdff0, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
811 | {"fucomip",2, 0xdfe8, _, ShortForm, { FloatReg, FloatAcc, 0} }, | |
cd22144a | 812 | |
3abaf930 ILT |
813 | /* MMX instructions. */ |
814 | ||
815 | {"emms", 0, 0x0f77, _, NoModrm, { 0, 0, 0 } }, | |
c2367582 ILT |
816 | {"movd", 2, 0x0f6e, _, Modrm, { Reg32|WordMem, RegMMX, 0 } }, |
817 | {"movd", 2, 0x0f7e, _, Modrm, { RegMMX, Reg32|WordMem, 0 } }, | |
3abaf930 ILT |
818 | {"movq", 2, 0x0f6f, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
819 | {"movq", 2, 0x0f7f, _, Modrm, { RegMMX, RegMMX|WordMem, 0 } }, | |
820 | {"packssdw", 2, 0x0f6b, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
821 | {"packsswb", 2, 0x0f63, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
822 | {"packuswb", 2, 0x0f67, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
823 | {"paddb", 2, 0x0ffc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
824 | {"paddw", 2, 0x0ffd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
825 | {"paddd", 2, 0x0ffe, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
826 | {"paddsb", 2, 0x0fec, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
827 | {"paddsw", 2, 0x0fed, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
828 | {"paddusb", 2, 0x0fdc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
829 | {"paddusw", 2, 0x0fdd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
c2367582 | 830 | {"pand", 2, 0x0fdb, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
3abaf930 ILT |
831 | {"pandn", 2, 0x0fdf, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, |
832 | {"pcmpeqb", 2, 0x0f74, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
833 | {"pcmpeqw", 2, 0x0f75, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
834 | {"pcmpeqd", 2, 0x0f76, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
835 | {"pcmpgtb", 2, 0x0f64, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
836 | {"pcmpgtw", 2, 0x0f65, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
837 | {"pcmpgtd", 2, 0x0f66, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
838 | {"pmaddwd", 2, 0x0ff5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
839 | {"pmulhw", 2, 0x0fe5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
840 | {"pmullw", 2, 0x0fd5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
841 | {"por", 2, 0x0feb, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
842 | {"psllw", 2, 0x0ff1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
843 | {"psllw", 2, 0x0f71, 6, Modrm, { Imm8, RegMMX, 0 } }, | |
844 | {"pslld", 2, 0x0ff2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
845 | {"pslld", 2, 0x0f72, 6, Modrm, { Imm8, RegMMX, 0 } }, | |
846 | {"psllq", 2, 0x0ff3, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
847 | {"psllq", 2, 0x0f73, 6, Modrm, { Imm8, RegMMX, 0 } }, | |
848 | {"psraw", 2, 0x0fe1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
849 | {"psraw", 2, 0x0f71, 4, Modrm, { Imm8, RegMMX, 0 } }, | |
850 | {"psrad", 2, 0x0fe2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
851 | {"psrad", 2, 0x0f72, 4, Modrm, { Imm8, RegMMX, 0 } }, | |
852 | {"psrlw", 2, 0x0fd1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
853 | {"psrlw", 2, 0x0f71, 2, Modrm, { Imm8, RegMMX, 0 } }, | |
854 | {"psrld", 2, 0x0fd2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
855 | {"psrld", 2, 0x0f72, 2, Modrm, { Imm8, RegMMX, 0 } }, | |
856 | {"psrlq", 2, 0x0fd3, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
857 | {"psrlq", 2, 0x0f73, 2, Modrm, { Imm8, RegMMX, 0 } }, | |
858 | {"psubb", 2, 0x0ff8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
859 | {"psubw", 2, 0x0ff9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
860 | {"psubd", 2, 0x0ffa, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
861 | {"psubsb", 2, 0x0fe8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
862 | {"psubsw", 2, 0x0fe9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
863 | {"psubusb", 2, 0x0fd8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
864 | {"psubusw", 2, 0x0fd9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
865 | {"punpckhbw", 2, 0x0f68, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
866 | {"punpckhwd", 2, 0x0f69, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
867 | {"punpckhdq", 2, 0x0f6a, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
868 | {"punpcklbw", 2, 0x0f60, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
869 | {"punpcklwd", 2, 0x0f61, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
870 | {"punpckldq", 2, 0x0f62, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
871 | {"pxor", 2, 0x0fef, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, | |
872 | ||
a43022bd | 873 | {"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */ |
ce868e5c JG |
874 | }; |
875 | #undef _ | |
876 | ||
fc0d7441 | 877 | static const template *const i386_optab_end |
ce868e5c JG |
878 | = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]); |
879 | ||
880 | /* 386 register table */ | |
881 | ||
882 | static const reg_entry i386_regtab[] = { | |
883 | /* 8 bit regs */ | |
884 | {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2}, | |
885 | {"bl", Reg8, 3}, | |
886 | {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7}, | |
887 | /* 16 bit regs */ | |
888 | {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3}, | |
889 | {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7}, | |
890 | /* 32 bit regs */ | |
891 | {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3}, | |
892 | {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7}, | |
893 | /* segment registers */ | |
894 | {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2}, | |
895 | {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5}, | |
896 | /* control registers */ | |
897 | {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3}, | |
cd22144a | 898 | {"cr4", Control, 4}, |
ce868e5c JG |
899 | /* debug registers */ |
900 | {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2}, | |
901 | {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7}, | |
cd22144a KR |
902 | {"dr0", Debug, 0}, {"dr1", Debug, 1}, {"dr2", Debug, 2}, |
903 | {"dr3", Debug, 3}, {"dr6", Debug, 6}, {"dr7", Debug, 7}, | |
ce868e5c | 904 | /* test registers */ |
527cabaf | 905 | {"tr3", Test, 3}, {"tr4", Test, 4}, {"tr5", Test, 5}, |
ce868e5c JG |
906 | {"tr6", Test, 6}, {"tr7", Test, 7}, |
907 | /* float registers */ | |
908 | {"st(0)", FloatReg|FloatAcc, 0}, | |
909 | {"st", FloatReg|FloatAcc, 0}, | |
c0d7b534 ILT |
910 | {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2}, |
911 | {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5}, | |
3abaf930 ILT |
912 | {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}, |
913 | {"mm0", RegMMX, 0}, {"mm1", RegMMX, 1}, {"mm2", RegMMX, 2}, | |
914 | {"mm3", RegMMX, 3}, {"mm4", RegMMX, 4}, {"mm5", RegMMX, 5}, | |
915 | {"mm6", RegMMX, 6}, {"mm7", RegMMX, 7} | |
ce868e5c JG |
916 | }; |
917 | ||
918 | #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ | |
919 | ||
fc0d7441 | 920 | static const reg_entry *const i386_regtab_end |
ce868e5c JG |
921 | = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]); |
922 | ||
923 | /* segment stuff */ | |
924 | static const seg_entry cs = { "cs", 0x2e }; | |
925 | static const seg_entry ds = { "ds", 0x3e }; | |
926 | static const seg_entry ss = { "ss", 0x36 }; | |
927 | static const seg_entry es = { "es", 0x26 }; | |
928 | static const seg_entry fs = { "fs", 0x64 }; | |
929 | static const seg_entry gs = { "gs", 0x65 }; | |
930 | static const seg_entry null = { "", 0x0 }; | |
931 | ||
932 | /* | |
933 | This table is used to store the default segment register implied by all | |
934 | possible memory addressing modes. | |
935 | It is indexed by the mode & modrm entries of the modrm byte as follows: | |
936 | index = (mode<<3) | modrm; | |
937 | */ | |
fc0d7441 | 938 | static const seg_entry *const one_byte_segment_defaults[] = { |
ce868e5c JG |
939 | /* mode 0 */ |
940 | &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds, | |
941 | /* mode 1 */ | |
942 | &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, | |
943 | /* mode 2 */ | |
944 | &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, | |
945 | /* mode 3 --- not a memory reference; never referenced */ | |
946 | }; | |
947 | ||
fc0d7441 | 948 | static const seg_entry *const two_byte_segment_defaults[] = { |
ce868e5c JG |
949 | /* mode 0 */ |
950 | &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, | |
951 | /* mode 1 */ | |
eff2a090 | 952 | &ds, &ds, &ds, &ds, &ss, &ss, &ds, &ds, |
ce868e5c | 953 | /* mode 2 */ |
eff2a090 | 954 | &ds, &ds, &ds, &ds, &ss, &ss, &ds, &ds, |
ce868e5c JG |
955 | /* mode 3 --- not a memory reference; never referenced */ |
956 | }; | |
957 | ||
958 | static const prefix_entry i386_prefixtab[] = { | |
a43022bd | 959 | #define ADDR_PREFIX_OPCODE 0x67 |
ce868e5c JG |
960 | { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing |
961 | * (How is this useful?) */ | |
962 | #define WORD_PREFIX_OPCODE 0x66 | |
963 | { "data16", 0x66 }, /* operand size prefix */ | |
964 | { "lock", 0xf0 }, /* bus lock prefix */ | |
965 | { "wait", 0x9b }, /* wait for coprocessor */ | |
966 | { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */ | |
967 | { "es", 0x26 }, { "fs", 0x64 }, | |
968 | { "gs", 0x65 }, { "ss", 0x36 }, | |
969 | /* REPE & REPNE used to detect rep/repne with a non-string instruction */ | |
970 | #define REPNE 0xf2 | |
971 | #define REPE 0xf3 | |
972 | { "rep", 0xf3 }, /* repeat string instructions */ | |
973 | { "repe", 0xf3 }, { "repz", 0xf3 }, | |
974 | { "repne", 0xf2 }, { "repnz", 0xf2 } | |
975 | }; | |
976 | ||
fc0d7441 | 977 | static const prefix_entry *const i386_prefixtab_end |
ce868e5c JG |
978 | = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]); |
979 | ||
980 | /* end of i386-opcode.h */ |