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Fix cpu_flags for sys{enter,exit} fx{save,restore}
[deliverable/binutils-gdb.git] / include / opcode / i386.h
CommitLineData
252b5132
RH		 1/* opcode/i386.h -- Intel 80386 opcode table
2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation.
3
4This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
5
6This program is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2 of the License, or
9(at your option) any later version.
10
11This program is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with this program; if not, write to the Free Software
18Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19
d0b47220
AM		 20/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
21 ix86 Unix assemblers, generate floating point instructions with
22 reversed source and destination registers in certain cases.
23 Unfortunately, gcc and possibly many other programs use this
24 reversed syntax, so we're stuck with it.
252b5132 25
7f3f1ea2
AM		 26 eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
27 `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
28 the expected st(3) = st(3) - st
252b5132
RH		 29
30 This happens with all the non-commutative arithmetic floating point
31 operations with two register operands, where the source register is
7f3f1ea2
AM		 32 %st, and destination register is %st(i). See FloatDR below.
33
34 The affected opcode map is dceX, dcfX, deeX, defX. */
252b5132 35
d0b47220 36#ifndef SYSV386_COMPAT
252b5132 37/* Set non-zero for broken, compatible instructions. Set to zero for
d0b47220 38 non-broken opcodes at your peril. gcc generates SystemV/386
252b5132 39 compatible instructions. */
d0b47220
AM		 40#define SYSV386_COMPAT 1
41#endif
42#ifndef OLDGCC_COMPAT
43/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
44 generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
45 reversed. */
46#define OLDGCC_COMPAT SYSV386_COMPAT
252b5132 47#endif
252b5132
RH		 48
49static const template i386_optab[] = {
50
51#define X None
252b5132
RH		 52#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
53#define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
54#define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf)
55#define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_dSuf|No_xSuf)
56#define d_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf)
57#define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_dSuf)
58#define bw_Suf (No_lSuf|No_sSuf|No_dSuf|No_xSuf)
59#define bl_Suf (No_wSuf|No_sSuf|No_dSuf|No_xSuf)
60#define wl_Suf (No_bSuf|No_sSuf|No_dSuf|No_xSuf)
e413e4e9 61#define wld_Suf (No_bSuf|No_sSuf|No_xSuf)
252b5132
RH		 62#define sl_Suf (No_bSuf|No_wSuf|No_dSuf|No_xSuf)
63#define sld_Suf (No_bSuf|No_wSuf|No_xSuf)
64#define sldx_Suf (No_bSuf|No_wSuf)
65#define bwl_Suf (No_sSuf|No_dSuf|No_xSuf)
66#define bwld_Suf (No_sSuf|No_xSuf)
67#define FP (NoSuf|IgnoreSize)
68#define l_FP (l_Suf|IgnoreSize)
69#define d_FP (d_Suf|IgnoreSize)
70#define x_FP (x_Suf|IgnoreSize)
71#define sl_FP (sl_Suf|IgnoreSize)
72#define sld_FP (sld_Suf|IgnoreSize)
73#define sldx_FP (sldx_Suf|IgnoreSize)
d0b47220 74#if SYSV386_COMPAT
7f3f1ea2
AM		 75/* Someone forgot that the FloatR bit reverses the operation when not
76 equal to the FloatD bit. ie. Changing only FloatD results in the
77 destination being swapped *and* the direction being reversed. */
252b5132
RH		 78#define FloatDR FloatD
79#else
80#define FloatDR (FloatD|FloatR)
81#endif
82
d0b47220 83/* Move instructions. */
252b5132 84#define MOV_AX_DISP32 0xa0
e413e4e9
AM		 85{ "mov", 2, 0xa0, X, 0, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
86{ "mov", 2, 0x88, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } },
87{ "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { Imm, Reg, 0 } },
88{ "mov", 2, 0xc6, X, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0 } },
89/* The segment register moves accept WordReg so that a segment register
252b5132
RH		 90 can be copied to a 32 bit register, and vice versa, without using a
91 size prefix. When moving to a 32 bit register, the upper 16 bits
92 are set to an implementation defined value (on the Pentium Pro,
93 the implementation defined value is zero). */
e413e4e9
AM		 94{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|WordMem, 0 } },
95{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|WordMem, 0 } },
96{ "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg2, 0 } },
97{ "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3, 0 } },
d0b47220 98/* Move to/from control debug registers. */
e413e4e9
AM		 99{ "mov", 2, 0x0f20, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32|InvMem, 0} },
100{ "mov", 2, 0x0f21, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32|InvMem, 0} },
101{ "mov", 2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} },
252b5132 102
d0b47220 103/* Move with sign extend. */
252b5132
RH		 104/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
105 conflict with the "movs" string move instruction. */
e413e4e9
AM		 106{"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} },
107{"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} },
108{"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} },
252b5132 109/* Intel Syntax */
e413e4e9
AM		 110{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} },
111{"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
252b5132 112
d0b47220 113/* Move with zero extend. */
e413e4e9
AM		 114{"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
115{"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} },
252b5132 116/* Intel Syntax */
e413e4e9
AM		 117{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} },
118{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
252b5132 119
d0b47220 120/* Push instructions. */
e413e4e9
AM		 121{"push", 1, 0x50, X, 0, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
122{"push", 1, 0xff, 6, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
123{"push", 1, 0x6a, X, Cpu186, wl_Suf|DefaultSize, { Imm8S, 0, 0} },
124{"push", 1, 0x68, X, Cpu186, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} },
125{"push", 1, 0x06, X, 0, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
126{"push", 1, 0x0fa0, X, Cpu386, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
127{"pusha", 0, 0x60, X, Cpu186, wld_Suf|DefaultSize, { 0, 0, 0 } },
252b5132 128
d0b47220 129/* Pop instructions. */
e413e4e9
AM		 130{"pop", 1, 0x58, X, 0, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
131{"pop", 1, 0x8f, 0, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
252b5132 132#define POP_SEG_SHORT 0x07
e413e4e9
AM		 133{"pop", 1, 0x07, X, 0, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
134{"pop", 1, 0x0fa1, X, Cpu386, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
135{"popa", 0, 0x61, X, Cpu186, wld_Suf|DefaultSize, { 0, 0, 0 } },
252b5132 136
d0b47220
AM		 137/* Exchange instructions.
138 xchg commutes: we allow both operand orders. */
e413e4e9
AM		 139{"xchg", 2, 0x90, X, 0, wl_Suf|ShortForm, { WordReg, Acc, 0 } },
140{"xchg", 2, 0x90, X, 0, wl_Suf|ShortForm, { Acc, WordReg, 0 } },
141{"xchg", 2, 0x86, X, 0, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
142{"xchg", 2, 0x86, X, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } },
252b5132 143
d0b47220 144/* In/out from ports. */
e413e4e9
AM		 145{"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } },
146{"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } },
147{"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } },
148{"in", 1, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } },
149{"out", 2, 0xe6, X, 0, bwl_Suf|W, { Acc, Imm8, 0 } },
150{"out", 2, 0xee, X, 0, bwl_Suf|W, { Acc, InOutPortReg, 0 } },
151{"out", 1, 0xe6, X, 0, bwl_Suf|W, { Imm8, 0, 0 } },
152{"out", 1, 0xee, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } },
252b5132 153
d0b47220 154/* Load effective address. */
e413e4e9 155{"lea", 2, 0x8d, X, 0, wl_Suf|Modrm, { WordMem, WordReg, 0 } },
252b5132 156
d0b47220 157/* Load segment registers from memory. */
e413e4e9
AM		 158{"lds", 2, 0xc5, X, 0, wl_Suf|Modrm, { WordMem, WordReg, 0} },
159{"les", 2, 0xc4, X, 0, wl_Suf|Modrm, { WordMem, WordReg, 0} },
160{"lfs", 2, 0x0fb4, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} },
161{"lgs", 2, 0x0fb5, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} },
162{"lss", 2, 0x0fb2, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} },
252b5132 163
d0b47220 164/* Flags register instructions. */
e413e4e9
AM		 165{"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} },
166{"cld", 0, 0xfc, X, 0, NoSuf, { 0, 0, 0} },
167{"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} },
168{"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} },
169{"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} },
170{"lahf", 0, 0x9f, X, 0, NoSuf, { 0, 0, 0} },
171{"sahf", 0, 0x9e, X, 0, NoSuf, { 0, 0, 0} },
172{"pushf", 0, 0x9c, X, 0, wld_Suf|DefaultSize, { 0, 0, 0} },
173{"popf", 0, 0x9d, X, 0, wld_Suf|DefaultSize, { 0, 0, 0} },
174{"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} },
175{"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} },
176{"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} },
252b5132 177
d0b47220 178/* Arithmetic. */
e413e4e9
AM		 179{"add", 2, 0x00, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
180{"add", 2, 0x83, 0, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
181{"add", 2, 0x04, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
182{"add", 2, 0x80, 0, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
183
184{"inc", 1, 0x40, X, 0, wl_Suf|ShortForm, { WordReg, 0, 0} },
185{"inc", 1, 0xfe, 0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
186
187{"sub", 2, 0x28, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
188{"sub", 2, 0x83, 5, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
189{"sub", 2, 0x2c, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
190{"sub", 2, 0x80, 5, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
191
192{"dec", 1, 0x48, X, 0, wl_Suf|ShortForm, { WordReg, 0, 0} },
193{"dec", 1, 0xfe, 1, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
194
195{"sbb", 2, 0x18, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
196{"sbb", 2, 0x83, 3, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
197{"sbb", 2, 0x1c, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
198{"sbb", 2, 0x80, 3, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
199
200{"cmp", 2, 0x38, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
201{"cmp", 2, 0x83, 7, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
202{"cmp", 2, 0x3c, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
203{"cmp", 2, 0x80, 7, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
204
205{"test", 2, 0x84, X, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} },
206{"test", 2, 0x84, X, 0, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} },
207{"test", 2, 0xa8, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
208{"test", 2, 0xf6, 0, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
209
210{"and", 2, 0x20, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
211{"and", 2, 0x83, 4, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
212{"and", 2, 0x24, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
213{"and", 2, 0x80, 4, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
214
215{"or", 2, 0x08, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
216{"or", 2, 0x83, 1, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
217{"or", 2, 0x0c, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
218{"or", 2, 0x80, 1, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
219
220{"xor", 2, 0x30, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
221{"xor", 2, 0x83, 6, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
222{"xor", 2, 0x34, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
223{"xor", 2, 0x80, 6, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
224
225/* clr with 1 operand is really xor with 2 operands. */
226{"clr", 1, 0x30, X, 0, bwl_Suf|W|Modrm|regKludge, { Reg, 0, 0 } },
227
228{"adc", 2, 0x10, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
229{"adc", 2, 0x83, 2, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
230{"adc", 2, 0x14, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
231{"adc", 2, 0x80, 2, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
232
233{"neg", 1, 0xf6, 3, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
234{"not", 1, 0xf6, 2, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
235
236{"aaa", 0, 0x37, X, 0, NoSuf, { 0, 0, 0} },
237{"aas", 0, 0x3f, X, 0, NoSuf, { 0, 0, 0} },
238{"daa", 0, 0x27, X, 0, NoSuf, { 0, 0, 0} },
239{"das", 0, 0x2f, X, 0, NoSuf, { 0, 0, 0} },
240{"aad", 0, 0xd50a, X, 0, NoSuf, { 0, 0, 0} },
241{"aad", 1, 0xd5, X, 0, NoSuf, { Imm8S, 0, 0} },
242{"aam", 0, 0xd40a, X, 0, NoSuf, { 0, 0, 0} },
243{"aam", 1, 0xd4, X, 0, NoSuf, { Imm8S, 0, 0} },
252b5132 244
d0b47220
AM		 245/* Conversion insns. */
246/* Intel naming */
e413e4e9
AM		 247{"cbw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} },
248{"cwde", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} },
249{"cwd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} },
250{"cdq", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} },
d0b47220 251/* AT&T naming */
e413e4e9
AM		 252{"cbtw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} },
253{"cwtl", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} },
254{"cwtd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} },
255{"cltd", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} },
252b5132
RH		 256
257/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
258 expanding 64-bit multiplies, and *cannot* be selected to accomplish
259 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
260 These multiplies can only be selected with single operand forms. */
e413e4e9
AM		 261{"mul", 1, 0xf6, 4, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
262{"imul", 1, 0xf6, 5, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
263{"imul", 2, 0x0faf, X, Cpu386, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
264{"imul", 3, 0x6b, X, Cpu186, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} },
265{"imul", 3, 0x69, X, Cpu186, wl_Suf|Modrm, { Imm16|Imm32, WordReg|WordMem, WordReg} },
252b5132
RH		 266/* imul with 2 operands mimics imul with 3 by putting the register in
267 both i.rm.reg & i.rm.regmem fields. regKludge enables this
268 transformation. */
e413e4e9
AM		 269{"imul", 2, 0x6b, X, Cpu186, wl_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
270{"imul", 2, 0x69, X, Cpu186, wl_Suf|Modrm|regKludge,{ Imm16|Imm32, WordReg, 0} },
271
272{"div", 1, 0xf6, 6, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
273{"div", 2, 0xf6, 6, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
274{"idiv", 1, 0xf6, 7, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
275{"idiv", 2, 0xf6, 7, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
276
277{"rol", 2, 0xd0, 0, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
278{"rol", 2, 0xc0, 0, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
279{"rol", 2, 0xd2, 0, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
280{"rol", 1, 0xd0, 0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
281
282{"ror", 2, 0xd0, 1, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
283{"ror", 2, 0xc0, 1, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
284{"ror", 2, 0xd2, 1, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
285{"ror", 1, 0xd0, 1, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
286
287{"rcl", 2, 0xd0, 2, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
288{"rcl", 2, 0xc0, 2, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
289{"rcl", 2, 0xd2, 2, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
290{"rcl", 1, 0xd0, 2, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
291
292{"rcr", 2, 0xd0, 3, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
293{"rcr", 2, 0xc0, 3, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
294{"rcr", 2, 0xd2, 3, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
295{"rcr", 1, 0xd0, 3, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
296
297{"sal", 2, 0xd0, 4, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
298{"sal", 2, 0xc0, 4, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
299{"sal", 2, 0xd2, 4, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
300{"sal", 1, 0xd0, 4, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
301
302{"shl", 2, 0xd0, 4, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
303{"shl", 2, 0xc0, 4, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
304{"shl", 2, 0xd2, 4, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
305{"shl", 1, 0xd0, 4, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
306
307{"shr", 2, 0xd0, 5, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
308{"shr", 2, 0xc0, 5, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
309{"shr", 2, 0xd2, 5, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
310{"shr", 1, 0xd0, 5, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
311
312{"sar", 2, 0xd0, 7, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
313{"sar", 2, 0xc0, 7, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
314{"sar", 2, 0xd2, 7, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
315{"sar", 1, 0xd0, 7, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
316
317{"shld", 3, 0x0fa4, X, Cpu386, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
318{"shld", 3, 0x0fa5, X, Cpu386, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
319{"shld", 2, 0x0fa5, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
320
321{"shrd", 3, 0x0fac, X, Cpu386, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
322{"shrd", 3, 0x0fad, X, Cpu386, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
323{"shrd", 2, 0x0fad, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
252b5132 324
d0b47220 325/* Control transfer instructions. */
e413e4e9
AM		 326{"call", 1, 0xe8, X, 0, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },
327{"call", 1, 0xff, 2, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} },
252b5132 328/* Intel Syntax */
e413e4e9 329{"call", 2, 0x9a, X, 0, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
3138f287 330/* Intel Syntax */
e413e4e9
AM		 331{"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} },
332{"lcall", 2, 0x9a, X, 0, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
333{"lcall", 1, 0xff, 3, 0, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} },
252b5132
RH		 334
335#define JUMP_PC_RELATIVE 0xeb
e413e4e9
AM		 336{"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp, 0, 0} },
337{"jmp", 1, 0xff, 4, 0, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
252b5132 338/* Intel Syntax */
e413e4e9 339{"jmp", 2, 0xea, X, 0, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
3138f287 340/* Intel Syntax */
e413e4e9
AM		 341{"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem, 0, 0} },
342{"ljmp", 2, 0xea, X, 0, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
343{"ljmp", 1, 0xff, 5, 0, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} },
252b5132 344
e413e4e9
AM		 345{"ret", 0, 0xc3, X, 0, wl_Suf|DefaultSize, { 0, 0, 0} },
346{"ret", 1, 0xc2, X, 0, wl_Suf|DefaultSize, { Imm16, 0, 0} },
347{"lret", 0, 0xcb, X, 0, wl_Suf|DefaultSize, { 0, 0, 0} },
348{"lret", 1, 0xca, X, 0, wl_Suf|DefaultSize, { Imm16, 0, 0} },
349{"enter", 2, 0xc8, X, Cpu186, wl_Suf|DefaultSize, { Imm16, Imm8, 0} },
350{"leave", 0, 0xc9, X, Cpu186, wl_Suf|DefaultSize, { 0, 0, 0} },
252b5132 351
d0b47220 352/* Conditional jumps. */
e413e4e9
AM		 353{"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} },
354{"jno", 1, 0x71, X, 0, NoSuf|Jump, { Disp, 0, 0} },
355{"jb", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
356{"jc", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
357{"jnae", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
358{"jnb", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
359{"jnc", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
360{"jae", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
361{"je", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} },
362{"jz", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} },
363{"jne", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} },
364{"jnz", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} },
365{"jbe", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} },
366{"jna", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} },
367{"jnbe", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} },
368{"ja", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} },
369{"js", 1, 0x78, X, 0, NoSuf|Jump, { Disp, 0, 0} },
370{"jns", 1, 0x79, X, 0, NoSuf|Jump, { Disp, 0, 0} },
371{"jp", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} },
372{"jpe", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} },
373{"jnp", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} },
374{"jpo", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} },
375{"jl", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} },
376{"jnge", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} },
377{"jnl", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} },
378{"jge", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} },
379{"jle", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} },
380{"jng", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} },
381{"jnle", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} },
382{"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} },
252b5132
RH		 383
384/* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
e413e4e9
AM		 385{"jcxz", 1, 0xe3, X, 0, NoSuf|JumpByte|Size16, { Disp, 0, 0} },
386{"jecxz", 1, 0xe3, X, 0, NoSuf|JumpByte|Size32, { Disp, 0, 0} },
252b5132
RH		 387
388/* The loop instructions also use the address size prefix to select
389 %cx rather than %ecx for the loop count, so the `w' form of these
390 instructions emit an address size prefix rather than a data size
391 prefix. */
e413e4e9
AM		 392{"loop", 1, 0xe2, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} },
393{"loopz", 1, 0xe1, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} },
394{"loope", 1, 0xe1, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} },
395{"loopnz", 1, 0xe0, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} },
396{"loopne", 1, 0xe0, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} },
252b5132 397
d0b47220 398/* Set byte on flag instructions. */
e413e4e9
AM		 399{"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
400{"setno", 1, 0x0f91, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
401{"setb", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
402{"setc", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
403{"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
404{"setnb", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
405{"setnc", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
406{"setae", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
407{"sete", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
408{"setz", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
409{"setne", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
410{"setnz", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
411{"setbe", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
412{"setna", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
413{"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
414{"seta", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
415{"sets", 1, 0x0f98, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
416{"setns", 1, 0x0f99, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
417{"setp", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
418{"setpe", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
419{"setnp", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
420{"setpo", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
421{"setl", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
422{"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
423{"setnl", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
424{"setge", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
425{"setle", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
426{"setng", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
427{"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
428{"setg", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
252b5132 429
d0b47220 430/* String manipulation. */
e413e4e9
AM		 431{"cmps", 0, 0xa6, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} },
432{"cmps", 2, 0xa6, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
433{"scmp", 0, 0xa6, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} },
434{"scmp", 2, 0xa6, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
435{"ins", 0, 0x6c, X, Cpu186, bwld_Suf|W|IsString, { 0, 0, 0} },
436{"ins", 2, 0x6c, X, Cpu186, bwld_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} },
437{"outs", 0, 0x6e, X, Cpu186, bwld_Suf|W|IsString, { 0, 0, 0} },
438{"outs", 2, 0x6e, X, Cpu186, bwld_Suf|W|IsString, { AnyMem, InOutPortReg, 0} },
439{"lods", 0, 0xac, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} },
440{"lods", 1, 0xac, X, 0, bwld_Suf|W|IsString, { AnyMem, 0, 0} },
441{"lods", 2, 0xac, X, 0, bwld_Suf|W|IsString, { AnyMem, Acc, 0} },
442{"slod", 0, 0xac, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} },
443{"slod", 1, 0xac, X, 0, bwld_Suf|W|IsString, { AnyMem, 0, 0} },
444{"slod", 2, 0xac, X, 0, bwld_Suf|W|IsString, { AnyMem, Acc, 0} },
445{"movs", 0, 0xa4, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} },
446{"movs", 2, 0xa4, X, 0, bwld_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
447{"smov", 0, 0xa4, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} },
448{"smov", 2, 0xa4, X, 0, bwld_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
449{"scas", 0, 0xae, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} },
450{"scas", 1, 0xae, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
451{"scas", 2, 0xae, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
452{"ssca", 0, 0xae, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} },
453{"ssca", 1, 0xae, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
454{"ssca", 2, 0xae, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
455{"stos", 0, 0xaa, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} },
456{"stos", 1, 0xaa, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
457{"stos", 2, 0xaa, X, 0, bwld_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
458{"ssto", 0, 0xaa, X, 0, bwld_Suf|W|IsString, { 0, 0, 0} },
459{"ssto", 1, 0xaa, X, 0, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
460{"ssto", 2, 0xaa, X, 0, bwld_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
461{"xlat", 0, 0xd7, X, 0, b_Suf|IsString, { 0, 0, 0} },
462{"xlat", 1, 0xd7, X, 0, b_Suf|IsString, { AnyMem, 0, 0} },
252b5132 463
d0b47220 464/* Bit manipulation. */
e413e4e9
AM		 465{"bsf", 2, 0x0fbc, X, Cpu386, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
466{"bsr", 2, 0x0fbd, X, Cpu386, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
467{"bt", 2, 0x0fa3, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
468{"bt", 2, 0x0fba, 4, Cpu386, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
469{"btc", 2, 0x0fbb, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
470{"btc", 2, 0x0fba, 7, Cpu386, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
471{"btr", 2, 0x0fb3, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
472{"btr", 2, 0x0fba, 6, Cpu386, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
473{"bts", 2, 0x0fab, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
474{"bts", 2, 0x0fba, 5, Cpu386, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
252b5132 475
d0b47220 476/* Interrupts & op. sys insns. */
252b5132 477/* See gas/config/tc-i386.c for conversion of 'int $3' into the special
d0b47220 478 int 3 insn. */
252b5132
RH		 479#define INT_OPCODE 0xcd
480#define INT3_OPCODE 0xcc
e413e4e9
AM		 481{"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} },
482{"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} },
483{"into", 0, 0xce, X, 0, NoSuf, { 0, 0, 0} },
484{"iret", 0, 0xcf, X, 0, wl_Suf, { 0, 0, 0} },
d0b47220 485/* i386sl, i486sl, later 486, and Pentium. */
e413e4e9 486{"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} },
252b5132 487
e413e4e9 488{"bound", 2, 0x62, X, Cpu186, wl_Suf|Modrm, { WordReg, WordMem, 0} },
252b5132 489
e413e4e9 490{"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} },
d0b47220 491/* nop is actually 'xchgl %eax, %eax'. */
e413e4e9 492{"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} },
252b5132 493
d0b47220 494/* Protection control. */
e413e4e9
AM		 495{"arpl", 2, 0x63, X, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
496{"lar", 2, 0x0f02, X, Cpu286, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
497{"lgdt", 1, 0x0f01, 2, Cpu286, wl_Suf|Modrm, { WordMem, 0, 0} },
498{"lidt", 1, 0x0f01, 3, Cpu286, wl_Suf|Modrm, { WordMem, 0, 0} },
499{"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
500{"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
501{"lsl", 2, 0x0f03, X, Cpu286, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
502{"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
503
504{"sgdt", 1, 0x0f01, 0, Cpu286, wl_Suf|Modrm, { WordMem, 0, 0} },
505{"sidt", 1, 0x0f01, 1, Cpu286, wl_Suf|Modrm, { WordMem, 0, 0} },
506{"sldt", 1, 0x0f00, 0, Cpu286, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} },
507{"smsw", 1, 0x0f01, 4, Cpu286, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} },
508{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
509
510{"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
511{"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
252b5132 512
d0b47220 513/* Floating point instructions. */
252b5132
RH		 514
515/* load */
e413e4e9
AM		 516{"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
517{"fld", 1, 0xd9, 0, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
518{"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
252b5132 519/* Intel Syntax */
e413e4e9
AM		 520{"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} },
521{"fild", 1, 0xdf, 0, 0, sl_Suf|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 522/* Intel Syntax */
e413e4e9
AM		 523{"fildd", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
524{"fildq", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
525{"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
526{"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
527{"fbld", 1, 0xdf, 4, 0, FP|Modrm, { LLongMem, 0, 0} },
252b5132
RH		 528
529/* store (no pop) */
e413e4e9
AM		 530{"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
531{"fst", 1, 0xd9, 2, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
532{"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
533{"fist", 1, 0xdf, 2, 0, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132
RH		 534
535/* store (with pop) */
e413e4e9
AM		 536{"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
537{"fstp", 1, 0xd9, 3, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
538{"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
252b5132 539/* Intel Syntax */
e413e4e9
AM		 540{"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} },
541{"fistp", 1, 0xdf, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 542/* Intel Syntax */
e413e4e9
AM		 543{"fistpd", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
544{"fistpq", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
545{"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
546{"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
547{"fbstp", 1, 0xdf, 6, 0, FP|Modrm, { LLongMem, 0, 0} },
252b5132
RH		 548
549/* exchange %st<n> with %st0 */
e413e4e9
AM		 550{"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
551/* alias for fxch %st(1) */
552{"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 553
554/* comparison (without pop) */
e413e4e9
AM		 555{"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
556/* alias for fcom %st(1) */
557{"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} },
558{"fcom", 1, 0xd8, 2, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
559{"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
560{"ficom", 1, 0xde, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132
RH		 561
562/* comparison (with pop) */
e413e4e9
AM		 563{"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
564/* alias for fcomp %st(1) */
565{"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} },
566{"fcomp", 1, 0xd8, 3, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
567{"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
568{"ficomp", 1, 0xde, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
569{"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 570
571/* unordered comparison (with pop) */
e413e4e9
AM		 572{"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} },
573/* alias for fucom %st(1) */
574{"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} },
575{"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} },
576/* alias for fucomp %st(1) */
577{"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} },
578{"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} },
252b5132 579
e413e4e9
AM		 580{"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} },
581{"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 582
583/* load constants into %st0 */
e413e4e9
AM		 584{"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} },
585{"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} },
586{"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} },
587{"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} },
588{"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} },
589{"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} },
590{"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 591
592/* arithmetic */
593
594/* add */
e413e4e9
AM		 595{"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
596/* alias for fadd %st(i), %st */
597{"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 598#if SYSV386_COMPAT
e413e4e9
AM		 599/* alias for faddp */
600{"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 601#endif
e413e4e9
AM		 602{"fadd", 1, 0xd8, 0, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
603{"fiadd", 1, 0xde, 0, 0, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 604
e413e4e9
AM		 605{"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
606{"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
607/* alias for faddp %st, %st(1) */
608{"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} },
609{"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
252b5132
RH		 610
611/* subtract */
e413e4e9
AM		 612{"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
613{"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 614#if SYSV386_COMPAT
e413e4e9
AM		 615/* alias for fsubp */
616{"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 617#endif
e413e4e9
AM		 618{"fsub", 1, 0xd8, 4, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
619{"fisub", 1, 0xde, 4, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 620
d0b47220 621#if SYSV386_COMPAT
e413e4e9
AM		 622{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
623{"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
624{"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },
d0b47220 625#if OLDGCC_COMPAT
e413e4e9 626{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 627#endif
252b5132 628#else
e413e4e9
AM		 629{"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
630{"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
631{"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 632#endif
633
634/* subtract reverse */
e413e4e9
AM		 635{"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
636{"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 637#if SYSV386_COMPAT
e413e4e9
AM		 638/* alias for fsubrp */
639{"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 640#endif
e413e4e9
AM		 641{"fsubr", 1, 0xd8, 5, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
642{"fisubr", 1, 0xde, 5, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 643
d0b47220 644#if SYSV386_COMPAT
e413e4e9
AM		 645{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
646{"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
647{"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },
d0b47220 648#if OLDGCC_COMPAT
e413e4e9 649{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 650#endif
252b5132 651#else
e413e4e9
AM		 652{"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
653{"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
654{"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 655#endif
656
657/* multiply */
e413e4e9
AM		 658{"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
659{"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 660#if SYSV386_COMPAT
e413e4e9
AM		 661/* alias for fmulp */
662{"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 663#endif
e413e4e9
AM		 664{"fmul", 1, 0xd8, 1, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
665{"fimul", 1, 0xde, 1, 0, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 666
e413e4e9
AM		 667{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
668{"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
669{"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} },
670{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
252b5132
RH		 671
672/* divide */
e413e4e9
AM		 673{"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
674{"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 675#if SYSV386_COMPAT
e413e4e9
AM		 676/* alias for fdivp */
677{"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 678#endif
e413e4e9
AM		 679{"fdiv", 1, 0xd8, 6, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
680{"fidiv", 1, 0xde, 6, 0, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 681
d0b47220 682#if SYSV386_COMPAT
e413e4e9
AM		 683{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
684{"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
685{"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },
d0b47220 686#if OLDGCC_COMPAT
e413e4e9 687{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 688#endif
252b5132 689#else
e413e4e9
AM		 690{"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
691{"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
692{"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 693#endif
694
695/* divide reverse */
e413e4e9
AM		 696{"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
697{"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 698#if SYSV386_COMPAT
e413e4e9
AM		 699/* alias for fdivrp */
700{"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 701#endif
e413e4e9
AM		 702{"fdivr", 1, 0xd8, 7, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
703{"fidivr", 1, 0xde, 7, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 704
d0b47220 705#if SYSV386_COMPAT
e413e4e9
AM		 706{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
707{"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
708{"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },
d0b47220 709#if OLDGCC_COMPAT
e413e4e9 710{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 711#endif
252b5132 712#else
e413e4e9
AM		 713{"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
714{"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
715{"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 716#endif
717
e413e4e9
AM		 718{"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} },
719{"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} },
720{"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} },
721{"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} },
722{"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} },
723{"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} },
724{"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} },
725{"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} },
726{"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} },
727{"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} },
728{"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} },
729{"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} },
730{"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} },
731{"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} },
732{"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} },
733{"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} },
734{"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} },
735{"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 736
737/* processor control */
e413e4e9
AM		 738{"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} },
739{"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} },
740{"fldcw", 1, 0xd9, 5, 0, FP|Modrm, { ShortMem, 0, 0} },
741{"fnstcw", 1, 0xd9, 7, 0, FP|Modrm, { ShortMem, 0, 0} },
742{"fstcw", 1, 0xd9, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} },
743{"fnstsw", 1, 0xdfe0, X, 0, FP, { Acc, 0, 0} },
744{"fnstsw", 1, 0xdd, 7, 0, FP|Modrm, { ShortMem, 0, 0} },
745{"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} },
746{"fstsw", 1, 0xdfe0, X, 0, FP|FWait, { Acc, 0, 0} },
747{"fstsw", 1, 0xdd, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} },
748{"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} },
749{"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} },
750{"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} },
d0b47220 751/* Short forms of fldenv, fstenv use data size prefix. */
e413e4e9
AM		 752{"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
753{"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
754{"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
755{"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
756{"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
757{"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
758
759{"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
252b5132 760/* P6:free st(i), pop st */
e413e4e9
AM		 761{"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
762{"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} },
252b5132 763#define FWAIT_OPCODE 0x9b
e413e4e9 764{"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} },
252b5132 765
d0b47220
AM		 766/* Opcode prefixes; we allow them as separate insns too. */
767
252b5132 768#define ADDR_PREFIX_OPCODE 0x67
e413e4e9
AM		 769{"addr16", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
770{"addr32", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
771{"aword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
772{"adword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
252b5132 773#define DATA_PREFIX_OPCODE 0x66
e413e4e9
AM		 774{"data16", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
775{"data32", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
776{"word", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
777{"dword", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
252b5132 778#define LOCK_PREFIX_OPCODE 0xf0
e413e4e9
AM		 779{"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
780{"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 781#define CS_PREFIX_OPCODE 0x2e
e413e4e9 782{"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 783#define DS_PREFIX_OPCODE 0x3e
e413e4e9 784{"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 785#define ES_PREFIX_OPCODE 0x26
e413e4e9 786{"es", 0, 0x26, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 787#define FS_PREFIX_OPCODE 0x64
e413e4e9 788{"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 789#define GS_PREFIX_OPCODE 0x65
e413e4e9 790{"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 791#define SS_PREFIX_OPCODE 0x36
e413e4e9 792{"ss", 0, 0x36, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132
RH		 793#define REPNE_PREFIX_OPCODE 0xf2
794#define REPE_PREFIX_OPCODE 0xf3
e413e4e9
AM		 795{"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
796{"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
797{"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
798{"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
799{"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 800
d0b47220 801/* 486 extensions. */
252b5132 802
e413e4e9
AM		 803{"bswap", 1, 0x0fc8, X, Cpu486, l_Suf|ShortForm, { Reg32, 0, 0 } },
804{"xadd", 2, 0x0fc0, X, Cpu486, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
805{"cmpxchg", 2, 0x0fb0, X, Cpu486, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
806{"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} },
807{"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} },
808{"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm, { AnyMem, 0, 0} },
252b5132 809
d0b47220 810/* 586 and late 486 extensions. */
e413e4e9 811{"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} },
252b5132 812
d0b47220 813/* Pentium extensions. */
e413e4e9
AM		 814{"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} },
815{"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} },
816{"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} },
817{"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm, { LLongMem, 0, 0} },
252b5132 818
558b0a60
AM		 819/* Pentium II/Pentium Pro extensions. */
820{"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} },
821{"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} },
822{"fxsave", 1, 0x0fae, 0, Cpu686, FP|Modrm, { LLongMem, 0, 0} },
823{"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm, { LLongMem, 0, 0} },
e413e4e9
AM		 824{"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} },
825/* official undefined instr. */
826{"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} },
827/* alias for ud2 */
828{"ud2a", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} },
829/* 2nd. official undefined instr. */
830{"ud2b", 0, 0x0fb9, X, Cpu686, NoSuf, { 0, 0, 0} },
831
832{"cmovo", 2, 0x0f40, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
833{"cmovno", 2, 0x0f41, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
834{"cmovb", 2, 0x0f42, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
835{"cmovc", 2, 0x0f42, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
836{"cmovnae", 2, 0x0f42, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
837{"cmovae", 2, 0x0f43, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
838{"cmovnc", 2, 0x0f43, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
839{"cmovnb", 2, 0x0f43, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
840{"cmove", 2, 0x0f44, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
841{"cmovz", 2, 0x0f44, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
842{"cmovne", 2, 0x0f45, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
843{"cmovnz", 2, 0x0f45, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
844{"cmovbe", 2, 0x0f46, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
845{"cmovna", 2, 0x0f46, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
846{"cmova", 2, 0x0f47, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
847{"cmovnbe", 2, 0x0f47, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
848{"cmovs", 2, 0x0f48, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
849{"cmovns", 2, 0x0f49, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
850{"cmovp", 2, 0x0f4a, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
851{"cmovnp", 2, 0x0f4b, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
852{"cmovl", 2, 0x0f4c, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
853{"cmovnge", 2, 0x0f4c, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
854{"cmovge", 2, 0x0f4d, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
855{"cmovnl", 2, 0x0f4d, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
856{"cmovle", 2, 0x0f4e, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
857{"cmovng", 2, 0x0f4e, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
858{"cmovg", 2, 0x0f4f, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
859{"cmovnle", 2, 0x0f4f, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
860
861{"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
862{"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
863{"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
864{"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
865{"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
866{"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
867{"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
868{"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
869{"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
870{"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
871{"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
872{"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
873
874{"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
875{"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
876{"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
877{"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
878{"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
879{"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
880{"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
881{"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
882{"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
883{"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
884{"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
885{"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
886{"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
887{"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
252b5132
RH		 888
889/* MMX instructions. */
890
e413e4e9
AM		 891{"emms", 0, 0x0f77, X, CpuMMX, FP, { 0, 0, 0 } },
892{"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } },
893{"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } },
894{"movq", 2, 0x0f6f, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
895{"movq", 2, 0x0f7f, X, CpuMMX, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } },
896{"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
897{"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
898{"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
899{"paddb", 2, 0x0ffc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
900{"paddw", 2, 0x0ffd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
901{"paddd", 2, 0x0ffe, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
902{"paddsb", 2, 0x0fec, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
903{"paddsw", 2, 0x0fed, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
904{"paddusb", 2, 0x0fdc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
905{"paddusw", 2, 0x0fdd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
906{"pand", 2, 0x0fdb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
907{"pandn", 2, 0x0fdf, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
908{"pcmpeqb", 2, 0x0f74, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
909{"pcmpeqw", 2, 0x0f75, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
910{"pcmpeqd", 2, 0x0f76, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
911{"pcmpgtb", 2, 0x0f64, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
912{"pcmpgtw", 2, 0x0f65, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
913{"pcmpgtd", 2, 0x0f66, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
914{"pmaddwd", 2, 0x0ff5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
915{"pmulhw", 2, 0x0fe5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
916{"pmullw", 2, 0x0fd5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
917{"por", 2, 0x0feb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
918{"psllw", 2, 0x0ff1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
919{"psllw", 2, 0x0f71, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
920{"pslld", 2, 0x0ff2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
921{"pslld", 2, 0x0f72, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
922{"psllq", 2, 0x0ff3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
923{"psllq", 2, 0x0f73, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
924{"psraw", 2, 0x0fe1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
925{"psraw", 2, 0x0f71, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
926{"psrad", 2, 0x0fe2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
927{"psrad", 2, 0x0f72, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
928{"psrlw", 2, 0x0fd1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
929{"psrlw", 2, 0x0f71, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
930{"psrld", 2, 0x0fd2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
931{"psrld", 2, 0x0f72, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
932{"psrlq", 2, 0x0fd3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
933{"psrlq", 2, 0x0f73, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
934{"psubb", 2, 0x0ff8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
935{"psubw", 2, 0x0ff9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
936{"psubd", 2, 0x0ffa, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
937{"psubsb", 2, 0x0fe8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
938{"psubsw", 2, 0x0fe9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
939{"psubusb", 2, 0x0fd8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
940{"psubusw", 2, 0x0fd9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
941{"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
942{"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
943{"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
944{"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
945{"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
946{"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
947{"pxor", 2, 0x0fef, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
c608c12e
AM		 948
949
d0b47220 950/* PIII Katmai New Instructions / SIMD instructions. */
c608c12e 951
e413e4e9
AM		 952{"addps", 2, 0x0f58, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
953{"addss", 2, 0xf30f58, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
954{"andnps", 2, 0x0f55, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
955{"andps", 2, 0x0f54, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
956{"cmpeqps", 2, 0x0fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
957{"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
958{"cmpleps", 2, 0x0fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
959{"cmpless", 2, 0xf30fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
960{"cmpltps", 2, 0x0fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
961{"cmpltss", 2, 0xf30fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
962{"cmpneqps", 2, 0x0fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
963{"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
964{"cmpnleps", 2, 0x0fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
965{"cmpnless", 2, 0xf30fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
966{"cmpnltps", 2, 0x0fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
967{"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
968{"cmpordps", 2, 0x0fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
969{"cmpordss", 2, 0xf30fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
970{"cmpunordps",2, 0x0fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
971{"cmpunordss",2, 0xf30fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
972{"cmpps", 3, 0x0fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
973{"cmpss", 3, 0xf30fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } },
974{"comiss", 2, 0x0f2f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
975{"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
976{"cvtps2pi", 2, 0x0f2d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
977{"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, FP|Modrm, { Reg32|WordMem, RegXMM, 0 } },
978{"cvtss2si", 2, 0xf30f2d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } },
979{"cvttps2pi", 2, 0x0f2c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
980{"cvttss2si", 2, 0xf30f2c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } },
981{"divps", 2, 0x0f5e, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
982{"divss", 2, 0xf30f5e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
983{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, FP|Modrm, { WordMem, 0, 0 } },
984{"maskmovq", 2, 0x0ff7, X, CpuSSE, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } },
985{"maxps", 2, 0x0f5f, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
986{"maxss", 2, 0xf30f5f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
987{"minps", 2, 0x0f5d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
988{"minss", 2, 0xf30f5d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
989{"movaps", 2, 0x0f28, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
990{"movaps", 2, 0x0f29, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
991{"movhlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
992{"movhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } },
993{"movhps", 2, 0x0f17, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
994{"movlhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
995{"movlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } },
996{"movlps", 2, 0x0f13, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
997{"movmskps", 2, 0x0f50, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } },
998{"movntps", 2, 0x0f2b, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
999{"movntq", 2, 0x0fe7, X, CpuSSE, FP|Modrm, { RegMMX, LLongMem, 0 } },
1000{"movss", 2, 0xf30f10, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1001{"movss", 2, 0xf30f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } },
1002{"movups", 2, 0x0f10, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1003{"movups", 2, 0x0f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
1004{"mulps", 2, 0x0f59, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1005{"mulss", 2, 0xf30f59, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1006{"orps", 2, 0x0f56, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1007{"pavgb", 2, 0x0fe0, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1008{"pavgw", 2, 0x0fe3, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1009{"pextrw", 3, 0x0fc5, X, CpuSSE, FP|Modrm, { Imm8, RegMMX, Reg32|InvMem } },
1010{"pinsrw", 3, 0x0fc4, X, CpuSSE, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } },
1011{"pmaxsw", 2, 0x0fee, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1012{"pmaxub", 2, 0x0fde, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1013{"pminsw", 2, 0x0fea, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1014{"pminub", 2, 0x0fda, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1015{"pmovmskb", 2, 0x0fd7, X, CpuSSE, FP|Modrm, { RegMMX, Reg32|InvMem, 0 } },
1016{"pmulhuw", 2, 0x0fe4, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1017{"prefetchnta", 1, 0x0f18, 0, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1018{"prefetcht0", 1, 0x0f18, 1, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1019{"prefetcht1", 1, 0x0f18, 2, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1020{"prefetcht2", 1, 0x0f18, 3, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1021{"psadbw", 2, 0x0ff6, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1022{"pshufw", 3, 0x0f70, X, CpuSSE, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } },
1023{"rcpps", 2, 0x0f53, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1024{"rcpss", 2, 0xf30f53, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1025{"rsqrtps", 2, 0x0f52, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1026{"rsqrtss", 2, 0xf30f52, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1027{"sfence", 0, 0x0faef8, X, CpuSSE, FP, { 0, 0, 0 } },
1028{"shufps", 3, 0x0fc6, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1029{"sqrtps", 2, 0x0f51, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1030{"sqrtss", 2, 0xf30f51, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1031{"stmxcsr", 1, 0x0fae, 3, CpuSSE, FP|Modrm, { WordMem, 0, 0 } },
1032{"subps", 2, 0x0f5c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1033{"subss", 2, 0xf30f5c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1034{"ucomiss", 2, 0x0f2e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1035{"unpckhps", 2, 0x0f15, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1036{"unpcklps", 2, 0x0f14, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1037{"xorps", 2, 0x0f57, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
c608c12e 1038
d0b47220 1039/* AMD 3DNow! instructions. */
c608c12e 1040
e413e4e9
AM		 1041{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } },
1042{"prefetchw",1, 0x0f0d, 1, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } },
1043{"femms", 0, 0x0f0e, X, Cpu3dnow, FP, { 0, 0, 0 } },
1044{"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1045{"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1046{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1047{"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1048{"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1049{"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1050{"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1051{"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1052{"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1053{"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1054{"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1055{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1056{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1057{"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1058{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1059{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1060{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1061{"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1062{"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1063{"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1064{"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1065{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1066{"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1067{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1068
1069/* sentinel */
1070{NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
252b5132
RH		 1071};
1072#undef X
252b5132
RH		 1073#undef NoSuf
1074#undef b_Suf
1075#undef w_Suf
1076#undef l_Suf
eecb386c
AM		 1077#undef d_Suf
1078#undef x_Suf
252b5132
RH		 1079#undef bw_Suf
1080#undef bl_Suf
1081#undef wl_Suf
e413e4e9 1082#undef wld_Suf
252b5132 1083#undef sl_Suf
eecb386c
AM		 1084#undef sld_Suf
1085#undef sldx_Suf
252b5132 1086#undef bwl_Suf
eecb386c 1087#undef bwld_Suf
252b5132
RH		 1088#undef FP
1089#undef l_FP
eecb386c
AM		 1090#undef d_FP
1091#undef x_FP
252b5132 1092#undef sl_FP
eecb386c
AM		 1093#undef sld_FP
1094#undef sldx_FP
252b5132
RH		 1095
1096#define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */
1097
1098
d0b47220 1099/* 386 register table. */
252b5132
RH		 1100
1101static const reg_entry i386_regtab[] = {
5f47d35b
AM		 1102 /* make %st first as we test for it */
1103 {"st", FloatReg|FloatAcc, 0},
252b5132
RH		 1104 /* 8 bit regs */
1105 {"al", Reg8|Acc, 0},
1106 {"cl", Reg8|ShiftCount, 1},
1107 {"dl", Reg8, 2},
1108 {"bl", Reg8, 3},
1109 {"ah", Reg8, 4},
1110 {"ch", Reg8, 5},
1111 {"dh", Reg8, 6},
1112 {"bh", Reg8, 7},
1113 /* 16 bit regs */
1114 {"ax", Reg16|Acc, 0},
1115 {"cx", Reg16, 1},
1116 {"dx", Reg16|InOutPortReg, 2},
1117 {"bx", Reg16|BaseIndex, 3},
1118 {"sp", Reg16, 4},
1119 {"bp", Reg16|BaseIndex, 5},
1120 {"si", Reg16|BaseIndex, 6},
1121 {"di", Reg16|BaseIndex, 7},
1122 /* 32 bit regs */
1123 {"eax", Reg32|BaseIndex|Acc, 0},
1124 {"ecx", Reg32|BaseIndex, 1},
1125 {"edx", Reg32|BaseIndex, 2},
1126 {"ebx", Reg32|BaseIndex, 3},
1127 {"esp", Reg32, 4},
1128 {"ebp", Reg32|BaseIndex, 5},
1129 {"esi", Reg32|BaseIndex, 6},
1130 {"edi", Reg32|BaseIndex, 7},
1131 /* segment registers */
1132 {"es", SReg2, 0},
1133 {"cs", SReg2, 1},
1134 {"ss", SReg2, 2},
1135 {"ds", SReg2, 3},
1136 {"fs", SReg3, 4},
1137 {"gs", SReg3, 5},
1138 /* control registers */
1139 {"cr0", Control, 0},
1140 {"cr1", Control, 1},
1141 {"cr2", Control, 2},
1142 {"cr3", Control, 3},
1143 {"cr4", Control, 4},
1144 {"cr5", Control, 5},
1145 {"cr6", Control, 6},
1146 {"cr7", Control, 7},
1147 /* debug registers */
1148 {"db0", Debug, 0},
1149 {"db1", Debug, 1},
1150 {"db2", Debug, 2},
1151 {"db3", Debug, 3},
1152 {"db4", Debug, 4},
1153 {"db5", Debug, 5},
1154 {"db6", Debug, 6},
1155 {"db7", Debug, 7},
1156 {"dr0", Debug, 0},
1157 {"dr1", Debug, 1},
1158 {"dr2", Debug, 2},
1159 {"dr3", Debug, 3},
1160 {"dr4", Debug, 4},
1161 {"dr5", Debug, 5},
1162 {"dr6", Debug, 6},
1163 {"dr7", Debug, 7},
1164 /* test registers */
1165 {"tr0", Test, 0},
1166 {"tr1", Test, 1},
1167 {"tr2", Test, 2},
1168 {"tr3", Test, 3},
1169 {"tr4", Test, 4},
1170 {"tr5", Test, 5},
1171 {"tr6", Test, 6},
1172 {"tr7", Test, 7},
5f47d35b 1173 /* mmx and simd registers */
252b5132
RH		 1174 {"mm0", RegMMX, 0},
1175 {"mm1", RegMMX, 1},
1176 {"mm2", RegMMX, 2},
1177 {"mm3", RegMMX, 3},
1178 {"mm4", RegMMX, 4},
1179 {"mm5", RegMMX, 5},
1180 {"mm6", RegMMX, 6},
c608c12e
AM		 1181 {"mm7", RegMMX, 7},
1182 {"xmm0", RegXMM, 0},
1183 {"xmm1", RegXMM, 1},
1184 {"xmm2", RegXMM, 2},
1185 {"xmm3", RegXMM, 3},
1186 {"xmm4", RegXMM, 4},
1187 {"xmm5", RegXMM, 5},
1188 {"xmm6", RegXMM, 6},
1189 {"xmm7", RegXMM, 7}
252b5132
RH		 1190};
1191
5f47d35b
AM		 1192static const reg_entry i386_float_regtab[] = {
1193 {"st(0)", FloatReg|FloatAcc, 0},
1194 {"st(1)", FloatReg, 1},
1195 {"st(2)", FloatReg, 2},
1196 {"st(3)", FloatReg, 3},
1197 {"st(4)", FloatReg, 4},
1198 {"st(5)", FloatReg, 5},
1199 {"st(6)", FloatReg, 6},
1200 {"st(7)", FloatReg, 7}
1201};
1202
252b5132
RH		 1203#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
1204
1205/* segment stuff */
1206static const seg_entry cs = { "cs", 0x2e };
1207static const seg_entry ds = { "ds", 0x3e };
1208static const seg_entry ss = { "ss", 0x36 };
1209static const seg_entry es = { "es", 0x26 };
1210static const seg_entry fs = { "fs", 0x64 };
1211static const seg_entry gs = { "gs", 0x65 };
1212
1213/* end of opcode/i386.h */
GDB Binutils - Deliverables
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