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Fix compile errors in set_mips_isa_type
[deliverable/binutils-gdb.git] / include / opcode / i386.h
CommitLineData
ce868e5c 1/* i386-opcode.h -- Intel 80386 opcode table
d411c9ef 2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation.
ce868e5c
JG		 3
4This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
5
6This program is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2 of the License, or
9(at your option) any later version.
10
11This program is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with this program; if not, write to the Free Software
cd22144a 18Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
ce868e5c 19
ed44fb7a
ILT		 20/* The UnixWare assembler, and probably other AT&T derived ix86 Unix
21 assemblers, generate floating point instructions with reversed
22 source and destination registers in certain cases. Unfortunately,
23 gcc and possibly many other programs use this reversed syntax, so
24 we're stuck with it.
25
26 eg. `fsub %st(3),%st' results in st <- st - st(3) as expected, but
b8e4d255 27 `fsub %st,%st(3)' results in st(3) <- st - st(3), rather than
ed44fb7a
ILT		 28 the expected st(3) <- st(3) - st !
29
30 This happens with all the non-commutative arithmetic floating point
31 operations with two register operands, where the source register is
32 %st, and destination register is %st(i). Look for FloatDR below. */
33
34#ifndef UNIXWARE_COMPAT
35/* Set non-zero for broken, compatible instructions. Set to zero for
36 non-broken opcodes at your peril. gcc generates UnixWare
37 compatible instructions. */
38#define UNIXWARE_COMPAT 1
39#endif
40
c0d7b534 41
ce868e5c
JG		 42static const template i386_optab[] = {
43
77be9a8a 44#define X None
ed44fb7a
ILT		 45#define ReverseModrm (ReverseRegRegmem|Modrm)
46#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf)
47#define b_Suf (No_wSuf|No_lSuf|No_sSuf)
48#define w_Suf (No_bSuf|No_lSuf|No_sSuf)
49#define l_Suf (No_bSuf|No_wSuf|No_sSuf)
50#define bw_Suf (No_lSuf|No_sSuf)
51#define bl_Suf (No_wSuf|No_sSuf)
52#define wl_Suf (No_bSuf|No_sSuf)
038915c9 53#define sl_Suf (No_bSuf|No_wSuf)
ed44fb7a 54#define bwl_Suf No_sSuf
b8e4d255
ILT		 55#define FP (NoSuf|IgnoreSize)
56#define l_FP (l_Suf|IgnoreSize)
57#define sl_FP (sl_Suf|IgnoreSize)
ed44fb7a
ILT		 58#if UNIXWARE_COMPAT
59#define FloatDR FloatD
60#else
61#define FloatDR (FloatD|FloatR)
62#endif
ffabaa53 63
ce868e5c 64/* move instructions */
a43022bd 65#define MOV_AX_DISP32 0xa0
038915c9 66{ "mov", 2, 0xa0, X, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
ed44fb7a
ILT		 67{ "mov", 2, 0x88, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } },
68{ "mov", 2, 0xb0, X, bwl_Suf|W|ShortForm, { Imm, Reg, 0 } },
69{ "mov", 2, 0xc6, X, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0 } },
70/* The next two instructions accept WordReg so that a segment register
71 can be copied to a 32 bit register, and vice versa, without using a
72 size prefix. When moving to a 32 bit register, the upper 16 bits
73 are set to an implementation defined value (on the Pentium Pro,
ffabaa53 74 the implementation defined value is zero). */
ed44fb7a 75{ "mov", 2, 0x8c, X, wl_Suf|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } },
b8e4d255 76{ "mov", 2, 0x8e, X, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3|SReg2, 0 } },
ce868e5c 77/* move to/from control debug registers */
b8e4d255
ILT		 78{ "mov", 2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32, 0} },
79{ "mov", 2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32, 0} },
80{ "mov", 2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32, 0} },
ce868e5c
JG		 81
82/* move with sign extend */
83/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
b8e4d255
ILT		 84 conflict with the "movs" string move instruction. */
85{"movsbl", 2, 0x0fbe, X, NoSuf|ReverseModrm, { Reg8|ByteMem, Reg32, 0} },
86{"movsbw", 2, 0x0fbe, X, NoSuf|ReverseModrm, { Reg8|ByteMem, Reg16, 0} },
87{"movswl", 2, 0x0fbf, X, NoSuf|ReverseModrm, { Reg16|ShortMem, Reg32, 0} },
ce868e5c
JG		 88
89/* move with zero extend */
b8e4d255
ILT		 90{"movzb", 2, 0x0fb6, X, wl_Suf|ReverseModrm, { Reg8|ByteMem, WordReg, 0} },
91{"movzwl", 2, 0x0fb7, X, NoSuf|ReverseModrm, { Reg16|ShortMem, Reg32, 0} },
ce868e5c
JG		 92
93/* push instructions */
ed44fb7a
ILT		 94{"push", 1, 0x50, X, wl_Suf|ShortForm, { WordReg,0,0 } },
95{"push", 1, 0xff, 6, wl_Suf|Modrm, { WordReg|WordMem, 0, 0 } },
96{"push", 1, 0x6a, X, wl_Suf, { Imm8S, 0, 0} },
97{"push", 1, 0x68, X, wl_Suf, { Imm16|Imm32, 0, 0} },
98{"push", 1, 0x06, X, wl_Suf|Seg2ShortForm, { SReg2,0,0 } },
99{"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm, { SReg3,0,0 } },
ce868e5c 100/* push all */
ed44fb7a 101{"pusha", 0, 0x60, X, wl_Suf, { 0, 0, 0 } },
ce868e5c
JG		 102
103/* pop instructions */
ed44fb7a
ILT		 104{"pop", 1, 0x58, X, wl_Suf|ShortForm, { WordReg,0,0 } },
105{"pop", 1, 0x8f, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0 } },
106#define POP_SEG_SHORT 0x07
107{"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm, { SReg2,0,0 } },
108{"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm, { SReg3,0,0 } },
ce868e5c 109/* pop all */
ed44fb7a 110{"popa", 0, 0x61, X, wl_Suf, { 0, 0, 0 } },
ce868e5c
JG		 111
112/* xchg exchange instructions
113 xchg commutes: we allow both operand orders */
ed44fb7a
ILT		 114{"xchg", 2, 0x90, X, wl_Suf|ShortForm, { WordReg, Acc, 0 } },
115{"xchg", 2, 0x90, X, wl_Suf|ShortForm, { Acc, WordReg, 0 } },
116{"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
117{"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } },
ce868e5c
JG		 118
119/* in/out from ports */
ed44fb7a
ILT		 120{"in", 2, 0xe4, X, bwl_Suf|W, { Imm8, Acc, 0 } },
121{"in", 2, 0xec, X, bwl_Suf|W, { InOutPortReg, Acc, 0 } },
122{"in", 1, 0xe4, X, bwl_Suf|W, { Imm8, 0, 0 } },
123{"in", 1, 0xec, X, bwl_Suf|W, { InOutPortReg, 0, 0 } },
124{"out", 2, 0xe6, X, bwl_Suf|W, { Acc, Imm8, 0 } },
125{"out", 2, 0xee, X, bwl_Suf|W, { Acc, InOutPortReg, 0 } },
126{"out", 1, 0xe6, X, bwl_Suf|W, { Imm8, 0, 0 } },
127{"out", 1, 0xee, X, bwl_Suf|W, { InOutPortReg, 0, 0 } },
fc0d7441 128
ce868e5c 129/* load effective address */
ed44fb7a 130{"lea", 2, 0x8d, X, wl_Suf|Modrm, { WordMem, WordReg, 0 } },
ce868e5c
JG		 131
132/* load segment registers from memory */
ed44fb7a
ILT		 133{"lds", 2, 0xc5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
134{"les", 2, 0xc4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
135{"lfs", 2, 0x0fb4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
136{"lgs", 2, 0x0fb5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
137{"lss", 2, 0x0fb2, X, wl_Suf|Modrm, { WordMem, WordReg, 0} },
ce868e5c
JG		 138
139/* flags register instructions */
ed44fb7a
ILT		 140{"clc", 0, 0xf8, X, NoSuf, { 0, 0, 0} },
141{"cld", 0, 0xfc, X, NoSuf, { 0, 0, 0} },
142{"cli", 0, 0xfa, X, NoSuf, { 0, 0, 0} },
143{"clts", 0, 0x0f06, X, NoSuf, { 0, 0, 0} },
144{"cmc", 0, 0xf5, X, NoSuf, { 0, 0, 0} },
145{"lahf", 0, 0x9f, X, NoSuf, { 0, 0, 0} },
146{"sahf", 0, 0x9e, X, NoSuf, { 0, 0, 0} },
147{"pushf", 0, 0x9c, X, wl_Suf, { 0, 0, 0} },
148{"popf", 0, 0x9d, X, wl_Suf, { 0, 0, 0} },
149{"stc", 0, 0xf9, X, NoSuf, { 0, 0, 0} },
150{"std", 0, 0xfd, X, NoSuf, { 0, 0, 0} },
151{"sti", 0, 0xfb, X, NoSuf, { 0, 0, 0} },
152
153/* arithmetic */
154{"add", 2, 0x00, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
155{"add", 2, 0x83, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
156{"add", 2, 0x04, X, bwl_Suf|W, { Imm, Acc, 0} },
157{"add", 2, 0x80, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
158
159{"inc", 1, 0x40, X, wl_Suf|ShortForm, { WordReg, 0, 0} },
160{"inc", 1, 0xfe, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
161
162{"sub", 2, 0x28, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
163{"sub", 2, 0x83, 5, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
164{"sub", 2, 0x2c, X, bwl_Suf|W, { Imm, Acc, 0} },
165{"sub", 2, 0x80, 5, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
166
167{"dec", 1, 0x48, X, wl_Suf|ShortForm, { WordReg, 0, 0} },
168{"dec", 1, 0xfe, 1, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
169
170{"sbb", 2, 0x18, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
171{"sbb", 2, 0x83, 3, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
172{"sbb", 2, 0x1c, X, bwl_Suf|W, { Imm, Acc, 0} },
173{"sbb", 2, 0x80, 3, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
174
175{"cmp", 2, 0x38, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
176{"cmp", 2, 0x83, 7, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
177{"cmp", 2, 0x3c, X, bwl_Suf|W, { Imm, Acc, 0} },
178{"cmp", 2, 0x80, 7, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
179
180{"test", 2, 0x84, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} },
181{"test", 2, 0x84, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} },
182{"test", 2, 0xa8, X, bwl_Suf|W, { Imm, Acc, 0} },
183{"test", 2, 0xf6, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
184
185{"and", 2, 0x20, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
186{"and", 2, 0x83, 4, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
187{"and", 2, 0x24, X, bwl_Suf|W, { Imm, Acc, 0} },
188{"and", 2, 0x80, 4, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
189
190{"or", 2, 0x08, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
191{"or", 2, 0x83, 1, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
192{"or", 2, 0x0c, X, bwl_Suf|W, { Imm, Acc, 0} },
193{"or", 2, 0x80, 1, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
194
195{"xor", 2, 0x30, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
196{"xor", 2, 0x83, 6, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
197{"xor", 2, 0x34, X, bwl_Suf|W, { Imm, Acc, 0} },
198{"xor", 2, 0x80, 6, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
199
200/* iclr with 1 operand is really xor with 2 operands. */
201{"clr", 1, 0x30, X, bwl_Suf|W|Modrm|regKludge, { Reg, 0, 0 } },
202
203{"adc", 2, 0x10, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
204{"adc", 2, 0x83, 2, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
205{"adc", 2, 0x14, X, bwl_Suf|W, { Imm, Acc, 0} },
206{"adc", 2, 0x80, 2, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
207
208{"neg", 1, 0xf6, 3, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
209{"not", 1, 0xf6, 2, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
210
211{"aaa", 0, 0x37, X, NoSuf, { 0, 0, 0} },
212{"aas", 0, 0x3f, X, NoSuf, { 0, 0, 0} },
213{"daa", 0, 0x27, X, NoSuf, { 0, 0, 0} },
214{"das", 0, 0x2f, X, NoSuf, { 0, 0, 0} },
215{"aad", 0, 0xd50a, X, NoSuf, { 0, 0, 0} },
216{"aam", 0, 0xd40a, X, NoSuf, { 0, 0, 0} },
ce868e5c
JG		 217
218/* conversion insns */
ed44fb7a 219/* conversion: intel naming */
b8e4d255
ILT		 220{"cbw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} },
221{"cwde", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} },
222{"cwd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} },
223{"cdq", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} },
ce868e5c 224/* att naming */
b8e4d255
ILT		 225{"cbtw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} },
226{"cwtl", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} },
227{"cwtd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} },
228{"cltd", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} },
ce868e5c
JG		 229
230/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
231 expanding 64-bit multiplies, and *cannot* be selected to accomplish
232 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
77be9a8a 233 These multiplies can only be selected with single operand forms. */
ed44fb7a
ILT		 234{"mul", 1, 0xf6, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
235{"imul", 1, 0xf6, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
236{"imul", 2, 0x0faf, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
237{"imul", 3, 0x6b, X, wl_Suf|ReverseModrm, { Imm8S, WordReg|WordMem, WordReg} },
238{"imul", 3, 0x69, X, wl_Suf|ReverseModrm, { Imm16|Imm32, WordReg|WordMem, WordReg} },
77be9a8a
ILT		 239/* imul with 2 operands mimics imul with 3 by putting the register in
240 both i.rm.reg & i.rm.regmem fields. regKludge enables this
241 transformation. */
ed44fb7a
ILT		 242{"imul", 2, 0x6b, X, wl_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
243{"imul", 2, 0x69, X, wl_Suf|Modrm|regKludge,{ Imm16|Imm32, WordReg, 0} },
244
245{"div", 1, 0xf6, 6, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
246{"div", 2, 0xf6, 6, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
247{"idiv", 1, 0xf6, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
248{"idiv", 2, 0xf6, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
249
250{"rol", 2, 0xd0, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
251{"rol", 2, 0xc0, 0, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
252{"rol", 2, 0xd2, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
253{"rol", 1, 0xd0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
254
255{"ror", 2, 0xd0, 1, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
256{"ror", 2, 0xc0, 1, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
257{"ror", 2, 0xd2, 1, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
258{"ror", 1, 0xd0, 1, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
259
260{"rcl", 2, 0xd0, 2, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
261{"rcl", 2, 0xc0, 2, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
262{"rcl", 2, 0xd2, 2, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
263{"rcl", 1, 0xd0, 2, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
264
265{"rcr", 2, 0xd0, 3, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
266{"rcr", 2, 0xc0, 3, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
267{"rcr", 2, 0xd2, 3, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
268{"rcr", 1, 0xd0, 3, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
269
270{"sal", 2, 0xd0, 4, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
271{"sal", 2, 0xc0, 4, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
272{"sal", 2, 0xd2, 4, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
273{"sal", 1, 0xd0, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
274{"shl", 2, 0xd0, 4, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
275{"shl", 2, 0xc0, 4, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
276{"shl", 2, 0xd2, 4, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
277{"shl", 1, 0xd0, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
278
279{"shld", 3, 0x0fa4, X, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
280{"shld", 3, 0x0fa5, X, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
281{"shld", 2, 0x0fa5, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
282
283{"shr", 2, 0xd0, 5, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
284{"shr", 2, 0xc0, 5, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
285{"shr", 2, 0xd2, 5, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
286{"shr", 1, 0xd0, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
287
288{"shrd", 3, 0x0fac, X, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
289{"shrd", 3, 0x0fad, X, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
290{"shrd", 2, 0x0fad, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
291
292{"sar", 2, 0xd0, 7, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
293{"sar", 2, 0xc0, 7, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
294{"sar", 2, 0xd2, 7, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
295{"sar", 1, 0xd0, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
ce868e5c
JG		 296
297/* control transfer instructions */
038915c9
ILT		 298{"call", 1, 0xe8, X, wl_Suf|JumpDword, { Disp16|Disp32, 0, 0} },
299{"call", 1, 0xff, 2, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
300{"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
301{"lcall", 1, 0xff, 3, wl_Suf|Modrm, { WordMem, 0, 0} },
ce868e5c
JG		 302
303#define JUMP_PC_RELATIVE 0xeb
ed44fb7a
ILT		 304{"jmp", 1, 0xeb, X, NoSuf|Jump, { Disp, 0, 0} },
305{"jmp", 1, 0xff, 4, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
038915c9 306{"ljmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
ed44fb7a
ILT		 307{"ljmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem, 0, 0} },
308
038915c9
ILT		 309{"ret", 0, 0xc3, X, wl_Suf, { 0, 0, 0} },
310{"ret", 1, 0xc2, X, wl_Suf, { Imm16, 0, 0} },
311{"lret", 0, 0xcb, X, wl_Suf, { 0, 0, 0} },
312{"lret", 1, 0xca, X, wl_Suf, { Imm16, 0, 0} },
313{"enter", 2, 0xc8, X, wl_Suf, { Imm16, Imm8, 0} },
314{"leave", 0, 0xc9, X, wl_Suf, { 0, 0, 0} },
ce868e5c
JG		 315
316/* conditional jumps */
ed44fb7a
ILT		 317{"jo", 1, 0x70, X, NoSuf|Jump, { Disp, 0, 0} },
318{"jno", 1, 0x71, X, NoSuf|Jump, { Disp, 0, 0} },
319{"jb", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} },
320{"jc", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} },
321{"jnae", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} },
322{"jnb", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} },
323{"jnc", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} },
324{"jae", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} },
325{"je", 1, 0x74, X, NoSuf|Jump, { Disp, 0, 0} },
326{"jz", 1, 0x74, X, NoSuf|Jump, { Disp, 0, 0} },
327{"jne", 1, 0x75, X, NoSuf|Jump, { Disp, 0, 0} },
328{"jnz", 1, 0x75, X, NoSuf|Jump, { Disp, 0, 0} },
329{"jbe", 1, 0x76, X, NoSuf|Jump, { Disp, 0, 0} },
330{"jna", 1, 0x76, X, NoSuf|Jump, { Disp, 0, 0} },
331{"jnbe", 1, 0x77, X, NoSuf|Jump, { Disp, 0, 0} },
332{"ja", 1, 0x77, X, NoSuf|Jump, { Disp, 0, 0} },
333{"js", 1, 0x78, X, NoSuf|Jump, { Disp, 0, 0} },
334{"jns", 1, 0x79, X, NoSuf|Jump, { Disp, 0, 0} },
335{"jp", 1, 0x7a, X, NoSuf|Jump, { Disp, 0, 0} },
336{"jpe", 1, 0x7a, X, NoSuf|Jump, { Disp, 0, 0} },
337{"jnp", 1, 0x7b, X, NoSuf|Jump, { Disp, 0, 0} },
338{"jpo", 1, 0x7b, X, NoSuf|Jump, { Disp, 0, 0} },
339{"jl", 1, 0x7c, X, NoSuf|Jump, { Disp, 0, 0} },
340{"jnge", 1, 0x7c, X, NoSuf|Jump, { Disp, 0, 0} },
341{"jnl", 1, 0x7d, X, NoSuf|Jump, { Disp, 0, 0} },
342{"jge", 1, 0x7d, X, NoSuf|Jump, { Disp, 0, 0} },
343{"jle", 1, 0x7e, X, NoSuf|Jump, { Disp, 0, 0} },
344{"jng", 1, 0x7e, X, NoSuf|Jump, { Disp, 0, 0} },
345{"jnle", 1, 0x7f, X, NoSuf|Jump, { Disp, 0, 0} },
346{"jg", 1, 0x7f, X, NoSuf|Jump, { Disp, 0, 0} },
ce868e5c 347
c2367582 348/* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
b8e4d255
ILT		 349{"jcxz", 1, 0xe3, X, NoSuf|JumpByte|Size16, { Disp, 0, 0} },
350{"jecxz", 1, 0xe3, X, NoSuf|JumpByte|Size32, { Disp, 0, 0} },
ed44fb7a
ILT		 351
352/* The loop instructions also use the address size prefix to select
353 %cx rather than %ecx for the loop count, so the `w' form of these
354 instructions emit an address size prefix rather than a data size
355 prefix. */
356{"loop", 1, 0xe2, X, wl_Suf|JumpByte, { Disp, 0, 0} },
357{"loopz", 1, 0xe1, X, wl_Suf|JumpByte, { Disp, 0, 0} },
358{"loope", 1, 0xe1, X, wl_Suf|JumpByte, { Disp, 0, 0} },
359{"loopnz", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} },
360{"loopne", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} },
ce868e5c
JG		 361
362/* set byte on flag instructions */
ed44fb7a
ILT		 363{"seto", 1, 0x0f90, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
364{"setno", 1, 0x0f91, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
365{"setb", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
366{"setc", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
367{"setnae", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
368{"setnb", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
369{"setnc", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
370{"setae", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
371{"sete", 1, 0x0f94, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
372{"setz", 1, 0x0f94, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
373{"setne", 1, 0x0f95, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
374{"setnz", 1, 0x0f95, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
375{"setbe", 1, 0x0f96, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
376{"setna", 1, 0x0f96, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
377{"setnbe", 1, 0x0f97, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
378{"seta", 1, 0x0f97, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
379{"sets", 1, 0x0f98, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
380{"setns", 1, 0x0f99, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
381{"setp", 1, 0x0f9a, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
382{"setpe", 1, 0x0f9a, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
383{"setnp", 1, 0x0f9b, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
384{"setpo", 1, 0x0f9b, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
385{"setl", 1, 0x0f9c, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
386{"setnge", 1, 0x0f9c, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
387{"setnl", 1, 0x0f9d, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
388{"setge", 1, 0x0f9d, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
389{"setle", 1, 0x0f9e, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
390{"setng", 1, 0x0f9e, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
391{"setnle", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
392{"setg", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
ce868e5c 393
ce868e5c 394/* string manipulation */
ed44fb7a
ILT		 395{"cmps", 0, 0xa6, X, bwl_Suf|W|IsString, { 0, 0, 0} },
396{"cmps", 2, 0xa6, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
397{"scmp", 0, 0xa6, X, bwl_Suf|W|IsString, { 0, 0, 0} },
398{"scmp", 2, 0xa6, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
399{"ins", 0, 0x6c, X, bwl_Suf|W|IsString, { 0, 0, 0} },
400{"ins", 2, 0x6c, X, bwl_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} },
401{"outs", 0, 0x6e, X, bwl_Suf|W|IsString, { 0, 0, 0} },
402{"outs", 2, 0x6e, X, bwl_Suf|W|IsString, { AnyMem, InOutPortReg, 0} },
403{"lods", 0, 0xac, X, bwl_Suf|W|IsString, { 0, 0, 0} },
404{"lods", 1, 0xac, X, bwl_Suf|W|IsString, { AnyMem, 0, 0} },
405{"lods", 2, 0xac, X, bwl_Suf|W|IsString, { AnyMem, Acc, 0} },
406{"slod", 0, 0xac, X, bwl_Suf|W|IsString, { 0, 0, 0} },
407{"slod", 1, 0xac, X, bwl_Suf|W|IsString, { AnyMem, 0, 0} },
408{"slod", 2, 0xac, X, bwl_Suf|W|IsString, { AnyMem, Acc, 0} },
409{"movs", 0, 0xa4, X, bwl_Suf|W|IsString, { 0, 0, 0} },
410{"movs", 2, 0xa4, X, bwl_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
411{"smov", 0, 0xa4, X, bwl_Suf|W|IsString, { 0, 0, 0} },
412{"smov", 2, 0xa4, X, bwl_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
413{"scas", 0, 0xae, X, bwl_Suf|W|IsString, { 0, 0, 0} },
414{"scas", 1, 0xae, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
415{"scas", 2, 0xae, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
416{"ssca", 0, 0xae, X, bwl_Suf|W|IsString, { 0, 0, 0} },
417{"ssca", 1, 0xae, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
418{"ssca", 2, 0xae, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
419{"stos", 0, 0xaa, X, bwl_Suf|W|IsString, { 0, 0, 0} },
420{"stos", 1, 0xaa, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
421{"stos", 2, 0xaa, X, bwl_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
422{"ssto", 0, 0xaa, X, bwl_Suf|W|IsString, { 0, 0, 0} },
423{"ssto", 1, 0xaa, X, bwl_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
424{"ssto", 2, 0xaa, X, bwl_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
425{"xlat", 0, 0xd7, X, b_Suf|IsString, { 0, 0, 0} },
426{"xlat", 1, 0xd7, X, b_Suf|IsString, { AnyMem, 0, 0} },
ce868e5c
JG		 427
428/* bit manipulation */
ed44fb7a
ILT		 429{"bsf", 2, 0x0fbc, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
430{"bsr", 2, 0x0fbd, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
431{"bt", 2, 0x0fa3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
432{"bt", 2, 0x0fba, 4, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
433{"btc", 2, 0x0fbb, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
434{"btc", 2, 0x0fba, 7, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
435{"btr", 2, 0x0fb3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
436{"btr", 2, 0x0fba, 6, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
437{"bts", 2, 0x0fab, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
438{"bts", 2, 0x0fba, 5, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
ce868e5c
JG		 439
440/* interrupts & op. sys insns */
a43022bd
KR		 441/* See gas/config/tc-i386.c for conversion of 'int $3' into the special
442 int 3 insn. */
ce868e5c
JG		 443#define INT_OPCODE 0xcd
444#define INT3_OPCODE 0xcc
ed44fb7a
ILT		 445{"int", 1, 0xcd, X, NoSuf, { Imm8, 0, 0} },
446{"int3", 0, 0xcc, X, NoSuf, { 0, 0, 0} },
447{"into", 0, 0xce, X, NoSuf, { 0, 0, 0} },
038915c9 448{"iret", 0, 0xcf, X, wl_Suf, { 0, 0, 0} },
cd22144a 449/* i386sl, i486sl, later 486, and Pentium */
ed44fb7a 450{"rsm", 0, 0x0faa, X, NoSuf, { 0, 0, 0} },
ce868e5c 451
ed44fb7a 452{"bound", 2, 0x62, X, wl_Suf|Modrm, { WordReg, WordMem, 0} },
ce868e5c 453
ed44fb7a 454{"hlt", 0, 0xf4, X, NoSuf, { 0, 0, 0} },
ce868e5c 455/* nop is actually 'xchgl %eax, %eax' */
ed44fb7a 456{"nop", 0, 0x90, X, NoSuf, { 0, 0, 0} },
ce868e5c
JG		 457
458/* protection control */
b8e4d255 459{"arpl", 2, 0x63, X, NoSuf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
ed44fb7a
ILT		 460{"lar", 2, 0x0f02, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
461{"lgdt", 1, 0x0f01, 2, wl_Suf|Modrm, { WordMem, 0, 0} },
462{"lidt", 1, 0x0f01, 3, wl_Suf|Modrm, { WordMem, 0, 0} },
b8e4d255
ILT		 463{"lldt", 1, 0x0f00, 2, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
464{"lmsw", 1, 0x0f01, 6, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
ed44fb7a 465{"lsl", 2, 0x0f03, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
b8e4d255 466{"ltr", 1, 0x0f00, 3, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
ed44fb7a
ILT		 467
468{"sgdt", 1, 0x0f01, 0, wl_Suf|Modrm, { WordMem, 0, 0} },
469{"sidt", 1, 0x0f01, 1, wl_Suf|Modrm, { WordMem, 0, 0} },
470{"sldt", 1, 0x0f00, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} },
471{"smsw", 1, 0x0f01, 4, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} },
b8e4d255 472{"str", 1, 0x0f00, 1, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
ed44fb7a 473
b8e4d255
ILT		 474{"verr", 1, 0x0f00, 4, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
475{"verw", 1, 0x0f00, 5, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
ce868e5c
JG		 476
477/* floating point instructions */
478
479/* load */
ed44fb7a
ILT		 480{"fld", 1, 0xd9c0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */
481{"fld", 1, 0xd9, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 <-- mem float/double */
482{"fld", 1, 0xd9c0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
483{"fild", 1, 0xdf, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 <-- mem word(16)/dword(32) */
484{"fildq", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */
485{"fildll", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */
486{"fldt", 1, 0xdb, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem efloat */
487{"fbld", 1, 0xdf, 4, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem bcd */
ce868e5c
JG		 488
489/* store (no pop) */
ed44fb7a
ILT		 490{"fst", 1, 0xddd0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */
491{"fst", 1, 0xd9, 2, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 --> mem float/double */
492{"fst", 1, 0xddd0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
493{"fist", 1, 0xdf, 2, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */
ce868e5c
JG		 494
495/* store (with pop) */
ed44fb7a
ILT		 496{"fstp", 1, 0xddd8, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */
497{"fstp", 1, 0xd9, 3, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 --> mem float/double */
498{"fstp", 1, 0xddd8, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
499{"fistp", 1, 0xdf, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */
500{"fistpq", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */
501{"fistpll",1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */
502{"fstpt", 1, 0xdb, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem efloat */
503{"fbstp", 1, 0xdf, 6, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem bcd */
ce868e5c
JG		 504
505/* exchange %st<n> with %st0 */
ed44fb7a
ILT		 506{"fxch", 1, 0xd9c8, X, FP|ShortForm, { FloatReg, 0, 0} },
507{"fxch", 0, 0xd9c9, X, FP, { 0, 0, 0} }, /* alias for fxch %st(1) */
ce868e5c
JG		 508
509/* comparison (without pop) */
ed44fb7a
ILT		 510{"fcom", 1, 0xd8d0, X, FP|ShortForm, { FloatReg, 0, 0} },
511{"fcom", 0, 0xd8d1, X, FP, { 0, 0, 0} }, /* alias for fcom %st(1) */
512{"fcom", 1, 0xd8, 2, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* compare %st0, mem float/double */
513{"fcom", 1, 0xd8d0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
514{"ficom", 1, 0xde, 2, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* compare %st0, mem word/dword */
ce868e5c
JG		 515
516/* comparison (with pop) */
ed44fb7a
ILT		 517{"fcomp", 1, 0xd8d8, X, FP|ShortForm, { FloatReg, 0, 0} },
518{"fcomp", 0, 0xd8d9, X, FP, { 0, 0, 0} }, /* alias for fcomp %st(1) */
519{"fcomp", 1, 0xd8, 3, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* compare %st0, mem float/double */
520{"fcomp", 1, 0xd8d8, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
521{"ficomp", 1, 0xde, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* compare %st0, mem word/dword */
522{"fcompp", 0, 0xded9, X, FP, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */
ce868e5c
JG		 523
524/* unordered comparison (with pop) */
ed44fb7a
ILT		 525{"fucom", 1, 0xdde0, X, FP|ShortForm, { FloatReg, 0, 0} },
526{"fucom", 0, 0xdde1, X, FP, { 0, 0, 0} }, /* alias for fucom %st(1) */
527{"fucomp", 1, 0xdde8, X, FP|ShortForm, { FloatReg, 0, 0} },
528{"fucomp", 0, 0xdde9, X, FP, { 0, 0, 0} }, /* alias for fucomp %st(1) */
529{"fucompp",0, 0xdae9, X, FP, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
ce868e5c 530
ed44fb7a
ILT		 531{"ftst", 0, 0xd9e4, X, FP, { 0, 0, 0} }, /* test %st0 */
532{"fxam", 0, 0xd9e5, X, FP, { 0, 0, 0} }, /* examine %st0 */
ce868e5c
JG		 533
534/* load constants into %st0 */
ed44fb7a
ILT		 535{"fld1", 0, 0xd9e8, X, FP, { 0, 0, 0} }, /* %st0 <-- 1.0 */
536{"fldl2t", 0, 0xd9e9, X, FP, { 0, 0, 0} }, /* %st0 <-- log2(10) */
537{"fldl2e", 0, 0xd9ea, X, FP, { 0, 0, 0} }, /* %st0 <-- log2(e) */
538{"fldpi", 0, 0xd9eb, X, FP, { 0, 0, 0} }, /* %st0 <-- pi */
539{"fldlg2", 0, 0xd9ec, X, FP, { 0, 0, 0} }, /* %st0 <-- log10(2) */
540{"fldln2", 0, 0xd9ed, X, FP, { 0, 0, 0} }, /* %st0 <-- ln(2) */
541{"fldz", 0, 0xd9ee, X, FP, { 0, 0, 0} }, /* %st0 <-- 0.0 */
ce868e5c
JG		 542
543/* arithmetic */
544
545/* add */
ed44fb7a
ILT		 546{"fadd", 2, 0xd8c0, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
547{"fadd", 1, 0xd8c0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for fadd %st(i), %st */
548#if UNIXWARE_COMPAT
549{"fadd", 0, 0xdec1, X, FP|Ugh, { 0, 0, 0} }, /* alias for faddp */
ce868e5c 550#endif
ed44fb7a
ILT		 551{"fadd", 1, 0xd8, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
552{"fiadd", 1, 0xde, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
553
554{"faddp", 2, 0xdec0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
555{"faddp", 1, 0xdec0, X, FP|ShortForm, { FloatReg, 0, 0} },
556{"faddp", 0, 0xdec1, X, FP, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
557{"faddp", 2, 0xdec0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
558
559/* subtract */
560{"fsub", 2, 0xd8e0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
561{"fsub", 1, 0xd8e0, X, FP|ShortForm, { FloatReg, 0, 0} },
562#if UNIXWARE_COMPAT
563{"fsub", 0, 0xdee1, X, FP|Ugh, { 0, 0, 0} }, /* alias for fsubp */
ce868e5c 564#endif
ed44fb7a
ILT		 565{"fsub", 1, 0xd8, 4, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
566{"fisub", 1, 0xde, 4, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
567
568#if UNIXWARE_COMPAT
569{"fsubp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
570{"fsubp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} },
571{"fsubp", 0, 0xdee1, X, FP, { 0, 0, 0} },
572{"fsubp", 2, 0xdee0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
ce868e5c 573#else
ed44fb7a
ILT		 574{"fsubp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
575{"fsubp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} },
576{"fsubp", 0, 0xdee9, X, FP, { 0, 0, 0} },
ce868e5c 577#endif
ed44fb7a
ILT		 578
579/* subtract reverse */
580{"fsubr", 2, 0xd8e8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
581{"fsubr", 1, 0xd8e8, X, FP|ShortForm, { FloatReg, 0, 0} },
582#if UNIXWARE_COMPAT
583{"fsubr", 0, 0xdee9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fsubrp */
ce868e5c 584#endif
ed44fb7a
ILT		 585{"fsubr", 1, 0xd8, 5, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
586{"fisubr", 1, 0xde, 5, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
587
588#if UNIXWARE_COMPAT
589{"fsubrp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
590{"fsubrp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} },
591{"fsubrp", 0, 0xdee9, X, FP, { 0, 0, 0} },
592{"fsubrp", 2, 0xdee8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
ce868e5c 593#else
ed44fb7a
ILT		 594{"fsubrp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
595{"fsubrp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} },
596{"fsubrp", 0, 0xdee1, X, FP, { 0, 0, 0} },
ce868e5c 597#endif
ed44fb7a
ILT		 598
599/* multiply */
600{"fmul", 2, 0xd8c8, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
601{"fmul", 1, 0xd8c8, X, FP|ShortForm, { FloatReg, 0, 0} },
602#if UNIXWARE_COMPAT
603{"fmul", 0, 0xdec9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fmulp */
604#endif
605{"fmul", 1, 0xd8, 1, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
606{"fimul", 1, 0xde, 1, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
607
608{"fmulp", 2, 0xdec8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
609{"fmulp", 1, 0xdec8, X, FP|ShortForm, { FloatReg, 0, 0} },
610{"fmulp", 0, 0xdec9, X, FP, { 0, 0, 0} },
611{"fmulp", 2, 0xdec8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
612
613/* divide */
614{"fdiv", 2, 0xd8f0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
615{"fdiv", 1, 0xd8f0, X, FP|ShortForm, { FloatReg, 0, 0} },
616#if UNIXWARE_COMPAT
617{"fdiv", 0, 0xdef1, X, FP|Ugh, { 0, 0, 0} }, /* alias for fdivp */
ce868e5c 618#endif
ed44fb7a
ILT		 619{"fdiv", 1, 0xd8, 6, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
620{"fidiv", 1, 0xde, 6, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
621
622#if UNIXWARE_COMPAT
623{"fdivp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
624{"fdivp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} },
625{"fdivp", 0, 0xdef1, X, FP, { 0, 0, 0} },
626{"fdivp", 2, 0xdef0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
ce868e5c 627#else
ed44fb7a
ILT		 628{"fdivp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
629{"fdivp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} },
630{"fdivp", 0, 0xdef9, X, FP, { 0, 0, 0} },
ce868e5c 631#endif
ed44fb7a
ILT		 632
633/* divide reverse */
634{"fdivr", 2, 0xd8f8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
635{"fdivr", 1, 0xd8f8, X, FP|ShortForm, { FloatReg, 0, 0} },
636#if UNIXWARE_COMPAT
637{"fdivr", 0, 0xdef9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fdivrp */
638#endif
639{"fdivr", 1, 0xd8, 7, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
640{"fidivr", 1, 0xde, 7, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
641
642#if UNIXWARE_COMPAT
643{"fdivrp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
644{"fdivrp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} },
645{"fdivrp", 0, 0xdef9, X, FP, { 0, 0, 0} },
646{"fdivrp", 2, 0xdef8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
ce868e5c 647#else
ed44fb7a
ILT		 648{"fdivrp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} },
649{"fdivrp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} },
650{"fdivrp", 0, 0xdef1, X, FP, { 0, 0, 0} },
ce868e5c 651#endif
ed44fb7a
ILT		 652
653{"f2xm1", 0, 0xd9f0, X, FP, { 0, 0, 0} },
654{"fyl2x", 0, 0xd9f1, X, FP, { 0, 0, 0} },
655{"fptan", 0, 0xd9f2, X, FP, { 0, 0, 0} },
656{"fpatan", 0, 0xd9f3, X, FP, { 0, 0, 0} },
657{"fxtract",0, 0xd9f4, X, FP, { 0, 0, 0} },
658{"fprem1", 0, 0xd9f5, X, FP, { 0, 0, 0} },
659{"fdecstp",0, 0xd9f6, X, FP, { 0, 0, 0} },
660{"fincstp",0, 0xd9f7, X, FP, { 0, 0, 0} },
661{"fprem", 0, 0xd9f8, X, FP, { 0, 0, 0} },
662{"fyl2xp1",0, 0xd9f9, X, FP, { 0, 0, 0} },
663{"fsqrt", 0, 0xd9fa, X, FP, { 0, 0, 0} },
664{"fsincos",0, 0xd9fb, X, FP, { 0, 0, 0} },
665{"frndint",0, 0xd9fc, X, FP, { 0, 0, 0} },
666{"fscale", 0, 0xd9fd, X, FP, { 0, 0, 0} },
667{"fsin", 0, 0xd9fe, X, FP, { 0, 0, 0} },
668{"fcos", 0, 0xd9ff, X, FP, { 0, 0, 0} },
669{"fchs", 0, 0xd9e0, X, FP, { 0, 0, 0} },
670{"fabs", 0, 0xd9e1, X, FP, { 0, 0, 0} },
ce868e5c
JG		 671
672/* processor control */
ed44fb7a
ILT		 673{"fninit", 0, 0xdbe3, X, FP, { 0, 0, 0} },
674{"finit", 0, 0xdbe3, X, FP|FWait, { 0, 0, 0} },
675{"fldcw", 1, 0xd9, 5, FP|Modrm, { ShortMem, 0, 0} },
676{"fnstcw", 1, 0xd9, 7, FP|Modrm, { ShortMem, 0, 0} },
677{"fstcw", 1, 0xd9, 7, FP|FWait|Modrm, { ShortMem, 0, 0} },
678{"fnstsw", 1, 0xdfe0, X, FP, { Acc, 0, 0} },
679{"fnstsw", 1, 0xdd, 7, FP|Modrm, { ShortMem, 0, 0} },
680{"fnstsw", 0, 0xdfe0, X, FP, { 0, 0, 0} },
681{"fstsw", 1, 0xdfe0, X, FP|FWait, { Acc, 0, 0} },
682{"fstsw", 1, 0xdd, 7, FP|FWait|Modrm, { ShortMem, 0, 0} },
683{"fstsw", 0, 0xdfe0, X, FP|FWait, { 0, 0, 0} },
684{"fnclex", 0, 0xdbe2, X, FP, { 0, 0, 0} },
685{"fclex", 0, 0xdbe2, X, FP|FWait, { 0, 0, 0} },
ed44fb7a 686/* Short forms of fldenv, fstenv use data size prefix.
038915c9
ILT		 687 FIXME: Are these the right suffixes? */
688{"fnstenv",1, 0xd9, 6, sl_Suf|Modrm, { LLongMem, 0, 0} },
689{"fstenv", 1, 0xd9, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
690{"fldenv", 1, 0xd9, 4, sl_Suf|Modrm, { LLongMem, 0, 0} },
691{"fnsave", 1, 0xdd, 6, sl_Suf|Modrm, { LLongMem, 0, 0} },
692{"fsave", 1, 0xdd, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
693{"frstor", 1, 0xdd, 4, sl_Suf|Modrm, { LLongMem, 0, 0} },
ed44fb7a
ILT		 694
695{"ffree", 1, 0xddc0, X, FP|ShortForm, { FloatReg, 0, 0} },
527cabaf 696/* P6:free st(i), pop st */
ed44fb7a
ILT		 697{"ffreep", 1, 0xdfc0, X, FP|ShortForm, { FloatReg, 0, 0} },
698{"fnop", 0, 0xd9d0, X, FP, { 0, 0, 0} },
ffd42166 699#define FWAIT_OPCODE 0x9b
ed44fb7a 700{"fwait", 0, 0x9b, X, FP, { 0, 0, 0} },
ce868e5c
JG		 701
702/*
703 opcode prefixes; we allow them as seperate insns too
ce868e5c 704*/
038915c9 705#define ADDR_PREFIX_OPCODE 0x67
b8e4d255
ILT		 706{"addr16", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
707{"addr32", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
708{"aword", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
709{"adword", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
038915c9 710#define DATA_PREFIX_OPCODE 0x66
b8e4d255
ILT		 711{"data16", 0, 0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
712{"data32", 0, 0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
713{"word", 0, 0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
714{"dword", 0, 0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
038915c9
ILT		 715#define LOCK_PREFIX_OPCODE 0xf0
716{"lock", 0, 0xf0, X, NoSuf|IsPrefix, { 0, 0, 0} },
717{"wait", 0, 0x9b, X, NoSuf|IsPrefix, { 0, 0, 0} },
718#define CS_PREFIX_OPCODE 0x2e
719{"cs", 0, 0x2e, X, NoSuf|IsPrefix, { 0, 0, 0} },
720#define DS_PREFIX_OPCODE 0x3e
721{"ds", 0, 0x3e, X, NoSuf|IsPrefix, { 0, 0, 0} },
722#define ES_PREFIX_OPCODE 0x26
723{"es", 0, 0x26, X, NoSuf|IsPrefix, { 0, 0, 0} },
724#define FS_PREFIX_OPCODE 0x64
725{"fs", 0, 0x64, X, NoSuf|IsPrefix, { 0, 0, 0} },
726#define GS_PREFIX_OPCODE 0x65
727{"gs", 0, 0x65, X, NoSuf|IsPrefix, { 0, 0, 0} },
728#define SS_PREFIX_OPCODE 0x36
729{"ss", 0, 0x36, X, NoSuf|IsPrefix, { 0, 0, 0} },
730#define REPNE_PREFIX_OPCODE 0xf2
731#define REPE_PREFIX_OPCODE 0xf3
732{"rep", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
733{"repe", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
734{"repz", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} },
735{"repne", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} },
736{"repnz", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} },
fc0d7441
ILT		 737
738/* 486 extensions */
739
ed44fb7a
ILT		 740{"bswap", 1, 0x0fc8, X, NoSuf|ShortForm, { Reg32,0,0 } },
741{"xadd", 2, 0x0fc0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
742{"cmpxchg", 2, 0x0fb0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
743{"invd", 0, 0x0f08, X, NoSuf, { 0, 0, 0} },
744{"wbinvd", 0, 0x0f09, X, NoSuf, { 0, 0, 0} },
745{"invlpg", 1, 0x0f01, 7, NoSuf|Modrm, { AnyMem, 0, 0} },
fc0d7441 746
cd22144a 747/* 586 and late 486 extensions */
ed44fb7a 748{"cpuid", 0, 0x0fa2, X, NoSuf, { 0, 0, 0} },
cd22144a
KR		 749
750/* Pentium extensions */
ed44fb7a
ILT		 751{"wrmsr", 0, 0x0f30, X, NoSuf, { 0, 0, 0} },
752{"rdtsc", 0, 0x0f31, X, NoSuf, { 0, 0, 0} },
753{"rdmsr", 0, 0x0f32, X, NoSuf, { 0, 0, 0} },
754{"cmpxchg8b",1,0x0fc7, 1, NoSuf|Modrm, { LLongMem, 0, 0} },
527cabaf
ILT		 755
756/* Pentium Pro extensions */
ed44fb7a
ILT		 757{"rdpmc", 0, 0x0f33, X, NoSuf, { 0, 0, 0} },
758
759{"ud2", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, /* official undefined instr. */
760
761{"cmovo", 2, 0x0f40, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
762{"cmovno", 2, 0x0f41, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
763{"cmovb", 2, 0x0f42, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
764{"cmovae", 2, 0x0f43, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
765{"cmove", 2, 0x0f44, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
766{"cmovne", 2, 0x0f45, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
767{"cmovbe", 2, 0x0f46, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
768{"cmova", 2, 0x0f47, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
769{"cmovs", 2, 0x0f48, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
770{"cmovns", 2, 0x0f49, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
771{"cmovp", 2, 0x0f4a, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
772{"cmovnp", 2, 0x0f4b, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
773{"cmovl", 2, 0x0f4c, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
774{"cmovge", 2, 0x0f4d, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
775{"cmovle", 2, 0x0f4e, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
776{"cmovg", 2, 0x0f4f, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} },
777
778{"fcmovb", 2, 0xdac0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
779{"fcmove", 2, 0xdac8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
780{"fcmovbe", 2, 0xdad0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
781{"fcmovu", 2, 0xdad8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
782{"fcmovnb", 2, 0xdbc0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
783{"fcmovne", 2, 0xdbc8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
784{"fcmovnbe",2, 0xdbd0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
785{"fcmovnu", 2, 0xdbd8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
786
787{"fcomi", 2, 0xdbf0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
788{"fucomi", 2, 0xdbe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
789{"fcomip", 2, 0xdff0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
790{"fucomip", 2, 0xdfe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
cd22144a 791
3abaf930
ILT		 792/* MMX instructions. */
793
ed44fb7a
ILT		 794{"emms", 0, 0x0f77, X, NoSuf, { 0, 0, 0 } },
795{"movd", 2, 0x0f6e, X, NoSuf|Modrm, { Reg32|LongMem, RegMMX, 0 } },
796{"movd", 2, 0x0f7e, X, NoSuf|Modrm, { RegMMX, Reg32|LongMem, 0 } },
797{"movq", 2, 0x0f6f, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
798{"movq", 2, 0x0f7f, X, NoSuf|Modrm, { RegMMX, RegMMX|LongMem, 0 } },
799{"packssdw", 2, 0x0f6b, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
800{"packsswb", 2, 0x0f63, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
801{"packuswb", 2, 0x0f67, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
802{"paddb", 2, 0x0ffc, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
803{"paddw", 2, 0x0ffd, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
804{"paddd", 2, 0x0ffe, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
805{"paddsb", 2, 0x0fec, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
806{"paddsw", 2, 0x0fed, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
807{"paddusb", 2, 0x0fdc, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
808{"paddusw", 2, 0x0fdd, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
809{"pand", 2, 0x0fdb, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
810{"pandn", 2, 0x0fdf, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
811{"pcmpeqb", 2, 0x0f74, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
812{"pcmpeqw", 2, 0x0f75, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
813{"pcmpeqd", 2, 0x0f76, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
814{"pcmpgtb", 2, 0x0f64, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
815{"pcmpgtw", 2, 0x0f65, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
816{"pcmpgtd", 2, 0x0f66, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
817{"pmaddwd", 2, 0x0ff5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
818{"pmulhw", 2, 0x0fe5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
819{"pmullw", 2, 0x0fd5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
820{"por", 2, 0x0feb, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
821{"psllw", 2, 0x0ff1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
822{"psllw", 2, 0x0f71, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
823{"pslld", 2, 0x0ff2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
824{"pslld", 2, 0x0f72, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
825{"psllq", 2, 0x0ff3, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
826{"psllq", 2, 0x0f73, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
827{"psraw", 2, 0x0fe1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
828{"psraw", 2, 0x0f71, 4, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
829{"psrad", 2, 0x0fe2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
830{"psrad", 2, 0x0f72, 4, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
831{"psrlw", 2, 0x0fd1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
832{"psrlw", 2, 0x0f71, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
833{"psrld", 2, 0x0fd2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
834{"psrld", 2, 0x0f72, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
835{"psrlq", 2, 0x0fd3, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
836{"psrlq", 2, 0x0f73, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } },
837{"psubb", 2, 0x0ff8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
838{"psubw", 2, 0x0ff9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
839{"psubd", 2, 0x0ffa, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
840{"psubsb", 2, 0x0fe8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
841{"psubsw", 2, 0x0fe9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
842{"psubusb", 2, 0x0fd8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
843{"psubusw", 2, 0x0fd9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
844{"punpckhbw",2, 0x0f68, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
845{"punpckhwd",2, 0x0f69, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
846{"punpckhdq",2, 0x0f6a, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
847{"punpcklbw",2, 0x0f60, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
848{"punpcklwd",2, 0x0f61, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
849{"punpckldq",2, 0x0f62, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
850{"pxor", 2, 0x0fef, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
3abaf930 851
038915c9 852{NULL, 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
ce868e5c 853};
77be9a8a 854#undef X
ed44fb7a
ILT		 855#undef ReverseModrm
856#undef NoSuf
857#undef b_Suf
858#undef w_Suf
859#undef l_Suf
860#undef bw_Suf
861#undef bl_Suf
862#undef wl_Suf
038915c9 863#undef sl_Suf
ed44fb7a
ILT		 864#undef bwl_Suf
865#undef FP
866#undef l_FP
867#undef sl_FP
ce868e5c 868
038915c9
ILT		 869#define MAX_OPCODE_SIZE 16 /* for parsing opcodes from input */
870
ce868e5c
JG		 871
872/* 386 register table */
873
874static const reg_entry i386_regtab[] = {
875 /* 8 bit regs */
77be9a8a
ILT		 876 {"al", Reg8|Acc, 0},
877 {"cl", Reg8|ShiftCount, 1},
878 {"dl", Reg8, 2},
ce868e5c 879 {"bl", Reg8, 3},
77be9a8a
ILT		 880 {"ah", Reg8, 4},
881 {"ch", Reg8, 5},
882 {"dh", Reg8, 6},
883 {"bh", Reg8, 7},
ce868e5c 884 /* 16 bit regs */
77be9a8a
ILT		 885 {"ax", Reg16|Acc, 0},
886 {"cx", Reg16, 1},
887 {"dx", Reg16|InOutPortReg, 2},
038915c9 888 {"bx", Reg16|BaseIndex, 3},
77be9a8a 889 {"sp", Reg16, 4},
038915c9
ILT		 890 {"bp", Reg16|BaseIndex, 5},
891 {"si", Reg16|BaseIndex, 6},
892 {"di", Reg16|BaseIndex, 7},
ce868e5c 893 /* 32 bit regs */
77be9a8a
ILT		 894 {"eax", Reg32|BaseIndex|Acc, 0},
895 {"ecx", Reg32|BaseIndex, 1},
896 {"edx", Reg32|BaseIndex, 2},
897 {"ebx", Reg32|BaseIndex, 3},
ed44fb7a 898 {"esp", Reg32, 4},
77be9a8a
ILT		 899 {"ebp", Reg32|BaseIndex, 5},
900 {"esi", Reg32|BaseIndex, 6},
901 {"edi", Reg32|BaseIndex, 7},
ce868e5c 902 /* segment registers */
77be9a8a
ILT		 903 {"es", SReg2, 0},
904 {"cs", SReg2, 1},
905 {"ss", SReg2, 2},
906 {"ds", SReg2, 3},
907 {"fs", SReg3, 4},
908 {"gs", SReg3, 5},
ce868e5c 909 /* control registers */
77be9a8a
ILT		 910 {"cr0", Control, 0},
911 {"cr2", Control, 2},
912 {"cr3", Control, 3},
cd22144a 913 {"cr4", Control, 4},
ce868e5c 914 /* debug registers */
77be9a8a
ILT		 915 {"db0", Debug, 0},
916 {"db1", Debug, 1},
917 {"db2", Debug, 2},
918 {"db3", Debug, 3},
919 {"db6", Debug, 6},
920 {"db7", Debug, 7},
921 {"dr0", Debug, 0},
922 {"dr1", Debug, 1},
923 {"dr2", Debug, 2},
924 {"dr3", Debug, 3},
925 {"dr6", Debug, 6},
926 {"dr7", Debug, 7},
ce868e5c 927 /* test registers */
77be9a8a
ILT		 928 {"tr3", Test, 3},
929 {"tr4", Test, 4},
930 {"tr5", Test, 5},
931 {"tr6", Test, 6},
932 {"tr7", Test, 7},
ce868e5c
JG		 933 /* float registers */
934 {"st(0)", FloatReg|FloatAcc, 0},
935 {"st", FloatReg|FloatAcc, 0},
77be9a8a
ILT		 936 {"st(1)", FloatReg, 1},
937 {"st(2)", FloatReg, 2},
938 {"st(3)", FloatReg, 3},
939 {"st(4)", FloatReg, 4},
940 {"st(5)", FloatReg, 5},
941 {"st(6)", FloatReg, 6},
942 {"st(7)", FloatReg, 7},
943 {"mm0", RegMMX, 0},
944 {"mm1", RegMMX, 1},
945 {"mm2", RegMMX, 2},
946 {"mm3", RegMMX, 3},
947 {"mm4", RegMMX, 4},
948 {"mm5", RegMMX, 5},
949 {"mm6", RegMMX, 6},
950 {"mm7", RegMMX, 7}
ce868e5c
JG		 951};
952
953#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
954
ce868e5c
JG		 955/* segment stuff */
956static const seg_entry cs = { "cs", 0x2e };
957static const seg_entry ds = { "ds", 0x3e };
958static const seg_entry ss = { "ss", 0x36 };
959static const seg_entry es = { "es", 0x26 };
960static const seg_entry fs = { "fs", 0x64 };
961static const seg_entry gs = { "gs", 0x65 };
ce868e5c 962
ce868e5c 963/* end of i386-opcode.h */
GDB Binutils - Deliverables
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