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Wed Jun 3 18:28:45 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
[deliverable/binutils-gdb.git] / include / opcode / i386.h
CommitLineData
ce868e5c 1/* i386-opcode.h -- Intel 80386 opcode table
d411c9ef 2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation.
ce868e5c
JG		 3
4This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
5
6This program is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2 of the License, or
9(at your option) any later version.
10
11This program is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with this program; if not, write to the Free Software
cd22144a 18Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
ce868e5c 19
c0d7b534
ILT		 20/* The NON_BROKEN_OPCODES cases use the operands in the reverse order
21 from that documented in the Intel manuals. The opcode values are
22 such that they actually generate different instructions. These
654b0845
ILT		 23 values must not be changed, as they are the values generated by the
24 UnixWare assembler, and possibly other ix86 assemblers. */
c0d7b534 25
ce868e5c
JG		 26static const template i386_optab[] = {
27
77be9a8a 28#define X None
ffabaa53 29
ce868e5c 30/* move instructions */
a43022bd 31#define MOV_AX_DISP32 0xa0
77be9a8a
ILT		 32{ "mov", 2, 0xa0, X, DW, { Disp32, Acc, 0 } },
33{ "mov", 2, 0x88, X, DW|Modrm, { Reg, Reg|Mem, 0 } },
34{ "mov", 2, 0xb0, X, ShortFormW, { Imm, Reg, 0 } },
35{ "mov", 2, 0xc6, X, W|Modrm, { Imm, Reg|Mem, 0 } },
eff2a090
ILT		 36/* The next instruction accepts WordReg so that `movl %gs,%esi' can be
37 used to move a segment register to a 32 bit register without using
ffabaa53
ILT		 38 a size prefix. This will set the upper 16 bits of the 32 bit
39 register to an implementation defined value (on the Pentium Pro,
40 the implementation defined value is zero). */
77be9a8a 41{ "mov", 2, 0x8c, X, D|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } },
ce868e5c 42/* move to/from control debug registers */
77be9a8a
ILT		 43{ "mov", 2, 0x0f20, X, D|Modrm, { Control, Reg32, 0} },
44{ "mov", 2, 0x0f21, X, D|Modrm, { Debug, Reg32, 0} },
45{ "mov", 2, 0x0f24, X, D|Modrm, { Test, Reg32, 0} },
ce868e5c
JG		 46
47/* move with sign extend */
48/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
49 conflict with the "movs" string move instruction. Thus,
77be9a8a 50 {"movsb", 2, 0x0fbe, X, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
ce868e5c 51 is not kosher; we must seperate the two instructions. */
77be9a8a
ILT		 52{"movsbl", 2, 0x0fbe, X, ReverseRegRegmem|Modrm|Data32, { Reg8|Mem, Reg32, 0} },
53{"movsbw", 2, 0x0fbe, X, ReverseRegRegmem|Modrm|Data16, { Reg8|Mem, Reg16, 0} },
54{"movswl", 2, 0x0fbf, X, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
ce868e5c
JG		 55
56/* move with zero extend */
77be9a8a
ILT		 57{"movzb", 2, 0x0fb6, X, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
58{"movzwl", 2, 0x0fb7, X, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
ce868e5c
JG		 59
60/* push instructions */
77be9a8a 61{"push", 1, 0x50, X, ShortForm, { WordReg,0,0 } },
fc0d7441 62{"push", 1, 0xff, 0x6, Modrm, { WordReg|WordMem, 0, 0 } },
77be9a8a
ILT		 63{"push", 1, 0x6a, X, 0, { Imm8S, 0, 0} },
64{"push", 1, 0x68, X, 0, { Imm16|Imm32, 0, 0} },
65{"push", 1, 0x06, X, Seg2ShortForm, { SReg2,0,0 } },
66{"push", 1, 0x0fa0, X, Seg3ShortForm, { SReg3,0,0 } },
ce868e5c 67/* push all */
77be9a8a 68{"pusha", 0, 0x60, X, 0, { 0, 0, 0 } },
ce868e5c
JG		 69
70/* pop instructions */
77be9a8a 71{"pop", 1, 0x58, X, ShortForm, { WordReg,0,0 } },
fc0d7441 72{"pop", 1, 0x8f, 0x0, Modrm, { WordReg|WordMem, 0, 0 } },
ce868e5c 73#define POP_SEG_SHORT 0x7
77be9a8a
ILT		 74{"pop", 1, 0x07, X, Seg2ShortForm, { SReg2,0,0 } },
75{"pop", 1, 0x0fa1, X, Seg3ShortForm, { SReg3,0,0 } },
ce868e5c 76/* pop all */
77be9a8a 77{"popa", 0, 0x61, X, 0, { 0, 0, 0 } },
ce868e5c
JG		 78
79/* xchg exchange instructions
80 xchg commutes: we allow both operand orders */
77be9a8a
ILT		 81{"xchg", 2, 0x90, X, ShortForm, { WordReg, Acc, 0 } },
82{"xchg", 2, 0x90, X, ShortForm, { Acc, WordReg, 0 } },
83{"xchg", 2, 0x86, X, W|Modrm, { Reg, Reg|Mem, 0 } },
84{"xchg", 2, 0x86, X, W|Modrm, { Reg|Mem, Reg, 0 } },
ce868e5c
JG		 85
86/* in/out from ports */
77be9a8a
ILT		 87{"in", 2, 0xe4, X, W, { Imm8, Acc, 0 } },
88{"in", 2, 0xec, X, W, { InOutPortReg, Acc, 0 } },
89{"in", 1, 0xe4, X, W, { Imm8, 0, 0 } },
90{"in", 1, 0xec, X, W, { InOutPortReg, 0, 0 } },
91{"out", 2, 0xe6, X, W, { Acc, Imm8, 0 } },
92{"out", 2, 0xee, X, W, { Acc, InOutPortReg, 0 } },
93{"out", 1, 0xe6, X, W, { Imm8, 0, 0 } },
94{"out", 1, 0xee, X, W, { InOutPortReg, 0, 0 } },
fc0d7441 95
ce868e5c 96/* load effective address */
77be9a8a 97{"lea", 2, 0x8d, X, Modrm, { WordMem, WordReg, 0 } },
ce868e5c
JG		 98
99/* load segment registers from memory */
77be9a8a
ILT		 100{"lds", 2, 0xc5, X, Modrm, { Mem, Reg32, 0} },
101{"les", 2, 0xc4, X, Modrm, { Mem, Reg32, 0} },
102{"lfs", 2, 0x0fb4, X, Modrm, { Mem, Reg32, 0} },
103{"lgs", 2, 0x0fb5, X, Modrm, { Mem, Reg32, 0} },
104{"lss", 2, 0x0fb2, X, Modrm, { Mem, Reg32, 0} },
ce868e5c
JG		 105
106/* flags register instructions */
77be9a8a
ILT		 107{"clc", 0, 0xf8, X, 0, { 0, 0, 0} },
108{"cld", 0, 0xfc, X, 0, { 0, 0, 0} },
109{"cli", 0, 0xfa, X, 0, { 0, 0, 0} },
110{"clts", 0, 0x0f06, X, 0, { 0, 0, 0} },
111{"cmc", 0, 0xf5, X, 0, { 0, 0, 0} },
112{"lahf", 0, 0x9f, X, 0, { 0, 0, 0} },
113{"sahf", 0, 0x9e, X, 0, { 0, 0, 0} },
114{"pushfl", 0, 0x9c, X, Data32, { 0, 0, 0} },
115{"popfl", 0, 0x9d, X, Data32, { 0, 0, 0} },
116{"pushfw", 0, 0x9c, X, Data16, { 0, 0, 0} },
117{"popfw", 0, 0x9d, X, Data16, { 0, 0, 0} },
118{"pushf", 0, 0x9c, X, 0, { 0, 0, 0} },
119{"popf", 0, 0x9d, X, 0, { 0, 0, 0} },
120{"stc", 0, 0xf9, X, 0, { 0, 0, 0} },
121{"std", 0, 0xfd, X, 0, { 0, 0, 0} },
122{"sti", 0, 0xfb, X, 0, { 0, 0, 0} },
123
124{"add", 2, 0x0, X, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 125{"add", 2, 0x83, 0, Modrm, { Imm8S, WordReg|WordMem, 0} },
77be9a8a 126{"add", 2, 0x4, X, W, { Imm, Acc, 0} },
fc0d7441
ILT		 127{"add", 2, 0x80, 0, W|Modrm, { Imm, Reg|Mem, 0} },
128
77be9a8a 129{"inc", 1, 0x40, X, ShortForm, { WordReg, 0, 0} },
fc0d7441
ILT		 130{"inc", 1, 0xfe, 0, W|Modrm, { Reg|Mem, 0, 0} },
131
77be9a8a 132{"sub", 2, 0x28, X, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 133{"sub", 2, 0x83, 5, Modrm, { Imm8S, WordReg|WordMem, 0} },
77be9a8a 134{"sub", 2, 0x2c, X, W, { Imm, Acc, 0} },
fc0d7441
ILT		 135{"sub", 2, 0x80, 5, W|Modrm, { Imm, Reg|Mem, 0} },
136
77be9a8a 137{"dec", 1, 0x48, X, ShortForm, { WordReg, 0, 0} },
fc0d7441
ILT		 138{"dec", 1, 0xfe, 1, W|Modrm, { Reg|Mem, 0, 0} },
139
77be9a8a 140{"sbb", 2, 0x18, X, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 141{"sbb", 2, 0x83, 3, Modrm, { Imm8S, WordReg|WordMem, 0} },
77be9a8a 142{"sbb", 2, 0x1c, X, W, { Imm, Acc, 0} },
fc0d7441
ILT		 143{"sbb", 2, 0x80, 3, W|Modrm, { Imm, Reg|Mem, 0} },
144
77be9a8a 145{"cmp", 2, 0x38, X, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 146{"cmp", 2, 0x83, 7, Modrm, { Imm8S, WordReg|WordMem, 0} },
77be9a8a 147{"cmp", 2, 0x3c, X, W, { Imm, Acc, 0} },
fc0d7441
ILT		 148{"cmp", 2, 0x80, 7, W|Modrm, { Imm, Reg|Mem, 0} },
149
77be9a8a
ILT		 150{"test", 2, 0x84, X, W|Modrm, { Reg|Mem, Reg, 0} },
151{"test", 2, 0x84, X, W|Modrm, { Reg, Reg|Mem, 0} },
152{"test", 2, 0xa8, X, W, { Imm, Acc, 0} },
fc0d7441
ILT		 153{"test", 2, 0xf6, 0, W|Modrm, { Imm, Reg|Mem, 0} },
154
77be9a8a 155{"and", 2, 0x20, X, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 156{"and", 2, 0x83, 4, Modrm, { Imm8S, WordReg|WordMem, 0} },
77be9a8a 157{"and", 2, 0x24, X, W, { Imm, Acc, 0} },
fc0d7441
ILT		 158{"and", 2, 0x80, 4, W|Modrm, { Imm, Reg|Mem, 0} },
159
77be9a8a 160{"or", 2, 0x08, X, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 161{"or", 2, 0x83, 1, Modrm, { Imm8S, WordReg|WordMem, 0} },
77be9a8a 162{"or", 2, 0x0c, X, W, { Imm, Acc, 0} },
fc0d7441
ILT		 163{"or", 2, 0x80, 1, W|Modrm, { Imm, Reg|Mem, 0} },
164
77be9a8a 165{"xor", 2, 0x30, X, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 166{"xor", 2, 0x83, 6, Modrm, { Imm8S, WordReg|WordMem, 0} },
77be9a8a 167{"xor", 2, 0x34, X, W, { Imm, Acc, 0} },
fc0d7441
ILT		 168{"xor", 2, 0x80, 6, W|Modrm, { Imm, Reg|Mem, 0} },
169
c00435ed 170/* iclr with 1 operand is really xor with 2 operands. */
77be9a8a 171{"clr", 1, 0x30, X, W|Modrm|regKludge, { Reg } },
c00435ed 172
77be9a8a 173{"adc", 2, 0x10, X, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 174{"adc", 2, 0x83, 2, Modrm, { Imm8S, WordReg|WordMem, 0} },
77be9a8a 175{"adc", 2, 0x14, X, W, { Imm, Acc, 0} },
fc0d7441
ILT		 176{"adc", 2, 0x80, 2, W|Modrm, { Imm, Reg|Mem, 0} },
177
178{"neg", 1, 0xf6, 3, W|Modrm, { Reg|Mem, 0, 0} },
179{"not", 1, 0xf6, 2, W|Modrm, { Reg|Mem, 0, 0} },
180
77be9a8a
ILT		 181{"aaa", 0, 0x37, X, 0, { 0, 0, 0} },
182{"aas", 0, 0x3f, X, 0, { 0, 0, 0} },
183{"daa", 0, 0x27, X, 0, { 0, 0, 0} },
184{"das", 0, 0x2f, X, 0, { 0, 0, 0} },
185{"aad", 0, 0xd50a, X, 0, { 0, 0, 0} },
186{"aam", 0, 0xd40a, X, 0, { 0, 0, 0} },
ce868e5c
JG		 187
188/* conversion insns */
189/* conversion: intel naming */
77be9a8a
ILT		 190{"cbw", 0, 0x98, X, Data16, { 0, 0, 0} },
191{"cwd", 0, 0x99, X, Data16, { 0, 0, 0} },
192{"cwde", 0, 0x98, X, Data32, { 0, 0, 0} },
193{"cdq", 0, 0x99, X, Data32, { 0, 0, 0} },
ce868e5c 194/* att naming */
77be9a8a
ILT		 195{"cbtw", 0, 0x98, X, Data16, { 0, 0, 0} },
196{"cwtl", 0, 0x98, X, Data32, { 0, 0, 0} },
197{"cwtd", 0, 0x99, X, Data16, { 0, 0, 0} },
198{"cltd", 0, 0x99, X, Data32, { 0, 0, 0} },
ce868e5c
JG		 199
200/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
201 expanding 64-bit multiplies, and *cannot* be selected to accomplish
202 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
77be9a8a 203 These multiplies can only be selected with single operand forms. */
fc0d7441
ILT		 204{"mul", 1, 0xf6, 4, W|Modrm, { Reg|Mem, 0, 0} },
205{"imul", 1, 0xf6, 5, W|Modrm, { Reg|Mem, 0, 0} },
77be9a8a
ILT		 206{"imul", 2, 0x0faf, X, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
207{"imul", 3, 0x6b, X, Modrm|ReverseRegRegmem, { Imm8S, WordReg|Mem, WordReg} },
208{"imul", 3, 0x69, X, Modrm|ReverseRegRegmem, { Imm16|Imm32, WordReg|Mem, WordReg} },
209/* imul with 2 operands mimics imul with 3 by putting the register in
210 both i.rm.reg & i.rm.regmem fields. regKludge enables this
211 transformation. */
212{"imul", 2, 0x6b, X, Modrm|regKludge, { Imm8S, WordReg, 0} },
213{"imul", 2, 0x69, X, Modrm|regKludge, { Imm16|Imm32, WordReg, 0} },
ce868e5c 214
fc0d7441
ILT		 215{"div", 1, 0xf6, 6, W|Modrm, { Reg|Mem, 0, 0} },
216{"div", 2, 0xf6, 6, W|Modrm, { Reg|Mem, Acc, 0} },
217{"idiv", 1, 0xf6, 7, W|Modrm, { Reg|Mem, 0, 0} },
218{"idiv", 2, 0xf6, 7, W|Modrm, { Reg|Mem, Acc, 0} },
219
220{"rol", 2, 0xd0, 0, W|Modrm, { Imm1, Reg|Mem, 0} },
221{"rol", 2, 0xc0, 0, W|Modrm, { Imm8, Reg|Mem, 0} },
222{"rol", 2, 0xd2, 0, W|Modrm, { ShiftCount, Reg|Mem, 0} },
223{"rol", 1, 0xd0, 0, W|Modrm, { Reg|Mem, 0, 0} },
224
225{"ror", 2, 0xd0, 1, W|Modrm, { Imm1, Reg|Mem, 0} },
226{"ror", 2, 0xc0, 1, W|Modrm, { Imm8, Reg|Mem, 0} },
227{"ror", 2, 0xd2, 1, W|Modrm, { ShiftCount, Reg|Mem, 0} },
228{"ror", 1, 0xd0, 1, W|Modrm, { Reg|Mem, 0, 0} },
229
230{"rcl", 2, 0xd0, 2, W|Modrm, { Imm1, Reg|Mem, 0} },
231{"rcl", 2, 0xc0, 2, W|Modrm, { Imm8, Reg|Mem, 0} },
232{"rcl", 2, 0xd2, 2, W|Modrm, { ShiftCount, Reg|Mem, 0} },
233{"rcl", 1, 0xd0, 2, W|Modrm, { Reg|Mem, 0, 0} },
234
235{"rcr", 2, 0xd0, 3, W|Modrm, { Imm1, Reg|Mem, 0} },
236{"rcr", 2, 0xc0, 3, W|Modrm, { Imm8, Reg|Mem, 0} },
237{"rcr", 2, 0xd2, 3, W|Modrm, { ShiftCount, Reg|Mem, 0} },
238{"rcr", 1, 0xd0, 3, W|Modrm, { Reg|Mem, 0, 0} },
239
240{"sal", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
241{"sal", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
242{"sal", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
243{"sal", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
244{"shl", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
245{"shl", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
246{"shl", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
247{"shl", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
248
77be9a8a
ILT		 249{"shld", 3, 0x0fa4, X, Modrm, { Imm8, WordReg, WordReg|Mem} },
250{"shld", 3, 0x0fa5, X, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
251{"shld", 2, 0x0fa5, X, Modrm, { WordReg, WordReg|Mem, 0} },
fc0d7441
ILT		 252
253{"shr", 2, 0xd0, 5, W|Modrm, { Imm1, Reg|Mem, 0} },
254{"shr", 2, 0xc0, 5, W|Modrm, { Imm8, Reg|Mem, 0} },
255{"shr", 2, 0xd2, 5, W|Modrm, { ShiftCount, Reg|Mem, 0} },
256{"shr", 1, 0xd0, 5, W|Modrm, { Reg|Mem, 0, 0} },
257
77be9a8a
ILT		 258{"shrd", 3, 0x0fac, X, Modrm, { Imm8, WordReg, WordReg|Mem} },
259{"shrd", 3, 0x0fad, X, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
260{"shrd", 2, 0x0fad, X, Modrm, { WordReg, WordReg|Mem, 0} },
fc0d7441
ILT		 261
262{"sar", 2, 0xd0, 7, W|Modrm, { Imm1, Reg|Mem, 0} },
263{"sar", 2, 0xc0, 7, W|Modrm, { Imm8, Reg|Mem, 0} },
264{"sar", 2, 0xd2, 7, W|Modrm, { ShiftCount, Reg|Mem, 0} },
265{"sar", 1, 0xd0, 7, W|Modrm, { Reg|Mem, 0, 0} },
ce868e5c
JG		 266
267/* control transfer instructions */
268#define CALL_PC_RELATIVE 0xe8
77be9a8a 269{"call", 1, 0xe8, X, JumpDword, { Disp32, 0, 0} },
a43022bd
KR		 270{"call", 1, 0xff, 2, Modrm|Data32, { Reg|Mem|JumpAbsolute, 0, 0} },
271{"callw", 1, 0xff, 2, Modrm|Data16, { Reg|Mem|JumpAbsolute, 0, 0} },
ce868e5c 272#define CALL_FAR_IMMEDIATE 0x9a
77be9a8a 273{"lcall", 2, 0x9a, X, JumpInterSegment, { Imm16, Imm32, 0} },
a43022bd
KR		 274{"lcall", 1, 0xff, 3, Modrm|Data32, { Mem, 0, 0} },
275{"lcallw", 1, 0xff, 3, Modrm|Data16, { Mem, 0, 0} },
ce868e5c
JG		 276
277#define JUMP_PC_RELATIVE 0xeb
77be9a8a 278{"jmp", 1, 0xeb, X, Jump, { Disp, 0, 0} },
fc0d7441 279{"jmp", 1, 0xff, 4, Modrm, { Reg32|Mem|JumpAbsolute, 0, 0} },
ce868e5c 280#define JUMP_FAR_IMMEDIATE 0xea
77be9a8a 281{"ljmp", 2, 0xea, X, JumpInterSegment, { Imm16, Imm32, 0} },
a43022bd
KR		 282{"ljmp", 1, 0xff, 5, Modrm|Data32, { Mem, 0, 0} },
283
77be9a8a
ILT		 284{"ret", 0, 0xc3, X, Data32, { 0, 0, 0} },
285{"ret", 1, 0xc2, X, Data32, { Imm16, 0, 0} },
286{"retw", 0, 0xc3, X, Data16, { 0, 0, 0} },
287{"retw", 1, 0xc2, X, Data16, { Imm16, 0, 0} },
288{"lret", 0, 0xcb, X, Data32, { 0, 0, 0} },
289{"lret", 1, 0xca, X, Data32, { Imm16, 0, 0} },
290{"lretw", 0, 0xcb, X, Data16, { 0, 0, 0} },
291{"lretw", 1, 0xca, X, Data16, { Imm16, 0, 0} },
292{"enter", 2, 0xc8, X, Data32, { Imm16, Imm8, 0} },
293{"leave", 0, 0xc9, X, Data32, { 0, 0, 0} },
294{"enterw", 2, 0xc8, X, Data16, { Imm16, Imm8, 0} },
295{"leavew", 0, 0xc9, X, Data16, { 0, 0, 0} },
ce868e5c
JG		 296
297/* conditional jumps */
77be9a8a 298{"jo", 1, 0x70, X, Jump, { Disp, 0, 0} },
ce868e5c 299
77be9a8a 300{"jno", 1, 0x71, X, Jump, { Disp, 0, 0} },
ce868e5c 301
77be9a8a
ILT		 302{"jb", 1, 0x72, X, Jump, { Disp, 0, 0} },
303{"jc", 1, 0x72, X, Jump, { Disp, 0, 0} },
304{"jnae", 1, 0x72, X, Jump, { Disp, 0, 0} },
ce868e5c 305
77be9a8a
ILT		 306{"jnb", 1, 0x73, X, Jump, { Disp, 0, 0} },
307{"jnc", 1, 0x73, X, Jump, { Disp, 0, 0} },
308{"jae", 1, 0x73, X, Jump, { Disp, 0, 0} },
ce868e5c 309
77be9a8a
ILT		 310{"je", 1, 0x74, X, Jump, { Disp, 0, 0} },
311{"jz", 1, 0x74, X, Jump, { Disp, 0, 0} },
ce868e5c 312
77be9a8a
ILT		 313{"jne", 1, 0x75, X, Jump, { Disp, 0, 0} },
314{"jnz", 1, 0x75, X, Jump, { Disp, 0, 0} },
ce868e5c 315
77be9a8a
ILT		 316{"jbe", 1, 0x76, X, Jump, { Disp, 0, 0} },
317{"jna", 1, 0x76, X, Jump, { Disp, 0, 0} },
ce868e5c 318
77be9a8a
ILT		 319{"jnbe", 1, 0x77, X, Jump, { Disp, 0, 0} },
320{"ja", 1, 0x77, X, Jump, { Disp, 0, 0} },
ce868e5c 321
77be9a8a 322{"js", 1, 0x78, X, Jump, { Disp, 0, 0} },
ce868e5c 323
77be9a8a 324{"jns", 1, 0x79, X, Jump, { Disp, 0, 0} },
ce868e5c 325
77be9a8a
ILT		 326{"jp", 1, 0x7a, X, Jump, { Disp, 0, 0} },
327{"jpe", 1, 0x7a, X, Jump, { Disp, 0, 0} },
ce868e5c 328
77be9a8a
ILT		 329{"jnp", 1, 0x7b, X, Jump, { Disp, 0, 0} },
330{"jpo", 1, 0x7b, X, Jump, { Disp, 0, 0} },
ce868e5c 331
77be9a8a
ILT		 332{"jl", 1, 0x7c, X, Jump, { Disp, 0, 0} },
333{"jnge", 1, 0x7c, X, Jump, { Disp, 0, 0} },
ce868e5c 334
77be9a8a
ILT		 335{"jnl", 1, 0x7d, X, Jump, { Disp, 0, 0} },
336{"jge", 1, 0x7d, X, Jump, { Disp, 0, 0} },
ce868e5c 337
77be9a8a
ILT		 338{"jle", 1, 0x7e, X, Jump, { Disp, 0, 0} },
339{"jng", 1, 0x7e, X, Jump, { Disp, 0, 0} },
ce868e5c 340
77be9a8a
ILT		 341{"jnle", 1, 0x7f, X, Jump, { Disp, 0, 0} },
342{"jg", 1, 0x7f, X, Jump, { Disp, 0, 0} },
ce868e5c 343
ce868e5c 344#define IS_JUMP_ON_CX_ZERO(o) \
ce868e5c
JG		 345 (o == 0xe3)
346
c2367582 347/* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
77be9a8a
ILT		 348{"jcxz", 1, 0xe3, X, JumpByte|Data16, { Disp, 0, 0} },
349{"jecxz", 1, 0xe3, X, JumpByte|Data32, { Disp, 0, 0} },
ce868e5c
JG		 350
351#define IS_LOOP_ECX_TIMES(o) \
352 (o == 0xe2 || o == 0xe1 || o == 0xe0)
353
77be9a8a 354{"loop", 1, 0xe2, X, JumpByte, { Disp, 0, 0} },
ce868e5c 355
77be9a8a
ILT		 356{"loopz", 1, 0xe1, X, JumpByte, { Disp, 0, 0} },
357{"loope", 1, 0xe1, X, JumpByte, { Disp, 0, 0} },
ce868e5c 358
77be9a8a
ILT		 359{"loopnz", 1, 0xe0, X, JumpByte, { Disp, 0, 0} },
360{"loopne", 1, 0xe0, X, JumpByte, { Disp, 0, 0} },
ce868e5c
JG		 361
362/* set byte on flag instructions */
fc0d7441 363{"seto", 1, 0x0f90, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 364
fc0d7441 365{"setno", 1, 0x0f91, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 366
fc0d7441
ILT		 367{"setb", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
368{"setc", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
369{"setnae", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 370
fc0d7441
ILT		 371{"setnb", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
372{"setnc", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
373{"setae", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 374
fc0d7441
ILT		 375{"sete", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
376{"setz", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 377
fc0d7441
ILT		 378{"setne", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
379{"setnz", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 380
fc0d7441
ILT		 381{"setbe", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
382{"setna", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 383
fc0d7441
ILT		 384{"setnbe", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
385{"seta", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 386
fc0d7441 387{"sets", 1, 0x0f98, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 388
fc0d7441 389{"setns", 1, 0x0f99, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 390
fc0d7441
ILT		 391{"setp", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
392{"setpe", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 393
fc0d7441
ILT		 394{"setnp", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
395{"setpo", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 396
fc0d7441
ILT		 397{"setl", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
398{"setnge", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 399
fc0d7441
ILT		 400{"setnl", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
401{"setge", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 402
fc0d7441
ILT		 403{"setle", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
404{"setng", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 405
fc0d7441
ILT		 406{"setnle", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
407{"setg", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 408
ce868e5c 409/* string manipulation */
77be9a8a
ILT		 410{"cmps", 0, 0xa6, X, W|IsString, { 0, 0, 0} },
411{"cmps", 2, 0xa6, X, W|IsString, { Mem|EsSeg, Mem, 0} },
412{"scmp", 0, 0xa6, X, W|IsString, { 0, 0, 0} },
413{"scmp", 2, 0xa6, X, W|IsString, { Mem|EsSeg, Mem, 0} },
414{"ins", 0, 0x6c, X, W|IsString, { 0, 0, 0} },
415{"ins", 2, 0x6c, X, W|IsString, { InOutPortReg, Mem|EsSeg, 0} },
416{"outs", 0, 0x6e, X, W|IsString, { 0, 0, 0} },
417{"outs", 2, 0x6e, X, W|IsString, { Mem, InOutPortReg, 0} },
418{"lods", 0, 0xac, X, W|IsString, { 0, 0, 0} },
419{"lods", 1, 0xac, X, W|IsString, { Mem, 0, 0} },
420{"lods", 2, 0xac, X, W|IsString, { Mem, Acc, 0} },
421{"slod", 0, 0xac, X, W|IsString, { 0, 0, 0} },
422{"slod", 1, 0xac, X, W|IsString, { Mem, 0, 0} },
423{"slod", 2, 0xac, X, W|IsString, { Mem, Acc, 0} },
424{"movs", 0, 0xa4, X, W|IsString, { 0, 0, 0} },
425{"movs", 2, 0xa4, X, W|IsString, { Mem, Mem|EsSeg, 0} },
426{"smov", 0, 0xa4, X, W|IsString, { 0, 0, 0} },
427{"smov", 2, 0xa4, X, W|IsString, { Mem, Mem|EsSeg, 0} },
428{"scas", 0, 0xae, X, W|IsString, { 0, 0, 0} },
429{"scas", 1, 0xae, X, W|IsString, { Mem|EsSeg, 0, 0} },
430{"scas", 2, 0xae, X, W|IsString, { Mem|EsSeg, Acc, 0} },
431{"ssca", 0, 0xae, X, W|IsString, { 0, 0, 0} },
432{"ssca", 1, 0xae, X, W|IsString, { Mem|EsSeg, 0, 0} },
433{"ssca", 2, 0xae, X, W|IsString, { Mem|EsSeg, Acc, 0} },
434{"stos", 0, 0xaa, X, W|IsString, { 0, 0, 0} },
435{"stos", 1, 0xaa, X, W|IsString, { Mem|EsSeg, 0, 0} },
436{"stos", 2, 0xaa, X, W|IsString, { Acc, Mem|EsSeg, 0} },
437{"ssto", 0, 0xaa, X, W|IsString, { 0, 0, 0} },
438{"ssto", 1, 0xaa, X, W|IsString, { Mem|EsSeg, 0, 0} },
439{"ssto", 2, 0xaa, X, W|IsString, { Acc, Mem|EsSeg, 0} },
440{"xlat", 0, 0xd7, X, IsString, { 0, 0, 0} },
441{"xlat", 1, 0xd7, X, IsString, { Mem, 0, 0} },
ce868e5c
JG		 442
443/* bit manipulation */
77be9a8a
ILT		 444{"bsf", 2, 0x0fbc, X, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
445{"bsr", 2, 0x0fbd, X, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
446{"bt", 2, 0x0fa3, X, Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 447{"bt", 2, 0x0fba, 4, Modrm, { Imm8, Reg|Mem, 0} },
77be9a8a 448{"btc", 2, 0x0fbb, X, Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 449{"btc", 2, 0x0fba, 7, Modrm, { Imm8, Reg|Mem, 0} },
77be9a8a 450{"btr", 2, 0x0fb3, X, Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 451{"btr", 2, 0x0fba, 6, Modrm, { Imm8, Reg|Mem, 0} },
77be9a8a 452{"bts", 2, 0x0fab, X, Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 453{"bts", 2, 0x0fba, 5, Modrm, { Imm8, Reg|Mem, 0} },
ce868e5c
JG		 454
455/* interrupts & op. sys insns */
a43022bd
KR		 456/* See gas/config/tc-i386.c for conversion of 'int $3' into the special
457 int 3 insn. */
ce868e5c
JG		 458#define INT_OPCODE 0xcd
459#define INT3_OPCODE 0xcc
77be9a8a
ILT		 460{"int", 1, 0xcd, X, 0, { Imm8, 0, 0} },
461{"int3", 0, 0xcc, X, 0, { 0, 0, 0} },
462{"into", 0, 0xce, X, 0, { 0, 0, 0} },
463{"iret", 0, 0xcf, X, Data32, { 0, 0, 0} },
464{"iretw", 0, 0xcf, X, Data16, { 0, 0, 0} },
cd22144a 465/* i386sl, i486sl, later 486, and Pentium */
77be9a8a 466{"rsm", 0, 0x0faa, X, 0,{ 0, 0, 0} },
ce868e5c 467
77be9a8a
ILT		 468{"boundl", 2, 0x62, X, Modrm|Data32, { Reg32, Mem, 0} },
469{"boundw", 2, 0x62, X, Modrm|Data16, { Reg16, Mem, 0} },
ce868e5c 470
77be9a8a
ILT		 471{"hlt", 0, 0xf4, X, 0, { 0, 0, 0} },
472{"wait", 0, 0x9b, X, 0, { 0, 0, 0} },
ce868e5c 473/* nop is actually 'xchgl %eax, %eax' */
77be9a8a 474{"nop", 0, 0x90, X, 0, { 0, 0, 0} },
ce868e5c
JG		 475
476/* protection control */
77be9a8a
ILT		 477{"arpl", 2, 0x63, X, Modrm, { Reg16, Reg16|Mem, 0} },
478{"lar", 2, 0x0f02, X, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
ffd42166
ILT		 479{"lgdt", 1, 0x0f01, 2, Modrm, { Mem, 0, 0} },
480{"lidt", 1, 0x0f01, 3, Modrm, { Mem, 0, 0} },
fc0d7441
ILT		 481{"lldt", 1, 0x0f00, 2, Modrm, { WordReg|Mem, 0, 0} },
482{"lmsw", 1, 0x0f01, 6, Modrm, { WordReg|Mem, 0, 0} },
77be9a8a 483{"lsl", 2, 0x0f03, X, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
fc0d7441
ILT		 484{"ltr", 1, 0x0f00, 3, Modrm, { WordReg|Mem, 0, 0} },
485
486{"sgdt", 1, 0x0f01, 0, Modrm, { Mem, 0, 0} },
487{"sidt", 1, 0x0f01, 1, Modrm, { Mem, 0, 0} },
488{"sldt", 1, 0x0f00, 0, Modrm, { WordReg|Mem, 0, 0} },
489{"smsw", 1, 0x0f01, 4, Modrm, { WordReg|Mem, 0, 0} },
490{"str", 1, 0x0f00, 1, Modrm, { Reg16|Mem, 0, 0} },
491
492{"verr", 1, 0x0f00, 4, Modrm, { WordReg|Mem, 0, 0} },
493{"verw", 1, 0x0f00, 5, Modrm, { WordReg|Mem, 0, 0} },
ce868e5c
JG		 494
495/* floating point instructions */
496
497/* load */
77be9a8a 498{"fld", 1, 0xd9c0, X, ShortForm, { FloatReg, 0, 0} }, /* register */
fc0d7441
ILT		 499{"flds", 1, 0xd9, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem float */
500{"fldl", 1, 0xdd, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem double */
77be9a8a 501{"fldl", 1, 0xd9c0, X, ShortForm, { FloatReg, 0, 0} }, /* register */
fc0d7441
ILT		 502{"fild", 1, 0xdf, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem word (16) */
503{"fildl", 1, 0xdb, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem dword (32) */
504{"fildq",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */
505{"fildll",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */
506{"fldt", 1, 0xdb, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem efloat */
507{"fbld", 1, 0xdf, 4, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem bcd */
ce868e5c
JG		 508
509/* store (no pop) */
77be9a8a 510{"fst", 1, 0xddd0, X, ShortForm, { FloatReg, 0, 0} }, /* register */
fc0d7441
ILT		 511{"fsts", 1, 0xd9, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */
512{"fstl", 1, 0xdd, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */
77be9a8a 513{"fstl", 1, 0xddd0, X, ShortForm, { FloatReg, 0, 0} }, /* register */
fc0d7441
ILT		 514{"fist", 1, 0xdf, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */
515{"fistl", 1, 0xdb, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */
ce868e5c
JG		 516
517/* store (with pop) */
77be9a8a 518{"fstp", 1, 0xddd8, X, ShortForm, { FloatReg, 0, 0} }, /* register */
fc0d7441
ILT		 519{"fstps", 1, 0xd9, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */
520{"fstpl", 1, 0xdd, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */
77be9a8a 521{"fstpl", 1, 0xddd8, X, ShortForm, { FloatReg, 0, 0} }, /* register */
fc0d7441
ILT		 522{"fistp", 1, 0xdf, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */
523{"fistpl",1, 0xdb, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */
524{"fistpq",1, 0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */
525{"fistpll",1,0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */
526{"fstpt", 1, 0xdb, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem efloat */
527{"fbstp", 1, 0xdf, 6, Modrm, { Mem, 0, 0} }, /* %st0 --> mem bcd */
ce868e5c
JG		 528
529/* exchange %st<n> with %st0 */
77be9a8a
ILT		 530{"fxch", 1, 0xd9c8, X, ShortForm, { FloatReg, 0, 0} },
531{"fxch", 0, 0xd9c9, X, 0, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */
ce868e5c
JG		 532
533/* comparison (without pop) */
77be9a8a 534{"fcom", 1, 0xd8d0, X, ShortForm, { FloatReg, 0, 0} },
fc0d7441 535{"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */
9df6ca2f 536{"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */
fc0d7441 537{"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */
77be9a8a 538{"fcoml", 1, 0xd8d0, X, ShortForm, { FloatReg, 0, 0} },
9df6ca2f 539{"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */
ce868e5c
JG		 540
541/* comparison (with pop) */
77be9a8a
ILT		 542{"fcomp", 1, 0xd8d8, X, ShortForm, { FloatReg, 0, 0} },
543{"fcomp", 0, 0xd8d9, X, 0, {0, 0, 0} }, /* fcomp %st, %st(1) */
fc0d7441 544{"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */
9df6ca2f 545{"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */
fc0d7441 546{"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */
77be9a8a 547{"fcompl", 1, 0xd8d8, X, ShortForm, { FloatReg, 0, 0} },
9df6ca2f 548{"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */
77be9a8a 549{"fcompp", 0, 0xded9, X, 0, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */
ce868e5c
JG		 550
551/* unordered comparison (with pop) */
77be9a8a
ILT		 552{"fucom", 1, 0xdde0, X, ShortForm, { FloatReg, 0, 0} },
553{"fucomp", 1, 0xdde8, X, ShortForm, { FloatReg, 0, 0} },
554{"fucompp", 0, 0xdae9, X, 0, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
ce868e5c 555
77be9a8a
ILT		 556{"ftst", 0, 0xd9e4, X, 0, { 0, 0, 0} }, /* test %st0 */
557{"fxam", 0, 0xd9e5, X, 0, { 0, 0, 0} }, /* examine %st0 */
ce868e5c
JG		 558
559/* load constants into %st0 */
77be9a8a
ILT		 560{"fld1", 0, 0xd9e8, X, 0, { 0, 0, 0} }, /* %st0 <-- 1.0 */
561{"fldl2t", 0, 0xd9e9, X, 0, { 0, 0, 0} }, /* %st0 <-- log2(10) */
562{"fldl2e", 0, 0xd9ea, X, 0, { 0, 0, 0} }, /* %st0 <-- log2(e) */
563{"fldpi", 0, 0xd9eb, X, 0, { 0, 0, 0} }, /* %st0 <-- pi */
564{"fldlg2", 0, 0xd9ec, X, 0, { 0, 0, 0} }, /* %st0 <-- log10(2) */
565{"fldln2", 0, 0xd9ed, X, 0, { 0, 0, 0} }, /* %st0 <-- ln(2) */
566{"fldz", 0, 0xd9ee, X, 0, { 0, 0, 0} }, /* %st0 <-- 0.0 */
ce868e5c
JG		 567
568/* arithmetic */
569
570/* add */
77be9a8a
ILT		 571{"fadd", 1, 0xd8c0, X, ShortForm, { FloatReg, 0, 0} },
572{"fadd", 2, 0xd8c0, X, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
573{"fadd", 0, 0xdcc1, X, 0, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */
574{"faddp", 1, 0xdec0, X, ShortForm, { FloatReg, 0, 0} },
575{"faddp", 2, 0xdec0, X, ShortForm, { FloatReg, FloatAcc, 0} },
576{"faddp", 2, 0xdec0, X, ShortForm, { FloatAcc, FloatReg, 0} },
577{"faddp", 0, 0xdec1, X, 0, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
fc0d7441
ILT		 578{"fadds", 1, 0xd8, 0, Modrm, { Mem, 0, 0} },
579{"fiaddl", 1, 0xda, 0, Modrm, { Mem, 0, 0} },
580{"faddl", 1, 0xdc, 0, Modrm, { Mem, 0, 0} },
581{"fiadds", 1, 0xde, 0, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 582
583/* sub */
584/* Note: intel has decided that certain of these operations are reversed
585 in assembler syntax. */
77be9a8a
ILT		 586{"fsub", 1, 0xd8e0, X, ShortForm, { FloatReg, 0, 0} },
587{"fsub", 2, 0xd8e0, X, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 588#ifdef NON_BROKEN_OPCODES
77be9a8a 589{"fsub", 2, 0xdce8, X, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 590#else
77be9a8a 591{"fsub", 2, 0xdce0, X, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 592#endif
77be9a8a
ILT		 593{"fsub", 0, 0xdce1, X, 0, { 0, 0, 0} },
594{"fsubp", 1, 0xdee8, X, ShortForm, { FloatReg, 0, 0} },
595{"fsubp", 2, 0xdee8, X, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 596#ifdef NON_BROKEN_OPCODES
77be9a8a
ILT		 597{"fsubp", 2, 0xdee8, X, ShortForm, { FloatAcc, FloatReg, 0} },
598{"fsubp", 0, 0xdee9, X, 0, { 0, 0, 0} },
ce868e5c 599#else
77be9a8a
ILT		 600{"fsubp", 2, 0xdee0, X, ShortForm, { FloatAcc, FloatReg, 0} },
601{"fsubp", 0, 0xdee1, X, 0, { 0, 0, 0} },
ce868e5c 602#endif
fc0d7441
ILT		 603{"fsubs", 1, 0xd8, 4, Modrm, { Mem, 0, 0} },
604{"fisubl", 1, 0xda, 4, Modrm, { Mem, 0, 0} },
605{"fsubl", 1, 0xdc, 4, Modrm, { Mem, 0, 0} },
606{"fisubs", 1, 0xde, 4, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 607
608/* sub reverse */
77be9a8a
ILT		 609{"fsubr", 1, 0xd8e8, X, ShortForm, { FloatReg, 0, 0} },
610{"fsubr", 2, 0xd8e8, X, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 611#ifdef NON_BROKEN_OPCODES
77be9a8a 612{"fsubr", 2, 0xdce0, X, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 613#else
77be9a8a 614{"fsubr", 2, 0xdce8, X, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 615#endif
77be9a8a
ILT		 616{"fsubr", 0, 0xdce9, X, 0, { 0, 0, 0} },
617{"fsubrp", 1, 0xdee0, X, ShortForm, { FloatReg, 0, 0} },
618{"fsubrp", 2, 0xdee0, X, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 619#ifdef NON_BROKEN_OPCODES
77be9a8a
ILT		 620{"fsubrp", 2, 0xdee0, X, ShortForm, { FloatAcc, FloatReg, 0} },
621{"fsubrp", 0, 0xdee1, X, 0, { 0, 0, 0} },
ce868e5c 622#else
77be9a8a
ILT		 623{"fsubrp", 2, 0xdee8, X, ShortForm, { FloatAcc, FloatReg, 0} },
624{"fsubrp", 0, 0xdee9, X, 0, { 0, 0, 0} },
ce868e5c 625#endif
fc0d7441
ILT		 626{"fsubrs", 1, 0xd8, 5, Modrm, { Mem, 0, 0} },
627{"fisubrl", 1, 0xda, 5, Modrm, { Mem, 0, 0} },
628{"fsubrl", 1, 0xdc, 5, Modrm, { Mem, 0, 0} },
629{"fisubrs", 1, 0xde, 5, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 630
631/* mul */
77be9a8a
ILT		 632{"fmul", 1, 0xd8c8, X, ShortForm, { FloatReg, 0, 0} },
633{"fmul", 2, 0xd8c8, X, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
634{"fmul", 0, 0xdcc9, X, 0, { 0, 0, 0} },
635{"fmulp", 1, 0xdec8, X, ShortForm, { FloatReg, 0, 0} },
636{"fmulp", 2, 0xdec8, X, ShortForm, { FloatReg, FloatAcc, 0} },
637{"fmulp", 2, 0xdec8, X, ShortForm, { FloatAcc, FloatReg, 0} },
638{"fmulp", 0, 0xdec9, X, 0, { 0, 0, 0} },
fc0d7441
ILT		 639{"fmuls", 1, 0xd8, 1, Modrm, { Mem, 0, 0} },
640{"fimull", 1, 0xda, 1, Modrm, { Mem, 0, 0} },
641{"fmull", 1, 0xdc, 1, Modrm, { Mem, 0, 0} },
642{"fimuls", 1, 0xde, 1, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 643
644/* div */
645/* Note: intel has decided that certain of these operations are reversed
646 in assembler syntax. */
77be9a8a
ILT		 647{"fdiv", 1, 0xd8f0, X, ShortForm, { FloatReg, 0, 0} },
648{"fdiv", 2, 0xd8f0, X, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 649#ifdef NON_BROKEN_OPCODES
77be9a8a 650{"fdiv", 2, 0xdcf8, X, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 651#else
77be9a8a 652{"fdiv", 2, 0xdcf0, X, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 653#endif
77be9a8a
ILT		 654{"fdiv", 0, 0xdcf1, X, 0, { 0, 0, 0} },
655{"fdivp", 1, 0xdef8, X, ShortForm, { FloatReg, 0, 0} },
656{"fdivp", 2, 0xdef8, X, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 657#ifdef NON_BROKEN_OPCODES
77be9a8a
ILT		 658{"fdivp", 2, 0xdef8, X, ShortForm, { FloatAcc, FloatReg, 0} },
659{"fdivp", 0, 0xdef9, X, 0, { 0, 0, 0} },
ce868e5c 660#else
77be9a8a
ILT		 661{"fdivp", 2, 0xdef0, X, ShortForm, { FloatAcc, FloatReg, 0} },
662{"fdivp", 0, 0xdef1, X, 0, { 0, 0, 0} },
ce868e5c 663#endif
fc0d7441
ILT		 664{"fdivs", 1, 0xd8, 6, Modrm, { Mem, 0, 0} },
665{"fidivl", 1, 0xda, 6, Modrm, { Mem, 0, 0} },
666{"fdivl", 1, 0xdc, 6, Modrm, { Mem, 0, 0} },
667{"fidivs", 1, 0xde, 6, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 668
669/* div reverse */
77be9a8a
ILT		 670{"fdivr", 1, 0xd8f8, X, ShortForm, { FloatReg, 0, 0} },
671{"fdivr", 2, 0xd8f8, X, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 672#ifdef NON_BROKEN_OPCODES
77be9a8a 673{"fdivr", 2, 0xdcf0, X, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 674#else
77be9a8a 675{"fdivr", 2, 0xdcf8, X, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 676#endif
77be9a8a
ILT		 677{"fdivr", 0, 0xdcf9, X, 0, { 0, 0, 0} },
678{"fdivrp", 1, 0xdef0, X, ShortForm, { FloatReg, 0, 0} },
679{"fdivrp", 2, 0xdef0, X, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 680#ifdef NON_BROKEN_OPCODES
77be9a8a
ILT		 681{"fdivrp", 2, 0xdef0, X, ShortForm, { FloatAcc, FloatReg, 0} },
682{"fdivrp", 0, 0xdef1, X, 0, { 0, 0, 0} },
ce868e5c 683#else
77be9a8a
ILT		 684{"fdivrp", 2, 0xdef8, X, ShortForm, { FloatAcc, FloatReg, 0} },
685{"fdivrp", 0, 0xdef9, X, 0, { 0, 0, 0} },
ce868e5c 686#endif
fc0d7441
ILT		 687{"fdivrs", 1, 0xd8, 7, Modrm, { Mem, 0, 0} },
688{"fidivrl", 1, 0xda, 7, Modrm, { Mem, 0, 0} },
689{"fdivrl", 1, 0xdc, 7, Modrm, { Mem, 0, 0} },
690{"fidivrs", 1, 0xde, 7, Modrm, { Mem, 0, 0} },
691
77be9a8a
ILT		 692{"f2xm1", 0, 0xd9f0, X, 0, { 0, 0, 0} },
693{"fyl2x", 0, 0xd9f1, X, 0, { 0, 0, 0} },
694{"fptan", 0, 0xd9f2, X, 0, { 0, 0, 0} },
695{"fpatan", 0, 0xd9f3, X, 0, { 0, 0, 0} },
696{"fxtract", 0, 0xd9f4, X, 0, { 0, 0, 0} },
697{"fprem1", 0, 0xd9f5, X, 0, { 0, 0, 0} },
698{"fdecstp", 0, 0xd9f6, X, 0, { 0, 0, 0} },
699{"fincstp", 0, 0xd9f7, X, 0, { 0, 0, 0} },
700{"fprem", 0, 0xd9f8, X, 0, { 0, 0, 0} },
701{"fyl2xp1", 0, 0xd9f9, X, 0, { 0, 0, 0} },
702{"fsqrt", 0, 0xd9fa, X, 0, { 0, 0, 0} },
703{"fsincos", 0, 0xd9fb, X, 0, { 0, 0, 0} },
704{"frndint", 0, 0xd9fc, X, 0, { 0, 0, 0} },
705{"fscale", 0, 0xd9fd, X, 0, { 0, 0, 0} },
706{"fsin", 0, 0xd9fe, X, 0, { 0, 0, 0} },
707{"fcos", 0, 0xd9ff, X, 0, { 0, 0, 0} },
708
709{"fchs", 0, 0xd9e0, X, 0, { 0, 0, 0} },
710{"fabs", 0, 0xd9e1, X, 0, { 0, 0, 0} },
ce868e5c
JG		 711
712/* processor control */
77be9a8a
ILT		 713{"fninit", 0, 0xdbe3, X, 0, { 0, 0, 0} },
714{"finit", 0, 0xdbe3, X, FWait, { 0, 0, 0} },
ffd42166
ILT		 715{"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} },
716{"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} },
717{"fstcw", 1, 0xd9, 7, FWait|Modrm, { Mem, 0, 0} },
77be9a8a 718{"fnstsw", 1, 0xdfe0, X, 0, { Acc, 0, 0} },
ffd42166 719{"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} },
77be9a8a
ILT		 720{"fnstsw", 0, 0xdfe0, X, 0, { 0, 0, 0} },
721{"fstsw", 1, 0xdfe0, X, FWait, { Acc, 0, 0} },
ffd42166 722{"fstsw", 1, 0xdd, 7, FWait|Modrm, { Mem, 0, 0} },
77be9a8a
ILT		 723{"fstsw", 0, 0xdfe0, X, FWait, { 0, 0, 0} },
724{"fnclex", 0, 0xdbe2, X, 0, { 0, 0, 0} },
725{"fclex", 0, 0xdbe2, X, FWait, { 0, 0, 0} },
ffd42166
ILT		 726{"fnstenv",1, 0xd9, 6, Modrm, { Mem, 0, 0} },
727{"fstenv", 1, 0xd9, 6, FWait|Modrm, { Mem, 0, 0} },
728{"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} },
729{"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} },
730{"fsave", 1, 0xdd, 6, FWait|Modrm, { Mem, 0, 0} },
731{"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} },
732/* Short forms of fldenv, fstenv use data size prefix. (At least I
733 think so. The PentPro prog ref I have says address size in one
734 place, operand size elsewhere). FIXME: Are these the right names? */
735{"fnstenvs",1, 0xd9, 6, Modrm|Data16, { Mem, 0, 0} },
736{"fstenvs", 1, 0xd9, 6, FWait|Modrm|Data16, { Mem, 0, 0} },
737{"fldenvs", 1, 0xd9, 4, Modrm|Data16, { Mem, 0, 0} },
738
77be9a8a 739{"ffree", 1, 0xddc0, X, ShortForm, { FloatReg, 0, 0} },
527cabaf 740/* P6:free st(i), pop st */
77be9a8a
ILT		 741{"ffreep", 1, 0xdfc0, X, ShortForm, { FloatReg, 0, 0} },
742{"fnop", 0, 0xd9d0, X, 0, { 0, 0, 0} },
ffd42166 743#define FWAIT_OPCODE 0x9b
77be9a8a 744{"fwait", 0, 0x9b, X, 0, { 0, 0, 0} },
ce868e5c
JG		 745
746/*
747 opcode prefixes; we allow them as seperate insns too
748 (see prefix table below)
749*/
77be9a8a
ILT		 750{"aword", 0, 0x67, X, 0, { 0, 0, 0} },
751{"addr16", 0, 0x67, X, 0, { 0, 0, 0} },
752{"word", 0, 0x66, X, 0, { 0, 0, 0} },
753{"data16", 0, 0x66, X, 0, { 0, 0, 0} },
754{"lock", 0, 0xf0, X, 0, { 0, 0, 0} },
755{"cs", 0, 0x2e, X, 0, { 0, 0, 0} },
756{"ds", 0, 0x3e, X, 0, { 0, 0, 0} },
757{"es", 0, 0x26, X, 0, { 0, 0, 0} },
758{"fs", 0, 0x64, X, 0, { 0, 0, 0} },
759{"gs", 0, 0x65, X, 0, { 0, 0, 0} },
760{"ss", 0, 0x36, X, 0, { 0, 0, 0} },
761{"rep", 0, 0xf3, X, 0, { 0, 0, 0} },
762{"repe", 0, 0xf3, X, 0, { 0, 0, 0} },
763{"repz", 0, 0xf3, X, 0, { 0, 0, 0} },
764{"repne", 0, 0xf2, X, 0, { 0, 0, 0} },
765{"repnz", 0, 0xf2, X, 0, { 0, 0, 0} },
fc0d7441
ILT		 766
767/* 486 extensions */
768
77be9a8a
ILT		 769{"bswap", 1, 0x0fc8, X, ShortForm, { Reg32,0,0 } },
770{"xadd", 2, 0x0fc0, X, W|Modrm, { Reg, Reg|Mem, 0 } },
771{"cmpxchg", 2, 0x0fb0, X, W|Modrm, { Reg, Reg|Mem, 0 } },
772{"invd", 0, 0x0f08, X, 0, { 0, 0, 0} },
773{"wbinvd", 0, 0x0f09, X, 0, { 0, 0, 0} },
fc0d7441
ILT		 774{"invlpg", 1, 0x0f01, 7, Modrm, { Mem, 0, 0} },
775
cd22144a 776/* 586 and late 486 extensions */
77be9a8a 777{"cpuid", 0, 0x0fa2, X, 0, { 0, 0, 0} },
cd22144a
KR		 778
779/* Pentium extensions */
77be9a8a
ILT		 780{"wrmsr", 0, 0x0f30, X, 0, { 0, 0, 0} },
781{"rdtsc", 0, 0x0f31, X, 0, { 0, 0, 0} },
782{"rdmsr", 0, 0x0f32, X, 0, { 0, 0, 0} },
527cabaf
ILT		 783{"cmpxchg8b", 1, 0x0fc7, 1, Modrm, { Mem, 0, 0} },
784
785/* Pentium Pro extensions */
77be9a8a
ILT		 786{"rdpmc", 0, 0x0f33, X, 0, { 0, 0, 0} },
787
788{"ud2", 0, 0x0f0b, X, 0, {0, 0, 0} }, /* official undefined instr. */
789
790{"cmovo", 2, 0x0f40, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
791{"cmovno", 2, 0x0f41, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
792{"cmovb", 2, 0x0f42, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
793{"cmovae", 2, 0x0f43, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
794{"cmove", 2, 0x0f44, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
795{"cmovne", 2, 0x0f45, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
796{"cmovbe", 2, 0x0f46, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
797{"cmova", 2, 0x0f47, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
798{"cmovs", 2, 0x0f48, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
799{"cmovns", 2, 0x0f49, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
800{"cmovp", 2, 0x0f4a, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
801{"cmovnp", 2, 0x0f4b, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
802{"cmovl", 2, 0x0f4c, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
803{"cmovge", 2, 0x0f4d, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
804{"cmovle", 2, 0x0f4e, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
805{"cmovg", 2, 0x0f4f, X, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
806
807{"fcmovb", 2, 0xdac0, X, ShortForm, { FloatReg, FloatAcc, 0} },
808{"fcmove", 2, 0xdac8, X, ShortForm, { FloatReg, FloatAcc, 0} },
809{"fcmovbe",2, 0xdad0, X, ShortForm, { FloatReg, FloatAcc, 0} },
810{"fcmovu", 2, 0xdad8, X, ShortForm, { FloatReg, FloatAcc, 0} },
811{"fcmovnb", 2, 0xdbc0, X, ShortForm, { FloatReg, FloatAcc, 0} },
812{"fcmovne", 2, 0xdbc8, X, ShortForm, { FloatReg, FloatAcc, 0} },
813{"fcmovnbe",2, 0xdbd0, X, ShortForm, { FloatReg, FloatAcc, 0} },
814{"fcmovnu", 2, 0xdbd8, X, ShortForm, { FloatReg, FloatAcc, 0} },
815
816{"fcomi", 2, 0xdbf0, X, ShortForm, { FloatReg, FloatAcc, 0} },
817{"fucomi", 2, 0xdbe8, X, ShortForm, { FloatReg, FloatAcc, 0} },
818{"fcomip", 2, 0xdff0, X, ShortForm, { FloatReg, FloatAcc, 0} },
819{"fucomip",2, 0xdfe8, X, ShortForm, { FloatReg, FloatAcc, 0} },
cd22144a 820
3abaf930
ILT		 821/* MMX instructions. */
822
77be9a8a
ILT		 823{"emms", 0, 0x0f77, X, 0, { 0, 0, 0 } },
824{"movd", 2, 0x0f6e, X, Modrm, { Reg32|WordMem, RegMMX, 0 } },
825{"movd", 2, 0x0f7e, X, Modrm, { RegMMX, Reg32|WordMem, 0 } },
826{"movq", 2, 0x0f6f, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
827{"movq", 2, 0x0f7f, X, Modrm, { RegMMX, RegMMX|WordMem, 0 } },
828{"packssdw", 2, 0x0f6b, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
829{"packsswb", 2, 0x0f63, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
830{"packuswb", 2, 0x0f67, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
831{"paddb", 2, 0x0ffc, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
832{"paddw", 2, 0x0ffd, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
833{"paddd", 2, 0x0ffe, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
834{"paddsb", 2, 0x0fec, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
835{"paddsw", 2, 0x0fed, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
836{"paddusb", 2, 0x0fdc, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
837{"paddusw", 2, 0x0fdd, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
838{"pand", 2, 0x0fdb, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
839{"pandn", 2, 0x0fdf, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
840{"pcmpeqb", 2, 0x0f74, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
841{"pcmpeqw", 2, 0x0f75, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
842{"pcmpeqd", 2, 0x0f76, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
843{"pcmpgtb", 2, 0x0f64, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
844{"pcmpgtw", 2, 0x0f65, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
845{"pcmpgtd", 2, 0x0f66, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
846{"pmaddwd", 2, 0x0ff5, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
847{"pmulhw", 2, 0x0fe5, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
848{"pmullw", 2, 0x0fd5, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
849{"por", 2, 0x0feb, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
850{"psllw", 2, 0x0ff1, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 851{"psllw", 2, 0x0f71, 6, Modrm, { Imm8, RegMMX, 0 } },
77be9a8a 852{"pslld", 2, 0x0ff2, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 853{"pslld", 2, 0x0f72, 6, Modrm, { Imm8, RegMMX, 0 } },
77be9a8a 854{"psllq", 2, 0x0ff3, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 855{"psllq", 2, 0x0f73, 6, Modrm, { Imm8, RegMMX, 0 } },
77be9a8a 856{"psraw", 2, 0x0fe1, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 857{"psraw", 2, 0x0f71, 4, Modrm, { Imm8, RegMMX, 0 } },
77be9a8a 858{"psrad", 2, 0x0fe2, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 859{"psrad", 2, 0x0f72, 4, Modrm, { Imm8, RegMMX, 0 } },
77be9a8a 860{"psrlw", 2, 0x0fd1, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 861{"psrlw", 2, 0x0f71, 2, Modrm, { Imm8, RegMMX, 0 } },
77be9a8a 862{"psrld", 2, 0x0fd2, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 863{"psrld", 2, 0x0f72, 2, Modrm, { Imm8, RegMMX, 0 } },
77be9a8a 864{"psrlq", 2, 0x0fd3, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 865{"psrlq", 2, 0x0f73, 2, Modrm, { Imm8, RegMMX, 0 } },
77be9a8a
ILT		 866{"psubb", 2, 0x0ff8, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
867{"psubw", 2, 0x0ff9, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
868{"psubd", 2, 0x0ffa, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
869{"psubsb", 2, 0x0fe8, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
870{"psubsw", 2, 0x0fe9, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
871{"psubusb", 2, 0x0fd8, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
872{"psubusw", 2, 0x0fd9, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
873{"punpckhbw", 2, 0x0f68, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
874{"punpckhwd", 2, 0x0f69, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
875{"punpckhdq", 2, 0x0f6a, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
876{"punpcklbw", 2, 0x0f60, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
877{"punpcklwd", 2, 0x0f61, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
878{"punpckldq", 2, 0x0f62, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
879{"pxor", 2, 0x0fef, X, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 880
a43022bd 881{"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
ce868e5c 882};
77be9a8a 883#undef X
ce868e5c 884
fc0d7441 885static const template *const i386_optab_end
ce868e5c
JG		 886 = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]);
887
888/* 386 register table */
889
890static const reg_entry i386_regtab[] = {
891 /* 8 bit regs */
77be9a8a
ILT		 892 {"al", Reg8|Acc, 0},
893 {"cl", Reg8|ShiftCount, 1},
894 {"dl", Reg8, 2},
ce868e5c 895 {"bl", Reg8, 3},
77be9a8a
ILT		 896 {"ah", Reg8, 4},
897 {"ch", Reg8, 5},
898 {"dh", Reg8, 6},
899 {"bh", Reg8, 7},
ce868e5c 900 /* 16 bit regs */
77be9a8a
ILT		 901 {"ax", Reg16|Acc, 0},
902 {"cx", Reg16, 1},
903 {"dx", Reg16|InOutPortReg, 2},
904 {"bx", Reg16, 3},
905 {"sp", Reg16, 4},
906 {"bp", Reg16, 5},
907 {"si", Reg16, 6},
908 {"di", Reg16, 7},
ce868e5c 909 /* 32 bit regs */
77be9a8a
ILT		 910 {"eax", Reg32|BaseIndex|Acc, 0},
911 {"ecx", Reg32|BaseIndex, 1},
912 {"edx", Reg32|BaseIndex, 2},
913 {"ebx", Reg32|BaseIndex, 3},
914 {"esp", Reg32|BaseIndex, 4},
915 {"ebp", Reg32|BaseIndex, 5},
916 {"esi", Reg32|BaseIndex, 6},
917 {"edi", Reg32|BaseIndex, 7},
ce868e5c 918 /* segment registers */
77be9a8a
ILT		 919 {"es", SReg2, 0},
920 {"cs", SReg2, 1},
921 {"ss", SReg2, 2},
922 {"ds", SReg2, 3},
923 {"fs", SReg3, 4},
924 {"gs", SReg3, 5},
ce868e5c 925 /* control registers */
77be9a8a
ILT		 926 {"cr0", Control, 0},
927 {"cr2", Control, 2},
928 {"cr3", Control, 3},
cd22144a 929 {"cr4", Control, 4},
ce868e5c 930 /* debug registers */
77be9a8a
ILT		 931 {"db0", Debug, 0},
932 {"db1", Debug, 1},
933 {"db2", Debug, 2},
934 {"db3", Debug, 3},
935 {"db6", Debug, 6},
936 {"db7", Debug, 7},
937 {"dr0", Debug, 0},
938 {"dr1", Debug, 1},
939 {"dr2", Debug, 2},
940 {"dr3", Debug, 3},
941 {"dr6", Debug, 6},
942 {"dr7", Debug, 7},
ce868e5c 943 /* test registers */
77be9a8a
ILT		 944 {"tr3", Test, 3},
945 {"tr4", Test, 4},
946 {"tr5", Test, 5},
947 {"tr6", Test, 6},
948 {"tr7", Test, 7},
ce868e5c
JG		 949 /* float registers */
950 {"st(0)", FloatReg|FloatAcc, 0},
951 {"st", FloatReg|FloatAcc, 0},
77be9a8a
ILT		 952 {"st(1)", FloatReg, 1},
953 {"st(2)", FloatReg, 2},
954 {"st(3)", FloatReg, 3},
955 {"st(4)", FloatReg, 4},
956 {"st(5)", FloatReg, 5},
957 {"st(6)", FloatReg, 6},
958 {"st(7)", FloatReg, 7},
959 {"mm0", RegMMX, 0},
960 {"mm1", RegMMX, 1},
961 {"mm2", RegMMX, 2},
962 {"mm3", RegMMX, 3},
963 {"mm4", RegMMX, 4},
964 {"mm5", RegMMX, 5},
965 {"mm6", RegMMX, 6},
966 {"mm7", RegMMX, 7}
ce868e5c
JG		 967};
968
969#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
970
fc0d7441 971static const reg_entry *const i386_regtab_end
ce868e5c
JG		 972 = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]);
973
974/* segment stuff */
975static const seg_entry cs = { "cs", 0x2e };
976static const seg_entry ds = { "ds", 0x3e };
977static const seg_entry ss = { "ss", 0x36 };
978static const seg_entry es = { "es", 0x26 };
979static const seg_entry fs = { "fs", 0x64 };
980static const seg_entry gs = { "gs", 0x65 };
ce868e5c
JG		 981
982static const prefix_entry i386_prefixtab[] = {
a43022bd 983#define ADDR_PREFIX_OPCODE 0x67
ce868e5c 984 { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
77be9a8a 985 useful when loop isns should use %cx. */
ce868e5c
JG		 986#define WORD_PREFIX_OPCODE 0x66
987 { "data16", 0x66 }, /* operand size prefix */
ffabaa53 988#define LOCK_PREFIX_OPCODE 0xf0
ce868e5c 989 { "lock", 0xf0 }, /* bus lock prefix */
77be9a8a 990 { "wait", FWAIT_OPCODE }, /* wait for coprocessor, not really a prefix */
ffabaa53
ILT		 991#define CS_PREFIX_OPCODE 0x2e
992 { "cs", 0x2e }, /* segment overrides ... */
993#define DS_PREFIX_OPCODE 0x3e
994 { "ds", 0x3e },
995#define ES_PREFIX_OPCODE 0x26
996 { "es", 0x26 },
997#define FS_PREFIX_OPCODE 0x64
998 { "fs", 0x64 },
999#define GS_PREFIX_OPCODE 0x65
1000 { "gs", 0x65 },
1001#define SS_PREFIX_OPCODE 0x36
1002 { "ss", 0x36 },
ce868e5c
JG		 1003/* REPE & REPNE used to detect rep/repne with a non-string instruction */
1004#define REPNE 0xf2
1005#define REPE 0xf3
77be9a8a
ILT		 1006 { "rep", 0xf3 }, /* repeat string instructions */
1007 { "repe", 0xf3 },
1008 { "repz", 0xf3 },
1009 { "repne", 0xf2 },
1010 { "repnz", 0xf2 }
ce868e5c
JG		 1011};
1012
fc0d7441 1013static const prefix_entry *const i386_prefixtab_end
ce868e5c
JG		 1014 = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);
1015
1016/* end of i386-opcode.h */
GDB Binutils - Deliverables
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