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* i386.h (Z_): Renamed from `_' to avoid clash with common alias
[deliverable/binutils-gdb.git] / include / opcode / i386.h
CommitLineData
ce868e5c 1/* i386-opcode.h -- Intel 80386 opcode table
d411c9ef 2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation.
ce868e5c
JG		 3
4This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
5
6This program is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2 of the License, or
9(at your option) any later version.
10
11This program is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with this program; if not, write to the Free Software
cd22144a 18Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
ce868e5c 19
c0d7b534
ILT		 20/* The NON_BROKEN_OPCODES cases use the operands in the reverse order
21 from that documented in the Intel manuals. The opcode values are
22 such that they actually generate different instructions. These
654b0845
ILT		 23 values must not be changed, as they are the values generated by the
24 UnixWare assembler, and possibly other ix86 assemblers. */
c0d7b534 25
ce868e5c
JG		 26static const template i386_optab[] = {
27
9d3a718c 28#define Z_ None
ffabaa53 29
ce868e5c 30/* move instructions */
a43022bd 31#define MOV_AX_DISP32 0xa0
9d3a718c
TT		 32{ "mov", 2, 0xa0, Z_, DW, { Disp32, Acc, 0 } },
33{ "mov", 2, 0x88, Z_, DW|Modrm, { Reg, Reg|Mem, 0 } },
34{ "mov", 2, 0xb0, Z_, ShortFormW, { Imm, Reg, 0 } },
35{ "mov", 2, 0xc6, Z_, W|Modrm, { Imm, Reg|Mem, 0 } },
eff2a090
ILT		 36/* The next instruction accepts WordReg so that `movl %gs,%esi' can be
37 used to move a segment register to a 32 bit register without using
ffabaa53
ILT		 38 a size prefix. This will set the upper 16 bits of the 32 bit
39 register to an implementation defined value (on the Pentium Pro,
40 the implementation defined value is zero). */
9d3a718c 41{ "mov", 2, 0x8c, Z_, D|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } },
ce868e5c 42/* move to/from control debug registers */
9d3a718c
TT		 43{ "mov", 2, 0x0f20, Z_, D|Modrm, { Control, Reg32, 0} },
44{ "mov", 2, 0x0f21, Z_, D|Modrm, { Debug, Reg32, 0} },
45{ "mov", 2, 0x0f24, Z_, D|Modrm, { Test, Reg32, 0} },
ce868e5c
JG		 46
47/* move with sign extend */
48/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
49 conflict with the "movs" string move instruction. Thus,
9d3a718c 50 {"movsb", 2, 0x0fbe, Z_, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
ce868e5c 51 is not kosher; we must seperate the two instructions. */
9d3a718c
TT		 52{"movsbl", 2, 0x0fbe, Z_, ReverseRegRegmem|Modrm|Data32, { Reg8|Mem, Reg32, 0} },
53{"movsbw", 2, 0x0fbe, Z_, ReverseRegRegmem|Modrm|Data16, { Reg8|Mem, Reg16, 0} },
54{"movswl", 2, 0x0fbf, Z_, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
ce868e5c
JG		 55
56/* move with zero extend */
9d3a718c
TT		 57{"movzb", 2, 0x0fb6, Z_, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
58{"movzwl", 2, 0x0fb7, Z_, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
ce868e5c
JG		 59
60/* push instructions */
9d3a718c 61{"push", 1, 0x50, Z_, ShortForm, { WordReg,0,0 } },
fc0d7441 62{"push", 1, 0xff, 0x6, Modrm, { WordReg|WordMem, 0, 0 } },
9d3a718c
TT		 63{"push", 1, 0x6a, Z_, 0, { Imm8S, 0, 0} },
64{"push", 1, 0x68, Z_, 0, { Imm16|Imm32, 0, 0} },
65{"push", 1, 0x06, Z_, Seg2ShortForm, { SReg2,0,0 } },
66{"push", 1, 0x0fa0, Z_, Seg3ShortForm, { SReg3,0,0 } },
ce868e5c 67/* push all */
9d3a718c 68{"pusha", 0, 0x60, Z_, 0, { 0, 0, 0 } },
ce868e5c
JG		 69
70/* pop instructions */
9d3a718c 71{"pop", 1, 0x58, Z_, ShortForm, { WordReg,0,0 } },
fc0d7441 72{"pop", 1, 0x8f, 0x0, Modrm, { WordReg|WordMem, 0, 0 } },
ce868e5c 73#define POP_SEG_SHORT 0x7
9d3a718c
TT		 74{"pop", 1, 0x07, Z_, Seg2ShortForm, { SReg2,0,0 } },
75{"pop", 1, 0x0fa1, Z_, Seg3ShortForm, { SReg3,0,0 } },
ce868e5c 76/* pop all */
9d3a718c 77{"popa", 0, 0x61, Z_, 0, { 0, 0, 0 } },
ce868e5c
JG		 78
79/* xchg exchange instructions
80 xchg commutes: we allow both operand orders */
9d3a718c
TT		 81{"xchg", 2, 0x90, Z_, ShortForm, { WordReg, Acc, 0 } },
82{"xchg", 2, 0x90, Z_, ShortForm, { Acc, WordReg, 0 } },
83{"xchg", 2, 0x86, Z_, W|Modrm, { Reg, Reg|Mem, 0 } },
84{"xchg", 2, 0x86, Z_, W|Modrm, { Reg|Mem, Reg, 0 } },
ce868e5c
JG		 85
86/* in/out from ports */
9d3a718c
TT		 87{"in", 2, 0xe4, Z_, W, { Imm8, Acc, 0 } },
88{"in", 2, 0xec, Z_, W, { InOutPortReg, Acc, 0 } },
89{"in", 1, 0xe4, Z_, W, { Imm8, 0, 0 } },
90{"in", 1, 0xec, Z_, W, { InOutPortReg, 0, 0 } },
91{"out", 2, 0xe6, Z_, W, { Acc, Imm8, 0 } },
92{"out", 2, 0xee, Z_, W, { Acc, InOutPortReg, 0 } },
93{"out", 1, 0xe6, Z_, W, { Imm8, 0, 0 } },
94{"out", 1, 0xee, Z_, W, { InOutPortReg, 0, 0 } },
fc0d7441 95
ce868e5c 96/* load effective address */
9d3a718c 97{"lea", 2, 0x8d, Z_, Modrm, { WordMem, WordReg, 0 } },
ce868e5c
JG		 98
99/* load segment registers from memory */
9d3a718c
TT		 100{"lds", 2, 0xc5, Z_, Modrm, { Mem, Reg32, 0} },
101{"les", 2, 0xc4, Z_, Modrm, { Mem, Reg32, 0} },
102{"lfs", 2, 0x0fb4, Z_, Modrm, { Mem, Reg32, 0} },
103{"lgs", 2, 0x0fb5, Z_, Modrm, { Mem, Reg32, 0} },
104{"lss", 2, 0x0fb2, Z_, Modrm, { Mem, Reg32, 0} },
ce868e5c
JG		 105
106/* flags register instructions */
9d3a718c
TT		 107{"clc", 0, 0xf8, Z_, 0, { 0, 0, 0} },
108{"cld", 0, 0xfc, Z_, 0, { 0, 0, 0} },
109{"cli", 0, 0xfa, Z_, 0, { 0, 0, 0} },
110{"clts", 0, 0x0f06, Z_, 0, { 0, 0, 0} },
111{"cmc", 0, 0xf5, Z_, 0, { 0, 0, 0} },
112{"lahf", 0, 0x9f, Z_, 0, { 0, 0, 0} },
113{"sahf", 0, 0x9e, Z_, 0, { 0, 0, 0} },
114{"pushfl", 0, 0x9c, Z_, Data32, { 0, 0, 0} },
115{"popfl", 0, 0x9d, Z_, Data32, { 0, 0, 0} },
116{"pushfw", 0, 0x9c, Z_, Data16, { 0, 0, 0} },
117{"popfw", 0, 0x9d, Z_, Data16, { 0, 0, 0} },
118{"pushf", 0, 0x9c, Z_, 0, { 0, 0, 0} },
119{"popf", 0, 0x9d, Z_, 0, { 0, 0, 0} },
120{"stc", 0, 0xf9, Z_, 0, { 0, 0, 0} },
121{"std", 0, 0xfd, Z_, 0, { 0, 0, 0} },
122{"sti", 0, 0xfb, Z_, 0, { 0, 0, 0} },
123
124{"add", 2, 0x0, Z_, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 125{"add", 2, 0x83, 0, Modrm, { Imm8S, WordReg|WordMem, 0} },
9d3a718c 126{"add", 2, 0x4, Z_, W, { Imm, Acc, 0} },
fc0d7441
ILT		 127{"add", 2, 0x80, 0, W|Modrm, { Imm, Reg|Mem, 0} },
128
9d3a718c 129{"inc", 1, 0x40, Z_, ShortForm, { WordReg, 0, 0} },
fc0d7441
ILT		 130{"inc", 1, 0xfe, 0, W|Modrm, { Reg|Mem, 0, 0} },
131
9d3a718c 132{"sub", 2, 0x28, Z_, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 133{"sub", 2, 0x83, 5, Modrm, { Imm8S, WordReg|WordMem, 0} },
9d3a718c 134{"sub", 2, 0x2c, Z_, W, { Imm, Acc, 0} },
fc0d7441
ILT		 135{"sub", 2, 0x80, 5, W|Modrm, { Imm, Reg|Mem, 0} },
136
9d3a718c 137{"dec", 1, 0x48, Z_, ShortForm, { WordReg, 0, 0} },
fc0d7441
ILT		 138{"dec", 1, 0xfe, 1, W|Modrm, { Reg|Mem, 0, 0} },
139
9d3a718c 140{"sbb", 2, 0x18, Z_, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 141{"sbb", 2, 0x83, 3, Modrm, { Imm8S, WordReg|WordMem, 0} },
9d3a718c 142{"sbb", 2, 0x1c, Z_, W, { Imm, Acc, 0} },
fc0d7441
ILT		 143{"sbb", 2, 0x80, 3, W|Modrm, { Imm, Reg|Mem, 0} },
144
9d3a718c 145{"cmp", 2, 0x38, Z_, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 146{"cmp", 2, 0x83, 7, Modrm, { Imm8S, WordReg|WordMem, 0} },
9d3a718c 147{"cmp", 2, 0x3c, Z_, W, { Imm, Acc, 0} },
fc0d7441
ILT		 148{"cmp", 2, 0x80, 7, W|Modrm, { Imm, Reg|Mem, 0} },
149
9d3a718c
TT		 150{"test", 2, 0x84, Z_, W|Modrm, { Reg|Mem, Reg, 0} },
151{"test", 2, 0x84, Z_, W|Modrm, { Reg, Reg|Mem, 0} },
152{"test", 2, 0xa8, Z_, W, { Imm, Acc, 0} },
fc0d7441
ILT		 153{"test", 2, 0xf6, 0, W|Modrm, { Imm, Reg|Mem, 0} },
154
9d3a718c 155{"and", 2, 0x20, Z_, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 156{"and", 2, 0x83, 4, Modrm, { Imm8S, WordReg|WordMem, 0} },
9d3a718c 157{"and", 2, 0x24, Z_, W, { Imm, Acc, 0} },
fc0d7441
ILT		 158{"and", 2, 0x80, 4, W|Modrm, { Imm, Reg|Mem, 0} },
159
9d3a718c 160{"or", 2, 0x08, Z_, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 161{"or", 2, 0x83, 1, Modrm, { Imm8S, WordReg|WordMem, 0} },
9d3a718c 162{"or", 2, 0x0c, Z_, W, { Imm, Acc, 0} },
fc0d7441
ILT		 163{"or", 2, 0x80, 1, W|Modrm, { Imm, Reg|Mem, 0} },
164
9d3a718c 165{"xor", 2, 0x30, Z_, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 166{"xor", 2, 0x83, 6, Modrm, { Imm8S, WordReg|WordMem, 0} },
9d3a718c 167{"xor", 2, 0x34, Z_, W, { Imm, Acc, 0} },
fc0d7441
ILT		 168{"xor", 2, 0x80, 6, W|Modrm, { Imm, Reg|Mem, 0} },
169
c00435ed 170/* iclr with 1 operand is really xor with 2 operands. */
9d3a718c 171{"clr", 1, 0x30, Z_, W|Modrm|iclrKludge, { Reg } },
c00435ed 172
9d3a718c 173{"adc", 2, 0x10, Z_, DW|Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 174{"adc", 2, 0x83, 2, Modrm, { Imm8S, WordReg|WordMem, 0} },
9d3a718c 175{"adc", 2, 0x14, Z_, W, { Imm, Acc, 0} },
fc0d7441
ILT		 176{"adc", 2, 0x80, 2, W|Modrm, { Imm, Reg|Mem, 0} },
177
178{"neg", 1, 0xf6, 3, W|Modrm, { Reg|Mem, 0, 0} },
179{"not", 1, 0xf6, 2, W|Modrm, { Reg|Mem, 0, 0} },
180
9d3a718c
TT		 181{"aaa", 0, 0x37, Z_, 0, { 0, 0, 0} },
182{"aas", 0, 0x3f, Z_, 0, { 0, 0, 0} },
183{"daa", 0, 0x27, Z_, 0, { 0, 0, 0} },
184{"das", 0, 0x2f, Z_, 0, { 0, 0, 0} },
185{"aad", 0, 0xd50a, Z_, 0, { 0, 0, 0} },
186{"aam", 0, 0xd40a, Z_, 0, { 0, 0, 0} },
ce868e5c
JG		 187
188/* conversion insns */
189/* conversion: intel naming */
9d3a718c
TT		 190{"cbw", 0, 0x98, Z_, Data16, { 0, 0, 0} },
191{"cwd", 0, 0x99, Z_, Data16, { 0, 0, 0} },
192{"cwde", 0, 0x98, Z_, Data32, { 0, 0, 0} },
193{"cdq", 0, 0x99, Z_, Data32, { 0, 0, 0} },
ce868e5c 194/* att naming */
9d3a718c
TT		 195{"cbtw", 0, 0x98, Z_, Data16, { 0, 0, 0} },
196{"cwtl", 0, 0x98, Z_, Data32, { 0, 0, 0} },
197{"cwtd", 0, 0x99, Z_, Data16, { 0, 0, 0} },
198{"cltd", 0, 0x99, Z_, Data32, { 0, 0, 0} },
ce868e5c
JG		 199
200/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
201 expanding 64-bit multiplies, and *cannot* be selected to accomplish
202 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
a43022bd 203 These multiplies can only be selected with single operand forms. */
fc0d7441
ILT		 204{"mul", 1, 0xf6, 4, W|Modrm, { Reg|Mem, 0, 0} },
205{"imul", 1, 0xf6, 5, W|Modrm, { Reg|Mem, 0, 0} },
ce868e5c
JG		 206
207
208
209
210/* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
211 These instructions are exceptions: 'imul $2, %eax, %ecx' would put
212 '%eax' in the reg field and '%ecx' in the regmem field if we did not
213 switch them. */
9d3a718c
TT		 214{"imul", 2, 0x0faf, Z_, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
215{"imul", 3, 0x6b, Z_, Modrm|ReverseRegRegmem, { Imm8S, WordReg|Mem, WordReg} },
216{"imul", 3, 0x69, Z_, Modrm|ReverseRegRegmem, { Imm16|Imm32, WordReg|Mem, WordReg} },
ce868e5c
JG		 217/*
218 imul with 2 operands mimicks imul with 3 by puting register both
219 in i.rm.reg & i.rm.regmem fields
220*/
9d3a718c
TT		 221{"imul", 2, 0x6b, Z_, Modrm|imulKludge, { Imm8S, WordReg, 0} },
222{"imul", 2, 0x69, Z_, Modrm|imulKludge, { Imm16|Imm32, WordReg, 0} },
fc0d7441
ILT		 223{"div", 1, 0xf6, 6, W|Modrm, { Reg|Mem, 0, 0} },
224{"div", 2, 0xf6, 6, W|Modrm, { Reg|Mem, Acc, 0} },
225{"idiv", 1, 0xf6, 7, W|Modrm, { Reg|Mem, 0, 0} },
226{"idiv", 2, 0xf6, 7, W|Modrm, { Reg|Mem, Acc, 0} },
227
228{"rol", 2, 0xd0, 0, W|Modrm, { Imm1, Reg|Mem, 0} },
229{"rol", 2, 0xc0, 0, W|Modrm, { Imm8, Reg|Mem, 0} },
230{"rol", 2, 0xd2, 0, W|Modrm, { ShiftCount, Reg|Mem, 0} },
231{"rol", 1, 0xd0, 0, W|Modrm, { Reg|Mem, 0, 0} },
232
233{"ror", 2, 0xd0, 1, W|Modrm, { Imm1, Reg|Mem, 0} },
234{"ror", 2, 0xc0, 1, W|Modrm, { Imm8, Reg|Mem, 0} },
235{"ror", 2, 0xd2, 1, W|Modrm, { ShiftCount, Reg|Mem, 0} },
236{"ror", 1, 0xd0, 1, W|Modrm, { Reg|Mem, 0, 0} },
237
238{"rcl", 2, 0xd0, 2, W|Modrm, { Imm1, Reg|Mem, 0} },
239{"rcl", 2, 0xc0, 2, W|Modrm, { Imm8, Reg|Mem, 0} },
240{"rcl", 2, 0xd2, 2, W|Modrm, { ShiftCount, Reg|Mem, 0} },
241{"rcl", 1, 0xd0, 2, W|Modrm, { Reg|Mem, 0, 0} },
242
243{"rcr", 2, 0xd0, 3, W|Modrm, { Imm1, Reg|Mem, 0} },
244{"rcr", 2, 0xc0, 3, W|Modrm, { Imm8, Reg|Mem, 0} },
245{"rcr", 2, 0xd2, 3, W|Modrm, { ShiftCount, Reg|Mem, 0} },
246{"rcr", 1, 0xd0, 3, W|Modrm, { Reg|Mem, 0, 0} },
247
248{"sal", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
249{"sal", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
250{"sal", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
251{"sal", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
252{"shl", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
253{"shl", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
254{"shl", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
255{"shl", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
256
9d3a718c
TT		 257{"shld", 3, 0x0fa4, Z_, Modrm, { Imm8, WordReg, WordReg|Mem} },
258{"shld", 3, 0x0fa5, Z_, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
259{"shld", 2, 0x0fa5, Z_, Modrm, { WordReg, WordReg|Mem, 0} },
fc0d7441
ILT		 260
261{"shr", 2, 0xd0, 5, W|Modrm, { Imm1, Reg|Mem, 0} },
262{"shr", 2, 0xc0, 5, W|Modrm, { Imm8, Reg|Mem, 0} },
263{"shr", 2, 0xd2, 5, W|Modrm, { ShiftCount, Reg|Mem, 0} },
264{"shr", 1, 0xd0, 5, W|Modrm, { Reg|Mem, 0, 0} },
265
9d3a718c
TT		 266{"shrd", 3, 0x0fac, Z_, Modrm, { Imm8, WordReg, WordReg|Mem} },
267{"shrd", 3, 0x0fad, Z_, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
268{"shrd", 2, 0x0fad, Z_, Modrm, { WordReg, WordReg|Mem, 0} },
fc0d7441
ILT		 269
270{"sar", 2, 0xd0, 7, W|Modrm, { Imm1, Reg|Mem, 0} },
271{"sar", 2, 0xc0, 7, W|Modrm, { Imm8, Reg|Mem, 0} },
272{"sar", 2, 0xd2, 7, W|Modrm, { ShiftCount, Reg|Mem, 0} },
273{"sar", 1, 0xd0, 7, W|Modrm, { Reg|Mem, 0, 0} },
ce868e5c
JG		 274
275/* control transfer instructions */
276#define CALL_PC_RELATIVE 0xe8
9d3a718c 277{"call", 1, 0xe8, Z_, JumpDword, { Disp32, 0, 0} },
a43022bd
KR		 278{"call", 1, 0xff, 2, Modrm|Data32, { Reg|Mem|JumpAbsolute, 0, 0} },
279{"callw", 1, 0xff, 2, Modrm|Data16, { Reg|Mem|JumpAbsolute, 0, 0} },
ce868e5c 280#define CALL_FAR_IMMEDIATE 0x9a
9d3a718c 281{"lcall", 2, 0x9a, Z_, JumpInterSegment, { Imm16, Imm32, 0} },
a43022bd
KR		 282{"lcall", 1, 0xff, 3, Modrm|Data32, { Mem, 0, 0} },
283{"lcallw", 1, 0xff, 3, Modrm|Data16, { Mem, 0, 0} },
ce868e5c
JG		 284
285#define JUMP_PC_RELATIVE 0xeb
9d3a718c 286{"jmp", 1, 0xeb, Z_, Jump, { Disp, 0, 0} },
fc0d7441 287{"jmp", 1, 0xff, 4, Modrm, { Reg32|Mem|JumpAbsolute, 0, 0} },
ce868e5c 288#define JUMP_FAR_IMMEDIATE 0xea
9d3a718c 289{"ljmp", 2, 0xea, Z_, JumpInterSegment, { Imm16, Imm32, 0} },
a43022bd
KR		 290{"ljmp", 1, 0xff, 5, Modrm|Data32, { Mem, 0, 0} },
291
9d3a718c
TT		 292{"ret", 0, 0xc3, Z_, Data32, { 0, 0, 0} },
293{"ret", 1, 0xc2, Z_, Data32, { Imm16, 0, 0} },
294{"retw", 0, 0xc3, Z_, Data16, { 0, 0, 0} },
295{"retw", 1, 0xc2, Z_, Data16, { Imm16, 0, 0} },
296{"lret", 0, 0xcb, Z_, Data32, { 0, 0, 0} },
297{"lret", 1, 0xca, Z_, Data32, { Imm16, 0, 0} },
298{"lretw", 0, 0xcb, Z_, Data16, { 0, 0, 0} },
299{"lretw", 1, 0xca, Z_, Data16, { Imm16, 0, 0} },
300{"enter", 2, 0xc8, Z_, Data32, { Imm16, Imm8, 0} },
301{"leave", 0, 0xc9, Z_, Data32, { 0, 0, 0} },
302{"enterw", 2, 0xc8, Z_, Data16, { Imm16, Imm8, 0} },
303{"leavew", 0, 0xc9, Z_, Data16, { 0, 0, 0} },
ce868e5c
JG		 304
305/* conditional jumps */
9d3a718c 306{"jo", 1, 0x70, Z_, Jump, { Disp, 0, 0} },
ce868e5c 307
9d3a718c 308{"jno", 1, 0x71, Z_, Jump, { Disp, 0, 0} },
ce868e5c 309
9d3a718c
TT		 310{"jb", 1, 0x72, Z_, Jump, { Disp, 0, 0} },
311{"jc", 1, 0x72, Z_, Jump, { Disp, 0, 0} },
312{"jnae", 1, 0x72, Z_, Jump, { Disp, 0, 0} },
ce868e5c 313
9d3a718c
TT		 314{"jnb", 1, 0x73, Z_, Jump, { Disp, 0, 0} },
315{"jnc", 1, 0x73, Z_, Jump, { Disp, 0, 0} },
316{"jae", 1, 0x73, Z_, Jump, { Disp, 0, 0} },
ce868e5c 317
9d3a718c
TT		 318{"je", 1, 0x74, Z_, Jump, { Disp, 0, 0} },
319{"jz", 1, 0x74, Z_, Jump, { Disp, 0, 0} },
ce868e5c 320
9d3a718c
TT		 321{"jne", 1, 0x75, Z_, Jump, { Disp, 0, 0} },
322{"jnz", 1, 0x75, Z_, Jump, { Disp, 0, 0} },
ce868e5c 323
9d3a718c
TT		 324{"jbe", 1, 0x76, Z_, Jump, { Disp, 0, 0} },
325{"jna", 1, 0x76, Z_, Jump, { Disp, 0, 0} },
ce868e5c 326
9d3a718c
TT		 327{"jnbe", 1, 0x77, Z_, Jump, { Disp, 0, 0} },
328{"ja", 1, 0x77, Z_, Jump, { Disp, 0, 0} },
ce868e5c 329
9d3a718c 330{"js", 1, 0x78, Z_, Jump, { Disp, 0, 0} },
ce868e5c 331
9d3a718c 332{"jns", 1, 0x79, Z_, Jump, { Disp, 0, 0} },
ce868e5c 333
9d3a718c
TT		 334{"jp", 1, 0x7a, Z_, Jump, { Disp, 0, 0} },
335{"jpe", 1, 0x7a, Z_, Jump, { Disp, 0, 0} },
ce868e5c 336
9d3a718c
TT		 337{"jnp", 1, 0x7b, Z_, Jump, { Disp, 0, 0} },
338{"jpo", 1, 0x7b, Z_, Jump, { Disp, 0, 0} },
ce868e5c 339
9d3a718c
TT		 340{"jl", 1, 0x7c, Z_, Jump, { Disp, 0, 0} },
341{"jnge", 1, 0x7c, Z_, Jump, { Disp, 0, 0} },
ce868e5c 342
9d3a718c
TT		 343{"jnl", 1, 0x7d, Z_, Jump, { Disp, 0, 0} },
344{"jge", 1, 0x7d, Z_, Jump, { Disp, 0, 0} },
ce868e5c 345
9d3a718c
TT		 346{"jle", 1, 0x7e, Z_, Jump, { Disp, 0, 0} },
347{"jng", 1, 0x7e, Z_, Jump, { Disp, 0, 0} },
ce868e5c 348
9d3a718c
TT		 349{"jnle", 1, 0x7f, Z_, Jump, { Disp, 0, 0} },
350{"jg", 1, 0x7f, Z_, Jump, { Disp, 0, 0} },
ce868e5c 351
ce868e5c 352#define IS_JUMP_ON_CX_ZERO(o) \
ce868e5c
JG		 353 (o == 0xe3)
354
c2367582 355/* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
9d3a718c
TT		 356{"jcxz", 1, 0xe3, Z_, JumpByte|Data16, { Disp, 0, 0} },
357{"jecxz", 1, 0xe3, Z_, JumpByte|Data32, { Disp, 0, 0} },
ce868e5c
JG		 358
359#define IS_LOOP_ECX_TIMES(o) \
360 (o == 0xe2 || o == 0xe1 || o == 0xe0)
361
9d3a718c 362{"loop", 1, 0xe2, Z_, JumpByte, { Disp, 0, 0} },
ce868e5c 363
9d3a718c
TT		 364{"loopz", 1, 0xe1, Z_, JumpByte, { Disp, 0, 0} },
365{"loope", 1, 0xe1, Z_, JumpByte, { Disp, 0, 0} },
ce868e5c 366
9d3a718c
TT		 367{"loopnz", 1, 0xe0, Z_, JumpByte, { Disp, 0, 0} },
368{"loopne", 1, 0xe0, Z_, JumpByte, { Disp, 0, 0} },
ce868e5c
JG		 369
370/* set byte on flag instructions */
fc0d7441 371{"seto", 1, 0x0f90, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 372
fc0d7441 373{"setno", 1, 0x0f91, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 374
fc0d7441
ILT		 375{"setb", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
376{"setc", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
377{"setnae", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 378
fc0d7441
ILT		 379{"setnb", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
380{"setnc", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
381{"setae", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 382
fc0d7441
ILT		 383{"sete", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
384{"setz", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 385
fc0d7441
ILT		 386{"setne", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
387{"setnz", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 388
fc0d7441
ILT		 389{"setbe", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
390{"setna", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 391
fc0d7441
ILT		 392{"setnbe", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
393{"seta", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 394
fc0d7441 395{"sets", 1, 0x0f98, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 396
fc0d7441 397{"setns", 1, 0x0f99, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 398
fc0d7441
ILT		 399{"setp", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
400{"setpe", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 401
fc0d7441
ILT		 402{"setnp", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
403{"setpo", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 404
fc0d7441
ILT		 405{"setl", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
406{"setnge", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 407
fc0d7441
ILT		 408{"setnl", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
409{"setge", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 410
fc0d7441
ILT		 411{"setle", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
412{"setng", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 413
fc0d7441
ILT		 414{"setnle", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
415{"setg", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 416
ce868e5c 417/* string manipulation */
9d3a718c
TT		 418{"cmps", 0, 0xa6, Z_, W|IsString, { 0, 0, 0} },
419{"scmp", 0, 0xa6, Z_, W|IsString, { 0, 0, 0} },
420{"ins", 0, 0x6c, Z_, W|IsString, { 0, 0, 0} },
421{"outs", 0, 0x6e, Z_, W|IsString, { 0, 0, 0} },
422{"lods", 0, 0xac, Z_, W|IsString, { 0, 0, 0} },
423{"slod", 0, 0xac, Z_, W|IsString, { 0, 0, 0} },
424{"movs", 0, 0xa4, Z_, W|IsString, { 0, 0, 0} },
425{"smov", 0, 0xa4, Z_, W|IsString, { 0, 0, 0} },
426{"scas", 0, 0xae, Z_, W|IsString, { 0, 0, 0} },
427{"ssca", 0, 0xae, Z_, W|IsString, { 0, 0, 0} },
428{"stos", 0, 0xaa, Z_, W|IsString, { 0, 0, 0} },
429{"ssto", 0, 0xaa, Z_, W|IsString, { 0, 0, 0} },
430{"xlat", 0, 0xd7, Z_, IsString, { 0, 0, 0} },
ce868e5c
JG		 431
432/* bit manipulation */
9d3a718c
TT		 433{"bsf", 2, 0x0fbc, Z_, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
434{"bsr", 2, 0x0fbd, Z_, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
435{"bt", 2, 0x0fa3, Z_, Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 436{"bt", 2, 0x0fba, 4, Modrm, { Imm8, Reg|Mem, 0} },
9d3a718c 437{"btc", 2, 0x0fbb, Z_, Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 438{"btc", 2, 0x0fba, 7, Modrm, { Imm8, Reg|Mem, 0} },
9d3a718c 439{"btr", 2, 0x0fb3, Z_, Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 440{"btr", 2, 0x0fba, 6, Modrm, { Imm8, Reg|Mem, 0} },
9d3a718c 441{"bts", 2, 0x0fab, Z_, Modrm, { Reg, Reg|Mem, 0} },
fc0d7441 442{"bts", 2, 0x0fba, 5, Modrm, { Imm8, Reg|Mem, 0} },
ce868e5c
JG		 443
444/* interrupts & op. sys insns */
a43022bd
KR		 445/* See gas/config/tc-i386.c for conversion of 'int $3' into the special
446 int 3 insn. */
ce868e5c
JG		 447#define INT_OPCODE 0xcd
448#define INT3_OPCODE 0xcc
9d3a718c
TT		 449{"int", 1, 0xcd, Z_, 0, { Imm8, 0, 0} },
450{"int3", 0, 0xcc, Z_, 0, { 0, 0, 0} },
451{"into", 0, 0xce, Z_, 0, { 0, 0, 0} },
452{"iret", 0, 0xcf, Z_, Data32, { 0, 0, 0} },
453{"iretw", 0, 0xcf, Z_, Data16, { 0, 0, 0} },
cd22144a 454/* i386sl, i486sl, later 486, and Pentium */
9d3a718c 455{"rsm", 0, 0x0faa, Z_, 0,{ 0, 0, 0} },
ce868e5c 456
9d3a718c
TT		 457{"boundl", 2, 0x62, Z_, Modrm|Data32, { Reg32, Mem, 0} },
458{"boundw", 2, 0x62, Z_, Modrm|Data16, { Reg16, Mem, 0} },
ce868e5c 459
9d3a718c
TT		 460{"hlt", 0, 0xf4, Z_, 0, { 0, 0, 0} },
461{"wait", 0, 0x9b, Z_, 0, { 0, 0, 0} },
ce868e5c 462/* nop is actually 'xchgl %eax, %eax' */
9d3a718c 463{"nop", 0, 0x90, Z_, 0, { 0, 0, 0} },
ce868e5c
JG		 464
465/* protection control */
9d3a718c
TT		 466{"arpl", 2, 0x63, Z_, Modrm, { Reg16, Reg16|Mem, 0} },
467{"lar", 2, 0x0f02, Z_, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
ffd42166
ILT		 468{"lgdt", 1, 0x0f01, 2, Modrm, { Mem, 0, 0} },
469{"lidt", 1, 0x0f01, 3, Modrm, { Mem, 0, 0} },
fc0d7441
ILT		 470{"lldt", 1, 0x0f00, 2, Modrm, { WordReg|Mem, 0, 0} },
471{"lmsw", 1, 0x0f01, 6, Modrm, { WordReg|Mem, 0, 0} },
9d3a718c 472{"lsl", 2, 0x0f03, Z_, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
fc0d7441
ILT		 473{"ltr", 1, 0x0f00, 3, Modrm, { WordReg|Mem, 0, 0} },
474
475{"sgdt", 1, 0x0f01, 0, Modrm, { Mem, 0, 0} },
476{"sidt", 1, 0x0f01, 1, Modrm, { Mem, 0, 0} },
477{"sldt", 1, 0x0f00, 0, Modrm, { WordReg|Mem, 0, 0} },
478{"smsw", 1, 0x0f01, 4, Modrm, { WordReg|Mem, 0, 0} },
479{"str", 1, 0x0f00, 1, Modrm, { Reg16|Mem, 0, 0} },
480
481{"verr", 1, 0x0f00, 4, Modrm, { WordReg|Mem, 0, 0} },
482{"verw", 1, 0x0f00, 5, Modrm, { WordReg|Mem, 0, 0} },
ce868e5c
JG		 483
484/* floating point instructions */
485
486/* load */
9d3a718c 487{"fld", 1, 0xd9c0, Z_, ShortForm, { FloatReg, 0, 0} }, /* register */
fc0d7441
ILT		 488{"flds", 1, 0xd9, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem float */
489{"fldl", 1, 0xdd, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem double */
9d3a718c 490{"fldl", 1, 0xd9c0, Z_, ShortForm, { FloatReg, 0, 0} }, /* register */
fc0d7441
ILT		 491{"fild", 1, 0xdf, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem word (16) */
492{"fildl", 1, 0xdb, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem dword (32) */
493{"fildq",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */
494{"fildll",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */
495{"fldt", 1, 0xdb, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem efloat */
496{"fbld", 1, 0xdf, 4, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem bcd */
ce868e5c
JG		 497
498/* store (no pop) */
9d3a718c 499{"fst", 1, 0xddd0, Z_, ShortForm, { FloatReg, 0, 0} }, /* register */
fc0d7441
ILT		 500{"fsts", 1, 0xd9, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */
501{"fstl", 1, 0xdd, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */
9d3a718c 502{"fstl", 1, 0xddd0, Z_, ShortForm, { FloatReg, 0, 0} }, /* register */
fc0d7441
ILT		 503{"fist", 1, 0xdf, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */
504{"fistl", 1, 0xdb, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */
ce868e5c
JG		 505
506/* store (with pop) */
9d3a718c 507{"fstp", 1, 0xddd8, Z_, ShortForm, { FloatReg, 0, 0} }, /* register */
fc0d7441
ILT		 508{"fstps", 1, 0xd9, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */
509{"fstpl", 1, 0xdd, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */
9d3a718c 510{"fstpl", 1, 0xddd8, Z_, ShortForm, { FloatReg, 0, 0} }, /* register */
fc0d7441
ILT		 511{"fistp", 1, 0xdf, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */
512{"fistpl",1, 0xdb, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */
513{"fistpq",1, 0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */
514{"fistpll",1,0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */
515{"fstpt", 1, 0xdb, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem efloat */
516{"fbstp", 1, 0xdf, 6, Modrm, { Mem, 0, 0} }, /* %st0 --> mem bcd */
ce868e5c
JG		 517
518/* exchange %st<n> with %st0 */
9d3a718c
TT		 519{"fxch", 1, 0xd9c8, Z_, ShortForm, { FloatReg, 0, 0} },
520{"fxch", 0, 0xd9c9, Z_, 0, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */
ce868e5c
JG		 521
522/* comparison (without pop) */
9d3a718c 523{"fcom", 1, 0xd8d0, Z_, ShortForm, { FloatReg, 0, 0} },
fc0d7441 524{"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */
9df6ca2f 525{"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */
fc0d7441 526{"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */
9d3a718c 527{"fcoml", 1, 0xd8d0, Z_, ShortForm, { FloatReg, 0, 0} },
9df6ca2f 528{"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */
ce868e5c
JG		 529
530/* comparison (with pop) */
9d3a718c
TT		 531{"fcomp", 1, 0xd8d8, Z_, ShortForm, { FloatReg, 0, 0} },
532{"fcomp", 0, 0xd8d9, Z_, 0, {0, 0, 0} }, /* fcomp %st, %st(1) */
fc0d7441 533{"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */
9df6ca2f 534{"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */
fc0d7441 535{"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */
9d3a718c 536{"fcompl", 1, 0xd8d8, Z_, ShortForm, { FloatReg, 0, 0} },
9df6ca2f 537{"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */
9d3a718c 538{"fcompp", 0, 0xded9, Z_, 0, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */
ce868e5c
JG		 539
540/* unordered comparison (with pop) */
9d3a718c
TT		 541{"fucom", 1, 0xdde0, Z_, ShortForm, { FloatReg, 0, 0} },
542{"fucomp", 1, 0xdde8, Z_, ShortForm, { FloatReg, 0, 0} },
543{"fucompp", 0, 0xdae9, Z_, 0, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
ce868e5c 544
9d3a718c
TT		 545{"ftst", 0, 0xd9e4, Z_, 0, { 0, 0, 0} }, /* test %st0 */
546{"fxam", 0, 0xd9e5, Z_, 0, { 0, 0, 0} }, /* examine %st0 */
ce868e5c
JG		 547
548/* load constants into %st0 */
9d3a718c
TT		 549{"fld1", 0, 0xd9e8, Z_, 0, { 0, 0, 0} }, /* %st0 <-- 1.0 */
550{"fldl2t", 0, 0xd9e9, Z_, 0, { 0, 0, 0} }, /* %st0 <-- log2(10) */
551{"fldl2e", 0, 0xd9ea, Z_, 0, { 0, 0, 0} }, /* %st0 <-- log2(e) */
552{"fldpi", 0, 0xd9eb, Z_, 0, { 0, 0, 0} }, /* %st0 <-- pi */
553{"fldlg2", 0, 0xd9ec, Z_, 0, { 0, 0, 0} }, /* %st0 <-- log10(2) */
554{"fldln2", 0, 0xd9ed, Z_, 0, { 0, 0, 0} }, /* %st0 <-- ln(2) */
555{"fldz", 0, 0xd9ee, Z_, 0, { 0, 0, 0} }, /* %st0 <-- 0.0 */
ce868e5c
JG		 556
557/* arithmetic */
558
559/* add */
9d3a718c
TT		 560{"fadd", 1, 0xd8c0, Z_, ShortForm, { FloatReg, 0, 0} },
561{"fadd", 2, 0xd8c0, Z_, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
562{"fadd", 0, 0xdcc1, Z_, 0, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */
563{"faddp", 1, 0xdec0, Z_, ShortForm, { FloatReg, 0, 0} },
564{"faddp", 2, 0xdec0, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
565{"faddp", 2, 0xdec0, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
566{"faddp", 0, 0xdec1, Z_, 0, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
fc0d7441
ILT		 567{"fadds", 1, 0xd8, 0, Modrm, { Mem, 0, 0} },
568{"fiaddl", 1, 0xda, 0, Modrm, { Mem, 0, 0} },
569{"faddl", 1, 0xdc, 0, Modrm, { Mem, 0, 0} },
570{"fiadds", 1, 0xde, 0, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 571
572/* sub */
573/* Note: intel has decided that certain of these operations are reversed
574 in assembler syntax. */
9d3a718c
TT		 575{"fsub", 1, 0xd8e0, Z_, ShortForm, { FloatReg, 0, 0} },
576{"fsub", 2, 0xd8e0, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 577#ifdef NON_BROKEN_OPCODES
9d3a718c 578{"fsub", 2, 0xdce8, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 579#else
9d3a718c 580{"fsub", 2, 0xdce0, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 581#endif
9d3a718c
TT		 582{"fsub", 0, 0xdce1, Z_, 0, { 0, 0, 0} },
583{"fsubp", 1, 0xdee8, Z_, ShortForm, { FloatReg, 0, 0} },
584{"fsubp", 2, 0xdee8, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 585#ifdef NON_BROKEN_OPCODES
9d3a718c
TT		 586{"fsubp", 2, 0xdee8, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
587{"fsubp", 0, 0xdee9, Z_, 0, { 0, 0, 0} },
ce868e5c 588#else
9d3a718c
TT		 589{"fsubp", 2, 0xdee0, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
590{"fsubp", 0, 0xdee1, Z_, 0, { 0, 0, 0} },
ce868e5c 591#endif
fc0d7441
ILT		 592{"fsubs", 1, 0xd8, 4, Modrm, { Mem, 0, 0} },
593{"fisubl", 1, 0xda, 4, Modrm, { Mem, 0, 0} },
594{"fsubl", 1, 0xdc, 4, Modrm, { Mem, 0, 0} },
595{"fisubs", 1, 0xde, 4, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 596
597/* sub reverse */
9d3a718c
TT		 598{"fsubr", 1, 0xd8e8, Z_, ShortForm, { FloatReg, 0, 0} },
599{"fsubr", 2, 0xd8e8, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 600#ifdef NON_BROKEN_OPCODES
9d3a718c 601{"fsubr", 2, 0xdce0, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 602#else
9d3a718c 603{"fsubr", 2, 0xdce8, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 604#endif
9d3a718c
TT		 605{"fsubr", 0, 0xdce9, Z_, 0, { 0, 0, 0} },
606{"fsubrp", 1, 0xdee0, Z_, ShortForm, { FloatReg, 0, 0} },
607{"fsubrp", 2, 0xdee0, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 608#ifdef NON_BROKEN_OPCODES
9d3a718c
TT		 609{"fsubrp", 2, 0xdee0, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
610{"fsubrp", 0, 0xdee1, Z_, 0, { 0, 0, 0} },
ce868e5c 611#else
9d3a718c
TT		 612{"fsubrp", 2, 0xdee8, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
613{"fsubrp", 0, 0xdee9, Z_, 0, { 0, 0, 0} },
ce868e5c 614#endif
fc0d7441
ILT		 615{"fsubrs", 1, 0xd8, 5, Modrm, { Mem, 0, 0} },
616{"fisubrl", 1, 0xda, 5, Modrm, { Mem, 0, 0} },
617{"fsubrl", 1, 0xdc, 5, Modrm, { Mem, 0, 0} },
618{"fisubrs", 1, 0xde, 5, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 619
620/* mul */
9d3a718c
TT		 621{"fmul", 1, 0xd8c8, Z_, ShortForm, { FloatReg, 0, 0} },
622{"fmul", 2, 0xd8c8, Z_, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
623{"fmul", 0, 0xdcc9, Z_, 0, { 0, 0, 0} },
624{"fmulp", 1, 0xdec8, Z_, ShortForm, { FloatReg, 0, 0} },
625{"fmulp", 2, 0xdec8, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
626{"fmulp", 2, 0xdec8, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
627{"fmulp", 0, 0xdec9, Z_, 0, { 0, 0, 0} },
fc0d7441
ILT		 628{"fmuls", 1, 0xd8, 1, Modrm, { Mem, 0, 0} },
629{"fimull", 1, 0xda, 1, Modrm, { Mem, 0, 0} },
630{"fmull", 1, 0xdc, 1, Modrm, { Mem, 0, 0} },
631{"fimuls", 1, 0xde, 1, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 632
633/* div */
634/* Note: intel has decided that certain of these operations are reversed
635 in assembler syntax. */
9d3a718c
TT		 636{"fdiv", 1, 0xd8f0, Z_, ShortForm, { FloatReg, 0, 0} },
637{"fdiv", 2, 0xd8f0, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 638#ifdef NON_BROKEN_OPCODES
9d3a718c 639{"fdiv", 2, 0xdcf8, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 640#else
9d3a718c 641{"fdiv", 2, 0xdcf0, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 642#endif
9d3a718c
TT		 643{"fdiv", 0, 0xdcf1, Z_, 0, { 0, 0, 0} },
644{"fdivp", 1, 0xdef8, Z_, ShortForm, { FloatReg, 0, 0} },
645{"fdivp", 2, 0xdef8, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 646#ifdef NON_BROKEN_OPCODES
9d3a718c
TT		 647{"fdivp", 2, 0xdef8, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
648{"fdivp", 0, 0xdef9, Z_, 0, { 0, 0, 0} },
ce868e5c 649#else
9d3a718c
TT		 650{"fdivp", 2, 0xdef0, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
651{"fdivp", 0, 0xdef1, Z_, 0, { 0, 0, 0} },
ce868e5c 652#endif
fc0d7441
ILT		 653{"fdivs", 1, 0xd8, 6, Modrm, { Mem, 0, 0} },
654{"fidivl", 1, 0xda, 6, Modrm, { Mem, 0, 0} },
655{"fdivl", 1, 0xdc, 6, Modrm, { Mem, 0, 0} },
656{"fidivs", 1, 0xde, 6, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 657
658/* div reverse */
9d3a718c
TT		 659{"fdivr", 1, 0xd8f8, Z_, ShortForm, { FloatReg, 0, 0} },
660{"fdivr", 2, 0xd8f8, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 661#ifdef NON_BROKEN_OPCODES
9d3a718c 662{"fdivr", 2, 0xdcf0, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 663#else
9d3a718c 664{"fdivr", 2, 0xdcf8, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 665#endif
9d3a718c
TT		 666{"fdivr", 0, 0xdcf9, Z_, 0, { 0, 0, 0} },
667{"fdivrp", 1, 0xdef0, Z_, ShortForm, { FloatReg, 0, 0} },
668{"fdivrp", 2, 0xdef0, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 669#ifdef NON_BROKEN_OPCODES
9d3a718c
TT		 670{"fdivrp", 2, 0xdef0, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
671{"fdivrp", 0, 0xdef1, Z_, 0, { 0, 0, 0} },
ce868e5c 672#else
9d3a718c
TT		 673{"fdivrp", 2, 0xdef8, Z_, ShortForm, { FloatAcc, FloatReg, 0} },
674{"fdivrp", 0, 0xdef9, Z_, 0, { 0, 0, 0} },
ce868e5c 675#endif
fc0d7441
ILT		 676{"fdivrs", 1, 0xd8, 7, Modrm, { Mem, 0, 0} },
677{"fidivrl", 1, 0xda, 7, Modrm, { Mem, 0, 0} },
678{"fdivrl", 1, 0xdc, 7, Modrm, { Mem, 0, 0} },
679{"fidivrs", 1, 0xde, 7, Modrm, { Mem, 0, 0} },
680
9d3a718c
TT		 681{"f2xm1", 0, 0xd9f0, Z_, 0, { 0, 0, 0} },
682{"fyl2x", 0, 0xd9f1, Z_, 0, { 0, 0, 0} },
683{"fptan", 0, 0xd9f2, Z_, 0, { 0, 0, 0} },
684{"fpatan", 0, 0xd9f3, Z_, 0, { 0, 0, 0} },
685{"fxtract", 0, 0xd9f4, Z_, 0, { 0, 0, 0} },
686{"fprem1", 0, 0xd9f5, Z_, 0, { 0, 0, 0} },
687{"fdecstp", 0, 0xd9f6, Z_, 0, { 0, 0, 0} },
688{"fincstp", 0, 0xd9f7, Z_, 0, { 0, 0, 0} },
689{"fprem", 0, 0xd9f8, Z_, 0, { 0, 0, 0} },
690{"fyl2xp1", 0, 0xd9f9, Z_, 0, { 0, 0, 0} },
691{"fsqrt", 0, 0xd9fa, Z_, 0, { 0, 0, 0} },
692{"fsincos", 0, 0xd9fb, Z_, 0, { 0, 0, 0} },
693{"frndint", 0, 0xd9fc, Z_, 0, { 0, 0, 0} },
694{"fscale", 0, 0xd9fd, Z_, 0, { 0, 0, 0} },
695{"fsin", 0, 0xd9fe, Z_, 0, { 0, 0, 0} },
696{"fcos", 0, 0xd9ff, Z_, 0, { 0, 0, 0} },
697
698{"fchs", 0, 0xd9e0, Z_, 0, { 0, 0, 0} },
699{"fabs", 0, 0xd9e1, Z_, 0, { 0, 0, 0} },
ce868e5c
JG		 700
701/* processor control */
9d3a718c
TT		 702{"fninit", 0, 0xdbe3, Z_, 0, { 0, 0, 0} },
703{"finit", 0, 0xdbe3, Z_, FWait, { 0, 0, 0} },
ffd42166
ILT		 704{"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} },
705{"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} },
706{"fstcw", 1, 0xd9, 7, FWait|Modrm, { Mem, 0, 0} },
9d3a718c 707{"fnstsw", 1, 0xdfe0, Z_, 0, { Acc, 0, 0} },
ffd42166 708{"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} },
9d3a718c
TT		 709{"fnstsw", 0, 0xdfe0, Z_, 0, { 0, 0, 0} },
710{"fstsw", 1, 0xdfe0, Z_, FWait, { Acc, 0, 0} },
ffd42166 711{"fstsw", 1, 0xdd, 7, FWait|Modrm, { Mem, 0, 0} },
9d3a718c
TT		 712{"fstsw", 0, 0xdfe0, Z_, FWait, { 0, 0, 0} },
713{"fnclex", 0, 0xdbe2, Z_, 0, { 0, 0, 0} },
714{"fclex", 0, 0xdbe2, Z_, FWait, { 0, 0, 0} },
ffd42166
ILT		 715{"fnstenv",1, 0xd9, 6, Modrm, { Mem, 0, 0} },
716{"fstenv", 1, 0xd9, 6, FWait|Modrm, { Mem, 0, 0} },
717{"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} },
718{"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} },
719{"fsave", 1, 0xdd, 6, FWait|Modrm, { Mem, 0, 0} },
720{"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} },
721/* Short forms of fldenv, fstenv use data size prefix. (At least I
722 think so. The PentPro prog ref I have says address size in one
723 place, operand size elsewhere). FIXME: Are these the right names? */
724{"fnstenvs",1, 0xd9, 6, Modrm|Data16, { Mem, 0, 0} },
725{"fstenvs", 1, 0xd9, 6, FWait|Modrm|Data16, { Mem, 0, 0} },
726{"fldenvs", 1, 0xd9, 4, Modrm|Data16, { Mem, 0, 0} },
727
9d3a718c 728{"ffree", 1, 0xddc0, Z_, ShortForm, { FloatReg, 0, 0} },
527cabaf 729/* P6:free st(i), pop st */
9d3a718c
TT		 730{"ffreep", 1, 0xdfc0, Z_, ShortForm, { FloatReg, 0, 0} },
731{"fnop", 0, 0xd9d0, Z_, 0, { 0, 0, 0} },
ffd42166 732#define FWAIT_OPCODE 0x9b
9d3a718c 733{"fwait", 0, 0x9b, Z_, 0, { 0, 0, 0} },
ce868e5c
JG		 734
735/*
736 opcode prefixes; we allow them as seperate insns too
737 (see prefix table below)
738*/
9d3a718c
TT		 739{"aword", 0, 0x67, Z_, 0, { 0, 0, 0} },
740{"addr16", 0, 0x67, Z_, 0, { 0, 0, 0} },
741{"word", 0, 0x66, Z_, 0, { 0, 0, 0} },
742{"data16", 0, 0x66, Z_, 0, { 0, 0, 0} },
743{"lock", 0, 0xf0, Z_, 0, { 0, 0, 0} },
744{"cs", 0, 0x2e, Z_, 0, { 0, 0, 0} },
745{"ds", 0, 0x3e, Z_, 0, { 0, 0, 0} },
746{"es", 0, 0x26, Z_, 0, { 0, 0, 0} },
747{"fs", 0, 0x64, Z_, 0, { 0, 0, 0} },
748{"gs", 0, 0x65, Z_, 0, { 0, 0, 0} },
749{"ss", 0, 0x36, Z_, 0, { 0, 0, 0} },
750{"rep", 0, 0xf3, Z_, 0, { 0, 0, 0} },
751{"repe", 0, 0xf3, Z_, 0, { 0, 0, 0} },
752{"repz", 0, 0xf3, Z_, 0, { 0, 0, 0} },
753{"repne", 0, 0xf2, Z_, 0, { 0, 0, 0} },
754{"repnz", 0, 0xf2, Z_, 0, { 0, 0, 0} },
fc0d7441
ILT		 755
756/* 486 extensions */
757
9d3a718c
TT		 758{"bswap", 1, 0x0fc8, Z_, ShortForm, { Reg32,0,0 } },
759{"xadd", 2, 0x0fc0, Z_, W|Modrm, { Reg, Reg|Mem, 0 } },
760{"cmpxchg", 2, 0x0fb0, Z_, W|Modrm, { Reg, Reg|Mem, 0 } },
761{"invd", 0, 0x0f08, Z_, 0, { 0, 0, 0} },
762{"wbinvd", 0, 0x0f09, Z_, 0, { 0, 0, 0} },
fc0d7441
ILT		 763{"invlpg", 1, 0x0f01, 7, Modrm, { Mem, 0, 0} },
764
cd22144a 765/* 586 and late 486 extensions */
9d3a718c 766{"cpuid", 0, 0x0fa2, Z_, 0, { 0, 0, 0} },
cd22144a
KR		 767
768/* Pentium extensions */
9d3a718c
TT		 769{"wrmsr", 0, 0x0f30, Z_, 0, { 0, 0, 0} },
770{"rdtsc", 0, 0x0f31, Z_, 0, { 0, 0, 0} },
771{"rdmsr", 0, 0x0f32, Z_, 0, { 0, 0, 0} },
527cabaf
ILT		 772{"cmpxchg8b", 1, 0x0fc7, 1, Modrm, { Mem, 0, 0} },
773
774/* Pentium Pro extensions */
9d3a718c
TT		 775{"rdpmc", 0, 0x0f33, Z_, 0, { 0, 0, 0} },
776
777{"ud2", 0, 0x0f0b, Z_, 0, {0, 0, 0} }, /* official undefined instr. */
778
779{"cmovo", 2, 0x0f40, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
780{"cmovno", 2, 0x0f41, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
781{"cmovb", 2, 0x0f42, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
782{"cmovae", 2, 0x0f43, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
783{"cmove", 2, 0x0f44, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
784{"cmovne", 2, 0x0f45, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
785{"cmovbe", 2, 0x0f46, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
786{"cmova", 2, 0x0f47, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
787{"cmovs", 2, 0x0f48, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
788{"cmovns", 2, 0x0f49, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
789{"cmovp", 2, 0x0f4a, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
790{"cmovnp", 2, 0x0f4b, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
791{"cmovl", 2, 0x0f4c, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
792{"cmovge", 2, 0x0f4d, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
793{"cmovle", 2, 0x0f4e, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
794{"cmovg", 2, 0x0f4f, Z_, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
795
796{"fcmovb", 2, 0xdac0, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
797{"fcmove", 2, 0xdac8, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
798{"fcmovbe",2, 0xdad0, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
799{"fcmovu", 2, 0xdad8, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
800{"fcmovnb", 2, 0xdbc0, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
801{"fcmovne", 2, 0xdbc8, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
802{"fcmovnbe",2, 0xdbd0, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
803{"fcmovnu", 2, 0xdbd8, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
804
805{"fcomi", 2, 0xdbf0, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
806{"fucomi", 2, 0xdbe8, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
807{"fcomip", 2, 0xdff0, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
808{"fucomip",2, 0xdfe8, Z_, ShortForm, { FloatReg, FloatAcc, 0} },
cd22144a 809
3abaf930
ILT		 810/* MMX instructions. */
811
9d3a718c
TT		 812{"emms", 0, 0x0f77, Z_, 0, { 0, 0, 0 } },
813{"movd", 2, 0x0f6e, Z_, Modrm, { Reg32|WordMem, RegMMX, 0 } },
814{"movd", 2, 0x0f7e, Z_, Modrm, { RegMMX, Reg32|WordMem, 0 } },
815{"movq", 2, 0x0f6f, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
816{"movq", 2, 0x0f7f, Z_, Modrm, { RegMMX, RegMMX|WordMem, 0 } },
817{"packssdw", 2, 0x0f6b, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
818{"packsswb", 2, 0x0f63, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
819{"packuswb", 2, 0x0f67, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
820{"paddb", 2, 0x0ffc, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
821{"paddw", 2, 0x0ffd, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
822{"paddd", 2, 0x0ffe, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
823{"paddsb", 2, 0x0fec, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
824{"paddsw", 2, 0x0fed, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
825{"paddusb", 2, 0x0fdc, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
826{"paddusw", 2, 0x0fdd, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
827{"pand", 2, 0x0fdb, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
828{"pandn", 2, 0x0fdf, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
829{"pcmpeqb", 2, 0x0f74, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
830{"pcmpeqw", 2, 0x0f75, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
831{"pcmpeqd", 2, 0x0f76, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
832{"pcmpgtb", 2, 0x0f64, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
833{"pcmpgtw", 2, 0x0f65, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
834{"pcmpgtd", 2, 0x0f66, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
835{"pmaddwd", 2, 0x0ff5, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
836{"pmulhw", 2, 0x0fe5, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
837{"pmullw", 2, 0x0fd5, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
838{"por", 2, 0x0feb, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
839{"psllw", 2, 0x0ff1, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 840{"psllw", 2, 0x0f71, 6, Modrm, { Imm8, RegMMX, 0 } },
9d3a718c 841{"pslld", 2, 0x0ff2, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 842{"pslld", 2, 0x0f72, 6, Modrm, { Imm8, RegMMX, 0 } },
9d3a718c 843{"psllq", 2, 0x0ff3, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 844{"psllq", 2, 0x0f73, 6, Modrm, { Imm8, RegMMX, 0 } },
9d3a718c 845{"psraw", 2, 0x0fe1, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 846{"psraw", 2, 0x0f71, 4, Modrm, { Imm8, RegMMX, 0 } },
9d3a718c 847{"psrad", 2, 0x0fe2, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 848{"psrad", 2, 0x0f72, 4, Modrm, { Imm8, RegMMX, 0 } },
9d3a718c 849{"psrlw", 2, 0x0fd1, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 850{"psrlw", 2, 0x0f71, 2, Modrm, { Imm8, RegMMX, 0 } },
9d3a718c 851{"psrld", 2, 0x0fd2, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 852{"psrld", 2, 0x0f72, 2, Modrm, { Imm8, RegMMX, 0 } },
9d3a718c 853{"psrlq", 2, 0x0fd3, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 854{"psrlq", 2, 0x0f73, 2, Modrm, { Imm8, RegMMX, 0 } },
9d3a718c
TT		 855{"psubb", 2, 0x0ff8, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
856{"psubw", 2, 0x0ff9, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
857{"psubd", 2, 0x0ffa, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
858{"psubsb", 2, 0x0fe8, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
859{"psubsw", 2, 0x0fe9, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
860{"psubusb", 2, 0x0fd8, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
861{"psubusw", 2, 0x0fd9, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
862{"punpckhbw", 2, 0x0f68, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
863{"punpckhwd", 2, 0x0f69, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
864{"punpckhdq", 2, 0x0f6a, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
865{"punpcklbw", 2, 0x0f60, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
866{"punpcklwd", 2, 0x0f61, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
867{"punpckldq", 2, 0x0f62, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
868{"pxor", 2, 0x0fef, Z_, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
3abaf930 869
a43022bd 870{"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
ce868e5c 871};
9d3a718c 872#undef Z_
ce868e5c 873
fc0d7441 874static const template *const i386_optab_end
ce868e5c
JG		 875 = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]);
876
877/* 386 register table */
878
879static const reg_entry i386_regtab[] = {
880 /* 8 bit regs */
881 {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2},
882 {"bl", Reg8, 3},
883 {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7},
884 /* 16 bit regs */
885 {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3},
886 {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7},
887 /* 32 bit regs */
888 {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3},
889 {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7},
890 /* segment registers */
891 {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2},
892 {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5},
893 /* control registers */
894 {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3},
cd22144a 895 {"cr4", Control, 4},
ce868e5c
JG		 896 /* debug registers */
897 {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2},
898 {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7},
cd22144a
KR		 899 {"dr0", Debug, 0}, {"dr1", Debug, 1}, {"dr2", Debug, 2},
900 {"dr3", Debug, 3}, {"dr6", Debug, 6}, {"dr7", Debug, 7},
ce868e5c 901 /* test registers */
527cabaf 902 {"tr3", Test, 3}, {"tr4", Test, 4}, {"tr5", Test, 5},
ce868e5c
JG		 903 {"tr6", Test, 6}, {"tr7", Test, 7},
904 /* float registers */
905 {"st(0)", FloatReg|FloatAcc, 0},
906 {"st", FloatReg|FloatAcc, 0},
c0d7b534
ILT		 907 {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2},
908 {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5},
3abaf930
ILT		 909 {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7},
910 {"mm0", RegMMX, 0}, {"mm1", RegMMX, 1}, {"mm2", RegMMX, 2},
911 {"mm3", RegMMX, 3}, {"mm4", RegMMX, 4}, {"mm5", RegMMX, 5},
912 {"mm6", RegMMX, 6}, {"mm7", RegMMX, 7}
ce868e5c
JG		 913};
914
915#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
916
fc0d7441 917static const reg_entry *const i386_regtab_end
ce868e5c
JG		 918 = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]);
919
920/* segment stuff */
921static const seg_entry cs = { "cs", 0x2e };
922static const seg_entry ds = { "ds", 0x3e };
923static const seg_entry ss = { "ss", 0x36 };
924static const seg_entry es = { "es", 0x26 };
925static const seg_entry fs = { "fs", 0x64 };
926static const seg_entry gs = { "gs", 0x65 };
927static const seg_entry null = { "", 0x0 };
928
929/*
930 This table is used to store the default segment register implied by all
931 possible memory addressing modes.
932 It is indexed by the mode & modrm entries of the modrm byte as follows:
933 index = (mode<<3) | modrm;
934*/
fc0d7441 935static const seg_entry *const one_byte_segment_defaults[] = {
ce868e5c
JG		 936 /* mode 0 */
937 &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds,
938 /* mode 1 */
939 &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
940 /* mode 2 */
941 &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
942 /* mode 3 --- not a memory reference; never referenced */
943};
944
fc0d7441 945static const seg_entry *const two_byte_segment_defaults[] = {
ce868e5c
JG		 946 /* mode 0 */
947 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
948 /* mode 1 */
eff2a090 949 &ds, &ds, &ds, &ds, &ss, &ss, &ds, &ds,
ce868e5c 950 /* mode 2 */
eff2a090 951 &ds, &ds, &ds, &ds, &ss, &ss, &ds, &ds,
ce868e5c
JG		 952 /* mode 3 --- not a memory reference; never referenced */
953};
954
955static const prefix_entry i386_prefixtab[] = {
a43022bd 956#define ADDR_PREFIX_OPCODE 0x67
ce868e5c
JG		 957 { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
958 * (How is this useful?) */
959#define WORD_PREFIX_OPCODE 0x66
960 { "data16", 0x66 }, /* operand size prefix */
ffabaa53 961#define LOCK_PREFIX_OPCODE 0xf0
ce868e5c 962 { "lock", 0xf0 }, /* bus lock prefix */
ffabaa53
ILT		 963 { "wait", 0x9b }, /* wait for coprocessor, not really a prefix */
964#define CS_PREFIX_OPCODE 0x2e
965 { "cs", 0x2e }, /* segment overrides ... */
966#define DS_PREFIX_OPCODE 0x3e
967 { "ds", 0x3e },
968#define ES_PREFIX_OPCODE 0x26
969 { "es", 0x26 },
970#define FS_PREFIX_OPCODE 0x64
971 { "fs", 0x64 },
972#define GS_PREFIX_OPCODE 0x65
973 { "gs", 0x65 },
974#define SS_PREFIX_OPCODE 0x36
975 { "ss", 0x36 },
ce868e5c
JG		 976/* REPE & REPNE used to detect rep/repne with a non-string instruction */
977#define REPNE 0xf2
978#define REPE 0xf3
979 { "rep", 0xf3 }, /* repeat string instructions */
980 { "repe", 0xf3 }, { "repz", 0xf3 },
981 { "repne", 0xf2 }, { "repnz", 0xf2 }
982};
983
fc0d7441 984static const prefix_entry *const i386_prefixtab_end
ce868e5c
JG		 985 = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);
986
987/* end of i386-opcode.h */
GDB Binutils - Deliverables
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