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* remote.c: Fix problems realized while showering.
[deliverable/binutils-gdb.git] / include / opcode / i386.h
CommitLineData
ce868e5c 1/* i386-opcode.h -- Intel 80386 opcode table
527cabaf 2 Copyright 1989, 91, 92, 93, 94, 95, 1996 Free Software Foundation.
ce868e5c
JG		 3
4This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
5
6This program is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2 of the License, or
9(at your option) any later version.
10
11This program is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License
17along with this program; if not, write to the Free Software
cd22144a 18Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
ce868e5c
JG		 19
20static const template i386_optab[] = {
21
22#define _ None
23/* move instructions */
a43022bd 24#define MOV_AX_DISP32 0xa0
fc0d7441
ILT		 25{ "mov", 2, 0xa0, _, DW|NoModrm, { Disp32, Acc, 0 } },
26{ "mov", 2, 0x88, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
27{ "mov", 2, 0xb0, _, ShortFormW, { Imm, Reg, 0 } },
28{ "mov", 2, 0xc6, _, W|Modrm, { Imm, Reg|Mem, 0 } },
29{ "mov", 2, 0x8c, _, D|Modrm, { SReg3|SReg2, Reg16|Mem, 0 } },
ce868e5c 30/* move to/from control debug registers */
fc0d7441
ILT		 31{ "mov", 2, 0x0f20, _, D|Modrm, { Control, Reg32, 0} },
32{ "mov", 2, 0x0f21, _, D|Modrm, { Debug, Reg32, 0} },
33{ "mov", 2, 0x0f24, _, D|Modrm, { Test, Reg32, 0} },
ce868e5c
JG		 34
35/* move with sign extend */
36/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
37 conflict with the "movs" string move instruction. Thus,
fc0d7441 38 {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
ce868e5c 39 is not kosher; we must seperate the two instructions. */
a43022bd
KR		 40{"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data32, { Reg8|Mem, Reg32, 0} },
41{"movsbw", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data16, { Reg8|Mem, Reg16, 0} },
fc0d7441 42{"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
ce868e5c
JG		 43
44/* move with zero extend */
fc0d7441
ILT		 45{"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} },
46{"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} },
ce868e5c
JG		 47
48/* push instructions */
fc0d7441
ILT		 49{"push", 1, 0x50, _, ShortForm, { WordReg,0,0 } },
50{"push", 1, 0xff, 0x6, Modrm, { WordReg|WordMem, 0, 0 } },
51{"push", 1, 0x6a, _, NoModrm, { Imm8S, 0, 0} },
a43022bd 52{"push", 1, 0x68, _, NoModrm, { Imm16|Imm32, 0, 0} },
fc0d7441
ILT		 53{"push", 1, 0x06, _, Seg2ShortForm, { SReg2,0,0 } },
54{"push", 1, 0x0fa0, _, Seg3ShortForm, { SReg3,0,0 } },
ce868e5c 55/* push all */
fc0d7441 56{"pusha", 0, 0x60, _, NoModrm, { 0, 0, 0 } },
ce868e5c
JG		 57
58/* pop instructions */
fc0d7441
ILT		 59{"pop", 1, 0x58, _, ShortForm, { WordReg,0,0 } },
60{"pop", 1, 0x8f, 0x0, Modrm, { WordReg|WordMem, 0, 0 } },
ce868e5c 61#define POP_SEG_SHORT 0x7
fc0d7441
ILT		 62{"pop", 1, 0x07, _, Seg2ShortForm, { SReg2,0,0 } },
63{"pop", 1, 0x0fa1, _, Seg3ShortForm, { SReg3,0,0 } },
ce868e5c 64/* pop all */
fc0d7441 65{"popa", 0, 0x61, _, NoModrm, { 0, 0, 0 } },
ce868e5c
JG		 66
67/* xchg exchange instructions
68 xchg commutes: we allow both operand orders */
fc0d7441
ILT		 69{"xchg", 2, 0x90, _, ShortForm, { WordReg, Acc, 0 } },
70{"xchg", 2, 0x90, _, ShortForm, { Acc, WordReg, 0 } },
71{"xchg", 2, 0x86, _, W|Modrm, { Reg, Reg|Mem, 0 } },
72{"xchg", 2, 0x86, _, W|Modrm, { Reg|Mem, Reg, 0 } },
ce868e5c
JG		 73
74/* in/out from ports */
fc0d7441
ILT		 75{"in", 2, 0xe4, _, W|NoModrm, { Imm8, Acc, 0 } },
76{"in", 2, 0xec, _, W|NoModrm, { InOutPortReg, Acc, 0 } },
77{"in", 1, 0xe4, _, W|NoModrm, { Imm8, 0, 0 } },
78{"in", 1, 0xec, _, W|NoModrm, { InOutPortReg, 0, 0 } },
79{"out", 2, 0xe6, _, W|NoModrm, { Acc, Imm8, 0 } },
80{"out", 2, 0xee, _, W|NoModrm, { Acc, InOutPortReg, 0 } },
81{"out", 1, 0xe6, _, W|NoModrm, { Imm8, 0, 0 } },
82{"out", 1, 0xee, _, W|NoModrm, { InOutPortReg, 0, 0 } },
83
ce868e5c 84/* load effective address */
fc0d7441 85{"lea", 2, 0x8d, _, Modrm, { WordMem, WordReg, 0 } },
ce868e5c
JG		 86
87/* load segment registers from memory */
fc0d7441
ILT		 88{"lds", 2, 0xc5, _, Modrm, { Mem, Reg32, 0} },
89{"les", 2, 0xc4, _, Modrm, { Mem, Reg32, 0} },
90{"lfs", 2, 0x0fb4, _, Modrm, { Mem, Reg32, 0} },
91{"lgs", 2, 0x0fb5, _, Modrm, { Mem, Reg32, 0} },
92{"lss", 2, 0x0fb2, _, Modrm, { Mem, Reg32, 0} },
ce868e5c
JG		 93
94/* flags register instructions */
fc0d7441
ILT		 95{"clc", 0, 0xf8, _, NoModrm, { 0, 0, 0} },
96{"cld", 0, 0xfc, _, NoModrm, { 0, 0, 0} },
97{"cli", 0, 0xfa, _, NoModrm, { 0, 0, 0} },
98{"clts", 0, 0x0f06, _, NoModrm, { 0, 0, 0} },
99{"cmc", 0, 0xf5, _, NoModrm, { 0, 0, 0} },
100{"lahf", 0, 0x9f, _, NoModrm, { 0, 0, 0} },
101{"sahf", 0, 0x9e, _, NoModrm, { 0, 0, 0} },
cd22144a
KR		 102{"pushfl", 0, 0x9c, _, NoModrm|Data32, { 0, 0, 0} },
103{"popfl", 0, 0x9d, _, NoModrm|Data32, { 0, 0, 0} },
a43022bd
KR		 104{"pushfw", 0, 0x9c, _, NoModrm|Data16, { 0, 0, 0} },
105{"popfw", 0, 0x9d, _, NoModrm|Data16, { 0, 0, 0} },
527cabaf
ILT		 106{"pushf", 0, 0x9c, _, NoModrm, { 0, 0, 0} },
107{"popf", 0, 0x9d, _, NoModrm, { 0, 0, 0} },
fc0d7441
ILT		 108{"stc", 0, 0xf9, _, NoModrm, { 0, 0, 0} },
109{"std", 0, 0xfd, _, NoModrm, { 0, 0, 0} },
110{"sti", 0, 0xfb, _, NoModrm, { 0, 0, 0} },
111
112{"add", 2, 0x0, _, DW|Modrm, { Reg, Reg|Mem, 0} },
113{"add", 2, 0x83, 0, Modrm, { Imm8S, WordReg|WordMem, 0} },
114{"add", 2, 0x4, _, W|NoModrm, { Imm, Acc, 0} },
115{"add", 2, 0x80, 0, W|Modrm, { Imm, Reg|Mem, 0} },
116
117{"inc", 1, 0x40, _, ShortForm, { WordReg, 0, 0} },
118{"inc", 1, 0xfe, 0, W|Modrm, { Reg|Mem, 0, 0} },
119
120{"sub", 2, 0x28, _, DW|Modrm, { Reg, Reg|Mem, 0} },
121{"sub", 2, 0x83, 5, Modrm, { Imm8S, WordReg|WordMem, 0} },
122{"sub", 2, 0x2c, _, W|NoModrm, { Imm, Acc, 0} },
123{"sub", 2, 0x80, 5, W|Modrm, { Imm, Reg|Mem, 0} },
124
125{"dec", 1, 0x48, _, ShortForm, { WordReg, 0, 0} },
126{"dec", 1, 0xfe, 1, W|Modrm, { Reg|Mem, 0, 0} },
127
128{"sbb", 2, 0x18, _, DW|Modrm, { Reg, Reg|Mem, 0} },
129{"sbb", 2, 0x83, 3, Modrm, { Imm8S, WordReg|WordMem, 0} },
130{"sbb", 2, 0x1c, _, W|NoModrm, { Imm, Acc, 0} },
131{"sbb", 2, 0x80, 3, W|Modrm, { Imm, Reg|Mem, 0} },
132
133{"cmp", 2, 0x38, _, DW|Modrm, { Reg, Reg|Mem, 0} },
134{"cmp", 2, 0x83, 7, Modrm, { Imm8S, WordReg|WordMem, 0} },
135{"cmp", 2, 0x3c, _, W|NoModrm, { Imm, Acc, 0} },
136{"cmp", 2, 0x80, 7, W|Modrm, { Imm, Reg|Mem, 0} },
137
138{"test", 2, 0x84, _, W|Modrm, { Reg|Mem, Reg, 0} },
139{"test", 2, 0x84, _, W|Modrm, { Reg, Reg|Mem, 0} },
140{"test", 2, 0xa8, _, W|NoModrm, { Imm, Acc, 0} },
141{"test", 2, 0xf6, 0, W|Modrm, { Imm, Reg|Mem, 0} },
142
143{"and", 2, 0x20, _, DW|Modrm, { Reg, Reg|Mem, 0} },
144{"and", 2, 0x83, 4, Modrm, { Imm8S, WordReg|WordMem, 0} },
145{"and", 2, 0x24, _, W|NoModrm, { Imm, Acc, 0} },
146{"and", 2, 0x80, 4, W|Modrm, { Imm, Reg|Mem, 0} },
147
148{"or", 2, 0x08, _, DW|Modrm, { Reg, Reg|Mem, 0} },
149{"or", 2, 0x83, 1, Modrm, { Imm8S, WordReg|WordMem, 0} },
150{"or", 2, 0x0c, _, W|NoModrm, { Imm, Acc, 0} },
151{"or", 2, 0x80, 1, W|Modrm, { Imm, Reg|Mem, 0} },
152
153{"xor", 2, 0x30, _, DW|Modrm, { Reg, Reg|Mem, 0} },
154{"xor", 2, 0x83, 6, Modrm, { Imm8S, WordReg|WordMem, 0} },
155{"xor", 2, 0x34, _, W|NoModrm, { Imm, Acc, 0} },
156{"xor", 2, 0x80, 6, W|Modrm, { Imm, Reg|Mem, 0} },
157
158{"adc", 2, 0x10, _, DW|Modrm, { Reg, Reg|Mem, 0} },
159{"adc", 2, 0x83, 2, Modrm, { Imm8S, WordReg|WordMem, 0} },
160{"adc", 2, 0x14, _, W|NoModrm, { Imm, Acc, 0} },
161{"adc", 2, 0x80, 2, W|Modrm, { Imm, Reg|Mem, 0} },
162
163{"neg", 1, 0xf6, 3, W|Modrm, { Reg|Mem, 0, 0} },
164{"not", 1, 0xf6, 2, W|Modrm, { Reg|Mem, 0, 0} },
165
166{"aaa", 0, 0x37, _, NoModrm, { 0, 0, 0} },
167{"aas", 0, 0x3f, _, NoModrm, { 0, 0, 0} },
168{"daa", 0, 0x27, _, NoModrm, { 0, 0, 0} },
169{"das", 0, 0x2f, _, NoModrm, { 0, 0, 0} },
170{"aad", 0, 0xd50a, _, NoModrm, { 0, 0, 0} },
171{"aam", 0, 0xd40a, _, NoModrm, { 0, 0, 0} },
ce868e5c
JG		 172
173/* conversion insns */
174/* conversion: intel naming */
a43022bd
KR		 175{"cbw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} },
176{"cwd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} },
177{"cwde", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} },
178{"cdq", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} },
ce868e5c 179/* att naming */
a43022bd
KR		 180{"cbtw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} },
181{"cwtl", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} },
182{"cwtd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} },
183{"cltd", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} },
ce868e5c
JG		 184
185/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
186 expanding 64-bit multiplies, and *cannot* be selected to accomplish
187 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
a43022bd 188 These multiplies can only be selected with single operand forms. */
fc0d7441
ILT		 189{"mul", 1, 0xf6, 4, W|Modrm, { Reg|Mem, 0, 0} },
190{"imul", 1, 0xf6, 5, W|Modrm, { Reg|Mem, 0, 0} },
ce868e5c
JG		 191
192
193
194
195/* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields.
196 These instructions are exceptions: 'imul $2, %eax, %ecx' would put
197 '%eax' in the reg field and '%ecx' in the regmem field if we did not
198 switch them. */
fc0d7441
ILT		 199{"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
200{"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, { Imm8S, WordReg|Mem, WordReg} },
201{"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, { Imm16|Imm32, WordReg|Mem, WordReg} },
ce868e5c
JG		 202/*
203 imul with 2 operands mimicks imul with 3 by puting register both
204 in i.rm.reg & i.rm.regmem fields
205*/
fc0d7441
ILT		 206{"imul", 2, 0x6b, _, Modrm|imulKludge, { Imm8S, WordReg, 0} },
207{"imul", 2, 0x69, _, Modrm|imulKludge, { Imm16|Imm32, WordReg, 0} },
208{"div", 1, 0xf6, 6, W|Modrm, { Reg|Mem, 0, 0} },
209{"div", 2, 0xf6, 6, W|Modrm, { Reg|Mem, Acc, 0} },
210{"idiv", 1, 0xf6, 7, W|Modrm, { Reg|Mem, 0, 0} },
211{"idiv", 2, 0xf6, 7, W|Modrm, { Reg|Mem, Acc, 0} },
212
213{"rol", 2, 0xd0, 0, W|Modrm, { Imm1, Reg|Mem, 0} },
214{"rol", 2, 0xc0, 0, W|Modrm, { Imm8, Reg|Mem, 0} },
215{"rol", 2, 0xd2, 0, W|Modrm, { ShiftCount, Reg|Mem, 0} },
216{"rol", 1, 0xd0, 0, W|Modrm, { Reg|Mem, 0, 0} },
217
218{"ror", 2, 0xd0, 1, W|Modrm, { Imm1, Reg|Mem, 0} },
219{"ror", 2, 0xc0, 1, W|Modrm, { Imm8, Reg|Mem, 0} },
220{"ror", 2, 0xd2, 1, W|Modrm, { ShiftCount, Reg|Mem, 0} },
221{"ror", 1, 0xd0, 1, W|Modrm, { Reg|Mem, 0, 0} },
222
223{"rcl", 2, 0xd0, 2, W|Modrm, { Imm1, Reg|Mem, 0} },
224{"rcl", 2, 0xc0, 2, W|Modrm, { Imm8, Reg|Mem, 0} },
225{"rcl", 2, 0xd2, 2, W|Modrm, { ShiftCount, Reg|Mem, 0} },
226{"rcl", 1, 0xd0, 2, W|Modrm, { Reg|Mem, 0, 0} },
227
228{"rcr", 2, 0xd0, 3, W|Modrm, { Imm1, Reg|Mem, 0} },
229{"rcr", 2, 0xc0, 3, W|Modrm, { Imm8, Reg|Mem, 0} },
230{"rcr", 2, 0xd2, 3, W|Modrm, { ShiftCount, Reg|Mem, 0} },
231{"rcr", 1, 0xd0, 3, W|Modrm, { Reg|Mem, 0, 0} },
232
233{"sal", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
234{"sal", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
235{"sal", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
236{"sal", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
237{"shl", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} },
238{"shl", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} },
239{"shl", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} },
240{"shl", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} },
241
242{"shld", 3, 0x0fa4, _, Modrm, { Imm8, WordReg, WordReg|Mem} },
243{"shld", 3, 0x0fa5, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
244{"shld", 2, 0x0fa5, _, Modrm, { WordReg, WordReg|Mem, 0} },
245
246{"shr", 2, 0xd0, 5, W|Modrm, { Imm1, Reg|Mem, 0} },
247{"shr", 2, 0xc0, 5, W|Modrm, { Imm8, Reg|Mem, 0} },
248{"shr", 2, 0xd2, 5, W|Modrm, { ShiftCount, Reg|Mem, 0} },
249{"shr", 1, 0xd0, 5, W|Modrm, { Reg|Mem, 0, 0} },
250
251{"shrd", 3, 0x0fac, _, Modrm, { Imm8, WordReg, WordReg|Mem} },
252{"shrd", 3, 0x0fad, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} },
253{"shrd", 2, 0x0fad, _, Modrm, { WordReg, WordReg|Mem, 0} },
254
255{"sar", 2, 0xd0, 7, W|Modrm, { Imm1, Reg|Mem, 0} },
256{"sar", 2, 0xc0, 7, W|Modrm, { Imm8, Reg|Mem, 0} },
257{"sar", 2, 0xd2, 7, W|Modrm, { ShiftCount, Reg|Mem, 0} },
258{"sar", 1, 0xd0, 7, W|Modrm, { Reg|Mem, 0, 0} },
ce868e5c
JG		 259
260/* control transfer instructions */
261#define CALL_PC_RELATIVE 0xe8
fc0d7441 262{"call", 1, 0xe8, _, JumpDword, { Disp32, 0, 0} },
a43022bd
KR		 263{"call", 1, 0xff, 2, Modrm|Data32, { Reg|Mem|JumpAbsolute, 0, 0} },
264{"callw", 1, 0xff, 2, Modrm|Data16, { Reg|Mem|JumpAbsolute, 0, 0} },
ce868e5c 265#define CALL_FAR_IMMEDIATE 0x9a
527cabaf 266{"lcall", 2, 0x9a, _, JumpInterSegment, { Imm16, Imm32, 0} },
a43022bd
KR		 267{"lcall", 1, 0xff, 3, Modrm|Data32, { Mem, 0, 0} },
268{"lcallw", 1, 0xff, 3, Modrm|Data16, { Mem, 0, 0} },
ce868e5c
JG		 269
270#define JUMP_PC_RELATIVE 0xeb
fc0d7441
ILT		 271{"jmp", 1, 0xeb, _, Jump, { Disp, 0, 0} },
272{"jmp", 1, 0xff, 4, Modrm, { Reg32|Mem|JumpAbsolute, 0, 0} },
ce868e5c 273#define JUMP_FAR_IMMEDIATE 0xea
fc0d7441 274{"ljmp", 2, 0xea, _, JumpInterSegment, { Imm16, Imm32, 0} },
a43022bd
KR		 275{"ljmp", 1, 0xff, 5, Modrm|Data32, { Mem, 0, 0} },
276
277{"ret", 0, 0xc3, _, NoModrm|Data32, { 0, 0, 0} },
278{"ret", 1, 0xc2, _, NoModrm|Data32, { Imm16, 0, 0} },
279{"retw", 0, 0xc3, _, NoModrm|Data16, { 0, 0, 0} },
280{"retw", 1, 0xc2, _, NoModrm|Data16, { Imm16, 0, 0} },
281{"lret", 0, 0xcb, _, NoModrm|Data32, { 0, 0, 0} },
282{"lret", 1, 0xca, _, NoModrm|Data32, { Imm16, 0, 0} },
283{"lretw", 0, 0xcb, _, NoModrm|Data16, { 0, 0, 0} },
284{"lretw", 1, 0xca, _, NoModrm|Data16, { Imm16, 0, 0} },
cd22144a
KR		 285{"enter", 2, 0xc8, _, NoModrm|Data32, { Imm16, Imm8, 0} },
286{"leave", 0, 0xc9, _, NoModrm|Data32, { 0, 0, 0} },
287{"enterw", 2, 0xc8, _, NoModrm|Data16, { Imm16, Imm8, 0} },
288{"leavew", 0, 0xc9, _, NoModrm|Data16, { 0, 0, 0} },
ce868e5c
JG		 289
290/* conditional jumps */
fc0d7441 291{"jo", 1, 0x70, _, Jump, { Disp, 0, 0} },
ce868e5c 292
fc0d7441 293{"jno", 1, 0x71, _, Jump, { Disp, 0, 0} },
ce868e5c 294
fc0d7441
ILT		 295{"jb", 1, 0x72, _, Jump, { Disp, 0, 0} },
296{"jc", 1, 0x72, _, Jump, { Disp, 0, 0} },
297{"jnae", 1, 0x72, _, Jump, { Disp, 0, 0} },
ce868e5c 298
fc0d7441
ILT		 299{"jnb", 1, 0x73, _, Jump, { Disp, 0, 0} },
300{"jnc", 1, 0x73, _, Jump, { Disp, 0, 0} },
301{"jae", 1, 0x73, _, Jump, { Disp, 0, 0} },
ce868e5c 302
fc0d7441
ILT		 303{"je", 1, 0x74, _, Jump, { Disp, 0, 0} },
304{"jz", 1, 0x74, _, Jump, { Disp, 0, 0} },
ce868e5c 305
fc0d7441
ILT		 306{"jne", 1, 0x75, _, Jump, { Disp, 0, 0} },
307{"jnz", 1, 0x75, _, Jump, { Disp, 0, 0} },
ce868e5c 308
fc0d7441
ILT		 309{"jbe", 1, 0x76, _, Jump, { Disp, 0, 0} },
310{"jna", 1, 0x76, _, Jump, { Disp, 0, 0} },
ce868e5c 311
fc0d7441
ILT		 312{"jnbe", 1, 0x77, _, Jump, { Disp, 0, 0} },
313{"ja", 1, 0x77, _, Jump, { Disp, 0, 0} },
ce868e5c 314
fc0d7441 315{"js", 1, 0x78, _, Jump, { Disp, 0, 0} },
ce868e5c 316
fc0d7441 317{"jns", 1, 0x79, _, Jump, { Disp, 0, 0} },
ce868e5c 318
fc0d7441
ILT		 319{"jp", 1, 0x7a, _, Jump, { Disp, 0, 0} },
320{"jpe", 1, 0x7a, _, Jump, { Disp, 0, 0} },
ce868e5c 321
fc0d7441
ILT		 322{"jnp", 1, 0x7b, _, Jump, { Disp, 0, 0} },
323{"jpo", 1, 0x7b, _, Jump, { Disp, 0, 0} },
ce868e5c 324
fc0d7441
ILT		 325{"jl", 1, 0x7c, _, Jump, { Disp, 0, 0} },
326{"jnge", 1, 0x7c, _, Jump, { Disp, 0, 0} },
ce868e5c 327
fc0d7441
ILT		 328{"jnl", 1, 0x7d, _, Jump, { Disp, 0, 0} },
329{"jge", 1, 0x7d, _, Jump, { Disp, 0, 0} },
ce868e5c 330
fc0d7441
ILT		 331{"jle", 1, 0x7e, _, Jump, { Disp, 0, 0} },
332{"jng", 1, 0x7e, _, Jump, { Disp, 0, 0} },
ce868e5c 333
fc0d7441
ILT		 334{"jnle", 1, 0x7f, _, Jump, { Disp, 0, 0} },
335{"jg", 1, 0x7f, _, Jump, { Disp, 0, 0} },
ce868e5c 336
a43022bd
KR		 337#if 0 /* XXX where are these macros used?
338 To get them working again, they need to take
339 an entire template as the parameter,
340 and check for Data16/Data32 flags. */
ce868e5c
JG		 341/* these turn into pseudo operations when disp is larger than 8 bits */
342#define IS_JUMP_ON_CX_ZERO(o) \
a43022bd 343 (o == 0x66e3)
ce868e5c
JG		 344#define IS_JUMP_ON_ECX_ZERO(o) \
345 (o == 0xe3)
a43022bd 346#endif
ce868e5c 347
a43022bd
KR		 348{"jcxz", 1, 0xe3, _, JumpByte|Data16, { Disp, 0, 0} },
349{"jecxz", 1, 0xe3, _, JumpByte|Data32, { Disp, 0, 0} },
ce868e5c
JG		 350
351#define IS_LOOP_ECX_TIMES(o) \
352 (o == 0xe2 || o == 0xe1 || o == 0xe0)
353
fc0d7441 354{"loop", 1, 0xe2, _, JumpByte, { Disp, 0, 0} },
ce868e5c 355
fc0d7441
ILT		 356{"loopz", 1, 0xe1, _, JumpByte, { Disp, 0, 0} },
357{"loope", 1, 0xe1, _, JumpByte, { Disp, 0, 0} },
ce868e5c 358
fc0d7441
ILT		 359{"loopnz", 1, 0xe0, _, JumpByte, { Disp, 0, 0} },
360{"loopne", 1, 0xe0, _, JumpByte, { Disp, 0, 0} },
ce868e5c
JG		 361
362/* set byte on flag instructions */
fc0d7441 363{"seto", 1, 0x0f90, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 364
fc0d7441 365{"setno", 1, 0x0f91, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 366
fc0d7441
ILT		 367{"setb", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
368{"setc", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
369{"setnae", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 370
fc0d7441
ILT		 371{"setnb", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
372{"setnc", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
373{"setae", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 374
fc0d7441
ILT		 375{"sete", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
376{"setz", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 377
fc0d7441
ILT		 378{"setne", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
379{"setnz", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 380
fc0d7441
ILT		 381{"setbe", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
382{"setna", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 383
fc0d7441
ILT		 384{"setnbe", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
385{"seta", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 386
fc0d7441 387{"sets", 1, 0x0f98, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 388
fc0d7441 389{"setns", 1, 0x0f99, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 390
fc0d7441
ILT		 391{"setp", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
392{"setpe", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 393
fc0d7441
ILT		 394{"setnp", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
395{"setpo", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 396
fc0d7441
ILT		 397{"setl", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
398{"setnge", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 399
fc0d7441
ILT		 400{"setnl", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
401{"setge", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 402
fc0d7441
ILT		 403{"setle", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
404{"setng", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c 405
fc0d7441
ILT		 406{"setnle", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
407{"setg", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} },
ce868e5c
JG		 408
409#define IS_STRING_INSTRUCTION(o) \
410 ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \
411 (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \
412 (o) == 0xd7)
413
414/* string manipulation */
fc0d7441
ILT		 415{"cmps", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} },
416{"scmp", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} },
417{"ins", 0, 0x6c, _, W|NoModrm, { 0, 0, 0} },
418{"outs", 0, 0x6e, _, W|NoModrm, { 0, 0, 0} },
419{"lods", 0, 0xac, _, W|NoModrm, { 0, 0, 0} },
420{"slod", 0, 0xac, _, W|NoModrm, { 0, 0, 0} },
421{"movs", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} },
422{"smov", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} },
423{"scas", 0, 0xae, _, W|NoModrm, { 0, 0, 0} },
424{"ssca", 0, 0xae, _, W|NoModrm, { 0, 0, 0} },
425{"stos", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} },
426{"ssto", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} },
427{"xlat", 0, 0xd7, _, NoModrm, { 0, 0, 0} },
ce868e5c
JG		 428
429/* bit manipulation */
fc0d7441
ILT		 430{"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
431{"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} },
432{"bt", 2, 0x0fa3, _, Modrm, { Reg, Reg|Mem, 0} },
433{"bt", 2, 0x0fba, 4, Modrm, { Imm8, Reg|Mem, 0} },
434{"btc", 2, 0x0fbb, _, Modrm, { Reg, Reg|Mem, 0} },
435{"btc", 2, 0x0fba, 7, Modrm, { Imm8, Reg|Mem, 0} },
436{"btr", 2, 0x0fb3, _, Modrm, { Reg, Reg|Mem, 0} },
437{"btr", 2, 0x0fba, 6, Modrm, { Imm8, Reg|Mem, 0} },
438{"bts", 2, 0x0fab, _, Modrm, { Reg, Reg|Mem, 0} },
439{"bts", 2, 0x0fba, 5, Modrm, { Imm8, Reg|Mem, 0} },
ce868e5c
JG		 440
441/* interrupts & op. sys insns */
a43022bd
KR		 442/* See gas/config/tc-i386.c for conversion of 'int $3' into the special
443 int 3 insn. */
ce868e5c
JG		 444#define INT_OPCODE 0xcd
445#define INT3_OPCODE 0xcc
fc0d7441
ILT		 446{"int", 1, 0xcd, _, NoModrm, { Imm8, 0, 0} },
447{"int3", 0, 0xcc, _, NoModrm, { 0, 0, 0} },
448{"into", 0, 0xce, _, NoModrm, { 0, 0, 0} },
a43022bd
KR		 449{"iret", 0, 0xcf, _, NoModrm|Data32, { 0, 0, 0} },
450{"iretw", 0, 0xcf, _, NoModrm|Data16, { 0, 0, 0} },
cd22144a 451/* i386sl, i486sl, later 486, and Pentium */
a43022bd 452{"rsm", 0, 0x0faa, _, NoModrm,{ 0, 0, 0} },
ce868e5c 453
a43022bd
KR		 454{"boundl", 2, 0x62, _, Modrm|Data32, { Reg32, Mem, 0} },
455{"boundw", 2, 0x62, _, Modrm|Data16, { Reg16, Mem, 0} },
ce868e5c 456
fc0d7441
ILT		 457{"hlt", 0, 0xf4, _, NoModrm, { 0, 0, 0} },
458{"wait", 0, 0x9b, _, NoModrm, { 0, 0, 0} },
ce868e5c 459/* nop is actually 'xchgl %eax, %eax' */
fc0d7441 460{"nop", 0, 0x90, _, NoModrm, { 0, 0, 0} },
ce868e5c
JG		 461
462/* protection control */
fc0d7441
ILT		 463{"arpl", 2, 0x63, _, Modrm, { Reg16, Reg16|Mem, 0} },
464{"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
465{"lgdt", 1, 0x0f01, 2, Modrm, { Mem, 0, 0} },
466{"lidt", 1, 0x0f01, 3, Modrm, { Mem, 0, 0} },
467{"lldt", 1, 0x0f00, 2, Modrm, { WordReg|Mem, 0, 0} },
468{"lmsw", 1, 0x0f01, 6, Modrm, { WordReg|Mem, 0, 0} },
469{"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} },
470{"ltr", 1, 0x0f00, 3, Modrm, { WordReg|Mem, 0, 0} },
471
472{"sgdt", 1, 0x0f01, 0, Modrm, { Mem, 0, 0} },
473{"sidt", 1, 0x0f01, 1, Modrm, { Mem, 0, 0} },
474{"sldt", 1, 0x0f00, 0, Modrm, { WordReg|Mem, 0, 0} },
475{"smsw", 1, 0x0f01, 4, Modrm, { WordReg|Mem, 0, 0} },
476{"str", 1, 0x0f00, 1, Modrm, { Reg16|Mem, 0, 0} },
477
478{"verr", 1, 0x0f00, 4, Modrm, { WordReg|Mem, 0, 0} },
479{"verw", 1, 0x0f00, 5, Modrm, { WordReg|Mem, 0, 0} },
ce868e5c
JG		 480
481/* floating point instructions */
482
483/* load */
fc0d7441
ILT		 484{"fld", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
485{"flds", 1, 0xd9, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem float */
486{"fldl", 1, 0xdd, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem double */
487{"fldl", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
488{"fild", 1, 0xdf, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem word (16) */
489{"fildl", 1, 0xdb, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem dword (32) */
490{"fildq",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */
491{"fildll",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */
492{"fldt", 1, 0xdb, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem efloat */
493{"fbld", 1, 0xdf, 4, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem bcd */
ce868e5c
JG		 494
495/* store (no pop) */
fc0d7441
ILT		 496{"fst", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
497{"fsts", 1, 0xd9, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */
498{"fstl", 1, 0xdd, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */
499{"fstl", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */
500{"fist", 1, 0xdf, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */
501{"fistl", 1, 0xdb, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */
ce868e5c
JG		 502
503/* store (with pop) */
fc0d7441
ILT		 504{"fstp", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */
505{"fstps", 1, 0xd9, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */
506{"fstpl", 1, 0xdd, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */
507{"fstpl", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */
508{"fistp", 1, 0xdf, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */
509{"fistpl",1, 0xdb, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */
510{"fistpq",1, 0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */
511{"fistpll",1,0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */
512{"fstpt", 1, 0xdb, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem efloat */
513{"fbstp", 1, 0xdf, 6, Modrm, { Mem, 0, 0} }, /* %st0 --> mem bcd */
ce868e5c
JG		 514
515/* exchange %st<n> with %st0 */
fc0d7441 516{"fxch", 1, 0xd9c8, _, ShortForm, { FloatReg, 0, 0} },
a43022bd 517{"fxch", 0, 0xd9c9, _, NoModrm, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */
ce868e5c
JG		 518
519/* comparison (without pop) */
fc0d7441
ILT		 520{"fcom", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} },
521{"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */
522{"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */
523{"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */
524{"fcoml", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} },
525{"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */
ce868e5c
JG		 526
527/* comparison (with pop) */
fc0d7441
ILT		 528{"fcomp", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} },
529{"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */
530{"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */
531{"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */
532{"fcompl", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} },
533{"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */
534{"fcompp", 0, 0xded9, _, NoModrm, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */
ce868e5c
JG		 535
536/* unordered comparison (with pop) */
fc0d7441
ILT		 537{"fucom", 1, 0xdde0, _, ShortForm, { FloatReg, 0, 0} },
538{"fucomp", 1, 0xdde8, _, ShortForm, { FloatReg, 0, 0} },
539{"fucompp", 0, 0xdae9, _, NoModrm, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */
ce868e5c 540
fc0d7441
ILT		 541{"ftst", 0, 0xd9e4, _, NoModrm, { 0, 0, 0} }, /* test %st0 */
542{"fxam", 0, 0xd9e5, _, NoModrm, { 0, 0, 0} }, /* examine %st0 */
ce868e5c
JG		 543
544/* load constants into %st0 */
fc0d7441
ILT		 545{"fld1", 0, 0xd9e8, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 1.0 */
546{"fldl2t", 0, 0xd9e9, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(10) */
547{"fldl2e", 0, 0xd9ea, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(e) */
548{"fldpi", 0, 0xd9eb, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- pi */
549{"fldlg2", 0, 0xd9ec, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log10(2) */
550{"fldln2", 0, 0xd9ed, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- ln(2) */
551{"fldz", 0, 0xd9ee, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 0.0 */
ce868e5c
JG		 552
553/* arithmetic */
554
555/* add */
fc0d7441
ILT		 556{"fadd", 1, 0xd8c0, _, ShortForm, { FloatReg, 0, 0} },
557{"fadd", 2, 0xd8c0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
558{"fadd", 0, 0xdcc1, _, NoModrm, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */
527cabaf
ILT		 559{"faddp", 1, 0xdec0, _, ShortForm, { FloatReg, 0, 0} },
560{"faddp", 2, 0xdec0, _, ShortForm, { FloatReg, FloatAcc, 0} },
561{"faddp", 2, 0xdec0, _, ShortForm, { FloatAcc, FloatReg, 0} },
fc0d7441
ILT		 562{"faddp", 0, 0xdec1, _, NoModrm, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */
563{"fadds", 1, 0xd8, 0, Modrm, { Mem, 0, 0} },
564{"fiaddl", 1, 0xda, 0, Modrm, { Mem, 0, 0} },
565{"faddl", 1, 0xdc, 0, Modrm, { Mem, 0, 0} },
566{"fiadds", 1, 0xde, 0, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 567
568/* sub */
569/* Note: intel has decided that certain of these operations are reversed
570 in assembler syntax. */
fc0d7441
ILT		 571{"fsub", 1, 0xd8e0, _, ShortForm, { FloatReg, 0, 0} },
572{"fsub", 2, 0xd8e0, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 573#ifdef NON_BROKEN_OPCODES
fc0d7441 574{"fsub", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 575#else
fc0d7441 576{"fsub", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 577#endif
fc0d7441 578{"fsub", 0, 0xdce1, _, NoModrm, { 0, 0, 0} },
527cabaf
ILT		 579{"fsubp", 1, 0xdee0, _, ShortForm, { FloatReg, 0, 0} },
580{"fsubp", 2, 0xdee0, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 581#ifdef NON_BROKEN_OPCODES
fc0d7441 582{"fsubp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 583#else
fc0d7441 584{"fsubp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 585#endif
fc0d7441
ILT		 586{"fsubp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} },
587{"fsubs", 1, 0xd8, 4, Modrm, { Mem, 0, 0} },
588{"fisubl", 1, 0xda, 4, Modrm, { Mem, 0, 0} },
589{"fsubl", 1, 0xdc, 4, Modrm, { Mem, 0, 0} },
590{"fisubs", 1, 0xde, 4, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 591
592/* sub reverse */
fc0d7441
ILT		 593{"fsubr", 1, 0xd8e8, _, ShortForm, { FloatReg, 0, 0} },
594{"fsubr", 2, 0xd8e8, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 595#ifdef NON_BROKEN_OPCODES
fc0d7441 596{"fsubr", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 597#else
fc0d7441 598{"fsubr", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 599#endif
fc0d7441 600{"fsubr", 0, 0xdce9, _, NoModrm, { 0, 0, 0} },
527cabaf
ILT		 601{"fsubrp", 1, 0xdee8, _, ShortForm, { FloatReg, 0, 0} },
602{"fsubrp", 2, 0xdee8, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 603#ifdef NON_BROKEN_OPCODES
fc0d7441 604{"fsubrp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 605#else
fc0d7441 606{"fsubrp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 607#endif
fc0d7441
ILT		 608{"fsubrp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} },
609{"fsubrs", 1, 0xd8, 5, Modrm, { Mem, 0, 0} },
610{"fisubrl", 1, 0xda, 5, Modrm, { Mem, 0, 0} },
611{"fsubrl", 1, 0xdc, 5, Modrm, { Mem, 0, 0} },
612{"fisubrs", 1, 0xde, 5, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 613
614/* mul */
fc0d7441
ILT		 615{"fmul", 1, 0xd8c8, _, ShortForm, { FloatReg, 0, 0} },
616{"fmul", 2, 0xd8c8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
617{"fmul", 0, 0xdcc9, _, NoModrm, { 0, 0, 0} },
527cabaf
ILT		 618{"fmulp", 1, 0xdec8, _, ShortForm, { FloatReg, 0, 0} },
619{"fmulp", 2, 0xdec8, _, ShortForm, { FloatReg, FloatAcc, 0} },
620{"fmulp", 2, 0xdec8, _, ShortForm, { FloatAcc, FloatReg, 0} },
fc0d7441
ILT		 621{"fmulp", 0, 0xdec9, _, NoModrm, { 0, 0, 0} },
622{"fmuls", 1, 0xd8, 1, Modrm, { Mem, 0, 0} },
623{"fimull", 1, 0xda, 1, Modrm, { Mem, 0, 0} },
624{"fmull", 1, 0xdc, 1, Modrm, { Mem, 0, 0} },
625{"fimuls", 1, 0xde, 1, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 626
627/* div */
628/* Note: intel has decided that certain of these operations are reversed
629 in assembler syntax. */
fc0d7441
ILT		 630{"fdiv", 1, 0xd8f0, _, ShortForm, { FloatReg, 0, 0} },
631{"fdiv", 2, 0xd8f0, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 632#ifdef NON_BROKEN_OPCODES
fc0d7441 633{"fdiv", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 634#else
fc0d7441 635{"fdiv", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 636#endif
fc0d7441 637{"fdiv", 0, 0xdcf1, _, NoModrm, { 0, 0, 0} },
527cabaf
ILT		 638{"fdivp", 1, 0xdef0, _, ShortForm, { FloatReg, 0, 0} },
639{"fdivp", 2, 0xdef0, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 640#ifdef NON_BROKEN_OPCODES
fc0d7441 641{"fdivp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 642#else
fc0d7441 643{"fdivp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 644#endif
fc0d7441
ILT		 645{"fdivp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} },
646{"fdivs", 1, 0xd8, 6, Modrm, { Mem, 0, 0} },
647{"fidivl", 1, 0xda, 6, Modrm, { Mem, 0, 0} },
648{"fdivl", 1, 0xdc, 6, Modrm, { Mem, 0, 0} },
649{"fidivs", 1, 0xde, 6, Modrm, { Mem, 0, 0} },
ce868e5c
JG		 650
651/* div reverse */
fc0d7441
ILT		 652{"fdivr", 1, 0xd8f8, _, ShortForm, { FloatReg, 0, 0} },
653{"fdivr", 2, 0xd8f8, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 654#ifdef NON_BROKEN_OPCODES
fc0d7441 655{"fdivr", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 656#else
fc0d7441 657{"fdivr", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 658#endif
fc0d7441 659{"fdivr", 0, 0xdcf9, _, NoModrm, { 0, 0, 0} },
527cabaf
ILT		 660{"fdivrp", 1, 0xdef8, _, ShortForm, { FloatReg, 0, 0} },
661{"fdivrp", 2, 0xdef8, _, ShortForm, { FloatReg, FloatAcc, 0} },
ce868e5c 662#ifdef NON_BROKEN_OPCODES
fc0d7441 663{"fdivrp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 664#else
fc0d7441 665{"fdivrp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} },
ce868e5c 666#endif
fc0d7441
ILT		 667{"fdivrp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} },
668{"fdivrs", 1, 0xd8, 7, Modrm, { Mem, 0, 0} },
669{"fidivrl", 1, 0xda, 7, Modrm, { Mem, 0, 0} },
670{"fdivrl", 1, 0xdc, 7, Modrm, { Mem, 0, 0} },
671{"fidivrs", 1, 0xde, 7, Modrm, { Mem, 0, 0} },
672
673{"f2xm1", 0, 0xd9f0, _, NoModrm, { 0, 0, 0} },
674{"fyl2x", 0, 0xd9f1, _, NoModrm, { 0, 0, 0} },
675{"fptan", 0, 0xd9f2, _, NoModrm, { 0, 0, 0} },
676{"fpatan", 0, 0xd9f3, _, NoModrm, { 0, 0, 0} },
677{"fxtract", 0, 0xd9f4, _, NoModrm, { 0, 0, 0} },
678{"fprem1", 0, 0xd9f5, _, NoModrm, { 0, 0, 0} },
679{"fdecstp", 0, 0xd9f6, _, NoModrm, { 0, 0, 0} },
680{"fincstp", 0, 0xd9f7, _, NoModrm, { 0, 0, 0} },
681{"fprem", 0, 0xd9f8, _, NoModrm, { 0, 0, 0} },
682{"fyl2xp1", 0, 0xd9f9, _, NoModrm, { 0, 0, 0} },
683{"fsqrt", 0, 0xd9fa, _, NoModrm, { 0, 0, 0} },
684{"fsincos", 0, 0xd9fb, _, NoModrm, { 0, 0, 0} },
685{"frndint", 0, 0xd9fc, _, NoModrm, { 0, 0, 0} },
686{"fscale", 0, 0xd9fd, _, NoModrm, { 0, 0, 0} },
687{"fsin", 0, 0xd9fe, _, NoModrm, { 0, 0, 0} },
688{"fcos", 0, 0xd9ff, _, NoModrm, { 0, 0, 0} },
689
690{"fchs", 0, 0xd9e0, _, NoModrm, { 0, 0, 0} },
691{"fabs", 0, 0xd9e1, _, NoModrm, { 0, 0, 0} },
ce868e5c
JG		 692
693/* processor control */
fc0d7441 694{"fninit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} },
527cabaf 695{"finit", 0, 0x9bdbe3, _, NoModrm, { 0, 0, 0} },
fc0d7441
ILT		 696{"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} },
697{"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} },
527cabaf 698{"fstcw", 1, 0x9bd9, 7, Modrm, { Mem, 0, 0} },
fc0d7441
ILT		 699{"fnstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} },
700{"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} },
701{"fnstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} },
527cabaf
ILT		 702{"fstsw", 1, 0x9bdfe0, _, NoModrm, { Acc, 0, 0} },
703{"fstsw", 1, 0x9bdd, 7, Modrm, { Mem, 0, 0} },
704{"fstsw", 0, 0x9bdfe0, _, NoModrm, { 0, 0, 0} },
fc0d7441 705{"fnclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} },
527cabaf 706{"fclex", 0, 0x9bdbe2, _, NoModrm, { 0, 0, 0} },
ce868e5c
JG		 707/*
708 We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
709 instructions; i'm not sure how to add them or how they are different.
710 My 386/387 book offers no details about this.
711*/
fc0d7441 712{"fnstenv", 1, 0xd9, 6, Modrm, { Mem, 0, 0} },
527cabaf 713{"fstenv", 1, 0x9bd9, 6, Modrm, { Mem, 0, 0} },
fc0d7441
ILT		 714{"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} },
715{"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} },
527cabaf 716{"fsave", 1, 0x9bdd, 6, Modrm, { Mem, 0, 0} },
fc0d7441 717{"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} },
ce868e5c 718
fc0d7441 719{"ffree", 1, 0xddc0, _, ShortForm, { FloatReg, 0, 0} },
527cabaf
ILT		 720/* P6:free st(i), pop st */
721{"ffreep", 1, 0xdfc0, _, ShortForm, { FloatReg, 0, 0} },
fc0d7441
ILT		 722{"fnop", 0, 0xd9d0, _, NoModrm, { 0, 0, 0} },
723{"fwait", 0, 0x9b, _, NoModrm, { 0, 0, 0} },
ce868e5c
JG		 724
725/*
726 opcode prefixes; we allow them as seperate insns too
727 (see prefix table below)
728*/
fc0d7441
ILT		 729{"aword", 0, 0x67, _, NoModrm, { 0, 0, 0} },
730{"addr16", 0, 0x67, _, NoModrm, { 0, 0, 0} },
731{"word", 0, 0x66, _, NoModrm, { 0, 0, 0} },
732{"data16", 0, 0x66, _, NoModrm, { 0, 0, 0} },
733{"lock", 0, 0xf0, _, NoModrm, { 0, 0, 0} },
734{"cs", 0, 0x2e, _, NoModrm, { 0, 0, 0} },
735{"ds", 0, 0x3e, _, NoModrm, { 0, 0, 0} },
736{"es", 0, 0x26, _, NoModrm, { 0, 0, 0} },
737{"fs", 0, 0x64, _, NoModrm, { 0, 0, 0} },
738{"gs", 0, 0x65, _, NoModrm, { 0, 0, 0} },
739{"ss", 0, 0x36, _, NoModrm, { 0, 0, 0} },
740{"rep", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
741{"repe", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
742{"repz", 0, 0xf3, _, NoModrm, { 0, 0, 0} },
743{"repne", 0, 0xf2, _, NoModrm, { 0, 0, 0} },
744{"repnz", 0, 0xf2, _, NoModrm, { 0, 0, 0} },
745
746/* 486 extensions */
747
748{"bswap", 1, 0x0fc8, _, ShortForm, { Reg32,0,0 } },
527cabaf
ILT		 749{"xadd", 2, 0x0fc0, _, W|Modrm, { Reg, Reg|Mem, 0 } },
750{"cmpxchg", 2, 0x0fb0, _, W|Modrm, { Reg, Reg|Mem, 0 } },
fc0d7441
ILT		 751{"invd", 0, 0x0f08, _, NoModrm, { 0, 0, 0} },
752{"wbinvd", 0, 0x0f09, _, NoModrm, { 0, 0, 0} },
753{"invlpg", 1, 0x0f01, 7, Modrm, { Mem, 0, 0} },
754
cd22144a
KR		 755/* 586 and late 486 extensions */
756{"cpuid", 0, 0x0fa2, _, NoModrm, { 0, 0, 0} },
757
758/* Pentium extensions */
759{"wrmsr", 0, 0x0f30, _, NoModrm, { 0, 0, 0} },
760{"rdtsc", 0, 0x0f31, _, NoModrm, { 0, 0, 0} },
761{"rdmsr", 0, 0x0f32, _, NoModrm, { 0, 0, 0} },
527cabaf
ILT		 762{"cmpxchg8b", 1, 0x0fc7, 1, Modrm, { Mem, 0, 0} },
763
764/* Pentium Pro extensions */
765{"rdpmc", 0, 0x0f33, _, NoModrm, { 0, 0, 0} },
766
767{"cmovo", 2, 0x0f40, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
768{"cmovno", 2, 0x0f41, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
769{"cmovb", 2, 0x0f42, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
770{"cmovae", 2, 0x0f43, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
771{"cmove", 2, 0x0f44, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
772{"cmovne", 2, 0x0f45, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
773{"cmovbe", 2, 0x0f46, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
774{"cmova", 2, 0x0f47, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
775{"cmovs", 2, 0x0f48, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
776{"cmovns", 2, 0x0f49, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
777{"cmovp", 2, 0x0f4a, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
778{"cmovnp", 2, 0x0f4b, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
779{"cmovl", 2, 0x0f4c, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
780{"cmovge", 2, 0x0f4d, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
781{"cmovle", 2, 0x0f4e, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
782{"cmovg", 2, 0x0f4f, _, W|Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
783
784{"fcmovb", 2, 0xdac0, _, ShortForm, { FloatReg, FloatAcc, 0} },
785{"fcmove", 2, 0xdac8, _, ShortForm, { FloatReg, FloatAcc, 0} },
786{"fcmovbe",2, 0xdad0, _, ShortForm, { FloatReg, FloatAcc, 0} },
787{"fcmovu", 2, 0xdad8, _, ShortForm, { FloatReg, FloatAcc, 0} },
788{"fcmovnb", 2, 0xdbc0, _, ShortForm, { FloatReg, FloatAcc, 0} },
789{"fcmovne", 2, 0xdbc8, _, ShortForm, { FloatReg, FloatAcc, 0} },
790{"fcmovnbe",2, 0xdbd0, _, ShortForm, { FloatReg, FloatAcc, 0} },
791{"fcmovnu", 2, 0xdbd8, _, ShortForm, { FloatReg, FloatAcc, 0} },
792
793{"fcomi", 2, 0xdbf0, _, ShortForm, { FloatReg, FloatAcc, 0} },
794{"fucomi", 2, 0xdbe8, _, ShortForm, { FloatReg, FloatAcc, 0} },
795{"fcomip", 2, 0xdff0, _, ShortForm, { FloatReg, FloatAcc, 0} },
796{"fucomip",2, 0xdfe8, _, ShortForm, { FloatReg, FloatAcc, 0} },
cd22144a 797
a43022bd 798{"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */
ce868e5c
JG		 799};
800#undef _
801
fc0d7441 802static const template *const i386_optab_end
ce868e5c
JG		 803 = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]);
804
805/* 386 register table */
806
807static const reg_entry i386_regtab[] = {
808 /* 8 bit regs */
809 {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2},
810 {"bl", Reg8, 3},
811 {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7},
812 /* 16 bit regs */
813 {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3},
814 {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7},
815 /* 32 bit regs */
816 {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3},
817 {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7},
818 /* segment registers */
819 {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2},
820 {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5},
821 /* control registers */
822 {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3},
cd22144a 823 {"cr4", Control, 4},
ce868e5c
JG		 824 /* debug registers */
825 {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2},
826 {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7},
cd22144a
KR		 827 {"dr0", Debug, 0}, {"dr1", Debug, 1}, {"dr2", Debug, 2},
828 {"dr3", Debug, 3}, {"dr6", Debug, 6}, {"dr7", Debug, 7},
ce868e5c 829 /* test registers */
527cabaf 830 {"tr3", Test, 3}, {"tr4", Test, 4}, {"tr5", Test, 5},
ce868e5c
JG		 831 {"tr6", Test, 6}, {"tr7", Test, 7},
832 /* float registers */
833 {"st(0)", FloatReg|FloatAcc, 0},
834 {"st", FloatReg|FloatAcc, 0},
835 {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2},
836 {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5},
837 {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}
838};
839
840#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
841
fc0d7441 842static const reg_entry *const i386_regtab_end
ce868e5c
JG		 843 = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]);
844
845/* segment stuff */
846static const seg_entry cs = { "cs", 0x2e };
847static const seg_entry ds = { "ds", 0x3e };
848static const seg_entry ss = { "ss", 0x36 };
849static const seg_entry es = { "es", 0x26 };
850static const seg_entry fs = { "fs", 0x64 };
851static const seg_entry gs = { "gs", 0x65 };
852static const seg_entry null = { "", 0x0 };
853
854/*
855 This table is used to store the default segment register implied by all
856 possible memory addressing modes.
857 It is indexed by the mode & modrm entries of the modrm byte as follows:
858 index = (mode<<3) | modrm;
859*/
fc0d7441 860static const seg_entry *const one_byte_segment_defaults[] = {
ce868e5c
JG		 861 /* mode 0 */
862 &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds,
863 /* mode 1 */
864 &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
865 /* mode 2 */
866 &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds,
867 /* mode 3 --- not a memory reference; never referenced */
868};
869
fc0d7441 870static const seg_entry *const two_byte_segment_defaults[] = {
ce868e5c
JG		 871 /* mode 0 */
872 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
873 /* mode 1 */
874 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
875 /* mode 2 */
876 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
877 /* mode 3 --- not a memory reference; never referenced */
878};
879
880static const prefix_entry i386_prefixtab[] = {
a43022bd 881#define ADDR_PREFIX_OPCODE 0x67
ce868e5c
JG		 882 { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing
883 * (How is this useful?) */
884#define WORD_PREFIX_OPCODE 0x66
885 { "data16", 0x66 }, /* operand size prefix */
886 { "lock", 0xf0 }, /* bus lock prefix */
887 { "wait", 0x9b }, /* wait for coprocessor */
888 { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */
889 { "es", 0x26 }, { "fs", 0x64 },
890 { "gs", 0x65 }, { "ss", 0x36 },
891/* REPE & REPNE used to detect rep/repne with a non-string instruction */
892#define REPNE 0xf2
893#define REPE 0xf3
894 { "rep", 0xf3 }, /* repeat string instructions */
895 { "repe", 0xf3 }, { "repz", 0xf3 },
896 { "repne", 0xf2 }, { "repnz", 0xf2 }
897};
898
fc0d7441 899static const prefix_entry *const i386_prefixtab_end
ce868e5c
JG		 900 = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]);
901
902/* end of i386-opcode.h */
GDB Binutils - Deliverables
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