projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* tc-i386.c (md_assemble): Refuse 's' and 'l' suffixes in the intel
[deliverable/binutils-gdb.git] / include / opcode / i386.h
CommitLineData
252b5132 1/* opcode/i386.h -- Intel 80386 opcode table
b722f2be
AM		 2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation.
252b5132
RH		 4
5This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 2 of the License, or
10(at your option) any later version.
11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this program; if not, write to the Free Software
19Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20
d0b47220
AM		 21/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived
22 ix86 Unix assemblers, generate floating point instructions with
23 reversed source and destination registers in certain cases.
24 Unfortunately, gcc and possibly many other programs use this
25 reversed syntax, so we're stuck with it.
252b5132 26
7f3f1ea2
AM		 27 eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but
28 `fsub %st,%st(3)' results in st(3) = st - st(3), rather than
29 the expected st(3) = st(3) - st
252b5132
RH		 30
31 This happens with all the non-commutative arithmetic floating point
32 operations with two register operands, where the source register is
7f3f1ea2
AM		 33 %st, and destination register is %st(i). See FloatDR below.
34
35 The affected opcode map is dceX, dcfX, deeX, defX. */
252b5132 36
d0b47220 37#ifndef SYSV386_COMPAT
252b5132 38/* Set non-zero for broken, compatible instructions. Set to zero for
d0b47220 39 non-broken opcodes at your peril. gcc generates SystemV/386
252b5132 40 compatible instructions. */
d0b47220
AM		 41#define SYSV386_COMPAT 1
42#endif
43#ifndef OLDGCC_COMPAT
44/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could
45 generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands
46 reversed. */
47#define OLDGCC_COMPAT SYSV386_COMPAT
252b5132 48#endif
252b5132
RH		 49
50static const template i386_optab[] = {
51
52#define X None
f16b83df
JH		 53#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf)
54#define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_xSuf)
55#define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf)
56#define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf)
57#define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf)
58#define bw_Suf (No_lSuf|No_sSuf|No_xSuf)
59#define bl_Suf (No_wSuf|No_sSuf|No_xSuf)
60#define wl_Suf (No_bSuf|No_sSuf|No_xSuf)
61#define sl_Suf (No_bSuf|No_wSuf|No_xSuf)
62#define bwl_Suf (No_sSuf|No_xSuf)
252b5132
RH		 63#define FP (NoSuf|IgnoreSize)
64#define l_FP (l_Suf|IgnoreSize)
252b5132
RH		 65#define x_FP (x_Suf|IgnoreSize)
66#define sl_FP (sl_Suf|IgnoreSize)
d0b47220 67#if SYSV386_COMPAT
7f3f1ea2
AM		 68/* Someone forgot that the FloatR bit reverses the operation when not
69 equal to the FloatD bit. ie. Changing only FloatD results in the
70 destination being swapped *and* the direction being reversed. */
252b5132
RH		 71#define FloatDR FloatD
72#else
73#define FloatDR (FloatD|FloatR)
74#endif
75
d0b47220 76/* Move instructions. */
252b5132 77#define MOV_AX_DISP32 0xa0
e413e4e9
AM		 78{ "mov", 2, 0xa0, X, 0, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
79{ "mov", 2, 0x88, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } },
80{ "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { Imm, Reg, 0 } },
81{ "mov", 2, 0xc6, X, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0 } },
82/* The segment register moves accept WordReg so that a segment register
252b5132
RH		 83 can be copied to a 32 bit register, and vice versa, without using a
84 size prefix. When moving to a 32 bit register, the upper 16 bits
85 are set to an implementation defined value (on the Pentium Pro,
86 the implementation defined value is zero). */
e413e4e9
AM		 87{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|WordMem, 0 } },
88{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|WordMem, 0 } },
89{ "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg2, 0 } },
90{ "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3, 0 } },
d0b47220 91/* Move to/from control debug registers. */
e413e4e9
AM		 92{ "mov", 2, 0x0f20, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32|InvMem, 0} },
93{ "mov", 2, 0x0f21, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32|InvMem, 0} },
94{ "mov", 2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} },
252b5132 95
d0b47220 96/* Move with sign extend. */
252b5132
RH		 97/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
98 conflict with the "movs" string move instruction. */
e413e4e9
AM		 99{"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} },
100{"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} },
101{"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} },
f9e0cf0b 102/* Intel Syntax next 2 insns */
e413e4e9 103{"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
fc29466d 104{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} },
252b5132 105
d0b47220 106/* Move with zero extend. */
e413e4e9
AM		 107{"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
108{"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} },
f9e0cf0b 109/* Intel Syntax next 2 insns */
e413e4e9 110{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} },
fc29466d 111{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} },
252b5132 112
d0b47220 113/* Push instructions. */
e413e4e9
AM		 114{"push", 1, 0x50, X, 0, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
115{"push", 1, 0xff, 6, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
116{"push", 1, 0x6a, X, Cpu186, wl_Suf|DefaultSize, { Imm8S, 0, 0} },
117{"push", 1, 0x68, X, Cpu186, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} },
118{"push", 1, 0x06, X, 0, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
119{"push", 1, 0x0fa0, X, Cpu386, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
f16b83df 120{"pusha", 0, 0x60, X, Cpu186, wl_Suf|DefaultSize, { 0, 0, 0 } },
252b5132 121
d0b47220 122/* Pop instructions. */
e413e4e9
AM		 123{"pop", 1, 0x58, X, 0, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } },
124{"pop", 1, 0x8f, 0, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } },
252b5132 125#define POP_SEG_SHORT 0x07
e413e4e9
AM		 126{"pop", 1, 0x07, X, 0, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
127{"pop", 1, 0x0fa1, X, Cpu386, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
f16b83df 128{"popa", 0, 0x61, X, Cpu186, wl_Suf|DefaultSize, { 0, 0, 0 } },
252b5132 129
d0b47220
AM		 130/* Exchange instructions.
131 xchg commutes: we allow both operand orders. */
e413e4e9
AM		 132{"xchg", 2, 0x90, X, 0, wl_Suf|ShortForm, { WordReg, Acc, 0 } },
133{"xchg", 2, 0x90, X, 0, wl_Suf|ShortForm, { Acc, WordReg, 0 } },
134{"xchg", 2, 0x86, X, 0, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
135{"xchg", 2, 0x86, X, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } },
252b5132 136
d0b47220 137/* In/out from ports. */
e413e4e9
AM		 138{"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } },
139{"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } },
140{"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } },
141{"in", 1, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } },
142{"out", 2, 0xe6, X, 0, bwl_Suf|W, { Acc, Imm8, 0 } },
143{"out", 2, 0xee, X, 0, bwl_Suf|W, { Acc, InOutPortReg, 0 } },
144{"out", 1, 0xe6, X, 0, bwl_Suf|W, { Imm8, 0, 0 } },
145{"out", 1, 0xee, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } },
252b5132 146
d0b47220 147/* Load effective address. */
e413e4e9 148{"lea", 2, 0x8d, X, 0, wl_Suf|Modrm, { WordMem, WordReg, 0 } },
252b5132 149
d0b47220 150/* Load segment registers from memory. */
e413e4e9
AM		 151{"lds", 2, 0xc5, X, 0, wl_Suf|Modrm, { WordMem, WordReg, 0} },
152{"les", 2, 0xc4, X, 0, wl_Suf|Modrm, { WordMem, WordReg, 0} },
153{"lfs", 2, 0x0fb4, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} },
154{"lgs", 2, 0x0fb5, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} },
155{"lss", 2, 0x0fb2, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} },
252b5132 156
d0b47220 157/* Flags register instructions. */
e413e4e9
AM		 158{"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} },
159{"cld", 0, 0xfc, X, 0, NoSuf, { 0, 0, 0} },
160{"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} },
161{"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} },
162{"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} },
163{"lahf", 0, 0x9f, X, 0, NoSuf, { 0, 0, 0} },
164{"sahf", 0, 0x9e, X, 0, NoSuf, { 0, 0, 0} },
f16b83df
JH		 165{"pushf", 0, 0x9c, X, 0, wl_Suf|DefaultSize, { 0, 0, 0} },
166{"popf", 0, 0x9d, X, 0, wl_Suf|DefaultSize, { 0, 0, 0} },
e413e4e9
AM		 167{"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} },
168{"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} },
169{"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} },
252b5132 170
d0b47220 171/* Arithmetic. */
e413e4e9
AM		 172{"add", 2, 0x00, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
173{"add", 2, 0x83, 0, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
174{"add", 2, 0x04, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
175{"add", 2, 0x80, 0, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
176
177{"inc", 1, 0x40, X, 0, wl_Suf|ShortForm, { WordReg, 0, 0} },
178{"inc", 1, 0xfe, 0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
179
180{"sub", 2, 0x28, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
181{"sub", 2, 0x83, 5, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
182{"sub", 2, 0x2c, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
183{"sub", 2, 0x80, 5, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
184
185{"dec", 1, 0x48, X, 0, wl_Suf|ShortForm, { WordReg, 0, 0} },
186{"dec", 1, 0xfe, 1, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
187
188{"sbb", 2, 0x18, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
189{"sbb", 2, 0x83, 3, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
190{"sbb", 2, 0x1c, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
191{"sbb", 2, 0x80, 3, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
192
193{"cmp", 2, 0x38, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
194{"cmp", 2, 0x83, 7, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
195{"cmp", 2, 0x3c, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
196{"cmp", 2, 0x80, 7, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
197
198{"test", 2, 0x84, X, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} },
199{"test", 2, 0x84, X, 0, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} },
200{"test", 2, 0xa8, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
201{"test", 2, 0xf6, 0, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
202
203{"and", 2, 0x20, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
204{"and", 2, 0x83, 4, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
205{"and", 2, 0x24, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
206{"and", 2, 0x80, 4, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
207
208{"or", 2, 0x08, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
209{"or", 2, 0x83, 1, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
210{"or", 2, 0x0c, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
211{"or", 2, 0x80, 1, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
212
213{"xor", 2, 0x30, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
214{"xor", 2, 0x83, 6, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
215{"xor", 2, 0x34, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
216{"xor", 2, 0x80, 6, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
217
218/* clr with 1 operand is really xor with 2 operands. */
219{"clr", 1, 0x30, X, 0, bwl_Suf|W|Modrm|regKludge, { Reg, 0, 0 } },
220
221{"adc", 2, 0x10, X, 0, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
222{"adc", 2, 0x83, 2, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} },
223{"adc", 2, 0x14, X, 0, bwl_Suf|W, { Imm, Acc, 0} },
224{"adc", 2, 0x80, 2, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} },
225
226{"neg", 1, 0xf6, 3, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
227{"not", 1, 0xf6, 2, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
228
229{"aaa", 0, 0x37, X, 0, NoSuf, { 0, 0, 0} },
230{"aas", 0, 0x3f, X, 0, NoSuf, { 0, 0, 0} },
231{"daa", 0, 0x27, X, 0, NoSuf, { 0, 0, 0} },
232{"das", 0, 0x2f, X, 0, NoSuf, { 0, 0, 0} },
233{"aad", 0, 0xd50a, X, 0, NoSuf, { 0, 0, 0} },
234{"aad", 1, 0xd5, X, 0, NoSuf, { Imm8S, 0, 0} },
235{"aam", 0, 0xd40a, X, 0, NoSuf, { 0, 0, 0} },
236{"aam", 1, 0xd4, X, 0, NoSuf, { Imm8S, 0, 0} },
252b5132 237
d0b47220
AM		 238/* Conversion insns. */
239/* Intel naming */
e413e4e9
AM		 240{"cbw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} },
241{"cwde", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} },
242{"cwd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} },
243{"cdq", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} },
d0b47220 244/* AT&T naming */
e413e4e9
AM		 245{"cbtw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} },
246{"cwtl", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} },
247{"cwtd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} },
248{"cltd", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} },
252b5132
RH		 249
250/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
251 expanding 64-bit multiplies, and *cannot* be selected to accomplish
252 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
253 These multiplies can only be selected with single operand forms. */
e413e4e9
AM		 254{"mul", 1, 0xf6, 4, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
255{"imul", 1, 0xf6, 5, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
256{"imul", 2, 0x0faf, X, Cpu386, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
257{"imul", 3, 0x6b, X, Cpu186, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} },
258{"imul", 3, 0x69, X, Cpu186, wl_Suf|Modrm, { Imm16|Imm32, WordReg|WordMem, WordReg} },
252b5132
RH		 259/* imul with 2 operands mimics imul with 3 by putting the register in
260 both i.rm.reg & i.rm.regmem fields. regKludge enables this
261 transformation. */
e413e4e9
AM		 262{"imul", 2, 0x6b, X, Cpu186, wl_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
263{"imul", 2, 0x69, X, Cpu186, wl_Suf|Modrm|regKludge,{ Imm16|Imm32, WordReg, 0} },
264
265{"div", 1, 0xf6, 6, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
266{"div", 2, 0xf6, 6, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
267{"idiv", 1, 0xf6, 7, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
268{"idiv", 2, 0xf6, 7, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} },
269
270{"rol", 2, 0xd0, 0, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
271{"rol", 2, 0xc0, 0, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
272{"rol", 2, 0xd2, 0, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
273{"rol", 1, 0xd0, 0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
274
275{"ror", 2, 0xd0, 1, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
276{"ror", 2, 0xc0, 1, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
277{"ror", 2, 0xd2, 1, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
278{"ror", 1, 0xd0, 1, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
279
280{"rcl", 2, 0xd0, 2, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
281{"rcl", 2, 0xc0, 2, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
282{"rcl", 2, 0xd2, 2, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
283{"rcl", 1, 0xd0, 2, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
284
285{"rcr", 2, 0xd0, 3, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
286{"rcr", 2, 0xc0, 3, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
287{"rcr", 2, 0xd2, 3, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
288{"rcr", 1, 0xd0, 3, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
289
290{"sal", 2, 0xd0, 4, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
291{"sal", 2, 0xc0, 4, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
292{"sal", 2, 0xd2, 4, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
293{"sal", 1, 0xd0, 4, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
294
295{"shl", 2, 0xd0, 4, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
296{"shl", 2, 0xc0, 4, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
297{"shl", 2, 0xd2, 4, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
298{"shl", 1, 0xd0, 4, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
299
300{"shr", 2, 0xd0, 5, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
301{"shr", 2, 0xc0, 5, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
302{"shr", 2, 0xd2, 5, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
303{"shr", 1, 0xd0, 5, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
304
305{"sar", 2, 0xd0, 7, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} },
306{"sar", 2, 0xc0, 7, Cpu186, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
307{"sar", 2, 0xd2, 7, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} },
308{"sar", 1, 0xd0, 7, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} },
309
310{"shld", 3, 0x0fa4, X, Cpu386, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
311{"shld", 3, 0x0fa5, X, Cpu386, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
312{"shld", 2, 0x0fa5, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
313
314{"shrd", 3, 0x0fac, X, Cpu386, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} },
315{"shrd", 3, 0x0fad, X, Cpu386, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} },
316{"shrd", 2, 0x0fad, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
252b5132 317
d0b47220 318/* Control transfer instructions. */
e413e4e9
AM		 319{"call", 1, 0xe8, X, 0, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} },
320{"call", 1, 0xff, 2, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} },
252b5132 321/* Intel Syntax */
e413e4e9 322{"call", 2, 0x9a, X, 0, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
3138f287 323/* Intel Syntax */
e413e4e9
AM		 324{"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} },
325{"lcall", 2, 0x9a, X, 0, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
326{"lcall", 1, 0xff, 3, 0, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} },
252b5132
RH		 327
328#define JUMP_PC_RELATIVE 0xeb
e413e4e9
AM		 329{"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp, 0, 0} },
330{"jmp", 1, 0xff, 4, 0, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} },
252b5132 331/* Intel Syntax */
e413e4e9 332{"jmp", 2, 0xea, X, 0, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
3138f287 333/* Intel Syntax */
e413e4e9
AM		 334{"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem, 0, 0} },
335{"ljmp", 2, 0xea, X, 0, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
336{"ljmp", 1, 0xff, 5, 0, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} },
252b5132 337
e413e4e9
AM		 338{"ret", 0, 0xc3, X, 0, wl_Suf|DefaultSize, { 0, 0, 0} },
339{"ret", 1, 0xc2, X, 0, wl_Suf|DefaultSize, { Imm16, 0, 0} },
340{"lret", 0, 0xcb, X, 0, wl_Suf|DefaultSize, { 0, 0, 0} },
341{"lret", 1, 0xca, X, 0, wl_Suf|DefaultSize, { Imm16, 0, 0} },
342{"enter", 2, 0xc8, X, Cpu186, wl_Suf|DefaultSize, { Imm16, Imm8, 0} },
343{"leave", 0, 0xc9, X, Cpu186, wl_Suf|DefaultSize, { 0, 0, 0} },
252b5132 344
d0b47220 345/* Conditional jumps. */
e413e4e9
AM		 346{"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} },
347{"jno", 1, 0x71, X, 0, NoSuf|Jump, { Disp, 0, 0} },
348{"jb", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
349{"jc", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
350{"jnae", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} },
351{"jnb", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
352{"jnc", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
353{"jae", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} },
354{"je", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} },
355{"jz", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} },
356{"jne", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} },
357{"jnz", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} },
358{"jbe", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} },
359{"jna", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} },
360{"jnbe", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} },
361{"ja", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} },
362{"js", 1, 0x78, X, 0, NoSuf|Jump, { Disp, 0, 0} },
363{"jns", 1, 0x79, X, 0, NoSuf|Jump, { Disp, 0, 0} },
364{"jp", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} },
365{"jpe", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} },
366{"jnp", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} },
367{"jpo", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} },
368{"jl", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} },
369{"jnge", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} },
370{"jnl", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} },
371{"jge", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} },
372{"jle", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} },
373{"jng", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} },
374{"jnle", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} },
375{"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} },
252b5132
RH		 376
377/* jcxz vs. jecxz is chosen on the basis of the address size prefix. */
e413e4e9
AM		 378{"jcxz", 1, 0xe3, X, 0, NoSuf|JumpByte|Size16, { Disp, 0, 0} },
379{"jecxz", 1, 0xe3, X, 0, NoSuf|JumpByte|Size32, { Disp, 0, 0} },
252b5132
RH		 380
381/* The loop instructions also use the address size prefix to select
382 %cx rather than %ecx for the loop count, so the `w' form of these
383 instructions emit an address size prefix rather than a data size
384 prefix. */
e413e4e9
AM		 385{"loop", 1, 0xe2, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} },
386{"loopz", 1, 0xe1, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} },
387{"loope", 1, 0xe1, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} },
388{"loopnz", 1, 0xe0, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} },
389{"loopne", 1, 0xe0, X, 0, wl_Suf|JumpByte, { Disp, 0, 0} },
252b5132 390
d0b47220 391/* Set byte on flag instructions. */
e413e4e9
AM		 392{"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
393{"setno", 1, 0x0f91, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
394{"setb", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
395{"setc", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
396{"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
397{"setnb", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
398{"setnc", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
399{"setae", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
400{"sete", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
401{"setz", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
402{"setne", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
403{"setnz", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
404{"setbe", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
405{"setna", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
406{"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
407{"seta", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
408{"sets", 1, 0x0f98, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
409{"setns", 1, 0x0f99, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
410{"setp", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
411{"setpe", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
412{"setnp", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
413{"setpo", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
414{"setl", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
415{"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
416{"setnl", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
417{"setge", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
418{"setle", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
419{"setng", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
420{"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
421{"setg", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} },
252b5132 422
d0b47220 423/* String manipulation. */
f16b83df
JH		 424{"cmps", 0, 0xa6, X, 0, bwl_Suf|W|IsString, { 0, 0, 0} },
425{"cmps", 2, 0xa6, X, 0, bwl_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
426{"scmp", 0, 0xa6, X, 0, bwl_Suf|W|IsString, { 0, 0, 0} },
427{"scmp", 2, 0xa6, X, 0, bwl_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} },
428{"ins", 0, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} },
429{"ins", 2, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} },
430{"outs", 0, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} },
431{"outs", 2, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { AnyMem, InOutPortReg, 0} },
432{"lods", 0, 0xac, X, 0, bwl_Suf|W|IsString, { 0, 0, 0} },
433{"lods", 1, 0xac, X, 0, bwl_Suf|W|IsString, { AnyMem, 0, 0} },
434{"lods", 2, 0xac, X, 0, bwl_Suf|W|IsString, { AnyMem, Acc, 0} },
435{"slod", 0, 0xac, X, 0, bwl_Suf|W|IsString, { 0, 0, 0} },
436{"slod", 1, 0xac, X, 0, bwl_Suf|W|IsString, { AnyMem, 0, 0} },
437{"slod", 2, 0xac, X, 0, bwl_Suf|W|IsString, { AnyMem, Acc, 0} },
438{"movs", 0, 0xa4, X, 0, bwl_Suf|W|IsString, { 0, 0, 0} },
439{"movs", 2, 0xa4, X, 0, bwl_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
440{"smov", 0, 0xa4, X, 0, bwl_Suf|W|IsString, { 0, 0, 0} },
441{"smov", 2, 0xa4, X, 0, bwl_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} },
442{"scas", 0, 0xae, X, 0, bwl_Suf|W|IsString, { 0, 0, 0} },
443{"scas", 1, 0xae, X, 0, bwl_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
444{"scas", 2, 0xae, X, 0, bwl_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
445{"ssca", 0, 0xae, X, 0, bwl_Suf|W|IsString, { 0, 0, 0} },
446{"ssca", 1, 0xae, X, 0, bwl_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
447{"ssca", 2, 0xae, X, 0, bwl_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} },
448{"stos", 0, 0xaa, X, 0, bwl_Suf|W|IsString, { 0, 0, 0} },
449{"stos", 1, 0xaa, X, 0, bwl_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
450{"stos", 2, 0xaa, X, 0, bwl_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
451{"ssto", 0, 0xaa, X, 0, bwl_Suf|W|IsString, { 0, 0, 0} },
452{"ssto", 1, 0xaa, X, 0, bwl_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} },
453{"ssto", 2, 0xaa, X, 0, bwl_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} },
e413e4e9
AM		 454{"xlat", 0, 0xd7, X, 0, b_Suf|IsString, { 0, 0, 0} },
455{"xlat", 1, 0xd7, X, 0, b_Suf|IsString, { AnyMem, 0, 0} },
252b5132 456
d0b47220 457/* Bit manipulation. */
e413e4e9
AM		 458{"bsf", 2, 0x0fbc, X, Cpu386, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
459{"bsr", 2, 0x0fbd, X, Cpu386, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
460{"bt", 2, 0x0fa3, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
461{"bt", 2, 0x0fba, 4, Cpu386, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
462{"btc", 2, 0x0fbb, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
463{"btc", 2, 0x0fba, 7, Cpu386, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
464{"btr", 2, 0x0fb3, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
465{"btr", 2, 0x0fba, 6, Cpu386, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
466{"bts", 2, 0x0fab, X, Cpu386, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} },
467{"bts", 2, 0x0fba, 5, Cpu386, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} },
252b5132 468
d0b47220 469/* Interrupts & op. sys insns. */
252b5132 470/* See gas/config/tc-i386.c for conversion of 'int $3' into the special
d0b47220 471 int 3 insn. */
252b5132
RH		 472#define INT_OPCODE 0xcd
473#define INT3_OPCODE 0xcc
e413e4e9
AM		 474{"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} },
475{"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} },
476{"into", 0, 0xce, X, 0, NoSuf, { 0, 0, 0} },
f16b83df 477{"iret", 0, 0xcf, X, 0, wl_Suf|DefaultSize, { 0, 0, 0} },
d0b47220 478/* i386sl, i486sl, later 486, and Pentium. */
e413e4e9 479{"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} },
252b5132 480
e413e4e9 481{"bound", 2, 0x62, X, Cpu186, wl_Suf|Modrm, { WordReg, WordMem, 0} },
252b5132 482
e413e4e9 483{"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} },
d0b47220 484/* nop is actually 'xchgl %eax, %eax'. */
e413e4e9 485{"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} },
252b5132 486
d0b47220 487/* Protection control. */
e413e4e9
AM		 488{"arpl", 2, 0x63, X, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
489{"lar", 2, 0x0f02, X, Cpu286, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
490{"lgdt", 1, 0x0f01, 2, Cpu286, wl_Suf|Modrm, { WordMem, 0, 0} },
491{"lidt", 1, 0x0f01, 3, Cpu286, wl_Suf|Modrm, { WordMem, 0, 0} },
492{"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
493{"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
494{"lsl", 2, 0x0f03, X, Cpu286, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
495{"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
496
497{"sgdt", 1, 0x0f01, 0, Cpu286, wl_Suf|Modrm, { WordMem, 0, 0} },
498{"sidt", 1, 0x0f01, 1, Cpu286, wl_Suf|Modrm, { WordMem, 0, 0} },
499{"sldt", 1, 0x0f00, 0, Cpu286, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} },
500{"smsw", 1, 0x0f01, 4, Cpu286, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} },
501{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
502
503{"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
504{"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
252b5132 505
d0b47220 506/* Floating point instructions. */
252b5132
RH		 507
508/* load */
e413e4e9 509{"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
f16b83df 510{"fld", 1, 0xd9, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9 511{"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
252b5132 512/* Intel Syntax */
e413e4e9 513{"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} },
f9e0cf0b 514{"fild", 1, 0xdf, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 515/* Intel Syntax */
e413e4e9
AM		 516{"fildd", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
517{"fildq", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
518{"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
519{"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} },
520{"fbld", 1, 0xdf, 4, 0, FP|Modrm, { LLongMem, 0, 0} },
252b5132
RH		 521
522/* store (no pop) */
e413e4e9 523{"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
f16b83df 524{"fst", 1, 0xd9, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9 525{"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
f16b83df 526{"fist", 1, 0xdf, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132
RH		 527
528/* store (with pop) */
e413e4e9 529{"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
f16b83df 530{"fstp", 1, 0xd9, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9 531{"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
252b5132 532/* Intel Syntax */
e413e4e9
AM		 533{"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} },
534{"fistp", 1, 0xdf, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 535/* Intel Syntax */
e413e4e9
AM		 536{"fistpd", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
537{"fistpq", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
538{"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
539{"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} },
540{"fbstp", 1, 0xdf, 6, 0, FP|Modrm, { LLongMem, 0, 0} },
252b5132
RH		 541
542/* exchange %st<n> with %st0 */
e413e4e9
AM		 543{"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
544/* alias for fxch %st(1) */
545{"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 546
547/* comparison (without pop) */
e413e4e9
AM		 548{"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
549/* alias for fcom %st(1) */
550{"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} },
f16b83df 551{"fcom", 1, 0xd8, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9
AM		 552{"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
553{"ficom", 1, 0xde, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132
RH		 554
555/* comparison (with pop) */
e413e4e9
AM		 556{"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
557/* alias for fcomp %st(1) */
558{"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} },
f16b83df 559{"fcomp", 1, 0xd8, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9
AM		 560{"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} },
561{"ficomp", 1, 0xde, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
562{"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 563
564/* unordered comparison (with pop) */
e413e4e9
AM		 565{"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} },
566/* alias for fucom %st(1) */
567{"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} },
568{"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} },
569/* alias for fucomp %st(1) */
570{"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} },
571{"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} },
252b5132 572
e413e4e9
AM		 573{"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} },
574{"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 575
576/* load constants into %st0 */
e413e4e9
AM		 577{"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} },
578{"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} },
579{"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} },
580{"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} },
581{"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} },
582{"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} },
583{"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 584
585/* arithmetic */
586
587/* add */
e413e4e9
AM		 588{"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
589/* alias for fadd %st(i), %st */
590{"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 591#if SYSV386_COMPAT
e413e4e9
AM		 592/* alias for faddp */
593{"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 594#endif
f16b83df
JH		 595{"fadd", 1, 0xd8, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
596{"fiadd", 1, 0xde, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 597
e413e4e9
AM		 598{"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
599{"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
600/* alias for faddp %st, %st(1) */
601{"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} },
602{"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
252b5132
RH		 603
604/* subtract */
e413e4e9
AM		 605{"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
606{"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 607#if SYSV386_COMPAT
e413e4e9
AM		 608/* alias for fsubp */
609{"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 610#endif
f16b83df 611{"fsub", 1, 0xd8, 4, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9 612{"fisub", 1, 0xde, 4, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 613
d0b47220 614#if SYSV386_COMPAT
e413e4e9
AM		 615{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
616{"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
617{"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },
d0b47220 618#if OLDGCC_COMPAT
e413e4e9 619{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 620#endif
252b5132 621#else
e413e4e9
AM		 622{"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
623{"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
624{"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 625#endif
626
627/* subtract reverse */
e413e4e9
AM		 628{"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
629{"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 630#if SYSV386_COMPAT
e413e4e9
AM		 631/* alias for fsubrp */
632{"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 633#endif
f16b83df 634{"fsubr", 1, 0xd8, 5, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9 635{"fisubr", 1, 0xde, 5, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 636
d0b47220 637#if SYSV386_COMPAT
e413e4e9
AM		 638{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
639{"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
640{"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} },
d0b47220 641#if OLDGCC_COMPAT
e413e4e9 642{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 643#endif
252b5132 644#else
e413e4e9
AM		 645{"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
646{"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
647{"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 648#endif
649
650/* multiply */
e413e4e9
AM		 651{"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} },
652{"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 653#if SYSV386_COMPAT
e413e4e9
AM		 654/* alias for fmulp */
655{"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 656#endif
f16b83df
JH		 657{"fmul", 1, 0xd8, 1, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
658{"fimul", 1, 0xde, 1, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 659
e413e4e9
AM		 660{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
661{"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
662{"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} },
663{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
252b5132
RH		 664
665/* divide */
e413e4e9
AM		 666{"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
667{"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 668#if SYSV386_COMPAT
e413e4e9
AM		 669/* alias for fdivp */
670{"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 671#endif
f16b83df
JH		 672{"fdiv", 1, 0xd8, 6, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
673{"fidiv", 1, 0xde, 6, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 674
d0b47220 675#if SYSV386_COMPAT
e413e4e9
AM		 676{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
677{"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
678{"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },
d0b47220 679#if OLDGCC_COMPAT
e413e4e9 680{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 681#endif
252b5132 682#else
e413e4e9
AM		 683{"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
684{"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
685{"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 686#endif
687
688/* divide reverse */
e413e4e9
AM		 689{"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} },
690{"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
d0b47220 691#if SYSV386_COMPAT
e413e4e9
AM		 692/* alias for fdivrp */
693{"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} },
252b5132 694#endif
f16b83df 695{"fdivr", 1, 0xd8, 7, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} },
e413e4e9 696{"fidivr", 1, 0xde, 7, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
252b5132 697
d0b47220 698#if SYSV386_COMPAT
e413e4e9
AM		 699{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
700{"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
701{"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} },
d0b47220 702#if OLDGCC_COMPAT
e413e4e9 703{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} },
d0b47220 704#endif
252b5132 705#else
e413e4e9
AM		 706{"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} },
707{"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
708{"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 709#endif
710
e413e4e9
AM		 711{"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} },
712{"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} },
713{"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} },
714{"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} },
715{"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} },
716{"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} },
717{"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} },
718{"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} },
719{"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} },
720{"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} },
721{"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} },
722{"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} },
723{"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} },
724{"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} },
725{"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} },
726{"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} },
727{"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} },
728{"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} },
252b5132
RH		 729
730/* processor control */
e413e4e9
AM		 731{"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} },
732{"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} },
733{"fldcw", 1, 0xd9, 5, 0, FP|Modrm, { ShortMem, 0, 0} },
734{"fnstcw", 1, 0xd9, 7, 0, FP|Modrm, { ShortMem, 0, 0} },
735{"fstcw", 1, 0xd9, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} },
736{"fnstsw", 1, 0xdfe0, X, 0, FP, { Acc, 0, 0} },
737{"fnstsw", 1, 0xdd, 7, 0, FP|Modrm, { ShortMem, 0, 0} },
738{"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} },
739{"fstsw", 1, 0xdfe0, X, 0, FP|FWait, { Acc, 0, 0} },
740{"fstsw", 1, 0xdd, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} },
741{"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} },
742{"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} },
743{"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} },
d0b47220 744/* Short forms of fldenv, fstenv use data size prefix. */
e413e4e9
AM		 745{"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
746{"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
747{"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
748{"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
749{"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} },
750{"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} },
751
752{"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} },
252b5132 753/* P6:free st(i), pop st */
e413e4e9
AM		 754{"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
755{"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} },
252b5132 756#define FWAIT_OPCODE 0x9b
e413e4e9 757{"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} },
252b5132 758
d0b47220
AM		 759/* Opcode prefixes; we allow them as separate insns too. */
760
252b5132 761#define ADDR_PREFIX_OPCODE 0x67
e413e4e9
AM		 762{"addr16", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
763{"addr32", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
764{"aword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
765{"adword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
252b5132 766#define DATA_PREFIX_OPCODE 0x66
e413e4e9
AM		 767{"data16", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
768{"data32", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
769{"word", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} },
770{"dword", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} },
252b5132 771#define LOCK_PREFIX_OPCODE 0xf0
e413e4e9
AM		 772{"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
773{"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 774#define CS_PREFIX_OPCODE 0x2e
e413e4e9 775{"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 776#define DS_PREFIX_OPCODE 0x3e
e413e4e9 777{"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 778#define ES_PREFIX_OPCODE 0x26
e413e4e9 779{"es", 0, 0x26, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 780#define FS_PREFIX_OPCODE 0x64
e413e4e9 781{"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 782#define GS_PREFIX_OPCODE 0x65
e413e4e9 783{"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 784#define SS_PREFIX_OPCODE 0x36
e413e4e9 785{"ss", 0, 0x36, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132
RH		 786#define REPNE_PREFIX_OPCODE 0xf2
787#define REPE_PREFIX_OPCODE 0xf3
e413e4e9
AM		 788{"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
789{"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
790{"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
791{"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
792{"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} },
252b5132 793
d0b47220 794/* 486 extensions. */
252b5132 795
e413e4e9
AM		 796{"bswap", 1, 0x0fc8, X, Cpu486, l_Suf|ShortForm, { Reg32, 0, 0 } },
797{"xadd", 2, 0x0fc0, X, Cpu486, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
798{"cmpxchg", 2, 0x0fb0, X, Cpu486, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
799{"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} },
800{"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} },
801{"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm, { AnyMem, 0, 0} },
252b5132 802
d0b47220 803/* 586 and late 486 extensions. */
e413e4e9 804{"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} },
252b5132 805
d0b47220 806/* Pentium extensions. */
e413e4e9
AM		 807{"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} },
808{"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} },
809{"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} },
810{"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm, { LLongMem, 0, 0} },
252b5132 811
558b0a60
AM		 812/* Pentium II/Pentium Pro extensions. */
813{"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} },
814{"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} },
815{"fxsave", 1, 0x0fae, 0, Cpu686, FP|Modrm, { LLongMem, 0, 0} },
816{"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm, { LLongMem, 0, 0} },
e413e4e9
AM		 817{"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} },
818/* official undefined instr. */
819{"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} },
820/* alias for ud2 */
821{"ud2a", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} },
822/* 2nd. official undefined instr. */
823{"ud2b", 0, 0x0fb9, X, Cpu686, NoSuf, { 0, 0, 0} },
824
825{"cmovo", 2, 0x0f40, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
826{"cmovno", 2, 0x0f41, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
827{"cmovb", 2, 0x0f42, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
828{"cmovc", 2, 0x0f42, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
829{"cmovnae", 2, 0x0f42, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
830{"cmovae", 2, 0x0f43, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
831{"cmovnc", 2, 0x0f43, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
832{"cmovnb", 2, 0x0f43, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
833{"cmove", 2, 0x0f44, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
834{"cmovz", 2, 0x0f44, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
835{"cmovne", 2, 0x0f45, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
836{"cmovnz", 2, 0x0f45, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
837{"cmovbe", 2, 0x0f46, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
838{"cmovna", 2, 0x0f46, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
839{"cmova", 2, 0x0f47, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
840{"cmovnbe", 2, 0x0f47, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
841{"cmovs", 2, 0x0f48, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
842{"cmovns", 2, 0x0f49, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
843{"cmovp", 2, 0x0f4a, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
844{"cmovnp", 2, 0x0f4b, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
845{"cmovl", 2, 0x0f4c, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
846{"cmovnge", 2, 0x0f4c, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
847{"cmovge", 2, 0x0f4d, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
848{"cmovnl", 2, 0x0f4d, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
849{"cmovle", 2, 0x0f4e, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
850{"cmovng", 2, 0x0f4e, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
851{"cmovg", 2, 0x0f4f, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
852{"cmovnle", 2, 0x0f4f, X, Cpu686, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
853
854{"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
855{"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
856{"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
857{"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
858{"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
859{"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
860{"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
861{"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
862{"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
863{"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
864{"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
865{"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
866
867{"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
868{"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
869{"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
870{"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
871{"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
872{"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
873{"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
874{"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
875{"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
876{"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
877{"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
878{"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} },
879{"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} },
880{"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} },
252b5132
RH		 881
882/* MMX instructions. */
883
e413e4e9
AM		 884{"emms", 0, 0x0f77, X, CpuMMX, FP, { 0, 0, 0 } },
885{"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } },
886{"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } },
887{"movq", 2, 0x0f6f, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
888{"movq", 2, 0x0f7f, X, CpuMMX, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } },
889{"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
890{"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
891{"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
892{"paddb", 2, 0x0ffc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
893{"paddw", 2, 0x0ffd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
894{"paddd", 2, 0x0ffe, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
895{"paddsb", 2, 0x0fec, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
896{"paddsw", 2, 0x0fed, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
897{"paddusb", 2, 0x0fdc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
898{"paddusw", 2, 0x0fdd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
899{"pand", 2, 0x0fdb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
900{"pandn", 2, 0x0fdf, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
901{"pcmpeqb", 2, 0x0f74, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
902{"pcmpeqw", 2, 0x0f75, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
903{"pcmpeqd", 2, 0x0f76, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
904{"pcmpgtb", 2, 0x0f64, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
905{"pcmpgtw", 2, 0x0f65, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
906{"pcmpgtd", 2, 0x0f66, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
907{"pmaddwd", 2, 0x0ff5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
908{"pmulhw", 2, 0x0fe5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
909{"pmullw", 2, 0x0fd5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
910{"por", 2, 0x0feb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
911{"psllw", 2, 0x0ff1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
912{"psllw", 2, 0x0f71, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
913{"pslld", 2, 0x0ff2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
914{"pslld", 2, 0x0f72, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
915{"psllq", 2, 0x0ff3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
916{"psllq", 2, 0x0f73, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
917{"psraw", 2, 0x0fe1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
918{"psraw", 2, 0x0f71, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
919{"psrad", 2, 0x0fe2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
920{"psrad", 2, 0x0f72, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
921{"psrlw", 2, 0x0fd1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
922{"psrlw", 2, 0x0f71, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
923{"psrld", 2, 0x0fd2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
924{"psrld", 2, 0x0f72, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
925{"psrlq", 2, 0x0fd3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
926{"psrlq", 2, 0x0f73, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } },
927{"psubb", 2, 0x0ff8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
928{"psubw", 2, 0x0ff9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
929{"psubd", 2, 0x0ffa, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
930{"psubsb", 2, 0x0fe8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
931{"psubsw", 2, 0x0fe9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
932{"psubusb", 2, 0x0fd8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
933{"psubusw", 2, 0x0fd9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
934{"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
935{"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
936{"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
937{"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
938{"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
939{"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
940{"pxor", 2, 0x0fef, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
c608c12e
AM		 941
942
d0b47220 943/* PIII Katmai New Instructions / SIMD instructions. */
c608c12e 944
e413e4e9
AM		 945{"addps", 2, 0x0f58, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
946{"addss", 2, 0xf30f58, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
947{"andnps", 2, 0x0f55, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
948{"andps", 2, 0x0f54, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
949{"cmpeqps", 2, 0x0fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
950{"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
951{"cmpleps", 2, 0x0fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
952{"cmpless", 2, 0xf30fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
953{"cmpltps", 2, 0x0fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
954{"cmpltss", 2, 0xf30fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
955{"cmpneqps", 2, 0x0fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
956{"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
957{"cmpnleps", 2, 0x0fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
958{"cmpnless", 2, 0xf30fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
959{"cmpnltps", 2, 0x0fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
960{"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
961{"cmpordps", 2, 0x0fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
962{"cmpordss", 2, 0xf30fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
963{"cmpunordps",2, 0x0fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
964{"cmpunordss",2, 0xf30fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
965{"cmpps", 3, 0x0fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
966{"cmpss", 3, 0xf30fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } },
967{"comiss", 2, 0x0f2f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
968{"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
969{"cvtps2pi", 2, 0x0f2d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
970{"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, FP|Modrm, { Reg32|WordMem, RegXMM, 0 } },
971{"cvtss2si", 2, 0xf30f2d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } },
972{"cvttps2pi", 2, 0x0f2c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
973{"cvttss2si", 2, 0xf30f2c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } },
974{"divps", 2, 0x0f5e, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
975{"divss", 2, 0xf30f5e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
976{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, FP|Modrm, { WordMem, 0, 0 } },
977{"maskmovq", 2, 0x0ff7, X, CpuSSE, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } },
978{"maxps", 2, 0x0f5f, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
979{"maxss", 2, 0xf30f5f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
980{"minps", 2, 0x0f5d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
981{"minss", 2, 0xf30f5d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
982{"movaps", 2, 0x0f28, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
983{"movaps", 2, 0x0f29, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
984{"movhlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
985{"movhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } },
986{"movhps", 2, 0x0f17, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
987{"movlhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } },
988{"movlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } },
989{"movlps", 2, 0x0f13, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
990{"movmskps", 2, 0x0f50, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } },
991{"movntps", 2, 0x0f2b, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } },
992{"movntq", 2, 0x0fe7, X, CpuSSE, FP|Modrm, { RegMMX, LLongMem, 0 } },
993{"movss", 2, 0xf30f10, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
994{"movss", 2, 0xf30f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } },
995{"movups", 2, 0x0f10, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
996{"movups", 2, 0x0f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
997{"mulps", 2, 0x0f59, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
998{"mulss", 2, 0xf30f59, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
999{"orps", 2, 0x0f56, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1000{"pavgb", 2, 0x0fe0, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1001{"pavgw", 2, 0x0fe3, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1002{"pextrw", 3, 0x0fc5, X, CpuSSE, FP|Modrm, { Imm8, RegMMX, Reg32|InvMem } },
1003{"pinsrw", 3, 0x0fc4, X, CpuSSE, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } },
1004{"pmaxsw", 2, 0x0fee, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1005{"pmaxub", 2, 0x0fde, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1006{"pminsw", 2, 0x0fea, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1007{"pminub", 2, 0x0fda, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1008{"pmovmskb", 2, 0x0fd7, X, CpuSSE, FP|Modrm, { RegMMX, Reg32|InvMem, 0 } },
1009{"pmulhuw", 2, 0x0fe4, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1010{"prefetchnta", 1, 0x0f18, 0, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1011{"prefetcht0", 1, 0x0f18, 1, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1012{"prefetcht1", 1, 0x0f18, 2, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1013{"prefetcht2", 1, 0x0f18, 3, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },
1014{"psadbw", 2, 0x0ff6, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
1015{"pshufw", 3, 0x0f70, X, CpuSSE, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } },
1016{"rcpps", 2, 0x0f53, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1017{"rcpss", 2, 0xf30f53, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1018{"rsqrtps", 2, 0x0f52, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1019{"rsqrtss", 2, 0xf30f52, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1020{"sfence", 0, 0x0faef8, X, CpuSSE, FP, { 0, 0, 0 } },
1021{"shufps", 3, 0x0fc6, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
1022{"sqrtps", 2, 0x0f51, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1023{"sqrtss", 2, 0xf30f51, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1024{"stmxcsr", 1, 0x0fae, 3, CpuSSE, FP|Modrm, { WordMem, 0, 0 } },
1025{"subps", 2, 0x0f5c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1026{"subss", 2, 0xf30f5c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1027{"ucomiss", 2, 0x0f2e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
1028{"unpckhps", 2, 0x0f15, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1029{"unpcklps", 2, 0x0f14, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
1030{"xorps", 2, 0x0f57, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
c608c12e 1031
d0b47220 1032/* AMD 3DNow! instructions. */
c608c12e 1033
e413e4e9
AM		 1034{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } },
1035{"prefetchw",1, 0x0f0d, 1, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } },
1036{"femms", 0, 0x0f0e, X, Cpu3dnow, FP, { 0, 0, 0 } },
1037{"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1038{"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1039{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1040{"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1041{"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1042{"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1043{"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1044{"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1045{"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1046{"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1047{"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1048{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1049{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1050{"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1051{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1052{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1053{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1054{"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1055{"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1056{"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1057{"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1058{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1059{"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1060{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } },
1061
1062/* sentinel */
1063{NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
252b5132
RH		 1064};
1065#undef X
252b5132
RH		 1066#undef NoSuf
1067#undef b_Suf
1068#undef w_Suf
1069#undef l_Suf
eecb386c 1070#undef x_Suf
252b5132
RH		 1071#undef bw_Suf
1072#undef bl_Suf
1073#undef wl_Suf
1074#undef sl_Suf
1075#undef bwl_Suf
1076#undef FP
1077#undef l_FP
eecb386c 1078#undef x_FP
252b5132
RH		 1079#undef sl_FP
1080
1081#define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */
1082
1083
d0b47220 1084/* 386 register table. */
252b5132
RH		 1085
1086static const reg_entry i386_regtab[] = {
5f47d35b
AM		 1087 /* make %st first as we test for it */
1088 {"st", FloatReg|FloatAcc, 0},
252b5132
RH		 1089 /* 8 bit regs */
1090 {"al", Reg8|Acc, 0},
1091 {"cl", Reg8|ShiftCount, 1},
1092 {"dl", Reg8, 2},
1093 {"bl", Reg8, 3},
1094 {"ah", Reg8, 4},
1095 {"ch", Reg8, 5},
1096 {"dh", Reg8, 6},
1097 {"bh", Reg8, 7},
1098 /* 16 bit regs */
1099 {"ax", Reg16|Acc, 0},
1100 {"cx", Reg16, 1},
1101 {"dx", Reg16|InOutPortReg, 2},
1102 {"bx", Reg16|BaseIndex, 3},
1103 {"sp", Reg16, 4},
1104 {"bp", Reg16|BaseIndex, 5},
1105 {"si", Reg16|BaseIndex, 6},
1106 {"di", Reg16|BaseIndex, 7},
1107 /* 32 bit regs */
1108 {"eax", Reg32|BaseIndex|Acc, 0},
1109 {"ecx", Reg32|BaseIndex, 1},
1110 {"edx", Reg32|BaseIndex, 2},
1111 {"ebx", Reg32|BaseIndex, 3},
1112 {"esp", Reg32, 4},
1113 {"ebp", Reg32|BaseIndex, 5},
1114 {"esi", Reg32|BaseIndex, 6},
1115 {"edi", Reg32|BaseIndex, 7},
1116 /* segment registers */
1117 {"es", SReg2, 0},
1118 {"cs", SReg2, 1},
1119 {"ss", SReg2, 2},
1120 {"ds", SReg2, 3},
1121 {"fs", SReg3, 4},
1122 {"gs", SReg3, 5},
1123 /* control registers */
1124 {"cr0", Control, 0},
1125 {"cr1", Control, 1},
1126 {"cr2", Control, 2},
1127 {"cr3", Control, 3},
1128 {"cr4", Control, 4},
1129 {"cr5", Control, 5},
1130 {"cr6", Control, 6},
1131 {"cr7", Control, 7},
1132 /* debug registers */
1133 {"db0", Debug, 0},
1134 {"db1", Debug, 1},
1135 {"db2", Debug, 2},
1136 {"db3", Debug, 3},
1137 {"db4", Debug, 4},
1138 {"db5", Debug, 5},
1139 {"db6", Debug, 6},
1140 {"db7", Debug, 7},
1141 {"dr0", Debug, 0},
1142 {"dr1", Debug, 1},
1143 {"dr2", Debug, 2},
1144 {"dr3", Debug, 3},
1145 {"dr4", Debug, 4},
1146 {"dr5", Debug, 5},
1147 {"dr6", Debug, 6},
1148 {"dr7", Debug, 7},
1149 /* test registers */
1150 {"tr0", Test, 0},
1151 {"tr1", Test, 1},
1152 {"tr2", Test, 2},
1153 {"tr3", Test, 3},
1154 {"tr4", Test, 4},
1155 {"tr5", Test, 5},
1156 {"tr6", Test, 6},
1157 {"tr7", Test, 7},
5f47d35b 1158 /* mmx and simd registers */
252b5132
RH		 1159 {"mm0", RegMMX, 0},
1160 {"mm1", RegMMX, 1},
1161 {"mm2", RegMMX, 2},
1162 {"mm3", RegMMX, 3},
1163 {"mm4", RegMMX, 4},
1164 {"mm5", RegMMX, 5},
1165 {"mm6", RegMMX, 6},
c608c12e
AM		 1166 {"mm7", RegMMX, 7},
1167 {"xmm0", RegXMM, 0},
1168 {"xmm1", RegXMM, 1},
1169 {"xmm2", RegXMM, 2},
1170 {"xmm3", RegXMM, 3},
1171 {"xmm4", RegXMM, 4},
1172 {"xmm5", RegXMM, 5},
1173 {"xmm6", RegXMM, 6},
1174 {"xmm7", RegXMM, 7}
252b5132
RH		 1175};
1176
5f47d35b
AM		 1177static const reg_entry i386_float_regtab[] = {
1178 {"st(0)", FloatReg|FloatAcc, 0},
1179 {"st(1)", FloatReg, 1},
1180 {"st(2)", FloatReg, 2},
1181 {"st(3)", FloatReg, 3},
1182 {"st(4)", FloatReg, 4},
1183 {"st(5)", FloatReg, 5},
1184 {"st(6)", FloatReg, 6},
1185 {"st(7)", FloatReg, 7}
1186};
1187
252b5132
RH		 1188#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */
1189
1190/* segment stuff */
1191static const seg_entry cs = { "cs", 0x2e };
1192static const seg_entry ds = { "ds", 0x3e };
1193static const seg_entry ss = { "ss", 0x36 };
1194static const seg_entry es = { "es", 0x26 };
1195static const seg_entry fs = { "fs", 0x64 };
1196static const seg_entry gs = { "gs", 0x65 };
1197
1198/* end of opcode/i386.h */
GDB Binutils - Deliverables
This page took 0.152159 seconds and 4 git commands to generate.